ConsoleImplConfigX86.cpp@ 104507

Last change on this file since 104507 was 104507, checked in by vboxsync, 9 months ago
VMM,Main: Some GCM adjustments. bugref:9735 bugref:10683
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1	/* $Id: ConsoleImplConfigX86.cpp 104507 2024-05-03 13:58:16Z vboxsync $ */
2	/** @file
3	* VBox Console COM Class implementation - VM Configuration Bits.
4	*
5	* @remark We've split out the code that the 64-bit VC++ v8 compiler finds
6	* problematic to optimize so we can disable optimizations and later,
7	* perhaps, find a real solution for it (like rewriting the code and
8	* to stop resemble a tonne of spaghetti).
9	*/
10
11	/*
12	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
13	*
14	* This file is part of VirtualBox base platform packages, as
15	* available from https://www.virtualbox.org.
16	*
17	* This program is free software; you can redistribute it and/or
18	* modify it under the terms of the GNU General Public License
19	* as published by the Free Software Foundation, in version 3 of the
20	* License.
21	*
22	* This program is distributed in the hope that it will be useful, but
23	* WITHOUT ANY WARRANTY; without even the implied warranty of
24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
25	* General Public License for more details.
26	*
27	* You should have received a copy of the GNU General Public License
28	* along with this program; if not, see <https://www.gnu.org/licenses>.
29	*
30	* SPDX-License-Identifier: GPL-3.0-only
31	*/
32
33
34	/*********************************************************************************************************************************
35	* Header Files *
36	*********************************************************************************************************************************/
37	#define LOG_GROUP LOG_GROUP_MAIN_CONSOLE
38	#include "LoggingNew.h"
39
40	#include "ConsoleImpl.h"
41	#include "DisplayImpl.h"
42	#include "NvramStoreImpl.h"
43	#include "PlatformImpl.h"
44	#include "VMMDev.h"
45	#include "Global.h"
46	#ifdef VBOX_WITH_PCI_PASSTHROUGH
47	# include "PCIRawDevImpl.h"
48	#endif
49
50	// generated header
51	#include "SchemaDefs.h"
52
53	#include "AutoCaller.h"
54
55	#include <iprt/base64.h>
56	#include <iprt/buildconfig.h>
57	#include <iprt/ctype.h>
58	#include <iprt/dir.h>
59	#include <iprt/file.h>
60	#include <iprt/param.h>
61	#include <iprt/path.h>
62	#include <iprt/string.h>
63	#include <iprt/system.h>
64	#if 0 /* enable to play with lots of memory. */
65	# include <iprt/env.h>
66	#endif
67	#include <iprt/stream.h>
68
69	#include <iprt/http.h>
70	#include <iprt/socket.h>
71	#include <iprt/uri.h>
72
73	#include <VBox/vmm/vmmr3vtable.h>
74	#include <VBox/vmm/vmapi.h>
75	#include <VBox/err.h>
76	#include <VBox/param.h>
77	#include <VBox/settings.h> /* For MachineConfigFile::getHostDefaultAudioDriver(). */
78	#include <VBox/vmm/pdmapi.h> /* For PDMR3DriverAttach/PDMR3DriverDetach. */
79	#include <VBox/vmm/pdmusb.h> /* For PDMR3UsbCreateEmulatedDevice. */
80	#include <VBox/vmm/pdmdev.h> /* For PDMAPICMODE enum. */
81	#include <VBox/vmm/pdmstorageifs.h>
82	#include <VBox/version.h>
83
84	#include <VBox/com/com.h>
85	#include <VBox/com/string.h>
86	#include <VBox/com/array.h>
87
88	#include "NetworkServiceRunner.h"
89	#include "BusAssignmentManager.h"
90	#ifdef VBOX_WITH_EXTPACK
91	# include "ExtPackManagerImpl.h"
92	#endif
93
94
95	/*********************************************************************************************************************************
96	* Internal Functions *
97	*********************************************************************************************************************************/
98
99	/* Darwin compile kludge */
100	#undef PVM
101
102	/**
103	* @throws HRESULT on extra data retrival error.
104	*/
105	static int getSmcDeviceKey(IVirtualBox pVirtualBox, IMachine pMachine, Utf8Str pStrKey, bool pfGetKeyFromRealSMC)
106	{
107	*pfGetKeyFromRealSMC = false;
108
109	/*
110	* The extra data takes precedence (if non-zero).
111	*/
112	GetExtraDataBoth(pVirtualBox, pMachine, "VBoxInternal2/SmcDeviceKey", pStrKey);
113	if (pStrKey->isNotEmpty())
114	return VINF_SUCCESS;
115
116	#ifdef RT_OS_DARWIN
117
118	/*
119	* Work done in EFI/DevSmc
120	*/
121	*pfGetKeyFromRealSMC = true;
122	int vrc = VINF_SUCCESS;
123
124	#else
125	/*
126	* Is it apple hardware in bootcamp?
127	*/
128	/** @todo implement + test RTSYSDMISTR_MANUFACTURER on all hosts.
129	* Currently falling back on the product name. */
130	char szManufacturer[256];
131	szManufacturer[0] = '\0';
132	RTSystemQueryDmiString(RTSYSDMISTR_MANUFACTURER, szManufacturer, sizeof(szManufacturer));
133	if (szManufacturer[0] != '\0')
134	{
135	if ( !strcmp(szManufacturer, "Apple Computer, Inc.")
136	\|\| !strcmp(szManufacturer, "Apple Inc.")
137	)
138	*pfGetKeyFromRealSMC = true;
139	}
140	else
141	{
142	char szProdName[256];
143	szProdName[0] = '\0';
144	RTSystemQueryDmiString(RTSYSDMISTR_PRODUCT_NAME, szProdName, sizeof(szProdName));
145	if ( ( !strncmp(szProdName, RT_STR_TUPLE("Mac"))
146	\|\| !strncmp(szProdName, RT_STR_TUPLE("iMac"))
147	\|\| !strncmp(szProdName, RT_STR_TUPLE("Xserve"))
148	)
149	&& !strchr(szProdName, ' ') /* no spaces */
150	&& RT_C_IS_DIGIT(szProdName[strlen(szProdName) - 1]) /* version number */
151	)
152	*pfGetKeyFromRealSMC = true;
153	}
154
155	int vrc = VINF_SUCCESS;
156	#endif
157
158	return vrc;
159	}
160
161
162	/*
163	* VC++ 8 / amd64 has some serious trouble with the next functions.
164	* As a temporary measure, we'll drop global optimizations.
165	*/
166	#if defined(_MSC_VER) && defined(RT_ARCH_AMD64)
167	# if _MSC_VER >= RT_MSC_VER_VC80 && _MSC_VER < RT_MSC_VER_VC100
168	# pragma optimize("g", off)
169	# endif
170	#endif
171
172	/** Helper that finds out the next HBA port used
173	*/
174	static LONG GetNextUsedPort(LONG aPortUsed[30], LONG lBaseVal, uint32_t u32Size)
175	{
176	LONG lNextPortUsed = 30;
177	for (size_t j = 0; j < u32Size; ++j)
178	{
179	if ( aPortUsed[j] > lBaseVal
180	&& aPortUsed[j] <= lNextPortUsed)
181	lNextPortUsed = aPortUsed[j];
182	}
183	return lNextPortUsed;
184	}
185
186	#define MAX_BIOS_LUN_COUNT 4
187
188	int Console::SetBiosDiskInfo(ComPtr<IMachine> pMachine, PCFGMNODE pCfg, PCFGMNODE pBiosCfg,
189	Bstr controllerName, const char * const s_apszBiosConfig[4])
190	{
191	RT_NOREF(pCfg);
192	HRESULT hrc;
193	#define MAX_DEVICES 30
194	#define H() AssertLogRelMsgReturn(!FAILED(hrc), ("hrc=%Rhrc\n", hrc), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR)
195	#define VRC() AssertLogRelMsgReturn(RT_SUCCESS(vrc), ("vrc=%Rrc\n", vrc), vrc)
196
197	LONG lPortLUN[MAX_BIOS_LUN_COUNT];
198	LONG lPortUsed[MAX_DEVICES];
199	uint32_t u32HDCount = 0;
200
201	/* init to max value */
202	lPortLUN[0] = MAX_DEVICES;
203
204	com::SafeIfaceArray<IMediumAttachment> atts;
205	hrc = pMachine->GetMediumAttachmentsOfController(controllerName.raw(),
206	ComSafeArrayAsOutParam(atts)); H();
207	size_t uNumAttachments = atts.size();
208	if (uNumAttachments > MAX_DEVICES)
209	{
210	LogRel(("Number of Attachments > Max=%d.\n", uNumAttachments));
211	uNumAttachments = MAX_DEVICES;
212	}
213
214	/* Find the relevant ports/IDs, i.e the ones to which a HD is attached. */
215	for (size_t j = 0; j < uNumAttachments; ++j)
216	{
217	IMediumAttachment *pMediumAtt = atts[j];
218	LONG lPortNum = 0;
219	hrc = pMediumAtt->COMGETTER(Port)(&lPortNum); H();
220	if (SUCCEEDED(hrc))
221	{
222	DeviceType_T lType;
223	hrc = pMediumAtt->COMGETTER(Type)(&lType); H();
224	if (SUCCEEDED(hrc) && lType == DeviceType_HardDisk)
225	{
226	/* find min port number used for HD */
227	if (lPortNum < lPortLUN[0])
228	lPortLUN[0] = lPortNum;
229	lPortUsed[u32HDCount++] = lPortNum;
230	LogFlowFunc(("HD port Count=%d\n", u32HDCount));
231	}
232	}
233	}
234
235
236	/* Pick only the top 4 used HD Ports as CMOS doesn't have space
237	* to save details for all 30 ports
238	*/
239	uint32_t u32MaxPortCount = MAX_BIOS_LUN_COUNT;
240	if (u32HDCount < MAX_BIOS_LUN_COUNT)
241	u32MaxPortCount = u32HDCount;
242	for (size_t j = 1; j < u32MaxPortCount; j++)
243	lPortLUN[j] = GetNextUsedPort(lPortUsed, lPortLUN[j-1], u32HDCount);
244	if (pBiosCfg)
245	{
246	for (size_t j = 0; j < u32MaxPortCount; j++)
247	{
248	InsertConfigInteger(pBiosCfg, s_apszBiosConfig[j], lPortLUN[j]);
249	LogFlowFunc(("Top %d HBA ports = %s, %d\n", j, s_apszBiosConfig[j], lPortLUN[j]));
250	}
251	}
252	return VINF_SUCCESS;
253	}
254
255	#ifdef VBOX_WITH_PCI_PASSTHROUGH
256	HRESULT Console::i_attachRawPCIDevices(PUVM pUVM, BusAssignmentManager *pBusMgr, PCFGMNODE pDevices)
257	{
258	# ifndef VBOX_WITH_EXTPACK
259	RT_NOREF(pUVM);
260	# endif
261	HRESULT hrc = S_OK;
262	PCFGMNODE pInst, pCfg, pLunL0, pLunL1;
263
264	SafeIfaceArray<IPCIDeviceAttachment> assignments;
265	ComPtr<IMachine> aMachine = i_machine();
266
267	hrc = aMachine->COMGETTER(PCIDeviceAssignments)(ComSafeArrayAsOutParam(assignments));
268	if ( hrc != S_OK
269	\|\| assignments.size() < 1)
270	return hrc;
271
272	/*
273	* PCI passthrough is only available if the proper ExtPack is installed.
274	*
275	* Note. Configuring PCI passthrough here and providing messages about
276	* the missing extpack isn't exactly clean, but it is a necessary evil
277	* to patch over legacy compatability issues introduced by the new
278	* distribution model.
279	*/
280	# ifdef VBOX_WITH_EXTPACK
281	static const char *s_pszPCIRawExtPackName = "Oracle VM VirtualBox Extension Pack";
282	if (!mptrExtPackManager->i_isExtPackUsable(s_pszPCIRawExtPackName))
283	/* Always fatal! */
284	return pVMM->pfnVMR3SetError(pUVM, VERR_NOT_FOUND, RT_SRC_POS,
285	N_("Implementation of the PCI passthrough framework not found!\n"
286	"The VM cannot be started. To fix this problem, either "
287	"install the '%s' or disable PCI passthrough via VBoxManage"),
288	s_pszPCIRawExtPackName);
289	# endif
290
291	/* Now actually add devices */
292	PCFGMNODE pPCIDevs = NULL;
293
294	if (assignments.size() > 0)
295	{
296	InsertConfigNode(pDevices, "pciraw", &pPCIDevs);
297
298	PCFGMNODE pRoot = CFGMR3GetParent(pDevices); Assert(pRoot);
299
300	/* Tell PGM to tell GPCIRaw about guest mappings. */
301	CFGMR3InsertNode(pRoot, "PGM", NULL);
302	InsertConfigInteger(CFGMR3GetChild(pRoot, "PGM"), "PciPassThrough", 1);
303
304	/*
305	* Currently, using IOMMU needed for PCI passthrough
306	* requires RAM preallocation.
307	*/
308	/** @todo check if we can lift this requirement */
309	CFGMR3RemoveValue(pRoot, "RamPreAlloc");
310	InsertConfigInteger(pRoot, "RamPreAlloc", 1);
311	}
312
313	for (size_t iDev = 0; iDev < assignments.size(); iDev++)
314	{
315	ComPtr<IPCIDeviceAttachment> const assignment = assignments[iDev];
316
317	LONG host;
318	hrc = assignment->COMGETTER(HostAddress)(&host); H();
319	LONG guest;
320	hrc = assignment->COMGETTER(GuestAddress)(&guest); H();
321	Bstr bstrDevName;
322	hrc = assignment->COMGETTER(Name)(bstrDevName.asOutParam()); H();
323
324	InsertConfigNodeF(pPCIDevs, &pInst, "%d", iDev);
325	InsertConfigInteger(pInst, "Trusted", 1);
326
327	PCIBusAddress HostPCIAddress(host);
328	Assert(HostPCIAddress.valid());
329	InsertConfigNode(pInst, "Config", &pCfg);
330	InsertConfigString(pCfg, "DeviceName", bstrDevName);
331
332	InsertConfigInteger(pCfg, "DetachHostDriver", 1);
333	InsertConfigInteger(pCfg, "HostPCIBusNo", HostPCIAddress.miBus);
334	InsertConfigInteger(pCfg, "HostPCIDeviceNo", HostPCIAddress.miDevice);
335	InsertConfigInteger(pCfg, "HostPCIFunctionNo", HostPCIAddress.miFn);
336
337	PCIBusAddress GuestPCIAddress(guest);
338	Assert(GuestPCIAddress.valid());
339	hrc = pBusMgr->assignHostPCIDevice("pciraw", pInst, HostPCIAddress, GuestPCIAddress, true);
340	if (hrc != S_OK)
341	return hrc;
342
343	InsertConfigInteger(pCfg, "GuestPCIBusNo", GuestPCIAddress.miBus);
344	InsertConfigInteger(pCfg, "GuestPCIDeviceNo", GuestPCIAddress.miDevice);
345	InsertConfigInteger(pCfg, "GuestPCIFunctionNo", GuestPCIAddress.miFn);
346
347	/* the driver */
348	InsertConfigNode(pInst, "LUN#0", &pLunL0);
349	InsertConfigString(pLunL0, "Driver", "pciraw");
350	InsertConfigNode(pLunL0, "AttachedDriver", &pLunL1);
351
352	/* the Main driver */
353	InsertConfigString(pLunL1, "Driver", "MainPciRaw");
354	InsertConfigNode(pLunL1, "Config", &pCfg);
355	PCIRawDev *pMainDev = new PCIRawDev(this);
356	# error This is not allowed any more
357	InsertConfigInteger(pCfg, "Object", (uintptr_t)pMainDev);
358	}
359
360	return hrc;
361	}
362	#endif
363
364
365	/**
366	* Worker for configConstructor.
367	*
368	* @return VBox status code.
369	* @param pUVM The user mode VM handle.
370	* @param pVM The cross context VM handle.
371	* @param pVMM The VMM vtable.
372	* @param pAlock The automatic lock instance. This is for when we have
373	* to leave it in order to avoid deadlocks (ext packs and
374	* more).
375	*/
376	int Console::i_configConstructorX86(PUVM pUVM, PVM pVM, PCVMMR3VTABLE pVMM, AutoWriteLock *pAlock)
377	{
378	RT_NOREF(pVM /* when everything is disabled */);
379	ComPtr<IMachine> pMachine = i_machine();
380
381	int vrc;
382	HRESULT hrc;
383	Utf8Str strTmp;
384	Bstr bstr;
385
386	#define H() AssertLogRelMsgReturn(!FAILED(hrc), ("hrc=%Rhrc\n", hrc), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR)
387
388	/*
389	* Get necessary objects and frequently used parameters.
390	*/
391	ComPtr<IVirtualBox> virtualBox;
392	hrc = pMachine->COMGETTER(Parent)(virtualBox.asOutParam()); H();
393
394	ComPtr<IHost> host;
395	hrc = virtualBox->COMGETTER(Host)(host.asOutParam()); H();
396
397	ComPtr<ISystemProperties> systemProperties;
398	hrc = virtualBox->COMGETTER(SystemProperties)(systemProperties.asOutParam()); H();
399
400	ComPtr<IFirmwareSettings> firmwareSettings;
401	hrc = pMachine->COMGETTER(FirmwareSettings)(firmwareSettings.asOutParam()); H();
402
403	ComPtr<INvramStore> nvramStore;
404	hrc = pMachine->COMGETTER(NonVolatileStore)(nvramStore.asOutParam()); H();
405
406	hrc = pMachine->COMGETTER(HardwareUUID)(bstr.asOutParam()); H();
407	RTUUID HardwareUuid;
408	vrc = RTUuidFromUtf16(&HardwareUuid, bstr.raw());
409	AssertRCReturn(vrc, vrc);
410
411	ULONG cRamMBs;
412	hrc = pMachine->COMGETTER(MemorySize)(&cRamMBs); H();
413	#if 0 /* enable to play with lots of memory. */
414	if (RTEnvExist("VBOX_RAM_SIZE"))
415	cRamMBs = RTStrToUInt64(RTEnvGet("VBOX_RAM_SIZE"));
416	#endif
417	uint64_t const cbRam = cRamMBs * (uint64_t)_1M;
418	uint32_t cbRamHole = MM_RAM_HOLE_SIZE_DEFAULT;
419	uint64_t uMcfgBase = 0;
420	uint32_t cbMcfgLength = 0;
421
422	ParavirtProvider_T enmParavirtProvider;
423	hrc = pMachine->GetEffectiveParavirtProvider(&enmParavirtProvider); H();
424
425	Bstr strParavirtDebug;
426	hrc = pMachine->COMGETTER(ParavirtDebug)(strParavirtDebug.asOutParam()); H();
427
428	BOOL fIOAPIC;
429	uint32_t uIoApicPciAddress = NIL_PCIBDF;
430	hrc = firmwareSettings->COMGETTER(IOAPICEnabled)(&fIOAPIC); H();
431
432	ComPtr<IPlatform> platform;
433	pMachine->COMGETTER(Platform)(platform.asOutParam()); H();
434
435	ChipsetType_T chipsetType;
436	hrc = platform->COMGETTER(ChipsetType)(&chipsetType); H();
437	if (chipsetType == ChipsetType_ICH9)
438	{
439	/* We'd better have 0x10000000 region, to cover 256 buses but this put
440	* too much load on hypervisor heap. Linux 4.8 currently complains with
441	* ``acpi PNP0A03:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f]
442	* only partially covers this bridge'' */
443	cbMcfgLength = 0x4000000; //0x10000000;
444	cbRamHole += cbMcfgLength;
445	uMcfgBase = _4G - cbRamHole;
446	}
447
448	/* Get the CPU profile name. */
449	Bstr bstrCpuProfile;
450	hrc = pMachine->COMGETTER(CPUProfile)(bstrCpuProfile.asOutParam()); H();
451
452	/* Get the X86 platform object. */
453	ComPtr<IPlatformX86> platformX86;
454	hrc = platform->COMGETTER(X86)(platformX86.asOutParam()); H();
455
456	/* Check if long mode is enabled. */
457	BOOL fIsGuest64Bit;
458	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_LongMode, &fIsGuest64Bit); H();
459
460	/*
461	* Figure out the IOMMU config.
462	*/
463	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
464	IommuType_T enmIommuType;
465	hrc = platform->COMGETTER(IommuType)(&enmIommuType); H();
466
467	/* Resolve 'automatic' type to an Intel or AMD IOMMU based on the host CPU. */
468	if (enmIommuType == IommuType_Automatic)
469	{
470	if ( bstrCpuProfile.startsWith("AMD")
471	\|\| bstrCpuProfile.startsWith("Quad-Core AMD")
472	\|\| bstrCpuProfile.startsWith("Hygon"))
473	enmIommuType = IommuType_AMD;
474	else if (bstrCpuProfile.startsWith("Intel"))
475	{
476	if ( bstrCpuProfile.equals("Intel 8086")
477	\|\| bstrCpuProfile.equals("Intel 80186")
478	\|\| bstrCpuProfile.equals("Intel 80286")
479	\|\| bstrCpuProfile.equals("Intel 80386")
480	\|\| bstrCpuProfile.equals("Intel 80486"))
481	enmIommuType = IommuType_None;
482	else
483	enmIommuType = IommuType_Intel;
484	}
485	# if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
486	else if (ASMIsAmdCpu())
487	enmIommuType = IommuType_AMD;
488	else if (ASMIsIntelCpu())
489	enmIommuType = IommuType_Intel;
490	# endif
491	else
492	{
493	/** @todo Should we handle other CPUs like Shanghai, VIA etc. here? */
494	LogRel(("WARNING! Unrecognized CPU type, IOMMU disabled.\n"));
495	enmIommuType = IommuType_None;
496	}
497	}
498
499	if (enmIommuType == IommuType_AMD)
500	{
501	# ifdef VBOX_WITH_IOMMU_AMD
502	/*
503	* Reserve the specific PCI address of the "SB I/O APIC" when using
504	* an AMD IOMMU. Required by Linux guests, see @bugref{9654#c23}.
505	*/
506	uIoApicPciAddress = VBOX_PCI_BDF_SB_IOAPIC;
507	# else
508	LogRel(("WARNING! AMD IOMMU not supported, IOMMU disabled.\n"));
509	enmIommuType = IommuType_None;
510	# endif
511	}
512
513	if (enmIommuType == IommuType_Intel)
514	{
515	# ifdef VBOX_WITH_IOMMU_INTEL
516	/*
517	* Reserve a unique PCI address for the I/O APIC when using
518	* an Intel IOMMU. For convenience we use the same address as
519	* we do on AMD, see @bugref{9967#c13}.
520	*/
521	uIoApicPciAddress = VBOX_PCI_BDF_SB_IOAPIC;
522	# else
523	LogRel(("WARNING! Intel IOMMU not supported, IOMMU disabled.\n"));
524	enmIommuType = IommuType_None;
525	# endif
526	}
527
528	if ( enmIommuType == IommuType_AMD
529	\|\| enmIommuType == IommuType_Intel)
530	{
531	if (chipsetType != ChipsetType_ICH9)
532	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
533	N_("IOMMU uses MSIs which requires the ICH9 chipset implementation."));
534	if (!fIOAPIC)
535	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
536	N_("IOMMU requires an I/O APIC for remapping interrupts."));
537	}
538	#else
539	IommuType_T const enmIommuType = IommuType_None;
540	#endif
541
542	/* Instantiate the bus assignment manager. */
543	Assert(enmIommuType != IommuType_Automatic);
544	BusAssignmentManager *pBusMgr = mBusMgr = BusAssignmentManager::createInstance(pVMM, chipsetType, enmIommuType);
545
546	ULONG cCpus = 1;
547	hrc = pMachine->COMGETTER(CPUCount)(&cCpus); H();
548
549	ULONG ulCpuExecutionCap = 100;
550	hrc = pMachine->COMGETTER(CPUExecutionCap)(&ulCpuExecutionCap); H();
551
552	VMExecutionEngine_T enmExecEngine = VMExecutionEngine_NotSet;
553	hrc = pMachine->COMGETTER(VMExecutionEngine)(&enmExecEngine); H();
554
555	LogRel(("Guest architecture: x86\n"));
556
557	Bstr osTypeId;
558	hrc = pMachine->COMGETTER(OSTypeId)(osTypeId.asOutParam()); H();
559	LogRel(("Guest OS type: '%s'\n", Utf8Str(osTypeId).c_str()));
560
561	APICMode_T apicMode;
562	hrc = firmwareSettings->COMGETTER(APICMode)(&apicMode); H();
563	uint32_t uFwAPIC;
564	switch (apicMode)
565	{
566	case APICMode_Disabled:
567	uFwAPIC = 0;
568	break;
569	case APICMode_APIC:
570	uFwAPIC = 1;
571	break;
572	case APICMode_X2APIC:
573	uFwAPIC = 2;
574	break;
575	default:
576	AssertMsgFailed(("Invalid APICMode=%d\n", apicMode));
577	uFwAPIC = 1;
578	break;
579	}
580
581	ComPtr<IGuestOSType> pGuestOSType;
582	virtualBox->GetGuestOSType(osTypeId.raw(), pGuestOSType.asOutParam());
583
584	BOOL fOsXGuest = FALSE;
585	BOOL fWinGuest = FALSE;
586	BOOL fOs2Guest = FALSE;
587	BOOL fW9xGuest = FALSE;
588	BOOL fDosGuest = FALSE;
589	if (pGuestOSType.isNotNull())
590	{
591	Bstr guestTypeFamilyId;
592	hrc = pGuestOSType->COMGETTER(FamilyId)(guestTypeFamilyId.asOutParam()); H();
593	fOsXGuest = guestTypeFamilyId == Bstr("MacOS");
594	fWinGuest = guestTypeFamilyId == Bstr("Windows");
595	fOs2Guest = osTypeId.startsWith(GUEST_OS_ID_STR_PARTIAL("OS2"));
596	fW9xGuest = osTypeId.startsWith(GUEST_OS_ID_STR_PARTIAL("Windows9")); /* Does not include Windows Me. */
597	fDosGuest = osTypeId.equals(GUEST_OS_ID_STR_X86("DOS")) \|\| osTypeId.equals(GUEST_OS_ID_STR_X86("Windows31"));
598	}
599
600	ComPtr<IPlatformProperties> platformProperties;
601	virtualBox->GetPlatformProperties(PlatformArchitecture_x86, platformProperties.asOutParam());
602
603	/*
604	* Get root node first.
605	* This is the only node in the tree.
606	*/
607	PCFGMNODE pRoot = pVMM->pfnCFGMR3GetRootU(pUVM);
608	Assert(pRoot);
609
610	// catching throws from InsertConfigString and friends.
611	try
612	{
613
614	/*
615	* Set the root (and VMM) level values.
616	*/
617	hrc = pMachine->COMGETTER(Name)(bstr.asOutParam()); H();
618	InsertConfigString(pRoot, "Name", bstr);
619	InsertConfigBytes(pRoot, "UUID", &HardwareUuid, sizeof(HardwareUuid));
620	InsertConfigInteger(pRoot, "RamSize", cbRam);
621	InsertConfigInteger(pRoot, "RamHoleSize", cbRamHole);
622	InsertConfigInteger(pRoot, "NumCPUs", cCpus);
623	InsertConfigInteger(pRoot, "CpuExecutionCap", ulCpuExecutionCap);
624	InsertConfigInteger(pRoot, "TimerMillies", 10);
625
626	BOOL fPageFusion = FALSE;
627	hrc = pMachine->COMGETTER(PageFusionEnabled)(&fPageFusion); H();
628	InsertConfigInteger(pRoot, "PageFusionAllowed", fPageFusion); /* boolean */
629
630	/* Not necessary, but makes sure this setting ends up in the release log. */
631	ULONG ulBalloonSize = 0;
632	hrc = pMachine->COMGETTER(MemoryBalloonSize)(&ulBalloonSize); H();
633	InsertConfigInteger(pRoot, "MemBalloonSize", ulBalloonSize);
634
635	/*
636	* EM values (before CPUM as it may need to set IemExecutesAll).
637	*/
638	PCFGMNODE pEM;
639	InsertConfigNode(pRoot, "EM", &pEM);
640
641	/* Triple fault behavior. */
642	BOOL fTripleFaultReset = false;
643	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_TripleFaultReset, &fTripleFaultReset); H();
644	InsertConfigInteger(pEM, "TripleFaultReset", fTripleFaultReset);
645
646	/*
647	* CPUM values.
648	*/
649	PCFGMNODE pCPUM;
650	InsertConfigNode(pRoot, "CPUM", &pCPUM);
651	PCFGMNODE pIsaExts;
652	InsertConfigNode(pCPUM, "IsaExts", &pIsaExts);
653
654	/* Host CPUID leaf overrides. */
655	for (uint32_t iOrdinal = 0; iOrdinal < _4K; iOrdinal++)
656	{
657	ULONG uLeaf, uSubLeaf, uEax, uEbx, uEcx, uEdx;
658	hrc = platformX86->GetCPUIDLeafByOrdinal(iOrdinal, &uLeaf, &uSubLeaf, &uEax, &uEbx, &uEcx, &uEdx);
659	if (hrc == E_INVALIDARG)
660	break;
661	H();
662	PCFGMNODE pLeaf;
663	InsertConfigNode(pCPUM, Utf8StrFmt("HostCPUID/%RX32", uLeaf).c_str(), &pLeaf);
664	/** @todo Figure out how to tell the VMM about uSubLeaf */
665	InsertConfigInteger(pLeaf, "eax", uEax);
666	InsertConfigInteger(pLeaf, "ebx", uEbx);
667	InsertConfigInteger(pLeaf, "ecx", uEcx);
668	InsertConfigInteger(pLeaf, "edx", uEdx);
669	}
670
671	/* We must limit CPUID count for Windows NT 4, as otherwise it stops
672	with error 0x3e (MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED). */
673	if (osTypeId == GUEST_OS_ID_STR_X86("WindowsNT4"))
674	{
675	LogRel(("Limiting CPUID leaf count for NT4 guests\n"));
676	InsertConfigInteger(pCPUM, "NT4LeafLimit", true);
677	}
678
679	if (fOsXGuest)
680	{
681	/* Expose extended MWAIT features to Mac OS X guests. */
682	LogRel(("Using MWAIT extensions\n"));
683	InsertConfigInteger(pIsaExts, "MWaitExtensions", true);
684
685	/* Fake the CPU family/model so the guest works. This is partly
686	because older mac releases really doesn't work on newer cpus,
687	and partly because mac os x expects more from systems with newer
688	cpus (MSRs, power features, whatever). */
689	uint32_t uMaxIntelFamilyModelStep = UINT32_MAX;
690	if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS")
691	\|\| osTypeId == GUEST_OS_ID_STR_X64("MacOS"))
692	uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482. */
693	else if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS106")
694	\|\| osTypeId == GUEST_OS_ID_STR_X64("MacOS106"))
695	uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482 */
696	else if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS107")
697	\|\| osTypeId == GUEST_OS_ID_STR_X64("MacOS107"))
698	uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482 / /* @todo figure out
699	what is required here. */
700	else if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS108")
701	\|\| osTypeId == GUEST_OS_ID_STR_X64("MacOS108"))
702	uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482 / /* @todo figure out
703	what is required here. */
704	else if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS109")
705	\|\| osTypeId == GUEST_OS_ID_STR_X64("MacOS109"))
706	uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482 / /* @todo figure
707	out what is required here. */
708	if (uMaxIntelFamilyModelStep != UINT32_MAX)
709	InsertConfigInteger(pCPUM, "MaxIntelFamilyModelStep", uMaxIntelFamilyModelStep);
710	}
711
712	/* CPU Portability level, */
713	ULONG uCpuIdPortabilityLevel = 0;
714	hrc = pMachine->COMGETTER(CPUIDPortabilityLevel)(&uCpuIdPortabilityLevel); H();
715	InsertConfigInteger(pCPUM, "PortableCpuIdLevel", uCpuIdPortabilityLevel);
716
717	/* Physical Address Extension (PAE) */
718	BOOL fEnablePAE = false;
719	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_PAE, &fEnablePAE); H();
720	fEnablePAE \|= fIsGuest64Bit;
721	InsertConfigInteger(pRoot, "EnablePAE", fEnablePAE);
722
723	/* 64-bit guests (long mode) */
724	InsertConfigInteger(pCPUM, "Enable64bit", fIsGuest64Bit);
725
726	/* APIC/X2APIC configuration */
727	BOOL fEnableAPIC = true;
728	BOOL fEnableX2APIC = true;
729	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_APIC, &fEnableAPIC); H();
730	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_X2APIC, &fEnableX2APIC); H();
731	if (fEnableX2APIC)
732	Assert(fEnableAPIC);
733
734	/* CPUM profile name. */
735	InsertConfigString(pCPUM, "GuestCpuName", bstrCpuProfile);
736
737	/*
738	* Temporary(?) hack to make sure we emulate the ancient 16-bit CPUs
739	* correctly. There are way too many #UDs we'll miss using VT-x,
740	* raw-mode or qemu for the 186 and 286, while we'll get undefined opcodes
741	* dead wrong on 8086 (see http://www.os2museum.com/wp/undocumented-8086-opcodes/).
742	*/
743	if ( bstrCpuProfile.equals("Intel 80386") /* just for now */
744	\|\| bstrCpuProfile.equals("Intel 80286")
745	\|\| bstrCpuProfile.equals("Intel 80186")
746	\|\| bstrCpuProfile.equals("Nec V20")
747	\|\| bstrCpuProfile.equals("Intel 8086") )
748	{
749	InsertConfigInteger(pEM, "IemExecutesAll", true);
750	if (!bstrCpuProfile.equals("Intel 80386"))
751	{
752	fEnableAPIC = false;
753	fIOAPIC = false;
754	}
755	fEnableX2APIC = false;
756	}
757
758	/* Adjust firmware APIC handling to stay within the VCPU limits. */
759	if (uFwAPIC == 2 && !fEnableX2APIC)
760	{
761	if (fEnableAPIC)
762	uFwAPIC = 1;
763	else
764	uFwAPIC = 0;
765	LogRel(("Limiting the firmware APIC level from x2APIC to %s\n", fEnableAPIC ? "APIC" : "Disabled"));
766	}
767	else if (uFwAPIC == 1 && !fEnableAPIC)
768	{
769	uFwAPIC = 0;
770	LogRel(("Limiting the firmware APIC level from APIC to Disabled\n"));
771	}
772
773	/* Speculation Control. */
774	BOOL fSpecCtrl = FALSE;
775	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_SpecCtrl, &fSpecCtrl); H();
776	InsertConfigInteger(pCPUM, "SpecCtrl", fSpecCtrl);
777
778	/* Nested VT-x / AMD-V. */
779	BOOL fNestedHWVirt = FALSE;
780	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_HWVirt, &fNestedHWVirt); H();
781	InsertConfigInteger(pCPUM, "NestedHWVirt", fNestedHWVirt ? true : false);
782
783	/*
784	* Hardware virtualization extensions.
785	*/
786	/* Sanitize valid/useful APIC combinations, see @bugref{8868}. */
787	if (!fEnableAPIC)
788	{
789	if (fIsGuest64Bit)
790	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
791	N_("Cannot disable the APIC for a 64-bit guest."));
792	if (cCpus > 1)
793	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
794	N_("Cannot disable the APIC for an SMP guest."));
795	if (fIOAPIC)
796	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
797	N_("Cannot disable the APIC when the I/O APIC is present."));
798	}
799
800	BOOL fHMEnabled;
801	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_Enabled, &fHMEnabled); H();
802	if (cCpus > 1 && !fHMEnabled)
803	{
804	LogRel(("Forced fHMEnabled to TRUE by SMP guest.\n"));
805	fHMEnabled = TRUE;
806	}
807
808	BOOL fHMForced;
809	fHMEnabled = fHMForced = TRUE;
810	LogRel(("fHMForced=true - No raw-mode support in this build!\n"));
811	if (!fHMForced) /* No need to query if already forced above. */
812	{
813	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_Force, &fHMForced); H();
814	if (fHMForced)
815	LogRel(("fHMForced=true - HWVirtExPropertyType_Force\n"));
816	}
817	InsertConfigInteger(pRoot, "HMEnabled", fHMEnabled);
818
819	/* /HM/xyz */
820	PCFGMNODE pHM;
821	InsertConfigNode(pRoot, "HM", &pHM);
822	InsertConfigInteger(pHM, "HMForced", fHMForced);
823	if (fHMEnabled)
824	{
825	/* Indicate whether 64-bit guests are supported or not. */
826	InsertConfigInteger(pHM, "64bitEnabled", fIsGuest64Bit);
827
828	/** @todo Not exactly pretty to check strings; VBOXOSTYPE would be better,
829	but that requires quite a bit of API change in Main. */
830	if ( fIOAPIC
831	&& ( osTypeId == GUEST_OS_ID_STR_X86("WindowsNT4")
832	\|\| osTypeId == GUEST_OS_ID_STR_X86("Windows2000")
833	\|\| osTypeId == GUEST_OS_ID_STR_X86("WindowsXP")
834	\|\| osTypeId == GUEST_OS_ID_STR_X86("Windows2003")))
835	{
836	/* Only allow TPR patching for NT, Win2k, XP and Windows Server 2003. (32 bits mode)
837	* We may want to consider adding more guest OSes (Solaris) later on.
838	*/
839	InsertConfigInteger(pHM, "TPRPatchingEnabled", 1);
840	}
841	}
842
843	/*
844	* Set VM execution engine.
845	*/
846	/** @todo r=aeichner Maybe provide a better VMM API for this instead of the different CFGM knobs. */
847	LogRel(("Using execution engine %u\n", enmExecEngine));
848	switch (enmExecEngine)
849	{
850	case VMExecutionEngine_HwVirt:
851	InsertConfigInteger(pEM, "IemExecutesAll", 0);
852	InsertConfigInteger(pEM, "IemRecompiled", 0);
853	InsertConfigInteger(pHM, "UseNEMInstead", 0);
854	InsertConfigInteger(pHM, "FallbackToNEM", 0);
855	InsertConfigInteger(pHM, "FallbackToIEM", 0);
856	break;
857	case VMExecutionEngine_NativeApi:
858	InsertConfigInteger(pEM, "IemExecutesAll", 0);
859	InsertConfigInteger(pEM, "IemRecompiled", 0);
860	InsertConfigInteger(pHM, "UseNEMInstead", 1);
861	InsertConfigInteger(pHM, "FallbackToNEM", 1);
862	InsertConfigInteger(pHM, "FallbackToIEM", 0);
863	break;
864	case VMExecutionEngine_Interpreter:
865	case VMExecutionEngine_Recompiler:
866	InsertConfigInteger(pEM, "IemExecutesAll", 1);
867	InsertConfigInteger(pEM, "IemRecompiled", enmExecEngine == VMExecutionEngine_Recompiler);
868	InsertConfigInteger(pHM, "UseNEMInstead", 0);
869	InsertConfigInteger(pHM, "FallbackToNEM", 0);
870	InsertConfigInteger(pHM, "FallbackToIEM", 1);
871	break;
872	case VMExecutionEngine_Default:
873	break; /* Nothing to do, let VMM decide. */
874	default:
875	AssertLogRelFailed();
876	}
877
878	/* HWVirtEx exclusive mode */
879	BOOL fHMExclusive = true;
880	hrc = platformProperties->COMGETTER(ExclusiveHwVirt)(&fHMExclusive); H();
881	InsertConfigInteger(pHM, "Exclusive", fHMExclusive);
882
883	/* Nested paging (VT-x/AMD-V) */
884	BOOL fEnableNestedPaging = false;
885	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_NestedPaging, &fEnableNestedPaging); H();
886	InsertConfigInteger(pHM, "EnableNestedPaging", fEnableNestedPaging);
887
888	/* Large pages; requires nested paging */
889	BOOL fEnableLargePages = false;
890	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_LargePages, &fEnableLargePages); H();
891	InsertConfigInteger(pHM, "EnableLargePages", fEnableLargePages);
892
893	/* VPID (VT-x) */
894	BOOL fEnableVPID = false;
895	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_VPID, &fEnableVPID); H();
896	InsertConfigInteger(pHM, "EnableVPID", fEnableVPID);
897
898	/* Unrestricted execution aka UX (VT-x) */
899	BOOL fEnableUX = false;
900	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_UnrestrictedExecution, &fEnableUX); H();
901	InsertConfigInteger(pHM, "EnableUX", fEnableUX);
902
903	/* Virtualized VMSAVE/VMLOAD (AMD-V) */
904	BOOL fVirtVmsaveVmload = true;
905	hrc = host->GetProcessorFeature(ProcessorFeature_VirtVmsaveVmload, &fVirtVmsaveVmload); H();
906	InsertConfigInteger(pHM, "SvmVirtVmsaveVmload", fVirtVmsaveVmload);
907
908	/* Indirect branch prediction boundraries. */
909	BOOL fIBPBOnVMExit = false;
910	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_IBPBOnVMExit, &fIBPBOnVMExit); H();
911	InsertConfigInteger(pHM, "IBPBOnVMExit", fIBPBOnVMExit);
912
913	BOOL fIBPBOnVMEntry = false;
914	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_IBPBOnVMEntry, &fIBPBOnVMEntry); H();
915	InsertConfigInteger(pHM, "IBPBOnVMEntry", fIBPBOnVMEntry);
916
917	BOOL fSpecCtrlByHost = false;
918	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_SpecCtrlByHost, &fSpecCtrlByHost); H();
919	InsertConfigInteger(pHM, "SpecCtrlByHost", fSpecCtrlByHost);
920
921	BOOL fL1DFlushOnSched = true;
922	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_L1DFlushOnEMTScheduling, &fL1DFlushOnSched); H();
923	InsertConfigInteger(pHM, "L1DFlushOnSched", fL1DFlushOnSched);
924
925	BOOL fL1DFlushOnVMEntry = false;
926	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_L1DFlushOnVMEntry, &fL1DFlushOnVMEntry); H();
927	InsertConfigInteger(pHM, "L1DFlushOnVMEntry", fL1DFlushOnVMEntry);
928
929	BOOL fMDSClearOnSched = true;
930	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_MDSClearOnEMTScheduling, &fMDSClearOnSched); H();
931	InsertConfigInteger(pHM, "MDSClearOnSched", fMDSClearOnSched);
932
933	BOOL fMDSClearOnVMEntry = false;
934	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_MDSClearOnVMEntry, &fMDSClearOnVMEntry); H();
935	InsertConfigInteger(pHM, "MDSClearOnVMEntry", fMDSClearOnVMEntry);
936
937	/* Reset overwrite. */
938	mfTurnResetIntoPowerOff = GetExtraDataBoth(virtualBox, pMachine,
939	"VBoxInternal2/TurnResetIntoPowerOff", &strTmp)->equals("1");
940	if (mfTurnResetIntoPowerOff)
941	InsertConfigInteger(pRoot, "PowerOffInsteadOfReset", 1);
942
943	/** @todo This is a bit redundant but in order to avoid forcing setting version bumps later on
944	* and don't magically change behavior of old VMs we have to keep this for now. As soon as the user sets
945	* the execution to anything else than Default the execution engine setting takes precedence.
946	*/
947	if (enmExecEngine == VMExecutionEngine_Default)
948	{
949	/* Use NEM rather than HM. */
950	BOOL fUseNativeApi = false;
951	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_UseNativeApi, &fUseNativeApi); H();
952	InsertConfigInteger(pHM, "UseNEMInstead", fUseNativeApi);
953	}
954
955	/* Enable workaround for missing TLB flush for OS/2 guests, see ticketref:20625. */
956	if (fOs2Guest)
957	InsertConfigInteger(pHM, "MissingOS2TlbFlushWorkaround", 1);
958
959	/*
960	* NEM
961	*/
962	PCFGMNODE pNEM;
963	InsertConfigNode(pRoot, "NEM", &pNEM);
964	InsertConfigInteger(pNEM, "Allow64BitGuests", fIsGuest64Bit);
965
966	/*
967	* Paravirt. provider.
968	*/
969	PCFGMNODE pParavirtNode;
970	InsertConfigNode(pRoot, "GIM", &pParavirtNode);
971	const char *pcszParavirtProvider;
972	bool fGimDeviceNeeded = true;
973	switch (enmParavirtProvider)
974	{
975	case ParavirtProvider_None:
976	pcszParavirtProvider = "None";
977	fGimDeviceNeeded = false;
978	break;
979
980	case ParavirtProvider_Minimal:
981	pcszParavirtProvider = "Minimal";
982	break;
983
984	case ParavirtProvider_HyperV:
985	pcszParavirtProvider = "HyperV";
986	break;
987
988	case ParavirtProvider_KVM:
989	pcszParavirtProvider = "KVM";
990	break;
991
992	default:
993	AssertMsgFailed(("Invalid enmParavirtProvider=%d\n", enmParavirtProvider));
994	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, N_("Invalid paravirt. provider '%d'"),
995	enmParavirtProvider);
996	}
997	InsertConfigString(pParavirtNode, "Provider", pcszParavirtProvider);
998
999	/*
1000	* Parse paravirt. debug options.
1001	*/
1002	bool fGimDebug = false;
1003	com::Utf8Str strGimDebugAddress = "127.0.0.1";
1004	uint32_t uGimDebugPort = 50000;
1005	if (strParavirtDebug.isNotEmpty())
1006	{
1007	/* Hyper-V debug options. */
1008	if (enmParavirtProvider == ParavirtProvider_HyperV)
1009	{
1010	bool fGimHvDebug = false;
1011	com::Utf8Str strGimHvVendor;
1012	bool fGimHvVsIf = false;
1013	bool fGimHvHypercallIf = false;
1014
1015	size_t uPos = 0;
1016	com::Utf8Str strDebugOptions = strParavirtDebug;
1017	com::Utf8Str strKey;
1018	com::Utf8Str strVal;
1019	while ((uPos = strDebugOptions.parseKeyValue(strKey, strVal, uPos)) != com::Utf8Str::npos)
1020	{
1021	if (strKey == "enabled")
1022	{
1023	if (strVal.toUInt32() == 1)
1024	{
1025	/* Apply defaults.
1026	The defaults are documented in the user manual,
1027	changes need to be reflected accordingly. */
1028	fGimHvDebug = true;
1029	strGimHvVendor = "Microsoft Hv";
1030	fGimHvVsIf = true;
1031	fGimHvHypercallIf = false;
1032	}
1033	/* else: ignore, i.e. don't assert below with 'enabled=0'. */
1034	}
1035	else if (strKey == "address")
1036	strGimDebugAddress = strVal;
1037	else if (strKey == "port")
1038	uGimDebugPort = strVal.toUInt32();
1039	else if (strKey == "vendor")
1040	strGimHvVendor = strVal;
1041	else if (strKey == "vsinterface")
1042	fGimHvVsIf = RT_BOOL(strVal.toUInt32());
1043	else if (strKey == "hypercallinterface")
1044	fGimHvHypercallIf = RT_BOOL(strVal.toUInt32());
1045	else
1046	{
1047	AssertMsgFailed(("Unrecognized Hyper-V debug option '%s'\n", strKey.c_str()));
1048	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1049	N_("Unrecognized Hyper-V debug option '%s' in '%s'"), strKey.c_str(),
1050	strDebugOptions.c_str());
1051	}
1052	}
1053
1054	/* Update HyperV CFGM node with active debug options. */
1055	if (fGimHvDebug)
1056	{
1057	PCFGMNODE pHvNode;
1058	InsertConfigNode(pParavirtNode, "HyperV", &pHvNode);
1059	InsertConfigString(pHvNode, "VendorID", strGimHvVendor);
1060	InsertConfigInteger(pHvNode, "VSInterface", fGimHvVsIf ? 1 : 0);
1061	InsertConfigInteger(pHvNode, "HypercallDebugInterface", fGimHvHypercallIf ? 1 : 0);
1062	fGimDebug = true;
1063	}
1064	}
1065	}
1066
1067	/*
1068	* Guest Compatibility Manager.
1069	*/
1070	PCFGMNODE pGcmNode;
1071	InsertConfigNode(pRoot, "GCM", &pGcmNode);
1072	/* OS/2 and Win9x guests can run DOS apps so they get the DOS specific
1073	fixes as well. */
1074	if (fDosGuest \|\| fOs2Guest \|\| fW9xGuest)
1075	InsertConfigInteger(pGcmNode, "DivByZeroDOS", 1);
1076	if (fOs2Guest)
1077	InsertConfigInteger(pGcmNode, "DivByZeroOS2", 1);
1078	if (fW9xGuest)
1079	InsertConfigInteger(pGcmNode, "DivByZeroWin9x", 1);
1080
1081	/*
1082	* MM values.
1083	*/
1084	PCFGMNODE pMM;
1085	InsertConfigNode(pRoot, "MM", &pMM);
1086	InsertConfigInteger(pMM, "CanUseLargerHeap", chipsetType == ChipsetType_ICH9);
1087
1088	/*
1089	* PDM config.
1090	* Load drivers in VBoxC.[so\|dll]
1091	*/
1092	vrc = i_configPdm(pMachine, pVMM, pUVM, pRoot); VRC();
1093
1094	/*
1095	* Devices
1096	*/
1097	PCFGMNODE pDevices = NULL; /* /Devices */
1098	PCFGMNODE pDev = NULL; /* /Devices/Dev/ */
1099	PCFGMNODE pInst = NULL; /* /Devices/Dev/0/ */
1100	PCFGMNODE pCfg = NULL; /* /Devices/Dev/.../Config/ */
1101	PCFGMNODE pLunL0 = NULL; /* /Devices/Dev/0/LUN#0/ */
1102	PCFGMNODE pLunL1 = NULL; /* /Devices/Dev/0/LUN#0/AttachedDriver/ */
1103	PCFGMNODE pBiosCfg = NULL; /* /Devices/pcbios/0/Config/ */
1104	PCFGMNODE pNetBootCfg = NULL; /* /Devices/pcbios/0/Config/NetBoot/ */
1105
1106	InsertConfigNode(pRoot, "Devices", &pDevices);
1107
1108	/*
1109	* GIM Device
1110	*/
1111	if (fGimDeviceNeeded)
1112	{
1113	InsertConfigNode(pDevices, "GIMDev", &pDev);
1114	InsertConfigNode(pDev, "0", &pInst);
1115	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1116	//InsertConfigNode(pInst, "Config", &pCfg);
1117
1118	if (fGimDebug)
1119	{
1120	InsertConfigNode(pInst, "LUN#998", &pLunL0);
1121	InsertConfigString(pLunL0, "Driver", "UDP");
1122	InsertConfigNode(pLunL0, "Config", &pLunL1);
1123	InsertConfigString(pLunL1, "ServerAddress", strGimDebugAddress);
1124	InsertConfigInteger(pLunL1, "ServerPort", uGimDebugPort);
1125	}
1126	}
1127
1128	/*
1129	* PC Arch.
1130	*/
1131	InsertConfigNode(pDevices, "pcarch", &pDev);
1132	InsertConfigNode(pDev, "0", &pInst);
1133	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1134	InsertConfigNode(pInst, "Config", &pCfg);
1135
1136	/*
1137	* The time offset
1138	*/
1139	LONG64 timeOffset;
1140	hrc = firmwareSettings->COMGETTER(TimeOffset)(&timeOffset); H();
1141	PCFGMNODE pTMNode;
1142	InsertConfigNode(pRoot, "TM", &pTMNode);
1143	InsertConfigInteger(pTMNode, "UTCOffset", timeOffset * 1000000);
1144
1145	/*
1146	* DMA
1147	*/
1148	InsertConfigNode(pDevices, "8237A", &pDev);
1149	InsertConfigNode(pDev, "0", &pInst);
1150	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1151
1152	/*
1153	* PCI buses.
1154	*/
1155	uint32_t uIocPCIAddress, uHbcPCIAddress;
1156	switch (chipsetType)
1157	{
1158	default:
1159	AssertFailed();
1160	RT_FALL_THRU();
1161	case ChipsetType_PIIX3:
1162	/* Create the base for adding bridges on demand */
1163	InsertConfigNode(pDevices, "pcibridge", NULL);
1164
1165	InsertConfigNode(pDevices, "pci", &pDev);
1166	uHbcPCIAddress = (0x0 << 16) \| 0;
1167	uIocPCIAddress = (0x1 << 16) \| 0; // ISA controller
1168	break;
1169	case ChipsetType_ICH9:
1170	/* Create the base for adding bridges on demand */
1171	InsertConfigNode(pDevices, "ich9pcibridge", NULL);
1172
1173	InsertConfigNode(pDevices, "ich9pci", &pDev);
1174	uHbcPCIAddress = (0x1e << 16) \| 0;
1175	uIocPCIAddress = (0x1f << 16) \| 0; // LPC controller
1176	break;
1177	}
1178	InsertConfigNode(pDev, "0", &pInst);
1179	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1180	InsertConfigNode(pInst, "Config", &pCfg);
1181	InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
1182	if (chipsetType == ChipsetType_ICH9)
1183	{
1184	/* Provide MCFG info */
1185	InsertConfigInteger(pCfg, "McfgBase", uMcfgBase);
1186	InsertConfigInteger(pCfg, "McfgLength", cbMcfgLength);
1187
1188	#ifdef VBOX_WITH_PCI_PASSTHROUGH
1189	/* Add PCI passthrough devices */
1190	hrc = i_attachRawPCIDevices(pUVM, pBusMgr, pDevices); H();
1191	#endif
1192
1193	if (enmIommuType == IommuType_AMD)
1194	{
1195	/* AMD IOMMU. */
1196	InsertConfigNode(pDevices, "iommu-amd", &pDev);
1197	InsertConfigNode(pDev, "0", &pInst);
1198	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1199	InsertConfigNode(pInst, "Config", &pCfg);
1200	hrc = pBusMgr->assignPCIDevice("iommu-amd", pInst); H();
1201
1202	/* The AMD IOMMU device needs to know which PCI slot it's in, see @bugref{9654#c104}. */
1203	{
1204	PCIBusAddress Address;
1205	if (pBusMgr->findPCIAddress("iommu-amd", 0, Address))
1206	{
1207	uint32_t const u32IommuAddress = (Address.miDevice << 16) \| Address.miFn;
1208	InsertConfigInteger(pCfg, "PCIAddress", u32IommuAddress);
1209	}
1210	else
1211	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1212	N_("Failed to find PCI address of the assigned IOMMU device!"));
1213	}
1214
1215	PCIBusAddress PCIAddr = PCIBusAddress((int32_t)uIoApicPciAddress);
1216	hrc = pBusMgr->assignPCIDevice("sb-ioapic", NULL /* pCfg /, PCIAddr, true /fGuestAddressRequired*/); H();
1217	}
1218	else if (enmIommuType == IommuType_Intel)
1219	{
1220	/* Intel IOMMU. */
1221	InsertConfigNode(pDevices, "iommu-intel", &pDev);
1222	InsertConfigNode(pDev, "0", &pInst);
1223	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1224	InsertConfigNode(pInst, "Config", &pCfg);
1225	hrc = pBusMgr->assignPCIDevice("iommu-intel", pInst); H();
1226
1227	PCIBusAddress PCIAddr = PCIBusAddress((int32_t)uIoApicPciAddress);
1228	hrc = pBusMgr->assignPCIDevice("sb-ioapic", NULL /* pCfg /, PCIAddr, true /fGuestAddressRequired*/); H();
1229	}
1230	}
1231
1232	/*
1233	* Enable the following devices: HPET, SMC and LPC on MacOS X guests or on ICH9 chipset
1234	*/
1235
1236	/*
1237	* High Precision Event Timer (HPET)
1238	*/
1239	BOOL fHPETEnabled;
1240	/* Other guests may wish to use HPET too, but MacOS X not functional without it */
1241	hrc = platformX86->COMGETTER(HPETEnabled)(&fHPETEnabled); H();
1242	/* so always enable HPET in extended profile */
1243	fHPETEnabled \|= fOsXGuest;
1244	/* HPET is always present on ICH9 */
1245	fHPETEnabled \|= (chipsetType == ChipsetType_ICH9);
1246	if (fHPETEnabled)
1247	{
1248	InsertConfigNode(pDevices, "hpet", &pDev);
1249	InsertConfigNode(pDev, "0", &pInst);
1250	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1251	InsertConfigNode(pInst, "Config", &pCfg);
1252	InsertConfigInteger(pCfg, "ICH9", (chipsetType == ChipsetType_ICH9) ? 1 : 0); /* boolean */
1253	}
1254
1255	/*
1256	* System Management Controller (SMC)
1257	*/
1258	BOOL fSmcEnabled;
1259	fSmcEnabled = fOsXGuest;
1260	if (fSmcEnabled)
1261	{
1262	InsertConfigNode(pDevices, "smc", &pDev);
1263	InsertConfigNode(pDev, "0", &pInst);
1264	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1265	InsertConfigNode(pInst, "Config", &pCfg);
1266
1267	bool fGetKeyFromRealSMC;
1268	Utf8Str strKey;
1269	vrc = getSmcDeviceKey(virtualBox, pMachine, &strKey, &fGetKeyFromRealSMC);
1270	AssertRCReturn(vrc, vrc);
1271
1272	if (!fGetKeyFromRealSMC)
1273	InsertConfigString(pCfg, "DeviceKey", strKey);
1274	InsertConfigInteger(pCfg, "GetKeyFromRealSMC", fGetKeyFromRealSMC);
1275	}
1276
1277	/*
1278	* Low Pin Count (LPC) bus
1279	*/
1280	BOOL fLpcEnabled;
1281	/** @todo implement appropriate getter */
1282	fLpcEnabled = fOsXGuest \|\| (chipsetType == ChipsetType_ICH9);
1283	if (fLpcEnabled)
1284	{
1285	InsertConfigNode(pDevices, "lpc", &pDev);
1286	InsertConfigNode(pDev, "0", &pInst);
1287	hrc = pBusMgr->assignPCIDevice("lpc", pInst); H();
1288	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1289	}
1290
1291	BOOL fShowRtc;
1292	fShowRtc = fOsXGuest \|\| (chipsetType == ChipsetType_ICH9);
1293
1294	/*
1295	* PS/2 keyboard & mouse.
1296	*/
1297	InsertConfigNode(pDevices, "pckbd", &pDev);
1298	InsertConfigNode(pDev, "0", &pInst);
1299	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1300	InsertConfigNode(pInst, "Config", &pCfg);
1301
1302	KeyboardHIDType_T aKbdHID;
1303	hrc = pMachine->COMGETTER(KeyboardHIDType)(&aKbdHID); H();
1304	if (aKbdHID != KeyboardHIDType_None)
1305	{
1306	InsertConfigNode(pInst, "LUN#0", &pLunL0);
1307	InsertConfigString(pLunL0, "Driver", "KeyboardQueue");
1308	InsertConfigNode(pLunL0, "Config", &pCfg);
1309	InsertConfigInteger(pCfg, "QueueSize", 64);
1310
1311	InsertConfigNode(pLunL0, "AttachedDriver", &pLunL1);
1312	InsertConfigString(pLunL1, "Driver", "MainKeyboard");
1313	}
1314
1315	PointingHIDType_T aPointingHID;
1316	hrc = pMachine->COMGETTER(PointingHIDType)(&aPointingHID); H();
1317	if (aPointingHID != PointingHIDType_None)
1318	{
1319	InsertConfigNode(pInst, "LUN#1", &pLunL0);
1320	InsertConfigString(pLunL0, "Driver", "MouseQueue");
1321	InsertConfigNode(pLunL0, "Config", &pCfg);
1322	InsertConfigInteger(pCfg, "QueueSize", 128);
1323
1324	InsertConfigNode(pLunL0, "AttachedDriver", &pLunL1);
1325	InsertConfigString(pLunL1, "Driver", "MainMouse");
1326	}
1327
1328	/*
1329	* i8254 Programmable Interval Timer And Dummy Speaker
1330	*/
1331	InsertConfigNode(pDevices, "i8254", &pDev);
1332	InsertConfigNode(pDev, "0", &pInst);
1333	InsertConfigNode(pInst, "Config", &pCfg);
1334	#ifdef DEBUG
1335	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1336	#endif
1337
1338	/*
1339	* i8259 Programmable Interrupt Controller.
1340	*/
1341	InsertConfigNode(pDevices, "i8259", &pDev);
1342	InsertConfigNode(pDev, "0", &pInst);
1343	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1344	InsertConfigNode(pInst, "Config", &pCfg);
1345
1346	/*
1347	* Advanced Programmable Interrupt Controller.
1348	* SMP: Each CPU has a LAPIC, but we have a single device representing all LAPICs states,
1349	* thus only single insert
1350	*/
1351	if (fEnableAPIC)
1352	{
1353	InsertConfigNode(pDevices, "apic", &pDev);
1354	InsertConfigNode(pDev, "0", &pInst);
1355	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1356	InsertConfigNode(pInst, "Config", &pCfg);
1357	InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
1358	PDMAPICMODE enmAPICMode = PDMAPICMODE_APIC;
1359	if (fEnableX2APIC)
1360	enmAPICMode = PDMAPICMODE_X2APIC;
1361	else if (!fEnableAPIC)
1362	enmAPICMode = PDMAPICMODE_NONE;
1363	InsertConfigInteger(pCfg, "Mode", enmAPICMode);
1364	InsertConfigInteger(pCfg, "NumCPUs", cCpus);
1365
1366	if (fIOAPIC)
1367	{
1368	/*
1369	* I/O Advanced Programmable Interrupt Controller.
1370	*/
1371	InsertConfigNode(pDevices, "ioapic", &pDev);
1372	InsertConfigNode(pDev, "0", &pInst);
1373	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1374	InsertConfigNode(pInst, "Config", &pCfg);
1375	InsertConfigInteger(pCfg, "NumCPUs", cCpus);
1376	if (enmIommuType == IommuType_AMD)
1377	InsertConfigInteger(pCfg, "PCIAddress", uIoApicPciAddress);
1378	else if (enmIommuType == IommuType_Intel)
1379	{
1380	InsertConfigString(pCfg, "ChipType", "DMAR");
1381	InsertConfigInteger(pCfg, "PCIAddress", uIoApicPciAddress);
1382	}
1383	}
1384	}
1385
1386	/*
1387	* RTC MC146818.
1388	*/
1389	InsertConfigNode(pDevices, "mc146818", &pDev);
1390	InsertConfigNode(pDev, "0", &pInst);
1391	InsertConfigNode(pInst, "Config", &pCfg);
1392	BOOL fRTCUseUTC;
1393	hrc = platform->COMGETTER(RTCUseUTC)(&fRTCUseUTC); H();
1394	InsertConfigInteger(pCfg, "UseUTC", fRTCUseUTC ? 1 : 0);
1395
1396	/*
1397	* VGA.
1398	*/
1399	ComPtr<IGraphicsAdapter> pGraphicsAdapter;
1400	hrc = pMachine->COMGETTER(GraphicsAdapter)(pGraphicsAdapter.asOutParam()); H();
1401	GraphicsControllerType_T enmGraphicsController;
1402	hrc = pGraphicsAdapter->COMGETTER(GraphicsControllerType)(&enmGraphicsController); H();
1403	switch (enmGraphicsController)
1404	{
1405	case GraphicsControllerType_Null:
1406	break;
1407	#ifdef VBOX_WITH_VMSVGA
1408	case GraphicsControllerType_VMSVGA:
1409	InsertConfigInteger(pHM, "LovelyMesaDrvWorkaround", 1); /* hits someone else logging backdoor. */
1410	InsertConfigInteger(pNEM, "LovelyMesaDrvWorkaround", 1); /* hits someone else logging backdoor. */
1411	RT_FALL_THROUGH();
1412	case GraphicsControllerType_VBoxSVGA:
1413	#endif
1414	case GraphicsControllerType_VBoxVGA:
1415	vrc = i_configGraphicsController(pDevices, enmGraphicsController, pBusMgr, pMachine, pGraphicsAdapter, firmwareSettings);
1416	if (FAILED(vrc))
1417	return vrc;
1418	break;
1419	default:
1420	AssertMsgFailed(("Invalid graphicsController=%d\n", enmGraphicsController));
1421	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1422	N_("Invalid graphics controller type '%d'"), enmGraphicsController);
1423	}
1424
1425	/*
1426	* Firmware.
1427	*/
1428	FirmwareType_T eFwType = FirmwareType_BIOS;
1429	hrc = firmwareSettings->COMGETTER(FirmwareType)(&eFwType); H();
1430
1431	#ifdef VBOX_WITH_EFI
1432	BOOL fEfiEnabled = (eFwType >= FirmwareType_EFI) && (eFwType <= FirmwareType_EFIDUAL);
1433	#else
1434	BOOL fEfiEnabled = false;
1435	#endif
1436	if (!fEfiEnabled)
1437	{
1438	/*
1439	* PC Bios.
1440	*/
1441	InsertConfigNode(pDevices, "pcbios", &pDev);
1442	InsertConfigNode(pDev, "0", &pInst);
1443	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1444	InsertConfigNode(pInst, "Config", &pBiosCfg);
1445	InsertConfigInteger(pBiosCfg, "NumCPUs", cCpus);
1446	InsertConfigString(pBiosCfg, "HardDiskDevice", "piix3ide");
1447	InsertConfigString(pBiosCfg, "FloppyDevice", "i82078");
1448	InsertConfigInteger(pBiosCfg, "IOAPIC", fIOAPIC);
1449	InsertConfigInteger(pBiosCfg, "APIC", uFwAPIC);
1450	BOOL fPXEDebug;
1451	hrc = firmwareSettings->COMGETTER(PXEDebugEnabled)(&fPXEDebug); H();
1452	InsertConfigInteger(pBiosCfg, "PXEDebug", fPXEDebug);
1453	InsertConfigBytes(pBiosCfg, "UUID", &HardwareUuid,sizeof(HardwareUuid));
1454	BOOL fUuidLe;
1455	hrc = firmwareSettings->COMGETTER(SMBIOSUuidLittleEndian)(&fUuidLe); H();
1456	InsertConfigInteger(pBiosCfg, "UuidLe", fUuidLe);
1457	BOOL fAutoSerialNumGen;
1458	hrc = firmwareSettings->COMGETTER(AutoSerialNumGen)(&fAutoSerialNumGen); H();
1459	if (fAutoSerialNumGen)
1460	InsertConfigString(pBiosCfg, "DmiSystemSerial", "VirtualBox-<DmiSystemUuid>");
1461	InsertConfigNode(pBiosCfg, "NetBoot", &pNetBootCfg);
1462	InsertConfigInteger(pBiosCfg, "McfgBase", uMcfgBase);
1463	InsertConfigInteger(pBiosCfg, "McfgLength", cbMcfgLength);
1464
1465	AssertMsgReturn(SchemaDefs::MaxBootPosition <= 9, ("Too many boot devices %d\n", SchemaDefs::MaxBootPosition),
1466	VERR_INVALID_PARAMETER);
1467
1468	for (ULONG pos = 1; pos <= SchemaDefs::MaxBootPosition; ++pos)
1469	{
1470	DeviceType_T enmBootDevice;
1471	hrc = pMachine->GetBootOrder(pos, &enmBootDevice); H();
1472
1473	char szParamName[] = "BootDeviceX";
1474	szParamName[sizeof(szParamName) - 2] = (char)(pos - 1 + '0');
1475
1476	const char *pszBootDevice;
1477	switch (enmBootDevice)
1478	{
1479	case DeviceType_Null:
1480	pszBootDevice = "NONE";
1481	break;
1482	case DeviceType_HardDisk:
1483	pszBootDevice = "IDE";
1484	break;
1485	case DeviceType_DVD:
1486	pszBootDevice = "DVD";
1487	break;
1488	case DeviceType_Floppy:
1489	pszBootDevice = "FLOPPY";
1490	break;
1491	case DeviceType_Network:
1492	pszBootDevice = "LAN";
1493	break;
1494	default:
1495	AssertMsgFailed(("Invalid enmBootDevice=%d\n", enmBootDevice));
1496	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1497	N_("Invalid boot device '%d'"), enmBootDevice);
1498	}
1499	InsertConfigString(pBiosCfg, szParamName, pszBootDevice);
1500	}
1501
1502	/** @todo @bugref{7145}: We might want to enable this by default for new VMs. For now,
1503	* this is required for Windows 2012 guests. */
1504	if (osTypeId == GUEST_OS_ID_STR_X64("Windows2012"))
1505	InsertConfigInteger(pBiosCfg, "DmiExposeMemoryTable", 1); /* boolean */
1506	}
1507	else
1508	{
1509	/* Autodetect firmware type, basing on guest type */
1510	if (eFwType == FirmwareType_EFI)
1511	eFwType = fIsGuest64Bit ? FirmwareType_EFI64 : FirmwareType_EFI32;
1512	bool const f64BitEntry = eFwType == FirmwareType_EFI64;
1513
1514	Assert(eFwType == FirmwareType_EFI64 \|\| eFwType == FirmwareType_EFI32 \|\| eFwType == FirmwareType_EFIDUAL);
1515	#ifdef VBOX_WITH_EFI_IN_DD2
1516	const char *pszEfiRomFile = eFwType == FirmwareType_EFIDUAL ? "VBoxEFIDual.fd"
1517	: eFwType == FirmwareType_EFI32 ? "VBoxEFI32.fd"
1518	: "VBoxEFI64.fd";
1519	#else
1520	Utf8Str efiRomFile;
1521	vrc = findEfiRom(virtualBox, PlatformArchitecture_x86, eFwType, &efiRomFile);
1522	AssertRCReturn(vrc, vrc);
1523	const char *pszEfiRomFile = efiRomFile.c_str();
1524	#endif
1525
1526	/* Get boot args */
1527	Utf8Str bootArgs;
1528	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiBootArgs", &bootArgs);
1529
1530	/* Get device props */
1531	Utf8Str deviceProps;
1532	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiDeviceProps", &deviceProps);
1533
1534	/* Get NVRAM file name */
1535	Utf8Str strNvram = mptrNvramStore->i_getNonVolatileStorageFile();
1536
1537	BOOL fUuidLe;
1538	hrc = firmwareSettings->COMGETTER(SMBIOSUuidLittleEndian)(&fUuidLe); H();
1539
1540	BOOL fAutoSerialNumGen;
1541	hrc = firmwareSettings->COMGETTER(AutoSerialNumGen)(&fAutoSerialNumGen); H();
1542
1543	/* Get graphics mode settings */
1544	uint32_t u32GraphicsMode = UINT32_MAX;
1545	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiGraphicsMode", &strTmp);
1546	if (strTmp.isEmpty())
1547	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiGopMode", &strTmp);
1548	if (!strTmp.isEmpty())
1549	u32GraphicsMode = strTmp.toUInt32();
1550
1551	/* Get graphics resolution settings, with some sanity checking */
1552	Utf8Str strResolution;
1553	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiGraphicsResolution", &strResolution);
1554	if (!strResolution.isEmpty())
1555	{
1556	size_t pos = strResolution.find("x");
1557	if (pos != strResolution.npos)
1558	{
1559	Utf8Str strH, strV;
1560	strH.assignEx(strResolution, 0, pos);
1561	strV.assignEx(strResolution, pos+1, strResolution.length()-pos-1);
1562	uint32_t u32H = strH.toUInt32();
1563	uint32_t u32V = strV.toUInt32();
1564	if (u32H == 0 \|\| u32V == 0)
1565	strResolution.setNull();
1566	}
1567	else
1568	strResolution.setNull();
1569	}
1570	else
1571	{
1572	uint32_t u32H = 0;
1573	uint32_t u32V = 0;
1574	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiHorizontalResolution", &strTmp);
1575	if (strTmp.isEmpty())
1576	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiUgaHorizontalResolution", &strTmp);
1577	if (!strTmp.isEmpty())
1578	u32H = strTmp.toUInt32();
1579
1580	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiVerticalResolution", &strTmp);
1581	if (strTmp.isEmpty())
1582	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiUgaVerticalResolution", &strTmp);
1583	if (!strTmp.isEmpty())
1584	u32V = strTmp.toUInt32();
1585	if (u32H != 0 && u32V != 0)
1586	strResolution = Utf8StrFmt("%ux%u", u32H, u32V);
1587	}
1588
1589	/*
1590	* EFI subtree.
1591	*/
1592	InsertConfigNode(pDevices, "efi", &pDev);
1593	InsertConfigNode(pDev, "0", &pInst);
1594	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1595	InsertConfigNode(pInst, "Config", &pCfg);
1596	InsertConfigInteger(pCfg, "NumCPUs", cCpus);
1597	InsertConfigInteger(pCfg, "McfgBase", uMcfgBase);
1598	InsertConfigInteger(pCfg, "McfgLength", cbMcfgLength);
1599	InsertConfigString(pCfg, "EfiRom", pszEfiRomFile);
1600	InsertConfigString(pCfg, "BootArgs", bootArgs);
1601	InsertConfigString(pCfg, "DeviceProps", deviceProps);
1602	InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
1603	InsertConfigInteger(pCfg, "APIC", uFwAPIC);
1604	InsertConfigBytes(pCfg, "UUID", &HardwareUuid,sizeof(HardwareUuid));
1605	InsertConfigInteger(pCfg, "UuidLe", fUuidLe);
1606	if (fAutoSerialNumGen)
1607	InsertConfigString(pCfg, "DmiSystemSerial", "VirtualBox-<DmiSystemUuid>");
1608	InsertConfigInteger(pCfg, "64BitEntry", f64BitEntry); /* boolean */
1609	InsertConfigString(pCfg, "NvramFile", strNvram);
1610	if (u32GraphicsMode != UINT32_MAX)
1611	InsertConfigInteger(pCfg, "GraphicsMode", u32GraphicsMode);
1612	if (!strResolution.isEmpty())
1613	InsertConfigString(pCfg, "GraphicsResolution", strResolution);
1614
1615	/* For OS X guests we'll force passing host's DMI info to the guest */
1616	if (fOsXGuest)
1617	{
1618	InsertConfigInteger(pCfg, "DmiUseHostInfo", 1);
1619	InsertConfigInteger(pCfg, "DmiExposeMemoryTable", 1);
1620	}
1621
1622	/* Attach the NVRAM storage driver. */
1623	InsertConfigNode(pInst, "LUN#0", &pLunL0);
1624	InsertConfigString(pLunL0, "Driver", "NvramStore");
1625	}
1626
1627	/*
1628	* The USB Controllers.
1629	*/
1630	PCFGMNODE pUsbDevices = NULL;
1631	vrc = i_configUsb(pMachine, pBusMgr, pRoot, pDevices, aKbdHID, aPointingHID, &pUsbDevices);
1632
1633	/*
1634	* Storage controllers.
1635	*/
1636	bool fFdcEnabled = false;
1637	vrc = i_configStorageCtrls(pMachine, pBusMgr, pVMM, pUVM,
1638	pDevices, pUsbDevices, pBiosCfg, &fFdcEnabled); VRC();
1639
1640	/*
1641	* Network adapters
1642	*/
1643	std::list<BootNic> llBootNics;
1644	vrc = i_configNetworkCtrls(pMachine, platformProperties, chipsetType, pBusMgr,
1645	pVMM, pUVM, pDevices, llBootNics); VRC();
1646
1647	/*
1648	* Build network boot information and transfer it to the BIOS.
1649	*/
1650	if (pNetBootCfg && !llBootNics.empty()) /* NetBoot node doesn't exist for EFI! */
1651	{
1652	llBootNics.sort(); /* Sort the list by boot priority. */
1653
1654	char achBootIdx[] = "0";
1655	unsigned uBootIdx = 0;
1656
1657	for (std::list<BootNic>::iterator it = llBootNics.begin(); it != llBootNics.end(); ++it)
1658	{
1659	/* A NIC with priority 0 is only used if it's first in the list. */
1660	if (it->mBootPrio == 0 && uBootIdx != 0)
1661	break;
1662
1663	PCFGMNODE pNetBtDevCfg;
1664	achBootIdx[0] = (char)('0' + uBootIdx++); /* Boot device order. */
1665	InsertConfigNode(pNetBootCfg, achBootIdx, &pNetBtDevCfg);
1666	InsertConfigInteger(pNetBtDevCfg, "NIC", it->mInstance);
1667	InsertConfigInteger(pNetBtDevCfg, "PCIBusNo", it->mPCIAddress.miBus);
1668	InsertConfigInteger(pNetBtDevCfg, "PCIDeviceNo", it->mPCIAddress.miDevice);
1669	InsertConfigInteger(pNetBtDevCfg, "PCIFunctionNo", it->mPCIAddress.miFn);
1670	}
1671	}
1672
1673	/*
1674	* Serial (UART) Ports
1675	*/
1676	/* serial enabled mask to be passed to dev ACPI */
1677	uint16_t auSerialIoPortBase[SchemaDefs::SerialPortCount] = {0};
1678	uint8_t auSerialIrq[SchemaDefs::SerialPortCount] = {0};
1679	InsertConfigNode(pDevices, "serial", &pDev);
1680	for (ULONG ulInstance = 0; ulInstance < SchemaDefs::SerialPortCount; ++ulInstance)
1681	{
1682	ComPtr<ISerialPort> serialPort;
1683	hrc = pMachine->GetSerialPort(ulInstance, serialPort.asOutParam()); H();
1684	BOOL fEnabledSerPort = FALSE;
1685	if (serialPort)
1686	{
1687	hrc = serialPort->COMGETTER(Enabled)(&fEnabledSerPort); H();
1688	}
1689	if (!fEnabledSerPort)
1690	{
1691	m_aeSerialPortMode[ulInstance] = PortMode_Disconnected;
1692	continue;
1693	}
1694
1695	InsertConfigNode(pDev, Utf8StrFmt("%u", ulInstance).c_str(), &pInst);
1696	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1697	InsertConfigNode(pInst, "Config", &pCfg);
1698
1699	ULONG ulIRQ;
1700	hrc = serialPort->COMGETTER(IRQ)(&ulIRQ); H();
1701	InsertConfigInteger(pCfg, "IRQ", ulIRQ);
1702	auSerialIrq[ulInstance] = (uint8_t)ulIRQ;
1703
1704	ULONG ulIOBase;
1705	hrc = serialPort->COMGETTER(IOAddress)(&ulIOBase); H();
1706	InsertConfigInteger(pCfg, "IOAddress", ulIOBase);
1707	auSerialIoPortBase[ulInstance] = (uint16_t)ulIOBase;
1708
1709	BOOL fServer;
1710	hrc = serialPort->COMGETTER(Server)(&fServer); H();
1711	hrc = serialPort->COMGETTER(Path)(bstr.asOutParam()); H();
1712	UartType_T eUartType;
1713	const char *pszUartType;
1714	hrc = serialPort->COMGETTER(UartType)(&eUartType); H();
1715	switch (eUartType)
1716	{
1717	case UartType_U16450: pszUartType = "16450"; break;
1718	case UartType_U16750: pszUartType = "16750"; break;
1719	default: AssertFailed(); RT_FALL_THRU();
1720	case UartType_U16550A: pszUartType = "16550A"; break;
1721	}
1722	InsertConfigString(pCfg, "UartType", pszUartType);
1723
1724	PortMode_T eHostMode;
1725	hrc = serialPort->COMGETTER(HostMode)(&eHostMode); H();
1726
1727	m_aeSerialPortMode[ulInstance] = eHostMode;
1728	if (eHostMode != PortMode_Disconnected)
1729	{
1730	vrc = i_configSerialPort(pInst, eHostMode, Utf8Str(bstr).c_str(), RT_BOOL(fServer));
1731	if (RT_FAILURE(vrc))
1732	return vrc;
1733	}
1734	}
1735
1736	/*
1737	* Parallel (LPT) Ports
1738	*/
1739	/* parallel enabled mask to be passed to dev ACPI */
1740	uint16_t auParallelIoPortBase[SchemaDefs::ParallelPortCount] = {0};
1741	uint8_t auParallelIrq[SchemaDefs::ParallelPortCount] = {0};
1742	InsertConfigNode(pDevices, "parallel", &pDev);
1743	for (ULONG ulInstance = 0; ulInstance < SchemaDefs::ParallelPortCount; ++ulInstance)
1744	{
1745	ComPtr<IParallelPort> parallelPort;
1746	hrc = pMachine->GetParallelPort(ulInstance, parallelPort.asOutParam()); H();
1747	BOOL fEnabledParPort = FALSE;
1748	if (parallelPort)
1749	{
1750	hrc = parallelPort->COMGETTER(Enabled)(&fEnabledParPort); H();
1751	}
1752	if (!fEnabledParPort)
1753	continue;
1754
1755	InsertConfigNode(pDev, Utf8StrFmt("%u", ulInstance).c_str(), &pInst);
1756	InsertConfigNode(pInst, "Config", &pCfg);
1757
1758	ULONG ulIRQ;
1759	hrc = parallelPort->COMGETTER(IRQ)(&ulIRQ); H();
1760	InsertConfigInteger(pCfg, "IRQ", ulIRQ);
1761	auParallelIrq[ulInstance] = (uint8_t)ulIRQ;
1762	ULONG ulIOBase;
1763	hrc = parallelPort->COMGETTER(IOBase)(&ulIOBase); H();
1764	InsertConfigInteger(pCfg, "IOBase", ulIOBase);
1765	auParallelIoPortBase[ulInstance] = (uint16_t)ulIOBase;
1766
1767	hrc = parallelPort->COMGETTER(Path)(bstr.asOutParam()); H();
1768	if (!bstr.isEmpty())
1769	{
1770	InsertConfigNode(pInst, "LUN#0", &pLunL0);
1771	InsertConfigString(pLunL0, "Driver", "HostParallel");
1772	InsertConfigNode(pLunL0, "Config", &pLunL1);
1773	InsertConfigString(pLunL1, "DevicePath", bstr);
1774	}
1775	}
1776
1777	vrc = i_configVmmDev(pMachine, pBusMgr, pDevices); VRC();
1778
1779	/*
1780	* Audio configuration.
1781	*/
1782	bool fAudioEnabled = false;
1783	vrc = i_configAudioCtrl(virtualBox, pMachine, pBusMgr, pDevices,
1784	fOsXGuest, &fAudioEnabled); VRC();
1785
1786	#if defined(VBOX_WITH_TPM)
1787	/*
1788	* Configure the Trusted Platform Module.
1789	*/
1790	ComObjPtr<ITrustedPlatformModule> ptrTpm;
1791	TpmType_T enmTpmType = TpmType_None;
1792
1793	hrc = pMachine->COMGETTER(TrustedPlatformModule)(ptrTpm.asOutParam()); H();
1794	hrc = ptrTpm->COMGETTER(Type)(&enmTpmType); H();
1795	if (enmTpmType != TpmType_None)
1796	{
1797	InsertConfigNode(pDevices, "tpm", &pDev);
1798	InsertConfigNode(pDev, "0", &pInst);
1799	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1800	InsertConfigNode(pInst, "Config", &pCfg);
1801	InsertConfigNode(pInst, "LUN#0", &pLunL0);
1802
1803	switch (enmTpmType)
1804	{
1805	case TpmType_v1_2:
1806	case TpmType_v2_0:
1807	InsertConfigString(pLunL0, "Driver", "TpmEmuTpms");
1808	InsertConfigNode(pLunL0, "Config", &pCfg);
1809	InsertConfigInteger(pCfg, "TpmVersion", enmTpmType == TpmType_v1_2 ? 1 : 2);
1810	InsertConfigNode(pLunL0, "AttachedDriver", &pLunL1);
1811	InsertConfigString(pLunL1, "Driver", "NvramStore");
1812	break;
1813	case TpmType_Host:
1814	#if defined(RT_OS_LINUX) \|\| defined(RT_OS_WINDOWS)
1815	InsertConfigString(pLunL0, "Driver", "TpmHost");
1816	InsertConfigNode(pLunL0, "Config", &pCfg);
1817	#endif
1818	break;
1819	case TpmType_Swtpm:
1820	hrc = ptrTpm->COMGETTER(Location)(bstr.asOutParam()); H();
1821	InsertConfigString(pLunL0, "Driver", "TpmEmu");
1822	InsertConfigNode(pLunL0, "Config", &pCfg);
1823	InsertConfigString(pCfg, "Location", bstr);
1824	break;
1825	default:
1826	AssertFailedBreak();
1827	}
1828	}
1829	#endif
1830
1831	/*
1832	* ACPI
1833	*/
1834	BOOL fACPI;
1835	hrc = firmwareSettings->COMGETTER(ACPIEnabled)(&fACPI); H();
1836	if (fACPI)
1837	{
1838	/* Always show the CPU leafs when we have multiple VCPUs or when the IO-APIC is enabled.
1839	* The Windows SMP kernel needs a CPU leaf or else its idle loop will burn cpu cycles; the
1840	* intelppm driver refuses to register an idle state handler.
1841	* Always show CPU leafs for OS X guests. */
1842	BOOL fShowCpu = fOsXGuest;
1843	if (cCpus > 1 \|\| fIOAPIC)
1844	fShowCpu = true;
1845
1846	BOOL fCpuHotPlug;
1847	hrc = pMachine->COMGETTER(CPUHotPlugEnabled)(&fCpuHotPlug); H();
1848
1849	InsertConfigNode(pDevices, "acpi", &pDev);
1850	InsertConfigNode(pDev, "0", &pInst);
1851	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1852	InsertConfigNode(pInst, "Config", &pCfg);
1853	hrc = pBusMgr->assignPCIDevice("acpi", pInst); H();
1854
1855	InsertConfigInteger(pCfg, "NumCPUs", cCpus);
1856
1857	InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
1858	InsertConfigInteger(pCfg, "FdcEnabled", fFdcEnabled);
1859	InsertConfigInteger(pCfg, "HpetEnabled", fHPETEnabled);
1860	InsertConfigInteger(pCfg, "SmcEnabled", fSmcEnabled);
1861	InsertConfigInteger(pCfg, "ShowRtc", fShowRtc);
1862	if (fOsXGuest && !llBootNics.empty())
1863	{
1864	BootNic aNic = llBootNics.front();
1865	uint32_t u32NicPCIAddr = (aNic.mPCIAddress.miDevice << 16) \| aNic.mPCIAddress.miFn;
1866	InsertConfigInteger(pCfg, "NicPciAddress", u32NicPCIAddr);
1867	}
1868	if (fOsXGuest && fAudioEnabled)
1869	{
1870	PCIBusAddress Address;
1871	if (pBusMgr->findPCIAddress("hda", 0, Address))
1872	{
1873	uint32_t u32AudioPCIAddr = (Address.miDevice << 16) \| Address.miFn;
1874	InsertConfigInteger(pCfg, "AudioPciAddress", u32AudioPCIAddr);
1875	}
1876	}
1877	if (fOsXGuest)
1878	{
1879	PCIBusAddress Address;
1880	if (pBusMgr->findPCIAddress("nvme", 0, Address))
1881	{
1882	uint32_t u32NvmePCIAddr = (Address.miDevice << 16) \| Address.miFn;
1883	InsertConfigInteger(pCfg, "NvmePciAddress", u32NvmePCIAddr);
1884	}
1885	}
1886	if (enmIommuType == IommuType_AMD)
1887	{
1888	PCIBusAddress Address;
1889	if (pBusMgr->findPCIAddress("iommu-amd", 0, Address))
1890	{
1891	uint32_t u32IommuAddress = (Address.miDevice << 16) \| Address.miFn;
1892	InsertConfigInteger(pCfg, "IommuAmdEnabled", true);
1893	InsertConfigInteger(pCfg, "IommuPciAddress", u32IommuAddress);
1894	if (pBusMgr->findPCIAddress("sb-ioapic", 0, Address))
1895	{
1896	uint32_t const u32SbIoapicAddress = (Address.miDevice << 16) \| Address.miFn;
1897	InsertConfigInteger(pCfg, "SbIoApicPciAddress", u32SbIoapicAddress);
1898	}
1899	else
1900	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1901	N_("AMD IOMMU is enabled, but the I/O APIC is not assigned a PCI address!"));
1902	}
1903	}
1904	else if (enmIommuType == IommuType_Intel)
1905	{
1906	PCIBusAddress Address;
1907	if (pBusMgr->findPCIAddress("iommu-intel", 0, Address))
1908	{
1909	uint32_t u32IommuAddress = (Address.miDevice << 16) \| Address.miFn;
1910	InsertConfigInteger(pCfg, "IommuIntelEnabled", true);
1911	InsertConfigInteger(pCfg, "IommuPciAddress", u32IommuAddress);
1912	if (pBusMgr->findPCIAddress("sb-ioapic", 0, Address))
1913	{
1914	uint32_t const u32SbIoapicAddress = (Address.miDevice << 16) \| Address.miFn;
1915	InsertConfigInteger(pCfg, "SbIoApicPciAddress", u32SbIoapicAddress);
1916	}
1917	else
1918	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1919	N_("Intel IOMMU is enabled, but the I/O APIC is not assigned a PCI address!"));
1920	}
1921	}
1922
1923	InsertConfigInteger(pCfg, "IocPciAddress", uIocPCIAddress);
1924	if (chipsetType == ChipsetType_ICH9)
1925	{
1926	InsertConfigInteger(pCfg, "McfgBase", uMcfgBase);
1927	InsertConfigInteger(pCfg, "McfgLength", cbMcfgLength);
1928	/* 64-bit prefetch window root resource: Only for ICH9 and if PAE or Long Mode is enabled (@bugref{5454}). */
1929	if (fIsGuest64Bit \|\| fEnablePAE)
1930	InsertConfigInteger(pCfg, "PciPref64Enabled", 1);
1931	}
1932	InsertConfigInteger(pCfg, "HostBusPciAddress", uHbcPCIAddress);
1933	InsertConfigInteger(pCfg, "ShowCpu", fShowCpu);
1934	InsertConfigInteger(pCfg, "CpuHotPlug", fCpuHotPlug);
1935
1936	InsertConfigInteger(pCfg, "Serial0IoPortBase", auSerialIoPortBase[0]);
1937	InsertConfigInteger(pCfg, "Serial0Irq", auSerialIrq[0]);
1938
1939	InsertConfigInteger(pCfg, "Serial1IoPortBase", auSerialIoPortBase[1]);
1940	InsertConfigInteger(pCfg, "Serial1Irq", auSerialIrq[1]);
1941
1942	if (auSerialIoPortBase[2])
1943	{
1944	InsertConfigInteger(pCfg, "Serial2IoPortBase", auSerialIoPortBase[2]);
1945	InsertConfigInteger(pCfg, "Serial2Irq", auSerialIrq[2]);
1946	}
1947
1948	if (auSerialIoPortBase[3])
1949	{
1950	InsertConfigInteger(pCfg, "Serial3IoPortBase", auSerialIoPortBase[3]);
1951	InsertConfigInteger(pCfg, "Serial3Irq", auSerialIrq[3]);
1952	}
1953
1954	InsertConfigInteger(pCfg, "Parallel0IoPortBase", auParallelIoPortBase[0]);
1955	InsertConfigInteger(pCfg, "Parallel0Irq", auParallelIrq[0]);
1956
1957	InsertConfigInteger(pCfg, "Parallel1IoPortBase", auParallelIoPortBase[1]);
1958	InsertConfigInteger(pCfg, "Parallel1Irq", auParallelIrq[1]);
1959
1960	#if defined(VBOX_WITH_TPM)
1961	switch (enmTpmType)
1962	{
1963	case TpmType_v1_2:
1964	InsertConfigString(pCfg, "TpmMode", "tis1.2");
1965	break;
1966	case TpmType_v2_0:
1967	InsertConfigString(pCfg, "TpmMode", "fifo2.0");
1968	break;
1969	/** @todo Host and swtpm. */
1970	default:
1971	break;
1972	}
1973	#endif
1974
1975	InsertConfigNode(pInst, "LUN#0", &pLunL0);
1976	InsertConfigString(pLunL0, "Driver", "ACPIHost");
1977	InsertConfigNode(pLunL0, "Config", &pCfg);
1978
1979	/* Attach the dummy CPU drivers */
1980	for (ULONG iCpuCurr = 1; iCpuCurr < cCpus; iCpuCurr++)
1981	{
1982	BOOL fCpuAttached = true;
1983
1984	if (fCpuHotPlug)
1985	{
1986	hrc = pMachine->GetCPUStatus(iCpuCurr, &fCpuAttached); H();
1987	}
1988
1989	if (fCpuAttached)
1990	{
1991	InsertConfigNode(pInst, Utf8StrFmt("LUN#%u", iCpuCurr).c_str(), &pLunL0);
1992	InsertConfigString(pLunL0, "Driver", "ACPICpu");
1993	InsertConfigNode(pLunL0, "Config", &pCfg);
1994	}
1995	}
1996	}
1997
1998	/*
1999	* Configure DBGF (Debug(ger) Facility) and DBGC (Debugger Console).
2000	*/
2001	vrc = i_configGuestDbg(virtualBox, pMachine, pRoot); VRC();
2002	}
2003	catch (ConfigError &x)
2004	{
2005	// InsertConfig threw something:
2006	pVMM->pfnVMR3SetError(pUVM, x.m_vrc, RT_SRC_POS, "Caught ConfigError: %Rrc - %s", x.m_vrc, x.what());
2007	return x.m_vrc;
2008	}
2009	catch (HRESULT hrcXcpt)
2010	{
2011	AssertLogRelMsgFailedReturn(("hrc=%Rhrc\n", hrcXcpt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR);
2012	}
2013
2014	#ifdef VBOX_WITH_EXTPACK
2015	/*
2016	* Call the extension pack hooks if everything went well thus far.
2017	*/
2018	if (RT_SUCCESS(vrc))
2019	{
2020	pAlock->release();
2021	vrc = mptrExtPackManager->i_callAllVmConfigureVmmHooks(this, pVM, pVMM);
2022	pAlock->acquire();
2023	}
2024	#endif
2025
2026	/*
2027	* Apply the CFGM overlay.
2028	*/
2029	if (RT_SUCCESS(vrc))
2030	vrc = i_configCfgmOverlay(pRoot, virtualBox, pMachine);
2031
2032	/*
2033	* Dump all extradata API settings tweaks, both global and per VM.
2034	*/
2035	if (RT_SUCCESS(vrc))
2036	vrc = i_configDumpAPISettingsTweaks(virtualBox, pMachine);
2037
2038	#undef H
2039
2040	pAlock->release(); /* Avoid triggering the lock order inversion check. */
2041
2042	/*
2043	* Register VM state change handler.
2044	*/
2045	int vrc2 = pVMM->pfnVMR3AtStateRegister(pUVM, Console::i_vmstateChangeCallback, this);
2046	AssertRC(vrc2);
2047	if (RT_SUCCESS(vrc))
2048	vrc = vrc2;
2049
2050	/*
2051	* Register VM runtime error handler.
2052	*/
2053	vrc2 = pVMM->pfnVMR3AtRuntimeErrorRegister(pUVM, Console::i_atVMRuntimeErrorCallback, this);
2054	AssertRC(vrc2);
2055	if (RT_SUCCESS(vrc))
2056	vrc = vrc2;
2057
2058	pAlock->acquire();
2059
2060	LogFlowFunc(("vrc = %Rrc\n", vrc));
2061	LogFlowFuncLeave();
2062
2063	return vrc;
2064	}

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source: vbox/trunk/src/VBox/Main/src-client/ConsoleImplConfigX86.cpp@ 104507

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