ConsoleImplConfigArmV8.cpp@ 106384

Last change on this file since 106384 was 106384, checked in by vboxsync, 6 months ago
Main: Code for configuring and enabling nested virtualization support on ARM (M3 based hardware + macOS 15.0 aka Sequioa), bugref:10747
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 46.6 KB

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1	/* $Id: ConsoleImplConfigArmV8.cpp 106384 2024-10-16 13:58:41Z vboxsync $ */
2	/** @file
3	* VBox Console COM Class implementation - VM Configuration Bits for ARMv8.
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_MAIN_CONSOLE
33	#include "LoggingNew.h"
34
35	#include "ConsoleImpl.h"
36	#include "ResourceStoreImpl.h"
37	#include "Global.h"
38	#include "VMMDev.h"
39
40	// generated header
41	#include "SchemaDefs.h"
42
43	#include "AutoCaller.h"
44
45	#include <iprt/buildconfig.h>
46	#include <iprt/ctype.h>
47	#include <iprt/dir.h>
48	#include <iprt/fdt.h>
49	#include <iprt/file.h>
50	#include <iprt/param.h>
51	#include <iprt/path.h>
52	#include <iprt/string.h>
53	#include <iprt/system.h>
54	#if 0 /* enable to play with lots of memory. */
55	# include <iprt/env.h>
56	#endif
57	#include <iprt/stream.h>
58
59	#include <iprt/formats/arm-psci.h>
60
61	#include <VBox/vmm/vmmr3vtable.h>
62	#include <VBox/vmm/vmapi.h>
63	#include <VBox/err.h>
64	#include <VBox/param.h>
65	#include <VBox/version.h>
66	#include <VBox/platforms/vbox-armv8.h>
67
68	#include "BusAssignmentManager.h"
69	#include "ResourceAssignmentManager.h"
70	#include "SystemTableBuilder.h"
71	#ifdef VBOX_WITH_EXTPACK
72	# include "ExtPackManagerImpl.h"
73	#endif
74
75
76	/*********************************************************************************************************************************
77	* Internal Functions *
78	*********************************************************************************************************************************/
79
80	/* Darwin compile kludge */
81	#undef PVM
82
83	#ifdef VBOX_WITH_VIRT_ARMV8
84	/**
85	* Worker for configConstructor.
86	*
87	* @return VBox status code.
88	* @param pUVM The user mode VM handle.
89	* @param pVM The cross context VM handle.
90	* @param pVMM The VMM vtable.
91	* @param pAlock The automatic lock instance. This is for when we have
92	* to leave it in order to avoid deadlocks (ext packs and
93	* more).
94	*/
95	int Console::i_configConstructorArmV8(PUVM pUVM, PVM pVM, PCVMMR3VTABLE pVMM, AutoWriteLock *pAlock)
96	{
97	RT_NOREF(pVM /* when everything is disabled */);
98	ComPtr<IMachine> pMachine = i_machine();
99
100	HRESULT hrc;
101	Utf8Str strTmp;
102	Bstr bstr;
103
104	RTFDT hFdt = NIL_RTFDT;
105	int vrc = RTFdtCreateEmpty(&hFdt);
106	AssertRCReturn(vrc, vrc);
107
108	#define H() AssertLogRelMsgReturnStmt(!FAILED(hrc), ("hrc=%Rhrc\n", hrc), RTFdtDestroy(hFdt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR)
109	#define VRC() AssertLogRelMsgReturnStmt(RT_SUCCESS(vrc), ("vrc=%Rrc\n", vrc), RTFdtDestroy(hFdt), vrc)
110
111	/*
112	* Get necessary objects and frequently used parameters.
113	*/
114	ComPtr<IVirtualBox> virtualBox;
115	hrc = pMachine->COMGETTER(Parent)(virtualBox.asOutParam()); H();
116
117	ComPtr<IHost> host;
118	hrc = virtualBox->COMGETTER(Host)(host.asOutParam()); H();
119
120	PlatformArchitecture_T platformArchHost;
121	hrc = host->COMGETTER(Architecture)(&platformArchHost); H();
122
123	ComPtr<ISystemProperties> systemProperties;
124	hrc = virtualBox->COMGETTER(SystemProperties)(systemProperties.asOutParam()); H();
125
126	ComPtr<IFirmwareSettings> firmwareSettings;
127	hrc = pMachine->COMGETTER(FirmwareSettings)(firmwareSettings.asOutParam()); H();
128
129	ComPtr<INvramStore> nvramStore;
130	hrc = pMachine->COMGETTER(NonVolatileStore)(nvramStore.asOutParam()); H();
131
132	hrc = pMachine->COMGETTER(HardwareUUID)(bstr.asOutParam()); H();
133	RTUUID HardwareUuid;
134	vrc = RTUuidFromUtf16(&HardwareUuid, bstr.raw());
135	AssertRCReturn(vrc, vrc);
136
137	ULONG cRamMBs;
138	hrc = pMachine->COMGETTER(MemorySize)(&cRamMBs); H();
139	uint64_t const cbRam = cRamMBs * (uint64_t)_1M;
140
141	ComPtr<IPlatform> platform;
142	hrc = pMachine->COMGETTER(Platform)(platform.asOutParam()); H();
143
144	/* Note: Should be guarded by VBOX_WITH_VIRT_ARMV8, but we check this anyway here. */
145	#if 1 /* For now we only support running ARM VMs on ARM hosts. */
146	PlatformArchitecture_T platformArchMachine;
147	hrc = platform->COMGETTER(Architecture)(&platformArchMachine); H();
148	if (platformArchMachine != platformArchHost)
149	return pVMM->pfnVMR3SetError(pUVM, VERR_PLATFORM_ARCH_NOT_SUPPORTED, RT_SRC_POS,
150	N_("VM platform architecture (%s) not supported on this host (%s)."),
151	Global::stringifyPlatformArchitecture(platformArchMachine),
152	Global::stringifyPlatformArchitecture(platformArchHost));
153	#endif
154
155	/* Get the ARM platform object. */
156	ComPtr<IPlatformARM> platformARM;
157	hrc = platform->COMGETTER(ARM)(platformARM.asOutParam()); H();
158
159	ComPtr<IPlatformProperties> pPlatformProperties;
160	hrc = platform->COMGETTER(Properties)(pPlatformProperties.asOutParam()); H();
161
162	ChipsetType_T chipsetType;
163	hrc = platform->COMGETTER(ChipsetType)(&chipsetType); H();
164
165	ULONG cCpus = 1;
166	hrc = pMachine->COMGETTER(CPUCount)(&cCpus); H();
167	Assert(cCpus);
168
169	ULONG ulCpuExecutionCap = 100;
170	hrc = pMachine->COMGETTER(CPUExecutionCap)(&ulCpuExecutionCap); H();
171
172	VMExecutionEngine_T enmExecEngine = VMExecutionEngine_NotSet;
173	hrc = pMachine->COMGETTER(VMExecutionEngine)(&enmExecEngine); H();
174
175	if ( enmExecEngine != VMExecutionEngine_Default
176	&& enmExecEngine != VMExecutionEngine_NativeApi)
177	{
178	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
179	N_("The ARM backend doesn't support any other execution engine than 'default' or 'native-api' right now."));
180	}
181
182	LogRel(("Guest architecture: ARM\n"));
183
184	Bstr osTypeId;
185	hrc = pMachine->COMGETTER(OSTypeId)(osTypeId.asOutParam()); H();
186	LogRel(("Guest OS type: '%s'\n", Utf8Str(osTypeId).c_str()));
187
188	BusAssignmentManager *pBusMgr = mBusMgr = BusAssignmentManager::createInstance(pVMM, chipsetType, IommuType_None);
189	ResourceAssignmentManager *pResMgr = ResourceAssignmentManager::createInstance(pVMM, chipsetType, IommuType_None,
190	RT_MAX(_1G + cbRam, _4G), /GCPhysMmio/
191	_1G, /GCPhysRam/
192	VBOXPLATFORMARMV8_PHYS_ADDR + _1M, /GCPhysMmio32Start/
193	_1G - (VBOXPLATFORMARMV8_PHYS_ADDR + _1M), /cbMmio32/
194	32 /cInterrupts/);
195	SystemTableBuilder *pSysTblsBldAcpi = NULL;
196
197	/*
198	* ACPI
199	*/
200	BOOL fACPI;
201	hrc = firmwareSettings->COMGETTER(ACPIEnabled)(&fACPI); H();
202	if (fACPI)
203	pSysTblsBldAcpi = SystemTableBuilder::createInstance(kSystemTableType_Acpi);
204
205
206	/*
207	* Get root node first.
208	* This is the only node in the tree.
209	*/
210	PCFGMNODE pRoot = pVMM->pfnCFGMR3GetRootU(pUVM);
211	Assert(pRoot);
212
213	RTGCPHYS GCPhysRam = NIL_RTGCPHYS;
214
215	// catching throws from InsertConfigString and friends.
216	try
217	{
218
219	/*
220	* Set the root (and VMM) level values.
221	*/
222	hrc = pMachine->COMGETTER(Name)(bstr.asOutParam()); H();
223	InsertConfigString(pRoot, "Name", bstr);
224	InsertConfigBytes(pRoot, "UUID", &HardwareUuid, sizeof(HardwareUuid));
225	InsertConfigInteger(pRoot, "NumCPUs", cCpus);
226	InsertConfigInteger(pRoot, "CpuExecutionCap", ulCpuExecutionCap);
227	InsertConfigInteger(pRoot, "TimerMillies", 10);
228
229	/*
230	* NEM
231	*/
232	PCFGMNODE pNEM;
233	InsertConfigNode(pRoot, "NEM", &pNEM);
234
235	uint32_t idPHandleIntCtrl = RTFdtPHandleAllocate(hFdt);
236	Assert(idPHandleIntCtrl != UINT32_MAX);
237	uint32_t idPHandleIntCtrlMsi = RTFdtPHandleAllocate(hFdt);
238	Assert(idPHandleIntCtrlMsi != UINT32_MAX); RT_NOREF(idPHandleIntCtrlMsi);
239	uint32_t idPHandleAbpPClk = RTFdtPHandleAllocate(hFdt);
240	Assert(idPHandleAbpPClk != UINT32_MAX);
241	uint32_t idPHandleGpio = RTFdtPHandleAllocate(hFdt);
242	Assert(idPHandleGpio != UINT32_MAX);
243
244	uint32_t aidPHandleCpus[VMM_MAX_CPU_COUNT];
245	for (uint32_t i = 0; i < cCpus; i++)
246	{
247	aidPHandleCpus[i] = RTFdtPHandleAllocate(hFdt);
248	Assert(aidPHandleCpus[i] != UINT32_MAX);
249	}
250
251	vrc = RTFdtNodePropertyAddU32( hFdt, "interrupt-parent", idPHandleIntCtrl); VRC();
252	vrc = RTFdtNodePropertyAddString(hFdt, "model", "linux,dummy-virt"); VRC();
253	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
254	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 2); VRC();
255	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "linux,dummy-virt"); VRC();
256
257	/* Configure the Power State Coordination Interface. */
258	vrc = RTFdtNodeAdd(hFdt, "psci"); VRC();
259	vrc = RTFdtNodePropertyAddU32( hFdt, "migrate", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_MIGRATE)); VRC();
260	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_on", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_ON)); VRC();
261	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_off", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_OFF)); VRC();
262	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_suspend", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_SUSPEND)); VRC();
263	vrc = RTFdtNodePropertyAddString(hFdt, "method", "hvc"); VRC();
264	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 3,
265	"arm,psci-1.0", "arm,psci-0.2", "arm,psci"); VRC();
266	vrc = RTFdtNodeFinalize(hFdt); VRC();
267
268	/* Configure the timer and clock. */
269	InsertConfigInteger(pNEM, "VTimerInterrupt", 0xb);
270	vrc = RTFdtNodeAdd(hFdt, "timer"); VRC();
271	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 12,
272	0x01, 0x0d, 0x104,
273	0x01, 0x0e, 0x104,
274	0x01, 0x0b, 0x104,
275	0x01, 0x0a, 0x104); VRC();
276	vrc = RTFdtNodePropertyAddEmpty( hFdt, "always-on"); VRC();
277	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,armv8-timer"); VRC();
278	vrc = RTFdtNodeFinalize(hFdt);
279
280	vrc = RTFdtNodeAdd(hFdt, "apb-clk"); VRC();
281	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleAbpPClk); VRC();
282	vrc = RTFdtNodePropertyAddString( hFdt, "clock-output-names", "clk24mhz"); VRC();
283	vrc = RTFdtNodePropertyAddU32( hFdt, "clock-frequency", 24 * 1000 * 1000); VRC();
284	vrc = RTFdtNodePropertyAddU32( hFdt, "#clock-cells", 0); VRC();
285	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "fixed-clock"); VRC();
286	vrc = RTFdtNodeFinalize(hFdt);
287
288	if (pSysTblsBldAcpi)
289	{
290	vrc = pSysTblsBldAcpi->configureClock();
291	VRC();
292	}
293
294	/*
295	* MM values.
296	*/
297	PCFGMNODE pMM;
298	InsertConfigNode(pRoot, "MM", &pMM);
299
300	/*
301	* Memory setup.
302	*/
303	PCFGMNODE pMem = NULL;
304	InsertConfigNode(pMM, "MemRegions", &pMem);
305
306	hrc = pResMgr->assignRamRegion("Conventional", cbRam, &GCPhysRam); H();
307
308	PCFGMNODE pMemRegion = NULL;
309	InsertConfigNode(pMem, "Conventional", &pMemRegion);
310	InsertConfigInteger(pMemRegion, "GCPhysStart", GCPhysRam);
311	InsertConfigInteger(pMemRegion, "Size", cbRam);
312
313	vrc = RTFdtNodeAddF(hFdt, "memory@%RGp", GCPhysRam); VRC();
314	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysRam, cbRam); VRC();
315	vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "memory"); VRC();
316	vrc = RTFdtNodeFinalize(hFdt); VRC();
317
318	if (pSysTblsBldAcpi)
319	{
320	vrc = pSysTblsBldAcpi->addMemory(GCPhysRam, cbRam);
321	VRC();
322	}
323
324	/* Configure the CPUs in the system, only one socket and cluster at the moment. */
325	vrc = RTFdtNodeAdd(hFdt, "cpus"); VRC();
326	vrc = RTFdtNodePropertyAddU32(hFdt, "#size-cells", 0); VRC();
327	vrc = RTFdtNodePropertyAddU32(hFdt, "#address-cells", 1); VRC();
328
329	vrc = RTFdtNodeAdd(hFdt, "socket0"); VRC();
330	vrc = RTFdtNodeAdd(hFdt, "cluster0"); VRC();
331
332	for (uint32_t i = 0; i < cCpus; i++)
333	{
334	vrc = RTFdtNodeAddF(hFdt, "core%u", i); VRC();
335	vrc = RTFdtNodePropertyAddU32(hFdt, "cpu", aidPHandleCpus[i]); VRC();
336	vrc = RTFdtNodeFinalize(hFdt); VRC();
337	}
338
339	vrc = RTFdtNodeFinalize(hFdt); VRC();
340	vrc = RTFdtNodeFinalize(hFdt); VRC();
341
342	for (uint32_t i = 0; i < cCpus; i++)
343	{
344	vrc = RTFdtNodeAddF(hFdt, "cpu@%u", i); VRC();
345	vrc = RTFdtNodePropertyAddU32(hFdt, "phandle", aidPHandleCpus[i]); VRC();
346	vrc = RTFdtNodePropertyAddU32(hFdt, "reg", i); VRC();
347	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "arm,cortex-a15"); VRC();
348	vrc = RTFdtNodePropertyAddString(hFdt, "device_type", "cpu"); VRC();
349	if (cCpus > 1)
350	{
351	vrc = RTFdtNodePropertyAddString(hFdt, "enable-method", "psci"); VRC();
352	}
353	vrc = RTFdtNodeFinalize(hFdt); VRC();
354
355	if (pSysTblsBldAcpi)
356	{
357	vrc = pSysTblsBldAcpi->addCpu(i);
358	VRC();
359	}
360	}
361
362	vrc = RTFdtNodeFinalize(hFdt); VRC();
363
364
365	/*
366	* CPUM values.
367	*/
368	PCFGMNODE pCpum;
369	InsertConfigNode(pRoot, "CPUM", &pCpum);
370
371	/* Nested Virtualization. */
372	BOOL fNestedHWVirt = FALSE;
373	hrc = platformARM->GetCPUProperty(CPUPropertyTypeARM_HWVirt, &fNestedHWVirt); H();
374	InsertConfigInteger(pCpum, "NestedHWVirt", fNestedHWVirt ? true : false);
375
376
377	/*
378	* PDM config.
379	* Load drivers in VBoxC.[so\|dll]
380	*/
381	vrc = i_configPdm(pMachine, pVMM, pUVM, pRoot); VRC();
382
383
384	/*
385	* VGA.
386	*/
387	ComPtr<IGraphicsAdapter> pGraphicsAdapter;
388	hrc = pMachine->COMGETTER(GraphicsAdapter)(pGraphicsAdapter.asOutParam()); H();
389	GraphicsControllerType_T enmGraphicsController;
390	hrc = pGraphicsAdapter->COMGETTER(GraphicsControllerType)(&enmGraphicsController); H();
391
392	/*
393	* Devices
394	*/
395	PCFGMNODE pDevices = NULL; /* /Devices */
396	PCFGMNODE pDev = NULL; /* /Devices/Dev/ */
397	PCFGMNODE pInst = NULL; /* /Devices/Dev/0/ */
398	PCFGMNODE pCfg = NULL; /* /Devices/Dev/.../Config/ */
399	PCFGMNODE pLunL0 = NULL; /* /Devices/Dev/0/LUN#0/ */
400
401	InsertConfigNode(pRoot, "Devices", &pDevices);
402
403	InsertConfigNode(pDevices, "pci-generic-ecam-bridge", NULL);
404
405	InsertConfigNode(pDevices, "platform", &pDev);
406	InsertConfigNode(pDev, "0", &pInst);
407	InsertConfigNode(pInst, "Config", &pCfg);
408	InsertConfigNode(pInst, "LUN#0", &pLunL0);
409	InsertConfigString(pLunL0, "Driver", "ResourceStore");
410
411	/* Add the resources. */
412	PCFGMNODE pResources = NULL; /* /Devices/platform/Config/Resources */
413	PCFGMNODE pRes = NULL; /* /Devices/platform/Config/Resources/<Resource> */
414	InsertConfigString(pCfg, "ResourceNamespace", "resources");
415	InsertConfigNode(pCfg, "Resources", &pResources);
416	InsertConfigNode(pResources, "EfiRom", &pRes);
417	InsertConfigInteger(pRes, "RegisterAsRom", 1);
418	InsertConfigInteger(pRes, "GCPhysLoadAddress", 0);
419
420	/** @todo r=aeichner 32-bit guests and query the firmware type from VBoxSVC. */
421	/*
422	* Firmware.
423	*/
424	FirmwareType_T eFwType = FirmwareType_EFI64;
425	#ifdef VBOX_WITH_EFI_IN_DD2
426	const char *pszEfiRomFile = eFwType == FirmwareType_EFIDUAL ? "<INVALID>"
427	: eFwType == FirmwareType_EFI32 ? "VBoxEFIAArch32.fd"
428	: "VBoxEFIAArch64.fd";
429	const char *pszKey = "ResourceId";
430	#else
431	Utf8Str efiRomFile;
432	vrc = findEfiRom(virtualBox, PlatformArchitecture_ARM, eFwType, &efiRomFile);
433	AssertRCReturn(vrc, vrc);
434	const char *pszEfiRomFile = efiRomFile.c_str();
435	const char *pszKey = "Filename";
436	#endif
437	InsertConfigString(pRes, pszKey, pszEfiRomFile);
438
439	InsertConfigNode(pResources, "ArmV8Desc", &pRes);
440	InsertConfigInteger(pRes, "RegisterAsRom", 1);
441	InsertConfigInteger(pRes, "GCPhysLoadAddress", VBOXPLATFORMARMV8_PHYS_ADDR);
442	InsertConfigString(pRes, "ResourceId", "VBoxArmV8Desc");
443
444	/*
445	* Configure the interrupt controller.
446	*/
447	RTGCPHYS GCPhysIntcDist;
448	RTGCPHYS GCPhysIntcReDist;
449	RTGCPHYS cbMmioIntcDist;
450	RTGCPHYS cbMmioIntcReDist;
451
452	/* Each vCPU needs on re-distributor, this would allow for up to 256 vCPUs in the future. */
453	hrc = pResMgr->assignMmioRegion("gic", 256 * _64K, &GCPhysIntcReDist, &cbMmioIntcReDist); H();
454	hrc = pResMgr->assignMmioRegion("gic", _64K, &GCPhysIntcDist, &cbMmioIntcDist); H();
455
456	#ifndef RT_OS_LINUX
457	InsertConfigNode(pDevices, "gic", &pDev);
458	#else
459	/* On Linux we default to the KVM in-kernel GIC for now. */
460	InsertConfigNode(pDevices, "gic-nem", &pDev);
461	#endif
462	InsertConfigNode(pDev, "0", &pInst);
463	InsertConfigInteger(pInst, "Trusted", 1);
464	InsertConfigNode(pInst, "Config", &pCfg);
465	InsertConfigInteger(pCfg, "DistributorMmioBase", GCPhysIntcDist);
466	InsertConfigInteger(pCfg, "RedistributorMmioBase", GCPhysIntcReDist);
467
468	vrc = RTFdtNodeAddF(hFdt, "intc@%RGp", GCPhysIntcDist); VRC();
469	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleIntCtrl); VRC();
470	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 4,
471	GCPhysIntcDist, cbMmioIntcDist, /* Distributor */
472	GCPhysIntcReDist, cbMmioIntcReDist); /* Re-Distributor */ VRC();
473	vrc = RTFdtNodePropertyAddU32( hFdt, "#redistributor-regions", 1); VRC();
474	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,gic-v3"); VRC();
475	vrc = RTFdtNodePropertyAddEmpty( hFdt, "ranges"); VRC();
476	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
477	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 2); VRC();
478	vrc = RTFdtNodePropertyAddEmpty( hFdt, "interrupt-controller"); VRC();
479	vrc = RTFdtNodePropertyAddU32( hFdt, "#interrupt-cells", 3); VRC();
480
481	if (pSysTblsBldAcpi)
482	{
483	vrc = pSysTblsBldAcpi->configureGic(cCpus, GCPhysIntcDist, cbMmioIntcDist,
484	GCPhysIntcReDist, cbMmioIntcReDist);
485	VRC();
486	}
487
488	#if 0
489	vrc = RTFdtNodeAddF(hFdt, "its@%RX32", 0x08080000); VRC();
490	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleIntCtrlMsi); VRC();
491	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4, 0, 0x08080000, 0, 0x20000); VRC();
492	vrc = RTFdtNodePropertyAddU32( hFdt, "#msi-cells", 1); VRC();
493	vrc = RTFdtNodePropertyAddEmpty( hFdt, "msi-controller"); VRC();
494	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,gic-v3-its"); VRC();
495	vrc = RTFdtNodeFinalize(hFdt); VRC();
496	#endif
497
498	vrc = RTFdtNodeFinalize(hFdt); VRC();
499
500	RTGCPHYS GCPhysMmioStart;
501	RTGCPHYS cbMmio;
502	if (enmGraphicsController == GraphicsControllerType_QemuRamFB)
503	{
504	hrc = pResMgr->assignMmioRegion("qemu-fw-cfg", _4K, &GCPhysMmioStart, &cbMmio); H();
505
506	InsertConfigNode(pDevices, "qemu-fw-cfg", &pDev);
507	InsertConfigNode(pDev, "0", &pInst);
508	InsertConfigNode(pInst, "Config", &pCfg);
509	InsertConfigInteger(pCfg, "MmioSize", cbMmio);
510	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
511	InsertConfigInteger(pCfg, "DmaEnabled", 1);
512	InsertConfigInteger(pCfg, "QemuRamfbSupport", 1);
513	InsertConfigNode(pInst, "LUN#0", &pLunL0);
514	InsertConfigString(pLunL0, "Driver", "MainDisplay");
515
516	vrc = RTFdtNodeAddF(hFdt, "fw-cfg@%RGp", GCPhysMmioStart); VRC();
517	vrc = RTFdtNodePropertyAddEmpty( hFdt, "dma-coherent"); VRC();
518	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
519	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "qemu,fw-cfg-mmio"); VRC();
520	vrc = RTFdtNodeFinalize(hFdt); VRC();
521
522	if (pSysTblsBldAcpi)
523	{
524	vrc = pSysTblsBldAcpi->addMmioDeviceNoIrq("qemu-fw-cfg", 0, GCPhysMmioStart, cbMmio);
525	VRC();
526	}
527	}
528
529	InsertConfigNode(pDevices, "flash-cfi", &pDev);
530	InsertConfigNode(pDev, "0", &pInst);
531	InsertConfigNode(pInst, "Config", &pCfg);
532	InsertConfigInteger(pCfg, "BaseAddress", 64 * _1M);
533	InsertConfigInteger(pCfg, "Size", 768 * _1K);
534	InsertConfigString(pCfg, "FlashFile", "nvram");
535	/* Attach the NVRAM storage driver. */
536	InsertConfigNode(pInst, "LUN#0", &pLunL0);
537	InsertConfigString(pLunL0, "Driver", "NvramStore");
538
539	vrc = RTFdtNodeAddF(hFdt, "flash@%RX32", 0); VRC();
540	vrc = RTFdtNodePropertyAddU32( hFdt, "bank-width", 4); VRC();
541	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 4,
542	0, 0x04000000, /* First region (EFI). */
543	0x04000000, 0x04000000); /* Second region (NVRAM). */ VRC();
544	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "cfi-flash"); VRC();
545	vrc = RTFdtNodeFinalize(hFdt); VRC();
546
547	InsertConfigNode(pDevices, "arm-pl011", &pDev);
548	for (ULONG ulInstance = 0; ulInstance < 1 /** @todo SchemaDefs::SerialPortCount*/; ++ulInstance)
549	{
550	ComPtr<ISerialPort> serialPort;
551	hrc = pMachine->GetSerialPort(ulInstance, serialPort.asOutParam()); H();
552	BOOL fEnabledSerPort = FALSE;
553	if (serialPort)
554	{
555	hrc = serialPort->COMGETTER(Enabled)(&fEnabledSerPort); H();
556	}
557	if (!fEnabledSerPort)
558	{
559	m_aeSerialPortMode[ulInstance] = PortMode_Disconnected;
560	continue;
561	}
562
563	InsertConfigNode(pDev, Utf8StrFmt("%u", ulInstance).c_str(), &pInst);
564	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
565	InsertConfigNode(pInst, "Config", &pCfg);
566
567	uint32_t iIrq = 0;
568	hrc = pResMgr->assignSingleInterrupt("arm-pl011", &iIrq); H();
569	hrc = pResMgr->assignMmioRegion("arm-pl011", _4K, &GCPhysMmioStart, &cbMmio); H();
570
571	InsertConfigInteger(pCfg, "Irq", iIrq);
572	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
573
574	vrc = RTFdtNodeAddF(hFdt, "pl011@%RGp", GCPhysMmioStart); VRC();
575	vrc = RTFdtNodePropertyAddStringList(hFdt, "clock-names", 2, "uartclk", "apb_pclk"); VRC();
576	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "clocks", 2,
577	idPHandleAbpPClk, idPHandleAbpPClk); VRC();
578	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
579	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
580	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
581	"arm,pl011", "arm,primecell"); VRC();
582	vrc = RTFdtNodeFinalize(hFdt); VRC();
583
584	if (pSysTblsBldAcpi)
585	{
586	vrc = pSysTblsBldAcpi->addMmioDevice("arm-pl011", ulInstance, GCPhysMmioStart, cbMmio, iIrq);
587	VRC();
588	}
589
590	BOOL fServer;
591	hrc = serialPort->COMGETTER(Server)(&fServer); H();
592	hrc = serialPort->COMGETTER(Path)(bstr.asOutParam()); H();
593
594	PortMode_T eHostMode;
595	hrc = serialPort->COMGETTER(HostMode)(&eHostMode); H();
596
597	m_aeSerialPortMode[ulInstance] = eHostMode;
598	if (eHostMode != PortMode_Disconnected)
599	{
600	vrc = i_configSerialPort(pInst, eHostMode, Utf8Str(bstr).c_str(), RT_BOOL(fServer));
601	if (RT_FAILURE(vrc))
602	return vrc;
603	}
604	}
605
606	BOOL fRTCUseUTC;
607	hrc = platform->COMGETTER(RTCUseUTC)(&fRTCUseUTC); H();
608
609	uint32_t iIrq = 0;
610	hrc = pResMgr->assignSingleInterrupt("arm-pl031-rtc", &iIrq); H();
611	hrc = pResMgr->assignMmioRegion("arm-pl031-rtc", _4K, &GCPhysMmioStart, &cbMmio); H();
612	InsertConfigNode(pDevices, "arm-pl031-rtc", &pDev);
613	InsertConfigNode(pDev, "0", &pInst);
614	InsertConfigNode(pInst, "Config", &pCfg);
615	InsertConfigInteger(pCfg, "Irq", iIrq);
616	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
617	InsertConfigInteger(pCfg, "UtcOffset", fRTCUseUTC ? 1 : 0);
618
619	vrc = RTFdtNodeAddF(hFdt, "pl032@%RGp", GCPhysMmioStart); VRC();
620	vrc = RTFdtNodePropertyAddString( hFdt, "clock-names", "apb_pclk"); VRC();
621	vrc = RTFdtNodePropertyAddU32( hFdt, "clocks", idPHandleAbpPClk); VRC();
622	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
623	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
624	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
625	"arm,pl031", "arm,primecell"); VRC();
626	vrc = RTFdtNodeFinalize(hFdt); VRC();
627
628	/* Configure gpio keys. */
629	hrc = pResMgr->assignSingleInterrupt("arm-pl061-gpio", &iIrq); H();
630	hrc = pResMgr->assignMmioRegion("arm-pl061-gpio", _4K, &GCPhysMmioStart, &cbMmio); H();
631	InsertConfigNode(pDevices, "arm-pl061-gpio",&pDev);
632	InsertConfigNode(pDev, "0", &pInst);
633	InsertConfigNode(pInst, "Config", &pCfg);
634	InsertConfigInteger(pCfg, "Irq", iIrq);
635	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
636	vrc = RTFdtNodeAddF(hFdt, "pl061@%RGp", GCPhysMmioStart); VRC();
637	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleGpio); VRC();
638	vrc = RTFdtNodePropertyAddString( hFdt, "clock-names", "apb_pclk"); VRC();
639	vrc = RTFdtNodePropertyAddU32( hFdt, "clocks", idPHandleAbpPClk); VRC();
640	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
641	vrc = RTFdtNodePropertyAddEmpty( hFdt, "gpio-controller"); VRC();
642	vrc = RTFdtNodePropertyAddU32( hFdt, "#gpio-cells", 2); VRC();
643	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
644	"arm,pl061", "arm,primecell"); VRC();
645	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
646	vrc = RTFdtNodeFinalize(hFdt); VRC();
647
648	if (pSysTblsBldAcpi)
649	{
650	vrc = pSysTblsBldAcpi->addMmioDevice("arm-pl061-gpio", 0, GCPhysMmioStart, _4K, iIrq);
651	VRC();
652	}
653
654	InsertConfigNode(pInst, "LUN#0", &pLunL0);
655	InsertConfigString(pLunL0, "Driver", "GpioButton");
656	InsertConfigNode(pLunL0, "Config", &pCfg);
657	InsertConfigInteger(pCfg, "PowerButtonGpio", 3);
658	InsertConfigInteger(pCfg, "SleepButtonGpio", 4);
659
660	vrc = RTFdtNodeAdd(hFdt, "gpio-keys"); VRC();
661	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "gpio-keys"); VRC();
662
663	vrc = RTFdtNodeAdd(hFdt, "poweroff"); VRC();
664	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "gpios", 3, idPHandleGpio, 3, 0); VRC();
665	vrc = RTFdtNodePropertyAddU32( hFdt, "linux,code", 0x74); VRC();
666	vrc = RTFdtNodePropertyAddString( hFdt, "label", "GPIO Key Poweroff"); VRC();
667	vrc = RTFdtNodeFinalize(hFdt); VRC();
668
669	vrc = RTFdtNodeAdd(hFdt, "suspend"); VRC();
670	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "gpios", 3, idPHandleGpio, 4, 0); VRC();
671	vrc = RTFdtNodePropertyAddU32( hFdt, "linux,code", 0xcd); VRC();
672	vrc = RTFdtNodePropertyAddString( hFdt, "label", "GPIO Key Suspend"); VRC();
673	vrc = RTFdtNodeFinalize(hFdt);
674
675	vrc = RTFdtNodeFinalize(hFdt); VRC();
676
677	hrc = pResMgr->assignInterrupts("pci-generic-ecam", 4 /cInterrupts/, &iIrq); H();
678	uint32_t aPinIrqs[] = { iIrq, iIrq + 1, iIrq + 2, iIrq + 3 };
679	RTGCPHYS GCPhysPciMmioEcam, GCPhysPciMmio, GCPhysPciMmio32;
680	RTGCPHYS cbPciMmioEcam, cbPciMmio, cbPciMmio32;
681	hrc = pResMgr->assignMmioRegionAligned("pci-pio", _64K, _64K, &GCPhysMmioStart, &cbMmio); H();
682	hrc = pResMgr->assignMmioRegion( "pci-ecam", 16 * _1M, &GCPhysPciMmioEcam, &cbPciMmioEcam); H();
683	hrc = pResMgr->assignMmioRegion( "pci-mmio", _2G, &GCPhysPciMmio, &cbPciMmio); H();
684	hrc = pResMgr->assignMmio32Region( "pci-mmio32", _1G - VBOXPLATFORMARMV8_PHYS_ADDR - _1M, &GCPhysPciMmio32, &cbPciMmio32); H();
685
686	InsertConfigNode(pDevices, "pci-generic-ecam", &pDev);
687	InsertConfigNode(pDev, "0", &pInst);
688	InsertConfigNode(pInst, "Config", &pCfg);
689	InsertConfigInteger(pCfg, "MmioEcamBase", GCPhysPciMmioEcam);
690	InsertConfigInteger(pCfg, "MmioEcamLength", cbPciMmioEcam);
691	InsertConfigInteger(pCfg, "MmioPioBase", GCPhysMmioStart);
692	InsertConfigInteger(pCfg, "MmioPioSize", cbMmio);
693	InsertConfigInteger(pCfg, "IntPinA", aPinIrqs[0]);
694	InsertConfigInteger(pCfg, "IntPinB", aPinIrqs[1]);
695	InsertConfigInteger(pCfg, "IntPinC", aPinIrqs[2]);
696	InsertConfigInteger(pCfg, "IntPinD", aPinIrqs[3]);
697	vrc = RTFdtNodeAddF(hFdt, "pcie@%RGp", GCPhysPciMmio); VRC();
698	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupt-map-mask", 4, 0xf800, 0, 0, 7); VRC();
699
700	uint32_t aIrqCells[32 * 4 * 10]; RT_ZERO(aIrqCells); /* Maximum of 32 devices on the root bus, each supporting 4 interrupts (INTA# ... INTD#). */
701	uint32_t *pau32IrqCell = &aIrqCells[0];
702	uint32_t iIrqPinSwizzle = 0;
703
704	for (uint32_t i = 0; i < 32; i++)
705	{
706	for (uint32_t iIrqPin = 0; iIrqPin < 4; iIrqPin++)
707	{
708	pau32IrqCell[0] = i << 11; /* The dev part, composed as dev.fn. */
709	pau32IrqCell[1] = 0;
710	pau32IrqCell[2] = 0;
711	pau32IrqCell[3] = iIrqPin + 1;
712	pau32IrqCell[4] = idPHandleIntCtrl;
713	pau32IrqCell[5] = 0;
714	pau32IrqCell[6] = 0;
715	pau32IrqCell[7] = 0;
716	pau32IrqCell[8] = aPinIrqs[(iIrqPinSwizzle + iIrqPin) % RT_ELEMENTS(aPinIrqs)];
717	pau32IrqCell[9] = 0x04;
718	pau32IrqCell += 10;
719	}
720
721	iIrqPinSwizzle++;
722	}
723
724	vrc = RTFdtNodePropertyAddCellsU32AsArray(hFdt, "interrupt-map", RT_ELEMENTS(aIrqCells), &aIrqCells[0]);
725	vrc = RTFdtNodePropertyAddU32( hFdt, "#interrupt-cells", 1); VRC();
726	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "ranges", 21,
727	0x1000000, 0, 0,
728	GCPhysMmioStart >> 32, GCPhysMmioStart, cbMmio >> 32, cbMmio,
729	0x2000000, GCPhysPciMmio32 >> 32, GCPhysPciMmio32, GCPhysPciMmio32 >> 32, GCPhysPciMmio32,
730	cbPciMmio32 >> 32, cbPciMmio32,
731	0x3000000, GCPhysPciMmio >> 32, GCPhysPciMmio, GCPhysPciMmio >> 32, GCPhysPciMmio,
732	cbPciMmio >> 32, cbPciMmio); VRC();
733	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysPciMmioEcam, cbPciMmioEcam); VRC();
734	/** @todo msi-map */
735	vrc = RTFdtNodePropertyAddEmpty( hFdt, "dma-coherent"); VRC();
736	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "bus-range", 2, 0, 0xf); VRC();
737	vrc = RTFdtNodePropertyAddU32( hFdt, "linux,pci-domain", 0); VRC();
738	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
739	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 3); VRC();
740	vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "pci"); VRC();
741	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "pci-host-ecam-generic"); VRC();
742	vrc = RTFdtNodeFinalize(hFdt); VRC();
743
744	if (pSysTblsBldAcpi)
745	{
746	vrc = pSysTblsBldAcpi->configurePcieRootBus("pci-generic-ecam", aPinIrqs, GCPhysMmioStart, GCPhysPciMmioEcam,
747	cbPciMmioEcam, GCPhysMmioStart, cbMmio, GCPhysPciMmio32, cbPciMmio32);
748	VRC();
749	}
750
751	/*
752	* VMSVGA compliant graphics controller.
753	*/
754	if ( enmGraphicsController != GraphicsControllerType_QemuRamFB
755	&& enmGraphicsController != GraphicsControllerType_Null)
756	{
757	vrc = i_configGraphicsController(pDevices, enmGraphicsController, pBusMgr, pMachine,
758	pGraphicsAdapter, firmwareSettings,
759	true /fForceVmSvga3/, false /fExposeLegacyVga/); VRC();
760	}
761
762	/*
763	* The USB Controllers and input devices.
764	*/
765	#if 0 /** @todo Make us of this and disallow PS/2 for ARM VMs for now. */
766	KeyboardHIDType_T aKbdHID;
767	hrc = pMachine->COMGETTER(KeyboardHIDType)(&aKbdHID); H();
768	#endif
769
770	PointingHIDType_T aPointingHID;
771	hrc = pMachine->COMGETTER(PointingHIDType)(&aPointingHID); H();
772
773	PCFGMNODE pUsbDevices = NULL;
774	vrc = i_configUsb(pMachine, pBusMgr, pRoot, pDevices, KeyboardHIDType_USBKeyboard, aPointingHID, &pUsbDevices);
775
776	/*
777	* Storage controllers.
778	*/
779	bool fFdcEnabled = false;
780	vrc = i_configStorageCtrls(pMachine, pBusMgr, pVMM, pUVM,
781	pDevices, pUsbDevices, NULL /pBiosCfg/, &fFdcEnabled); VRC();
782
783	/*
784	* Network adapters
785	*/
786	std::list<BootNic> llBootNics;
787	vrc = i_configNetworkCtrls(pMachine, pPlatformProperties, chipsetType, pBusMgr,
788	pVMM, pUVM, pDevices, llBootNics); VRC();
789
790	/*
791	* The VMM device.
792	*/
793	vrc = i_configVmmDev(pMachine, pBusMgr, pDevices, true /fMmioReq/); VRC();
794
795	/*
796	* Audio configuration.
797	*/
798	bool fAudioEnabled = false;
799	vrc = i_configAudioCtrl(virtualBox, pMachine, pBusMgr, pDevices,
800	false /fOsXGuest/, &fAudioEnabled); VRC();
801	}
802	catch (ConfigError &x)
803	{
804	RTFdtDestroy(hFdt);
805
806	// InsertConfig threw something:
807	pVMM->pfnVMR3SetError(pUVM, x.m_vrc, RT_SRC_POS, "Caught ConfigError: %Rrc - %s", x.m_vrc, x.what());
808	return x.m_vrc;
809	}
810	catch (HRESULT hrcXcpt)
811	{
812	RTFdtDestroy(hFdt);
813	AssertLogRelMsgFailedReturn(("hrc=%Rhrc\n", hrcXcpt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR);
814	}
815
816	#ifdef VBOX_WITH_EXTPACK
817	/*
818	* Call the extension pack hooks if everything went well thus far.
819	*/
820	if (RT_SUCCESS(vrc))
821	{
822	pAlock->release();
823	vrc = mptrExtPackManager->i_callAllVmConfigureVmmHooks(this, pVM, pVMM);
824	pAlock->acquire();
825	}
826	#endif
827
828	#if 0
829	vrc = RTFdtNodeAdd(hFdt, "chosen"); VRC();
830	vrc = RTFdtNodePropertyAddString( hFdt, "stdout-path", "pl011@9000000"); VRC();
831	vrc = RTFdtNodePropertyAddString( hFdt, "stdin-path", "pl011@9000000"); VRC();
832	vrc = RTFdtNodeFinalize(hFdt);
833	#endif
834
835	/* Finalize the FDT and add it to the resource store. */
836	vrc = RTFdtFinalize(hFdt);
837	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
838
839	RTVFSFILE hVfsFileDesc = NIL_RTVFSFILE;
840	vrc = RTVfsMemFileCreate(NIL_RTVFSIOSTREAM, 0 /cbEstimate/, &hVfsFileDesc);
841	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
842	RTVFSIOSTREAM hVfsIosDesc = RTVfsFileToIoStream(hVfsFileDesc);
843	AssertRelease(hVfsIosDesc != NIL_RTVFSIOSTREAM);
844
845	/* Initialize the VBox platform descriptor. */
846	VBOXPLATFORMARMV8 ArmV8Platform; RT_ZERO(ArmV8Platform);
847
848	/* Make room for the descriptor at the beginning. */
849	vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, sizeof(ArmV8Platform));
850	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
851
852	vrc = RTFdtDumpToVfsIoStrm(hFdt, RTFDTTYPE_DTB, 0 /fFlags/, hVfsIosDesc, NULL /pErrInfo/);
853	uint64_t cbFdt = 0;
854	if (RT_SUCCESS(vrc))
855	{
856	vrc = RTVfsFileQuerySize(hVfsFileDesc, &cbFdt);
857	cbFdt -= sizeof(ArmV8Platform);
858	}
859	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
860
861	vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, (RTFOFF)(RT_ALIGN_64(cbFdt, _64K) - cbFdt));
862	AssertRCReturn(vrc, vrc);
863
864	RTGCPHYS GCPhysMmioStart;
865	RTGCPHYS cbMmio;
866	hrc = pResMgr->queryMmioRegion(&GCPhysMmioStart, &cbMmio);
867	Assert(SUCCEEDED(hrc));
868
869	RTGCPHYS GCPhysMmio32Start;
870	RTGCPHYS cbMmio32;
871	hrc = pResMgr->queryMmio32Region(&GCPhysMmio32Start, &cbMmio32);
872	Assert(SUCCEEDED(hrc));
873
874	RTGCPHYS GCPhysXsdp = NIL_RTGCPHYS;
875	size_t cbAcpiXsdp = 0;
876	size_t cbAcpi = 0;
877	if (pSysTblsBldAcpi)
878	{
879	vrc = pSysTblsBldAcpi->finishTables(VBOXPLATFORMARMV8_PHYS_ADDR + sizeof(ArmV8Platform) + RT_ALIGN_64(cbFdt, _64K),
880	hVfsIosDesc, &GCPhysXsdp, &cbAcpiXsdp, &cbAcpi);
881	AssertRCReturn(vrc, vrc);
882	Assert(GCPhysXsdp > VBOXPLATFORMARMV8_PHYS_ADDR);
883
884	/* Dump the ACPI table for debugging purposes if requested. */
885	Bstr SysTblsDumpVal;
886	hrc = mMachine->GetExtraData(Bstr("VBoxInternal2/DumpSysTables").raw(),
887	SysTblsDumpVal.asOutParam());
888	if ( hrc == S_OK
889	&& SysTblsDumpVal.isNotEmpty())
890	{
891	vrc = pSysTblsBldAcpi->dumpTables(Utf8Str(SysTblsDumpVal).c_str());
892	AssertRCReturn(vrc, vrc);
893	}
894
895	delete pSysTblsBldAcpi;
896
897	vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, (RTFOFF)(RT_ALIGN_64(cbAcpi, _64K) - cbAcpi));
898	AssertRCReturn(vrc, vrc);
899	}
900
901	ArmV8Platform.u32Magic = VBOXPLATFORMARMV8_MAGIC;
902	ArmV8Platform.u32Version = VBOXPLATFORMARMV8_VERSION;
903	ArmV8Platform.cbDesc = sizeof(ArmV8Platform);
904	ArmV8Platform.fFlags = 0;
905	ArmV8Platform.u64PhysAddrRamBase = GCPhysRam;
906	ArmV8Platform.cbRamBase = cbRam;
907	ArmV8Platform.i64OffFdt = sizeof(ArmV8Platform);
908	ArmV8Platform.cbFdt = RT_ALIGN_64(cbFdt, _64K);
909	if (cbAcpi)
910	{
911	ArmV8Platform.i64OffAcpi = sizeof(ArmV8Platform) + RT_ALIGN_64(cbFdt, _64K);
912	ArmV8Platform.cbAcpi = RT_ALIGN_64(cbAcpi, _64K);
913	ArmV8Platform.i64OffAcpiXsdp = GCPhysXsdp - VBOXPLATFORMARMV8_PHYS_ADDR;
914	ArmV8Platform.cbAcpiXsdp = cbAcpiXsdp;
915	}
916	ArmV8Platform.i64OffUefiRom = -128 * _1M;
917	ArmV8Platform.cbUefiRom = _64M;
918	ArmV8Platform.i64OffMmio = GCPhysMmioStart - _128M;
919	ArmV8Platform.cbMmio = cbMmio;
920	ArmV8Platform.i64OffMmio32 = GCPhysMmio32Start - _128M;
921	ArmV8Platform.cbMmio32 = cbMmio32;
922
923	/* Add the VBox platform descriptor to the resource store. */
924	vrc = RTVfsIoStrmWriteAt(hVfsIosDesc, 0, &ArmV8Platform, sizeof(ArmV8Platform), true /fBlocking/, NULL /pcbWritten/);
925	RTVfsIoStrmRelease(hVfsIosDesc);
926	vrc = mptrResourceStore->i_addItem("resources", "VBoxArmV8Desc", hVfsFileDesc);
927	RTVfsFileRelease(hVfsFileDesc);
928	AssertRCReturn(vrc, vrc);
929
930	/* Dump the DTB for debugging purposes if requested. */
931	Bstr DtbDumpVal;
932	hrc = mMachine->GetExtraData(Bstr("VBoxInternal2/DumpDtb").raw(),
933	DtbDumpVal.asOutParam());
934	if ( hrc == S_OK
935	&& DtbDumpVal.isNotEmpty())
936	{
937	vrc = RTFdtDumpToFile(hFdt, RTFDTTYPE_DTB, 0 /fFlags/, Utf8Str(DtbDumpVal).c_str(), NULL /pErrInfo/);
938	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
939	}
940
941	delete pResMgr; /* Delete the address/interrupt assignment manager. */
942
943	/*
944	* Apply the CFGM overlay.
945	*/
946	if (RT_SUCCESS(vrc))
947	vrc = i_configCfgmOverlay(pRoot, virtualBox, pMachine);
948
949	/*
950	* Dump all extradata API settings tweaks, both global and per VM.
951	*/
952	if (RT_SUCCESS(vrc))
953	vrc = i_configDumpAPISettingsTweaks(virtualBox, pMachine);
954
955	#undef H
956
957	pAlock->release(); /* Avoid triggering the lock order inversion check. */
958
959	/*
960	* Register VM state change handler.
961	*/
962	int vrc2 = pVMM->pfnVMR3AtStateRegister(pUVM, Console::i_vmstateChangeCallback, this);
963	AssertRC(vrc2);
964	if (RT_SUCCESS(vrc))
965	vrc = vrc2;
966
967	/*
968	* Register VM runtime error handler.
969	*/
970	vrc2 = pVMM->pfnVMR3AtRuntimeErrorRegister(pUVM, Console::i_atVMRuntimeErrorCallback, this);
971	AssertRC(vrc2);
972	if (RT_SUCCESS(vrc))
973	vrc = vrc2;
974
975	pAlock->acquire();
976
977	LogFlowFunc(("vrc = %Rrc\n", vrc));
978	LogFlowFuncLeave();
979
980	return vrc;
981	}
982	#endif /* !VBOX_WITH_VIRT_ARMV8 */
983

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source: vbox/trunk/src/VBox/Main/src-client/ConsoleImplConfigArmV8.cpp@ 106384

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