ConsoleImplConfigArmV8.cpp@ 106361

Last change on this file since 106361 was 106361, checked in by vboxsync, 6 weeks ago
Main/ConsoleImplConfigArmV8.cpp: Generate ACPI tables if ACPI is enabled for the VM, bugref:10733 [scm]
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1	/* $Id: ConsoleImplConfigArmV8.cpp 106361 2024-10-16 13:01:54Z vboxsync $ */
2	/** @file
3	* VBox Console COM Class implementation - VM Configuration Bits for ARMv8.
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_MAIN_CONSOLE
33	#include "LoggingNew.h"
34
35	#include "ConsoleImpl.h"
36	#include "ResourceStoreImpl.h"
37	#include "Global.h"
38	#include "VMMDev.h"
39
40	// generated header
41	#include "SchemaDefs.h"
42
43	#include "AutoCaller.h"
44
45	#include <iprt/buildconfig.h>
46	#include <iprt/ctype.h>
47	#include <iprt/dir.h>
48	#include <iprt/fdt.h>
49	#include <iprt/file.h>
50	#include <iprt/param.h>
51	#include <iprt/path.h>
52	#include <iprt/string.h>
53	#include <iprt/system.h>
54	#if 0 /* enable to play with lots of memory. */
55	# include <iprt/env.h>
56	#endif
57	#include <iprt/stream.h>
58
59	#include <iprt/formats/arm-psci.h>
60
61	#include <VBox/vmm/vmmr3vtable.h>
62	#include <VBox/vmm/vmapi.h>
63	#include <VBox/err.h>
64	#include <VBox/param.h>
65	#include <VBox/version.h>
66	#include <VBox/platforms/vbox-armv8.h>
67
68	#include "BusAssignmentManager.h"
69	#include "ResourceAssignmentManager.h"
70	#include "SystemTableBuilder.h"
71	#ifdef VBOX_WITH_EXTPACK
72	# include "ExtPackManagerImpl.h"
73	#endif
74
75
76	/*********************************************************************************************************************************
77	* Internal Functions *
78	*********************************************************************************************************************************/
79
80	/* Darwin compile kludge */
81	#undef PVM
82
83	#ifdef VBOX_WITH_VIRT_ARMV8
84	/**
85	* Worker for configConstructor.
86	*
87	* @return VBox status code.
88	* @param pUVM The user mode VM handle.
89	* @param pVM The cross context VM handle.
90	* @param pVMM The VMM vtable.
91	* @param pAlock The automatic lock instance. This is for when we have
92	* to leave it in order to avoid deadlocks (ext packs and
93	* more).
94	*/
95	int Console::i_configConstructorArmV8(PUVM pUVM, PVM pVM, PCVMMR3VTABLE pVMM, AutoWriteLock *pAlock)
96	{
97	RT_NOREF(pVM /* when everything is disabled */);
98	ComPtr<IMachine> pMachine = i_machine();
99
100	HRESULT hrc;
101	Utf8Str strTmp;
102	Bstr bstr;
103
104	RTFDT hFdt = NIL_RTFDT;
105	int vrc = RTFdtCreateEmpty(&hFdt);
106	AssertRCReturn(vrc, vrc);
107
108	#define H() AssertLogRelMsgReturnStmt(!FAILED(hrc), ("hrc=%Rhrc\n", hrc), RTFdtDestroy(hFdt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR)
109	#define VRC() AssertLogRelMsgReturnStmt(RT_SUCCESS(vrc), ("vrc=%Rrc\n", vrc), RTFdtDestroy(hFdt), vrc)
110
111	/*
112	* Get necessary objects and frequently used parameters.
113	*/
114	ComPtr<IVirtualBox> virtualBox;
115	hrc = pMachine->COMGETTER(Parent)(virtualBox.asOutParam()); H();
116
117	ComPtr<IHost> host;
118	hrc = virtualBox->COMGETTER(Host)(host.asOutParam()); H();
119
120	PlatformArchitecture_T platformArchHost;
121	hrc = host->COMGETTER(Architecture)(&platformArchHost); H();
122
123	ComPtr<ISystemProperties> systemProperties;
124	hrc = virtualBox->COMGETTER(SystemProperties)(systemProperties.asOutParam()); H();
125
126	ComPtr<IFirmwareSettings> firmwareSettings;
127	hrc = pMachine->COMGETTER(FirmwareSettings)(firmwareSettings.asOutParam()); H();
128
129	ComPtr<INvramStore> nvramStore;
130	hrc = pMachine->COMGETTER(NonVolatileStore)(nvramStore.asOutParam()); H();
131
132	hrc = pMachine->COMGETTER(HardwareUUID)(bstr.asOutParam()); H();
133	RTUUID HardwareUuid;
134	vrc = RTUuidFromUtf16(&HardwareUuid, bstr.raw());
135	AssertRCReturn(vrc, vrc);
136
137	ULONG cRamMBs;
138	hrc = pMachine->COMGETTER(MemorySize)(&cRamMBs); H();
139	uint64_t const cbRam = cRamMBs * (uint64_t)_1M;
140
141	ComPtr<IPlatform> platform;
142	hrc = pMachine->COMGETTER(Platform)(platform.asOutParam()); H();
143
144	/* Note: Should be guarded by VBOX_WITH_VIRT_ARMV8, but we check this anyway here. */
145	#if 1 /* For now we only support running ARM VMs on ARM hosts. */
146	PlatformArchitecture_T platformArchMachine;
147	hrc = platform->COMGETTER(Architecture)(&platformArchMachine); H();
148	if (platformArchMachine != platformArchHost)
149	return pVMM->pfnVMR3SetError(pUVM, VERR_PLATFORM_ARCH_NOT_SUPPORTED, RT_SRC_POS,
150	N_("VM platform architecture (%s) not supported on this host (%s)."),
151	Global::stringifyPlatformArchitecture(platformArchMachine),
152	Global::stringifyPlatformArchitecture(platformArchHost));
153	#endif
154
155	ComPtr<IPlatformProperties> pPlatformProperties;
156	hrc = platform->COMGETTER(Properties)(pPlatformProperties.asOutParam()); H();
157
158	ChipsetType_T chipsetType;
159	hrc = platform->COMGETTER(ChipsetType)(&chipsetType); H();
160
161	ULONG cCpus = 1;
162	hrc = pMachine->COMGETTER(CPUCount)(&cCpus); H();
163	Assert(cCpus);
164
165	ULONG ulCpuExecutionCap = 100;
166	hrc = pMachine->COMGETTER(CPUExecutionCap)(&ulCpuExecutionCap); H();
167
168	VMExecutionEngine_T enmExecEngine = VMExecutionEngine_NotSet;
169	hrc = pMachine->COMGETTER(VMExecutionEngine)(&enmExecEngine); H();
170
171	if ( enmExecEngine != VMExecutionEngine_Default
172	&& enmExecEngine != VMExecutionEngine_NativeApi)
173	{
174	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
175	N_("The ARM backend doesn't support any other execution engine than 'default' or 'native-api' right now."));
176	}
177
178	LogRel(("Guest architecture: ARM\n"));
179
180	Bstr osTypeId;
181	hrc = pMachine->COMGETTER(OSTypeId)(osTypeId.asOutParam()); H();
182	LogRel(("Guest OS type: '%s'\n", Utf8Str(osTypeId).c_str()));
183
184	BusAssignmentManager *pBusMgr = mBusMgr = BusAssignmentManager::createInstance(pVMM, chipsetType, IommuType_None);
185	ResourceAssignmentManager *pResMgr = ResourceAssignmentManager::createInstance(pVMM, chipsetType, IommuType_None,
186	RT_MAX(_1G + cbRam, _4G), /GCPhysMmio/
187	_1G, /GCPhysRam/
188	VBOXPLATFORMARMV8_PHYS_ADDR + _1M, /GCPhysMmio32Start/
189	_1G - (VBOXPLATFORMARMV8_PHYS_ADDR + _1M), /cbMmio32/
190	32 /cInterrupts/);
191	SystemTableBuilder *pSysTblsBldAcpi = NULL;
192
193	/*
194	* ACPI
195	*/
196	BOOL fACPI;
197	hrc = firmwareSettings->COMGETTER(ACPIEnabled)(&fACPI); H();
198	if (fACPI)
199	pSysTblsBldAcpi = SystemTableBuilder::createInstance(kSystemTableType_Acpi);
200
201
202	/*
203	* Get root node first.
204	* This is the only node in the tree.
205	*/
206	PCFGMNODE pRoot = pVMM->pfnCFGMR3GetRootU(pUVM);
207	Assert(pRoot);
208
209	RTGCPHYS GCPhysRam = NIL_RTGCPHYS;
210
211	// catching throws from InsertConfigString and friends.
212	try
213	{
214
215	/*
216	* Set the root (and VMM) level values.
217	*/
218	hrc = pMachine->COMGETTER(Name)(bstr.asOutParam()); H();
219	InsertConfigString(pRoot, "Name", bstr);
220	InsertConfigBytes(pRoot, "UUID", &HardwareUuid, sizeof(HardwareUuid));
221	InsertConfigInteger(pRoot, "NumCPUs", cCpus);
222	InsertConfigInteger(pRoot, "CpuExecutionCap", ulCpuExecutionCap);
223	InsertConfigInteger(pRoot, "TimerMillies", 10);
224
225	/*
226	* NEM
227	*/
228	PCFGMNODE pNEM;
229	InsertConfigNode(pRoot, "NEM", &pNEM);
230
231	uint32_t idPHandleIntCtrl = RTFdtPHandleAllocate(hFdt);
232	Assert(idPHandleIntCtrl != UINT32_MAX);
233	uint32_t idPHandleIntCtrlMsi = RTFdtPHandleAllocate(hFdt);
234	Assert(idPHandleIntCtrlMsi != UINT32_MAX); RT_NOREF(idPHandleIntCtrlMsi);
235	uint32_t idPHandleAbpPClk = RTFdtPHandleAllocate(hFdt);
236	Assert(idPHandleAbpPClk != UINT32_MAX);
237	uint32_t idPHandleGpio = RTFdtPHandleAllocate(hFdt);
238	Assert(idPHandleGpio != UINT32_MAX);
239
240	uint32_t aidPHandleCpus[VMM_MAX_CPU_COUNT];
241	for (uint32_t i = 0; i < cCpus; i++)
242	{
243	aidPHandleCpus[i] = RTFdtPHandleAllocate(hFdt);
244	Assert(aidPHandleCpus[i] != UINT32_MAX);
245	}
246
247	vrc = RTFdtNodePropertyAddU32( hFdt, "interrupt-parent", idPHandleIntCtrl); VRC();
248	vrc = RTFdtNodePropertyAddString(hFdt, "model", "linux,dummy-virt"); VRC();
249	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
250	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 2); VRC();
251	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "linux,dummy-virt"); VRC();
252
253	/* Configure the Power State Coordination Interface. */
254	vrc = RTFdtNodeAdd(hFdt, "psci"); VRC();
255	vrc = RTFdtNodePropertyAddU32( hFdt, "migrate", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_MIGRATE)); VRC();
256	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_on", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_ON)); VRC();
257	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_off", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_OFF)); VRC();
258	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_suspend", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_SUSPEND)); VRC();
259	vrc = RTFdtNodePropertyAddString(hFdt, "method", "hvc"); VRC();
260	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 3,
261	"arm,psci-1.0", "arm,psci-0.2", "arm,psci"); VRC();
262	vrc = RTFdtNodeFinalize(hFdt); VRC();
263
264	/* Configure the timer and clock. */
265	InsertConfigInteger(pNEM, "VTimerInterrupt", 0xb);
266	vrc = RTFdtNodeAdd(hFdt, "timer"); VRC();
267	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 12,
268	0x01, 0x0d, 0x104,
269	0x01, 0x0e, 0x104,
270	0x01, 0x0b, 0x104,
271	0x01, 0x0a, 0x104); VRC();
272	vrc = RTFdtNodePropertyAddEmpty( hFdt, "always-on"); VRC();
273	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,armv8-timer"); VRC();
274	vrc = RTFdtNodeFinalize(hFdt);
275
276	vrc = RTFdtNodeAdd(hFdt, "apb-clk"); VRC();
277	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleAbpPClk); VRC();
278	vrc = RTFdtNodePropertyAddString( hFdt, "clock-output-names", "clk24mhz"); VRC();
279	vrc = RTFdtNodePropertyAddU32( hFdt, "clock-frequency", 24 * 1000 * 1000); VRC();
280	vrc = RTFdtNodePropertyAddU32( hFdt, "#clock-cells", 0); VRC();
281	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "fixed-clock"); VRC();
282	vrc = RTFdtNodeFinalize(hFdt);
283
284	if (pSysTblsBldAcpi)
285	{
286	vrc = pSysTblsBldAcpi->configureClock();
287	VRC();
288	}
289
290	/*
291	* MM values.
292	*/
293	PCFGMNODE pMM;
294	InsertConfigNode(pRoot, "MM", &pMM);
295
296	/*
297	* Memory setup.
298	*/
299	PCFGMNODE pMem = NULL;
300	InsertConfigNode(pMM, "MemRegions", &pMem);
301
302	hrc = pResMgr->assignRamRegion("Conventional", cbRam, &GCPhysRam); H();
303
304	PCFGMNODE pMemRegion = NULL;
305	InsertConfigNode(pMem, "Conventional", &pMemRegion);
306	InsertConfigInteger(pMemRegion, "GCPhysStart", GCPhysRam);
307	InsertConfigInteger(pMemRegion, "Size", cbRam);
308
309	vrc = RTFdtNodeAddF(hFdt, "memory@%RGp", GCPhysRam); VRC();
310	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysRam, cbRam); VRC();
311	vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "memory"); VRC();
312	vrc = RTFdtNodeFinalize(hFdt); VRC();
313
314	if (pSysTblsBldAcpi)
315	{
316	vrc = pSysTblsBldAcpi->addMemory(GCPhysRam, cbRam);
317	VRC();
318	}
319
320	/* Configure the CPUs in the system, only one socket and cluster at the moment. */
321	vrc = RTFdtNodeAdd(hFdt, "cpus"); VRC();
322	vrc = RTFdtNodePropertyAddU32(hFdt, "#size-cells", 0); VRC();
323	vrc = RTFdtNodePropertyAddU32(hFdt, "#address-cells", 1); VRC();
324
325	vrc = RTFdtNodeAdd(hFdt, "socket0"); VRC();
326	vrc = RTFdtNodeAdd(hFdt, "cluster0"); VRC();
327
328	for (uint32_t i = 0; i < cCpus; i++)
329	{
330	vrc = RTFdtNodeAddF(hFdt, "core%u", i); VRC();
331	vrc = RTFdtNodePropertyAddU32(hFdt, "cpu", aidPHandleCpus[i]); VRC();
332	vrc = RTFdtNodeFinalize(hFdt); VRC();
333	}
334
335	vrc = RTFdtNodeFinalize(hFdt); VRC();
336	vrc = RTFdtNodeFinalize(hFdt); VRC();
337
338	for (uint32_t i = 0; i < cCpus; i++)
339	{
340	vrc = RTFdtNodeAddF(hFdt, "cpu@%u", i); VRC();
341	vrc = RTFdtNodePropertyAddU32(hFdt, "phandle", aidPHandleCpus[i]); VRC();
342	vrc = RTFdtNodePropertyAddU32(hFdt, "reg", i); VRC();
343	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "arm,cortex-a15"); VRC();
344	vrc = RTFdtNodePropertyAddString(hFdt, "device_type", "cpu"); VRC();
345	if (cCpus > 1)
346	{
347	vrc = RTFdtNodePropertyAddString(hFdt, "enable-method", "psci"); VRC();
348	}
349	vrc = RTFdtNodeFinalize(hFdt); VRC();
350
351	if (pSysTblsBldAcpi)
352	{
353	vrc = pSysTblsBldAcpi->addCpu(i);
354	VRC();
355	}
356	}
357
358	vrc = RTFdtNodeFinalize(hFdt); VRC();
359
360
361	/*
362	* CPUM values.
363	*/
364	PCFGMNODE pCpum;
365	InsertConfigNode(pRoot, "CPUM", &pCpum);
366
367
368	/*
369	* PDM config.
370	* Load drivers in VBoxC.[so\|dll]
371	*/
372	vrc = i_configPdm(pMachine, pVMM, pUVM, pRoot); VRC();
373
374
375	/*
376	* VGA.
377	*/
378	ComPtr<IGraphicsAdapter> pGraphicsAdapter;
379	hrc = pMachine->COMGETTER(GraphicsAdapter)(pGraphicsAdapter.asOutParam()); H();
380	GraphicsControllerType_T enmGraphicsController;
381	hrc = pGraphicsAdapter->COMGETTER(GraphicsControllerType)(&enmGraphicsController); H();
382
383	/*
384	* Devices
385	*/
386	PCFGMNODE pDevices = NULL; /* /Devices */
387	PCFGMNODE pDev = NULL; /* /Devices/Dev/ */
388	PCFGMNODE pInst = NULL; /* /Devices/Dev/0/ */
389	PCFGMNODE pCfg = NULL; /* /Devices/Dev/.../Config/ */
390	PCFGMNODE pLunL0 = NULL; /* /Devices/Dev/0/LUN#0/ */
391
392	InsertConfigNode(pRoot, "Devices", &pDevices);
393
394	InsertConfigNode(pDevices, "pci-generic-ecam-bridge", NULL);
395
396	InsertConfigNode(pDevices, "platform", &pDev);
397	InsertConfigNode(pDev, "0", &pInst);
398	InsertConfigNode(pInst, "Config", &pCfg);
399	InsertConfigNode(pInst, "LUN#0", &pLunL0);
400	InsertConfigString(pLunL0, "Driver", "ResourceStore");
401
402	/* Add the resources. */
403	PCFGMNODE pResources = NULL; /* /Devices/platform/Config/Resources */
404	PCFGMNODE pRes = NULL; /* /Devices/platform/Config/Resources/<Resource> */
405	InsertConfigString(pCfg, "ResourceNamespace", "resources");
406	InsertConfigNode(pCfg, "Resources", &pResources);
407	InsertConfigNode(pResources, "EfiRom", &pRes);
408	InsertConfigInteger(pRes, "RegisterAsRom", 1);
409	InsertConfigInteger(pRes, "GCPhysLoadAddress", 0);
410
411	/** @todo r=aeichner 32-bit guests and query the firmware type from VBoxSVC. */
412	/*
413	* Firmware.
414	*/
415	FirmwareType_T eFwType = FirmwareType_EFI64;
416	#ifdef VBOX_WITH_EFI_IN_DD2
417	const char *pszEfiRomFile = eFwType == FirmwareType_EFIDUAL ? "<INVALID>"
418	: eFwType == FirmwareType_EFI32 ? "VBoxEFIAArch32.fd"
419	: "VBoxEFIAArch64.fd";
420	const char *pszKey = "ResourceId";
421	#else
422	Utf8Str efiRomFile;
423	vrc = findEfiRom(virtualBox, PlatformArchitecture_ARM, eFwType, &efiRomFile);
424	AssertRCReturn(vrc, vrc);
425	const char *pszEfiRomFile = efiRomFile.c_str();
426	const char *pszKey = "Filename";
427	#endif
428	InsertConfigString(pRes, pszKey, pszEfiRomFile);
429
430	InsertConfigNode(pResources, "ArmV8Desc", &pRes);
431	InsertConfigInteger(pRes, "RegisterAsRom", 1);
432	InsertConfigInteger(pRes, "GCPhysLoadAddress", VBOXPLATFORMARMV8_PHYS_ADDR);
433	InsertConfigString(pRes, "ResourceId", "VBoxArmV8Desc");
434
435	/*
436	* Configure the interrupt controller.
437	*/
438	RTGCPHYS GCPhysIntcDist;
439	RTGCPHYS GCPhysIntcReDist;
440	RTGCPHYS cbMmioIntcDist;
441	RTGCPHYS cbMmioIntcReDist;
442
443	/* Each vCPU needs on re-distributor, this would allow for up to 256 vCPUs in the future. */
444	hrc = pResMgr->assignMmioRegion("gic", 256 * _64K, &GCPhysIntcReDist, &cbMmioIntcReDist); H();
445	hrc = pResMgr->assignMmioRegion("gic", _64K, &GCPhysIntcDist, &cbMmioIntcDist); H();
446
447	#ifndef RT_OS_LINUX
448	InsertConfigNode(pDevices, "gic", &pDev);
449	#else
450	/* On Linux we default to the KVM in-kernel GIC for now. */
451	InsertConfigNode(pDevices, "gic-nem", &pDev);
452	#endif
453	InsertConfigNode(pDev, "0", &pInst);
454	InsertConfigInteger(pInst, "Trusted", 1);
455	InsertConfigNode(pInst, "Config", &pCfg);
456	InsertConfigInteger(pCfg, "DistributorMmioBase", GCPhysIntcDist);
457	InsertConfigInteger(pCfg, "RedistributorMmioBase", GCPhysIntcReDist);
458
459	vrc = RTFdtNodeAddF(hFdt, "intc@%RGp", GCPhysIntcDist); VRC();
460	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleIntCtrl); VRC();
461	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 4,
462	GCPhysIntcDist, cbMmioIntcDist, /* Distributor */
463	GCPhysIntcReDist, cbMmioIntcReDist); /* Re-Distributor */ VRC();
464	vrc = RTFdtNodePropertyAddU32( hFdt, "#redistributor-regions", 1); VRC();
465	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,gic-v3"); VRC();
466	vrc = RTFdtNodePropertyAddEmpty( hFdt, "ranges"); VRC();
467	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
468	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 2); VRC();
469	vrc = RTFdtNodePropertyAddEmpty( hFdt, "interrupt-controller"); VRC();
470	vrc = RTFdtNodePropertyAddU32( hFdt, "#interrupt-cells", 3); VRC();
471
472	if (pSysTblsBldAcpi)
473	{
474	vrc = pSysTblsBldAcpi->configureGic(cCpus, GCPhysIntcDist, cbMmioIntcDist,
475	GCPhysIntcReDist, cbMmioIntcReDist);
476	VRC();
477	}
478
479	#if 0
480	vrc = RTFdtNodeAddF(hFdt, "its@%RX32", 0x08080000); VRC();
481	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleIntCtrlMsi); VRC();
482	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4, 0, 0x08080000, 0, 0x20000); VRC();
483	vrc = RTFdtNodePropertyAddU32( hFdt, "#msi-cells", 1); VRC();
484	vrc = RTFdtNodePropertyAddEmpty( hFdt, "msi-controller"); VRC();
485	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,gic-v3-its"); VRC();
486	vrc = RTFdtNodeFinalize(hFdt); VRC();
487	#endif
488
489	vrc = RTFdtNodeFinalize(hFdt); VRC();
490
491	RTGCPHYS GCPhysMmioStart;
492	RTGCPHYS cbMmio;
493	if (enmGraphicsController == GraphicsControllerType_QemuRamFB)
494	{
495	hrc = pResMgr->assignMmioRegion("qemu-fw-cfg", _4K, &GCPhysMmioStart, &cbMmio); H();
496
497	InsertConfigNode(pDevices, "qemu-fw-cfg", &pDev);
498	InsertConfigNode(pDev, "0", &pInst);
499	InsertConfigNode(pInst, "Config", &pCfg);
500	InsertConfigInteger(pCfg, "MmioSize", cbMmio);
501	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
502	InsertConfigInteger(pCfg, "DmaEnabled", 1);
503	InsertConfigInteger(pCfg, "QemuRamfbSupport", 1);
504	InsertConfigNode(pInst, "LUN#0", &pLunL0);
505	InsertConfigString(pLunL0, "Driver", "MainDisplay");
506
507	vrc = RTFdtNodeAddF(hFdt, "fw-cfg@%RGp", GCPhysMmioStart); VRC();
508	vrc = RTFdtNodePropertyAddEmpty( hFdt, "dma-coherent"); VRC();
509	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
510	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "qemu,fw-cfg-mmio"); VRC();
511	vrc = RTFdtNodeFinalize(hFdt); VRC();
512
513	if (pSysTblsBldAcpi)
514	{
515	vrc = pSysTblsBldAcpi->addMmioDeviceNoIrq("qemu-fw-cfg", 0, GCPhysMmioStart, cbMmio);
516	VRC();
517	}
518	}
519
520	InsertConfigNode(pDevices, "flash-cfi", &pDev);
521	InsertConfigNode(pDev, "0", &pInst);
522	InsertConfigNode(pInst, "Config", &pCfg);
523	InsertConfigInteger(pCfg, "BaseAddress", 64 * _1M);
524	InsertConfigInteger(pCfg, "Size", 768 * _1K);
525	InsertConfigString(pCfg, "FlashFile", "nvram");
526	/* Attach the NVRAM storage driver. */
527	InsertConfigNode(pInst, "LUN#0", &pLunL0);
528	InsertConfigString(pLunL0, "Driver", "NvramStore");
529
530	vrc = RTFdtNodeAddF(hFdt, "flash@%RX32", 0); VRC();
531	vrc = RTFdtNodePropertyAddU32( hFdt, "bank-width", 4); VRC();
532	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 4,
533	0, 0x04000000, /* First region (EFI). */
534	0x04000000, 0x04000000); /* Second region (NVRAM). */ VRC();
535	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "cfi-flash"); VRC();
536	vrc = RTFdtNodeFinalize(hFdt); VRC();
537
538	InsertConfigNode(pDevices, "arm-pl011", &pDev);
539	for (ULONG ulInstance = 0; ulInstance < 1 /** @todo SchemaDefs::SerialPortCount*/; ++ulInstance)
540	{
541	ComPtr<ISerialPort> serialPort;
542	hrc = pMachine->GetSerialPort(ulInstance, serialPort.asOutParam()); H();
543	BOOL fEnabledSerPort = FALSE;
544	if (serialPort)
545	{
546	hrc = serialPort->COMGETTER(Enabled)(&fEnabledSerPort); H();
547	}
548	if (!fEnabledSerPort)
549	{
550	m_aeSerialPortMode[ulInstance] = PortMode_Disconnected;
551	continue;
552	}
553
554	InsertConfigNode(pDev, Utf8StrFmt("%u", ulInstance).c_str(), &pInst);
555	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
556	InsertConfigNode(pInst, "Config", &pCfg);
557
558	uint32_t iIrq = 0;
559	hrc = pResMgr->assignSingleInterrupt("arm-pl011", &iIrq); H();
560	hrc = pResMgr->assignMmioRegion("arm-pl011", _4K, &GCPhysMmioStart, &cbMmio); H();
561
562	InsertConfigInteger(pCfg, "Irq", iIrq);
563	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
564
565	vrc = RTFdtNodeAddF(hFdt, "pl011@%RGp", GCPhysMmioStart); VRC();
566	vrc = RTFdtNodePropertyAddStringList(hFdt, "clock-names", 2, "uartclk", "apb_pclk"); VRC();
567	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "clocks", 2,
568	idPHandleAbpPClk, idPHandleAbpPClk); VRC();
569	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
570	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
571	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
572	"arm,pl011", "arm,primecell"); VRC();
573	vrc = RTFdtNodeFinalize(hFdt); VRC();
574
575	if (pSysTblsBldAcpi)
576	{
577	vrc = pSysTblsBldAcpi->addMmioDevice("arm-pl011", ulInstance, GCPhysMmioStart, cbMmio, iIrq);
578	VRC();
579	}
580
581	BOOL fServer;
582	hrc = serialPort->COMGETTER(Server)(&fServer); H();
583	hrc = serialPort->COMGETTER(Path)(bstr.asOutParam()); H();
584
585	PortMode_T eHostMode;
586	hrc = serialPort->COMGETTER(HostMode)(&eHostMode); H();
587
588	m_aeSerialPortMode[ulInstance] = eHostMode;
589	if (eHostMode != PortMode_Disconnected)
590	{
591	vrc = i_configSerialPort(pInst, eHostMode, Utf8Str(bstr).c_str(), RT_BOOL(fServer));
592	if (RT_FAILURE(vrc))
593	return vrc;
594	}
595	}
596
597	BOOL fRTCUseUTC;
598	hrc = platform->COMGETTER(RTCUseUTC)(&fRTCUseUTC); H();
599
600	uint32_t iIrq = 0;
601	hrc = pResMgr->assignSingleInterrupt("arm-pl031-rtc", &iIrq); H();
602	hrc = pResMgr->assignMmioRegion("arm-pl031-rtc", _4K, &GCPhysMmioStart, &cbMmio); H();
603	InsertConfigNode(pDevices, "arm-pl031-rtc", &pDev);
604	InsertConfigNode(pDev, "0", &pInst);
605	InsertConfigNode(pInst, "Config", &pCfg);
606	InsertConfigInteger(pCfg, "Irq", iIrq);
607	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
608	InsertConfigInteger(pCfg, "UtcOffset", fRTCUseUTC ? 1 : 0);
609
610	vrc = RTFdtNodeAddF(hFdt, "pl032@%RGp", GCPhysMmioStart); VRC();
611	vrc = RTFdtNodePropertyAddString( hFdt, "clock-names", "apb_pclk"); VRC();
612	vrc = RTFdtNodePropertyAddU32( hFdt, "clocks", idPHandleAbpPClk); VRC();
613	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
614	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
615	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
616	"arm,pl031", "arm,primecell"); VRC();
617	vrc = RTFdtNodeFinalize(hFdt); VRC();
618
619	/* Configure gpio keys. */
620	hrc = pResMgr->assignSingleInterrupt("arm-pl061-gpio", &iIrq); H();
621	hrc = pResMgr->assignMmioRegion("arm-pl061-gpio", _4K, &GCPhysMmioStart, &cbMmio); H();
622	InsertConfigNode(pDevices, "arm-pl061-gpio",&pDev);
623	InsertConfigNode(pDev, "0", &pInst);
624	InsertConfigNode(pInst, "Config", &pCfg);
625	InsertConfigInteger(pCfg, "Irq", iIrq);
626	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
627	vrc = RTFdtNodeAddF(hFdt, "pl061@%RGp", GCPhysMmioStart); VRC();
628	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleGpio); VRC();
629	vrc = RTFdtNodePropertyAddString( hFdt, "clock-names", "apb_pclk"); VRC();
630	vrc = RTFdtNodePropertyAddU32( hFdt, "clocks", idPHandleAbpPClk); VRC();
631	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
632	vrc = RTFdtNodePropertyAddEmpty( hFdt, "gpio-controller"); VRC();
633	vrc = RTFdtNodePropertyAddU32( hFdt, "#gpio-cells", 2); VRC();
634	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
635	"arm,pl061", "arm,primecell"); VRC();
636	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
637	vrc = RTFdtNodeFinalize(hFdt); VRC();
638
639	if (pSysTblsBldAcpi)
640	{
641	vrc = pSysTblsBldAcpi->addMmioDevice("arm-pl061-gpio", 0, GCPhysMmioStart, _4K, iIrq);
642	VRC();
643	}
644
645	InsertConfigNode(pInst, "LUN#0", &pLunL0);
646	InsertConfigString(pLunL0, "Driver", "GpioButton");
647	InsertConfigNode(pLunL0, "Config", &pCfg);
648	InsertConfigInteger(pCfg, "PowerButtonGpio", 3);
649	InsertConfigInteger(pCfg, "SleepButtonGpio", 4);
650
651	vrc = RTFdtNodeAdd(hFdt, "gpio-keys"); VRC();
652	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "gpio-keys"); VRC();
653
654	vrc = RTFdtNodeAdd(hFdt, "poweroff"); VRC();
655	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "gpios", 3, idPHandleGpio, 3, 0); VRC();
656	vrc = RTFdtNodePropertyAddU32( hFdt, "linux,code", 0x74); VRC();
657	vrc = RTFdtNodePropertyAddString( hFdt, "label", "GPIO Key Poweroff"); VRC();
658	vrc = RTFdtNodeFinalize(hFdt); VRC();
659
660	vrc = RTFdtNodeAdd(hFdt, "suspend"); VRC();
661	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "gpios", 3, idPHandleGpio, 4, 0); VRC();
662	vrc = RTFdtNodePropertyAddU32( hFdt, "linux,code", 0xcd); VRC();
663	vrc = RTFdtNodePropertyAddString( hFdt, "label", "GPIO Key Suspend"); VRC();
664	vrc = RTFdtNodeFinalize(hFdt);
665
666	vrc = RTFdtNodeFinalize(hFdt); VRC();
667
668	hrc = pResMgr->assignInterrupts("pci-generic-ecam", 4 /cInterrupts/, &iIrq); H();
669	uint32_t aPinIrqs[] = { iIrq, iIrq + 1, iIrq + 2, iIrq + 3 };
670	RTGCPHYS GCPhysPciMmioEcam, GCPhysPciMmio, GCPhysPciMmio32;
671	RTGCPHYS cbPciMmioEcam, cbPciMmio, cbPciMmio32;
672	hrc = pResMgr->assignMmioRegionAligned("pci-pio", _64K, _64K, &GCPhysMmioStart, &cbMmio); H();
673	hrc = pResMgr->assignMmioRegion( "pci-ecam", 16 * _1M, &GCPhysPciMmioEcam, &cbPciMmioEcam); H();
674	hrc = pResMgr->assignMmioRegion( "pci-mmio", _2G, &GCPhysPciMmio, &cbPciMmio); H();
675	hrc = pResMgr->assignMmio32Region( "pci-mmio32", _1G - VBOXPLATFORMARMV8_PHYS_ADDR - _1M, &GCPhysPciMmio32, &cbPciMmio32); H();
676
677	InsertConfigNode(pDevices, "pci-generic-ecam", &pDev);
678	InsertConfigNode(pDev, "0", &pInst);
679	InsertConfigNode(pInst, "Config", &pCfg);
680	InsertConfigInteger(pCfg, "MmioEcamBase", GCPhysPciMmioEcam);
681	InsertConfigInteger(pCfg, "MmioEcamLength", cbPciMmioEcam);
682	InsertConfigInteger(pCfg, "MmioPioBase", GCPhysMmioStart);
683	InsertConfigInteger(pCfg, "MmioPioSize", cbMmio);
684	InsertConfigInteger(pCfg, "IntPinA", aPinIrqs[0]);
685	InsertConfigInteger(pCfg, "IntPinB", aPinIrqs[1]);
686	InsertConfigInteger(pCfg, "IntPinC", aPinIrqs[2]);
687	InsertConfigInteger(pCfg, "IntPinD", aPinIrqs[3]);
688	vrc = RTFdtNodeAddF(hFdt, "pcie@%RGp", GCPhysPciMmio); VRC();
689	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupt-map-mask", 4, 0xf800, 0, 0, 7); VRC();
690
691	uint32_t aIrqCells[32 * 4 * 10]; RT_ZERO(aIrqCells); /* Maximum of 32 devices on the root bus, each supporting 4 interrupts (INTA# ... INTD#). */
692	uint32_t *pau32IrqCell = &aIrqCells[0];
693	uint32_t iIrqPinSwizzle = 0;
694
695	for (uint32_t i = 0; i < 32; i++)
696	{
697	for (uint32_t iIrqPin = 0; iIrqPin < 4; iIrqPin++)
698	{
699	pau32IrqCell[0] = i << 11; /* The dev part, composed as dev.fn. */
700	pau32IrqCell[1] = 0;
701	pau32IrqCell[2] = 0;
702	pau32IrqCell[3] = iIrqPin + 1;
703	pau32IrqCell[4] = idPHandleIntCtrl;
704	pau32IrqCell[5] = 0;
705	pau32IrqCell[6] = 0;
706	pau32IrqCell[7] = 0;
707	pau32IrqCell[8] = aPinIrqs[(iIrqPinSwizzle + iIrqPin) % RT_ELEMENTS(aPinIrqs)];
708	pau32IrqCell[9] = 0x04;
709	pau32IrqCell += 10;
710	}
711
712	iIrqPinSwizzle++;
713	}
714
715	vrc = RTFdtNodePropertyAddCellsU32AsArray(hFdt, "interrupt-map", RT_ELEMENTS(aIrqCells), &aIrqCells[0]);
716	vrc = RTFdtNodePropertyAddU32( hFdt, "#interrupt-cells", 1); VRC();
717	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "ranges", 21,
718	0x1000000, 0, 0,
719	GCPhysMmioStart >> 32, GCPhysMmioStart, cbMmio >> 32, cbMmio,
720	0x2000000, GCPhysPciMmio32 >> 32, GCPhysPciMmio32, GCPhysPciMmio32 >> 32, GCPhysPciMmio32,
721	cbPciMmio32 >> 32, cbPciMmio32,
722	0x3000000, GCPhysPciMmio >> 32, GCPhysPciMmio, GCPhysPciMmio >> 32, GCPhysPciMmio,
723	cbPciMmio >> 32, cbPciMmio); VRC();
724	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysPciMmioEcam, cbPciMmioEcam); VRC();
725	/** @todo msi-map */
726	vrc = RTFdtNodePropertyAddEmpty( hFdt, "dma-coherent"); VRC();
727	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "bus-range", 2, 0, 0xf); VRC();
728	vrc = RTFdtNodePropertyAddU32( hFdt, "linux,pci-domain", 0); VRC();
729	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
730	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 3); VRC();
731	vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "pci"); VRC();
732	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "pci-host-ecam-generic"); VRC();
733	vrc = RTFdtNodeFinalize(hFdt); VRC();
734
735	if (pSysTblsBldAcpi)
736	{
737	vrc = pSysTblsBldAcpi->configurePcieRootBus("pci-generic-ecam", aPinIrqs, GCPhysMmioStart, GCPhysPciMmioEcam,
738	cbPciMmioEcam, GCPhysMmioStart, cbMmio, GCPhysPciMmio32, cbPciMmio32);
739	VRC();
740	}
741
742	/*
743	* VMSVGA compliant graphics controller.
744	*/
745	if ( enmGraphicsController != GraphicsControllerType_QemuRamFB
746	&& enmGraphicsController != GraphicsControllerType_Null)
747	{
748	vrc = i_configGraphicsController(pDevices, enmGraphicsController, pBusMgr, pMachine,
749	pGraphicsAdapter, firmwareSettings,
750	true /fForceVmSvga3/, false /fExposeLegacyVga/); VRC();
751	}
752
753	/*
754	* The USB Controllers and input devices.
755	*/
756	#if 0 /** @todo Make us of this and disallow PS/2 for ARM VMs for now. */
757	KeyboardHIDType_T aKbdHID;
758	hrc = pMachine->COMGETTER(KeyboardHIDType)(&aKbdHID); H();
759	#endif
760
761	PointingHIDType_T aPointingHID;
762	hrc = pMachine->COMGETTER(PointingHIDType)(&aPointingHID); H();
763
764	PCFGMNODE pUsbDevices = NULL;
765	vrc = i_configUsb(pMachine, pBusMgr, pRoot, pDevices, KeyboardHIDType_USBKeyboard, aPointingHID, &pUsbDevices);
766
767	/*
768	* Storage controllers.
769	*/
770	bool fFdcEnabled = false;
771	vrc = i_configStorageCtrls(pMachine, pBusMgr, pVMM, pUVM,
772	pDevices, pUsbDevices, NULL /pBiosCfg/, &fFdcEnabled); VRC();
773
774	/*
775	* Network adapters
776	*/
777	std::list<BootNic> llBootNics;
778	vrc = i_configNetworkCtrls(pMachine, pPlatformProperties, chipsetType, pBusMgr,
779	pVMM, pUVM, pDevices, llBootNics); VRC();
780
781	/*
782	* The VMM device.
783	*/
784	vrc = i_configVmmDev(pMachine, pBusMgr, pDevices, true /fMmioReq/); VRC();
785
786	/*
787	* Audio configuration.
788	*/
789	bool fAudioEnabled = false;
790	vrc = i_configAudioCtrl(virtualBox, pMachine, pBusMgr, pDevices,
791	false /fOsXGuest/, &fAudioEnabled); VRC();
792	}
793	catch (ConfigError &x)
794	{
795	RTFdtDestroy(hFdt);
796
797	// InsertConfig threw something:
798	pVMM->pfnVMR3SetError(pUVM, x.m_vrc, RT_SRC_POS, "Caught ConfigError: %Rrc - %s", x.m_vrc, x.what());
799	return x.m_vrc;
800	}
801	catch (HRESULT hrcXcpt)
802	{
803	RTFdtDestroy(hFdt);
804	AssertLogRelMsgFailedReturn(("hrc=%Rhrc\n", hrcXcpt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR);
805	}
806
807	#ifdef VBOX_WITH_EXTPACK
808	/*
809	* Call the extension pack hooks if everything went well thus far.
810	*/
811	if (RT_SUCCESS(vrc))
812	{
813	pAlock->release();
814	vrc = mptrExtPackManager->i_callAllVmConfigureVmmHooks(this, pVM, pVMM);
815	pAlock->acquire();
816	}
817	#endif
818
819	#if 0
820	vrc = RTFdtNodeAdd(hFdt, "chosen"); VRC();
821	vrc = RTFdtNodePropertyAddString( hFdt, "stdout-path", "pl011@9000000"); VRC();
822	vrc = RTFdtNodePropertyAddString( hFdt, "stdin-path", "pl011@9000000"); VRC();
823	vrc = RTFdtNodeFinalize(hFdt);
824	#endif
825
826	/* Finalize the FDT and add it to the resource store. */
827	vrc = RTFdtFinalize(hFdt);
828	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
829
830	RTVFSFILE hVfsFileDesc = NIL_RTVFSFILE;
831	vrc = RTVfsMemFileCreate(NIL_RTVFSIOSTREAM, 0 /cbEstimate/, &hVfsFileDesc);
832	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
833	RTVFSIOSTREAM hVfsIosDesc = RTVfsFileToIoStream(hVfsFileDesc);
834	AssertRelease(hVfsIosDesc != NIL_RTVFSIOSTREAM);
835
836	/* Initialize the VBox platform descriptor. */
837	VBOXPLATFORMARMV8 ArmV8Platform; RT_ZERO(ArmV8Platform);
838
839	/* Make room for the descriptor at the beginning. */
840	vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, sizeof(ArmV8Platform));
841	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
842
843	vrc = RTFdtDumpToVfsIoStrm(hFdt, RTFDTTYPE_DTB, 0 /fFlags/, hVfsIosDesc, NULL /pErrInfo/);
844	uint64_t cbFdt = 0;
845	if (RT_SUCCESS(vrc))
846	{
847	vrc = RTVfsFileQuerySize(hVfsFileDesc, &cbFdt);
848	cbFdt -= sizeof(ArmV8Platform);
849	}
850	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
851
852	vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, (RTFOFF)(RT_ALIGN_64(cbFdt, _64K) - cbFdt));
853	AssertRCReturn(vrc, vrc);
854
855	RTGCPHYS GCPhysMmioStart;
856	RTGCPHYS cbMmio;
857	hrc = pResMgr->queryMmioRegion(&GCPhysMmioStart, &cbMmio);
858	Assert(SUCCEEDED(hrc));
859
860	RTGCPHYS GCPhysMmio32Start;
861	RTGCPHYS cbMmio32;
862	hrc = pResMgr->queryMmio32Region(&GCPhysMmio32Start, &cbMmio32);
863	Assert(SUCCEEDED(hrc));
864
865	RTGCPHYS GCPhysXsdp = NIL_RTGCPHYS;
866	size_t cbAcpiXsdp = 0;
867	size_t cbAcpi = 0;
868	if (pSysTblsBldAcpi)
869	{
870	vrc = pSysTblsBldAcpi->finishTables(VBOXPLATFORMARMV8_PHYS_ADDR + sizeof(ArmV8Platform) + RT_ALIGN_64(cbFdt, _64K),
871	hVfsIosDesc, &GCPhysXsdp, &cbAcpiXsdp, &cbAcpi);
872	AssertRCReturn(vrc, vrc);
873	Assert(GCPhysXsdp > VBOXPLATFORMARMV8_PHYS_ADDR);
874
875	/* Dump the ACPI table for debugging purposes if requested. */
876	Bstr SysTblsDumpVal;
877	hrc = mMachine->GetExtraData(Bstr("VBoxInternal2/DumpSysTables").raw(),
878	SysTblsDumpVal.asOutParam());
879	if ( hrc == S_OK
880	&& SysTblsDumpVal.isNotEmpty())
881	{
882	vrc = pSysTblsBldAcpi->dumpTables(Utf8Str(SysTblsDumpVal).c_str());
883	AssertRCReturn(vrc, vrc);
884	}
885
886	delete pSysTblsBldAcpi;
887
888	vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, (RTFOFF)(RT_ALIGN_64(cbAcpi, _64K) - cbAcpi));
889	AssertRCReturn(vrc, vrc);
890	}
891
892	ArmV8Platform.u32Magic = VBOXPLATFORMARMV8_MAGIC;
893	ArmV8Platform.u32Version = VBOXPLATFORMARMV8_VERSION;
894	ArmV8Platform.cbDesc = sizeof(ArmV8Platform);
895	ArmV8Platform.fFlags = 0;
896	ArmV8Platform.u64PhysAddrRamBase = GCPhysRam;
897	ArmV8Platform.cbRamBase = cbRam;
898	ArmV8Platform.i64OffFdt = sizeof(ArmV8Platform);
899	ArmV8Platform.cbFdt = RT_ALIGN_64(cbFdt, _64K);
900	if (cbAcpi)
901	{
902	ArmV8Platform.i64OffAcpi = sizeof(ArmV8Platform) + RT_ALIGN_64(cbFdt, _64K);
903	ArmV8Platform.cbAcpi = RT_ALIGN_64(cbAcpi, _64K);
904	ArmV8Platform.i64OffAcpiXsdp = GCPhysXsdp - VBOXPLATFORMARMV8_PHYS_ADDR;
905	ArmV8Platform.cbAcpiXsdp = cbAcpiXsdp;
906	}
907	ArmV8Platform.i64OffUefiRom = -128 * _1M;
908	ArmV8Platform.cbUefiRom = _64M;
909	ArmV8Platform.i64OffMmio = GCPhysMmioStart - _128M;
910	ArmV8Platform.cbMmio = cbMmio;
911	ArmV8Platform.i64OffMmio32 = GCPhysMmio32Start - _128M;
912	ArmV8Platform.cbMmio32 = cbMmio32;
913
914	/* Add the VBox platform descriptor to the resource store. */
915	vrc = RTVfsIoStrmWriteAt(hVfsIosDesc, 0, &ArmV8Platform, sizeof(ArmV8Platform), true /fBlocking/, NULL /pcbWritten/);
916	RTVfsIoStrmRelease(hVfsIosDesc);
917	vrc = mptrResourceStore->i_addItem("resources", "VBoxArmV8Desc", hVfsFileDesc);
918	RTVfsFileRelease(hVfsFileDesc);
919	AssertRCReturn(vrc, vrc);
920
921	/* Dump the DTB for debugging purposes if requested. */
922	Bstr DtbDumpVal;
923	hrc = mMachine->GetExtraData(Bstr("VBoxInternal2/DumpDtb").raw(),
924	DtbDumpVal.asOutParam());
925	if ( hrc == S_OK
926	&& DtbDumpVal.isNotEmpty())
927	{
928	vrc = RTFdtDumpToFile(hFdt, RTFDTTYPE_DTB, 0 /fFlags/, Utf8Str(DtbDumpVal).c_str(), NULL /pErrInfo/);
929	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
930	}
931
932	delete pResMgr; /* Delete the address/interrupt assignment manager. */
933
934	/*
935	* Apply the CFGM overlay.
936	*/
937	if (RT_SUCCESS(vrc))
938	vrc = i_configCfgmOverlay(pRoot, virtualBox, pMachine);
939
940	/*
941	* Dump all extradata API settings tweaks, both global and per VM.
942	*/
943	if (RT_SUCCESS(vrc))
944	vrc = i_configDumpAPISettingsTweaks(virtualBox, pMachine);
945
946	#undef H
947
948	pAlock->release(); /* Avoid triggering the lock order inversion check. */
949
950	/*
951	* Register VM state change handler.
952	*/
953	int vrc2 = pVMM->pfnVMR3AtStateRegister(pUVM, Console::i_vmstateChangeCallback, this);
954	AssertRC(vrc2);
955	if (RT_SUCCESS(vrc))
956	vrc = vrc2;
957
958	/*
959	* Register VM runtime error handler.
960	*/
961	vrc2 = pVMM->pfnVMR3AtRuntimeErrorRegister(pUVM, Console::i_atVMRuntimeErrorCallback, this);
962	AssertRC(vrc2);
963	if (RT_SUCCESS(vrc))
964	vrc = vrc2;
965
966	pAlock->acquire();
967
968	LogFlowFunc(("vrc = %Rrc\n", vrc));
969	LogFlowFuncLeave();
970
971	return vrc;
972	}
973	#endif /* !VBOX_WITH_VIRT_ARMV8 */
974

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source: vbox/trunk/src/VBox/Main/src-client/ConsoleImplConfigArmV8.cpp@ 106361

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