ConsoleImplConfigArmV8.cpp@ 101481

Last change on this file since 101481 was 101480, checked in by vboxsync, 17 months ago
Main/src-all,Main/src-client: Add support for PCI bridges for the Armv8 virtual platform and add interrupt descriptors for all slots in the FDT, bugref:10528
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1	/* $Id: ConsoleImplConfigArmV8.cpp 101480 2023-10-17 14:39:59Z vboxsync $ */
2	/** @file
3	* VBox Console COM Class implementation - VM Configuration Bits for ARMv8.
4	*/
5
6	/*
7	* Copyright (C) 2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_MAIN_CONSOLE
33	#include "LoggingNew.h"
34
35	#include "ConsoleImpl.h"
36	#include "ResourceStoreImpl.h"
37	#include "Global.h"
38	#include "VMMDev.h"
39
40	// generated header
41	#include "SchemaDefs.h"
42
43	#include "AutoCaller.h"
44
45	#include <iprt/buildconfig.h>
46	#include <iprt/ctype.h>
47	#include <iprt/dir.h>
48	#include <iprt/fdt.h>
49	#include <iprt/file.h>
50	#include <iprt/param.h>
51	#include <iprt/path.h>
52	#include <iprt/string.h>
53	#include <iprt/system.h>
54	#if 0 /* enable to play with lots of memory. */
55	# include <iprt/env.h>
56	#endif
57	#include <iprt/stream.h>
58
59	#include <iprt/formats/arm-psci.h>
60
61	#include <VBox/vmm/vmmr3vtable.h>
62	#include <VBox/vmm/vmapi.h>
63	#include <VBox/err.h>
64	#include <VBox/param.h>
65	#include <VBox/version.h>
66	#include <VBox/platforms/vbox-armv8.h>
67
68	#include "BusAssignmentManager.h"
69	#ifdef VBOX_WITH_EXTPACK
70	# include "ExtPackManagerImpl.h"
71	#endif
72
73
74	/*********************************************************************************************************************************
75	* Internal Functions *
76	*********************************************************************************************************************************/
77
78	/* Darwin compile kludge */
79	#undef PVM
80
81	#ifdef VBOX_WITH_VIRT_ARMV8
82	/**
83	* Worker for configConstructor.
84	*
85	* @return VBox status code.
86	* @param pUVM The user mode VM handle.
87	* @param pVM The cross context VM handle.
88	* @param pVMM The VMM vtable.
89	* @param pAlock The automatic lock instance. This is for when we have
90	* to leave it in order to avoid deadlocks (ext packs and
91	* more).
92	*
93	* @todo This is a big hack at the moment and provides a static VM config to work with, will be adjusted later
94	* on to adhere to the VM config when sorting out the API bits.
95	*/
96	int Console::i_configConstructorArmV8(PUVM pUVM, PVM pVM, PCVMMR3VTABLE pVMM, AutoWriteLock *pAlock)
97	{
98	RT_NOREF(pVM /* when everything is disabled */);
99	ComPtr<IMachine> pMachine = i_machine();
100
101	HRESULT hrc;
102	Utf8Str strTmp;
103	Bstr bstr;
104
105	RTFDT hFdt = NIL_RTFDT;
106	int vrc = RTFdtCreateEmpty(&hFdt);
107	AssertRCReturn(vrc, vrc);
108
109	#define H() AssertLogRelMsgReturnStmt(!FAILED(hrc), ("hrc=%Rhrc\n", hrc), RTFdtDestroy(hFdt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR)
110	#define VRC() AssertLogRelMsgReturnStmt(RT_SUCCESS(vrc), ("vrc=%Rrc\n", vrc), RTFdtDestroy(hFdt), vrc)
111
112	/** @todo Find a way to figure it out before CPUM is set up, can't use CPUMGetGuestAddrWidths() and on macOS we need
113	* access to Hypervisor.framework to query the ID registers (Linux can in theory parse /proc/cpuinfo, no idea for Windows). */
114	RTGCPHYS GCPhysTopOfAddrSpace = RT_BIT_64(36);
115
116	/*
117	* Get necessary objects and frequently used parameters.
118	*/
119	ComPtr<IVirtualBox> virtualBox;
120	hrc = pMachine->COMGETTER(Parent)(virtualBox.asOutParam()); H();
121
122	ComPtr<IHost> host;
123	hrc = virtualBox->COMGETTER(Host)(host.asOutParam()); H();
124
125	PlatformArchitecture_T platformArchHost;
126	hrc = host->COMGETTER(Architecture)(&platformArchHost); H();
127
128	ComPtr<ISystemProperties> systemProperties;
129	hrc = virtualBox->COMGETTER(SystemProperties)(systemProperties.asOutParam()); H();
130
131	ComPtr<IFirmwareSettings> firmwareSettings;
132	hrc = pMachine->COMGETTER(FirmwareSettings)(firmwareSettings.asOutParam()); H();
133
134	ComPtr<INvramStore> nvramStore;
135	hrc = pMachine->COMGETTER(NonVolatileStore)(nvramStore.asOutParam()); H();
136
137	hrc = pMachine->COMGETTER(HardwareUUID)(bstr.asOutParam()); H();
138	RTUUID HardwareUuid;
139	vrc = RTUuidFromUtf16(&HardwareUuid, bstr.raw());
140	AssertRCReturn(vrc, vrc);
141
142	ULONG cRamMBs;
143	hrc = pMachine->COMGETTER(MemorySize)(&cRamMBs); H();
144	uint64_t const cbRam = cRamMBs * (uint64_t)_1M;
145
146	ComPtr<IPlatform> platform;
147	hrc = pMachine->COMGETTER(Platform)(platform.asOutParam()); H();
148
149	/* Note: Should be guarded by VBOX_WITH_VIRT_ARMV8, but we check this anyway here. */
150	#if 1 /* For now we only support running ARM VMs on ARM hosts. */
151	PlatformArchitecture_T platformArchMachine;
152	hrc = platform->COMGETTER(Architecture)(&platformArchMachine); H();
153	if (platformArchMachine != platformArchHost)
154	return pVMM->pfnVMR3SetError(pUVM, VERR_PLATFORM_ARCH_NOT_SUPPORTED, RT_SRC_POS,
155	N_("VM platform architecture (%s) not supported on this host (%s)."),
156	Global::stringifyPlatformArchitecture(platformArchMachine),
157	Global::stringifyPlatformArchitecture(platformArchHost));
158	#endif
159
160	ComPtr<IPlatformProperties> pPlatformProperties;
161	hrc = platform->COMGETTER(Properties)(pPlatformProperties.asOutParam()); H();
162
163	ChipsetType_T chipsetType;
164	hrc = platform->COMGETTER(ChipsetType)(&chipsetType); H();
165
166	ULONG cCpus = 1;
167	hrc = pMachine->COMGETTER(CPUCount)(&cCpus); H();
168	Assert(cCpus);
169
170	ULONG ulCpuExecutionCap = 100;
171	hrc = pMachine->COMGETTER(CPUExecutionCap)(&ulCpuExecutionCap); H();
172
173	LogRel(("Guest architecture: ARM\n"));
174
175	Bstr osTypeId;
176	hrc = pMachine->COMGETTER(OSTypeId)(osTypeId.asOutParam()); H();
177	LogRel(("Guest OS type: '%s'\n", Utf8Str(osTypeId).c_str()));
178
179	BusAssignmentManager *pBusMgr = mBusMgr = BusAssignmentManager::createInstance(pVMM, chipsetType, IommuType_None);
180
181	/*
182	* Get root node first.
183	* This is the only node in the tree.
184	*/
185	PCFGMNODE pRoot = pVMM->pfnCFGMR3GetRootU(pUVM);
186	Assert(pRoot);
187
188	// catching throws from InsertConfigString and friends.
189	try
190	{
191
192	/*
193	* Set the root (and VMM) level values.
194	*/
195	hrc = pMachine->COMGETTER(Name)(bstr.asOutParam()); H();
196	InsertConfigString(pRoot, "Name", bstr);
197	InsertConfigBytes(pRoot, "UUID", &HardwareUuid, sizeof(HardwareUuid));
198	InsertConfigInteger(pRoot, "NumCPUs", cCpus);
199	InsertConfigInteger(pRoot, "CpuExecutionCap", ulCpuExecutionCap);
200	InsertConfigInteger(pRoot, "TimerMillies", 10);
201
202	uint32_t idPHandleIntCtrl = RTFdtPHandleAllocate(hFdt);
203	Assert(idPHandleIntCtrl != UINT32_MAX);
204	uint32_t idPHandleIntCtrlMsi = RTFdtPHandleAllocate(hFdt);
205	Assert(idPHandleIntCtrlMsi != UINT32_MAX); RT_NOREF(idPHandleIntCtrlMsi);
206	uint32_t idPHandleAbpPClk = RTFdtPHandleAllocate(hFdt);
207	Assert(idPHandleAbpPClk != UINT32_MAX);
208	uint32_t idPHandleGpio = RTFdtPHandleAllocate(hFdt);
209	Assert(idPHandleGpio != UINT32_MAX);
210
211	uint32_t aidPHandleCpus[VMM_MAX_CPU_COUNT];
212	for (uint32_t i = 0; i < cCpus; i++)
213	{
214	aidPHandleCpus[i] = RTFdtPHandleAllocate(hFdt);
215	Assert(aidPHandleCpus[i] != UINT32_MAX);
216	}
217
218	vrc = RTFdtNodePropertyAddU32( hFdt, "interrupt-parent", idPHandleIntCtrl); VRC();
219	vrc = RTFdtNodePropertyAddString(hFdt, "model", "linux,dummy-virt"); VRC();
220	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
221	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 2); VRC();
222	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "linux,dummy-virt"); VRC();
223
224	/* Configure the Power State Coordination Interface. */
225	vrc = RTFdtNodeAdd(hFdt, "psci"); VRC();
226	vrc = RTFdtNodePropertyAddU32( hFdt, "migrate", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_MIGRATE)); VRC();
227	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_on", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_ON)); VRC();
228	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_off", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_OFF)); VRC();
229	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_suspend", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_SUSPEND)); VRC();
230	vrc = RTFdtNodePropertyAddString(hFdt, "method", "hvc"); VRC();
231	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 3,
232	"arm,psci-1.0", "arm,psci-0.2", "arm,psci"); VRC();
233	vrc = RTFdtNodeFinalize(hFdt); VRC();
234
235	/* Configure the timer and clock. */
236	vrc = RTFdtNodeAdd(hFdt, "timer"); VRC();
237	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 12,
238	0x01, 0x0d, 0x104,
239	0x01, 0x0e, 0x104,
240	0x01, 0x0b, 0x104,
241	0x01, 0x0a, 0x104); VRC();
242	vrc = RTFdtNodePropertyAddEmpty( hFdt, "always-on"); VRC();
243	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,armv7-timer"); VRC();
244	vrc = RTFdtNodeFinalize(hFdt);
245
246	vrc = RTFdtNodeAdd(hFdt, "apb-clk"); VRC();
247	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleAbpPClk); VRC();
248	vrc = RTFdtNodePropertyAddString( hFdt, "clock-output-names", "clk24mhz"); VRC();
249	vrc = RTFdtNodePropertyAddU32( hFdt, "clock-frequency", 24 * 1000 * 1000); VRC();
250	vrc = RTFdtNodePropertyAddU32( hFdt, "#clock-cells", 0); VRC();
251	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "fixed-clock"); VRC();
252	vrc = RTFdtNodeFinalize(hFdt);
253
254	/* Configure gpio keys (non functional at the moment). */
255	vrc = RTFdtNodeAdd(hFdt, "gpio-keys"); VRC();
256	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "gpio-keys"); VRC();
257
258	vrc = RTFdtNodeAdd(hFdt, "poweroff"); VRC();
259	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "gpios", 3, idPHandleGpio, 3, 0); VRC();
260	vrc = RTFdtNodePropertyAddU32( hFdt, "linux,code", 0x74); VRC();
261	vrc = RTFdtNodePropertyAddString( hFdt, "label", "GPIO Key Poweroff"); VRC();
262	vrc = RTFdtNodeFinalize(hFdt); VRC();
263
264	vrc = RTFdtNodeFinalize(hFdt); VRC();
265
266	/*
267	* NEM
268	*/
269	PCFGMNODE pNEM;
270	InsertConfigNode(pRoot, "NEM", &pNEM);
271
272	/*
273	* MM values.
274	*/
275	PCFGMNODE pMM;
276	InsertConfigNode(pRoot, "MM", &pMM);
277
278	/*
279	* Memory setup.
280	*/
281	PCFGMNODE pMem = NULL;
282	InsertConfigNode(pMM, "MemRegions", &pMem);
283
284	PCFGMNODE pMemRegion = NULL;
285	InsertConfigNode(pMem, "Conventional", &pMemRegion);
286	InsertConfigInteger(pMemRegion, "GCPhysStart", 0x40000000);
287	InsertConfigInteger(pMemRegion, "Size", cbRam);
288
289	vrc = RTFdtNodeAddF(hFdt, "memory@%RX32", 0x40000000); VRC();
290	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4,
291	0, 0x40000000,
292	(uint32_t)(cbRam >> 32), cbRam & UINT32_MAX); VRC();
293	vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "memory"); VRC();
294	vrc = RTFdtNodeFinalize(hFdt); VRC();
295
296	/* Configure the CPUs in the system, only one socket and cluster at the moment. */
297	vrc = RTFdtNodeAdd(hFdt, "cpus"); VRC();
298	vrc = RTFdtNodePropertyAddU32(hFdt, "#size-cells", 0); VRC();
299	vrc = RTFdtNodePropertyAddU32(hFdt, "#address-cells", 1); VRC();
300
301	vrc = RTFdtNodeAdd(hFdt, "socket0"); VRC();
302	vrc = RTFdtNodeAdd(hFdt, "cluster0"); VRC();
303
304	for (uint32_t i = 0; i < cCpus; i++)
305	{
306	vrc = RTFdtNodeAddF(hFdt, "core%u", i); VRC();
307	vrc = RTFdtNodePropertyAddU32(hFdt, "cpu", aidPHandleCpus[i]); VRC();
308	vrc = RTFdtNodeFinalize(hFdt); VRC();
309	}
310
311	vrc = RTFdtNodeFinalize(hFdt); VRC();
312	vrc = RTFdtNodeFinalize(hFdt); VRC();
313
314	for (uint32_t i = 0; i < cCpus; i++)
315	{
316	vrc = RTFdtNodeAddF(hFdt, "cpu@%u", i); VRC();
317	vrc = RTFdtNodePropertyAddU32(hFdt, "phandle", aidPHandleCpus[i]); VRC();
318	vrc = RTFdtNodePropertyAddU32(hFdt, "reg", i); VRC();
319	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "arm,cortex-a15"); VRC();
320	vrc = RTFdtNodePropertyAddString(hFdt, "device_type", "cpu"); VRC();
321	if (cCpus > 1)
322	{
323	vrc = RTFdtNodePropertyAddString(hFdt, "enable-method", "psci"); VRC();
324	}
325	vrc = RTFdtNodeFinalize(hFdt); VRC();
326	}
327
328	vrc = RTFdtNodeFinalize(hFdt); VRC();
329
330
331	/*
332	* PDM config.
333	* Load drivers in VBoxC.[so\|dll]
334	*/
335	vrc = i_configPdm(pMachine, pVMM, pUVM, pRoot); VRC();
336
337
338	/*
339	* VGA.
340	*/
341	ComPtr<IGraphicsAdapter> pGraphicsAdapter;
342	hrc = pMachine->COMGETTER(GraphicsAdapter)(pGraphicsAdapter.asOutParam()); H();
343	GraphicsControllerType_T enmGraphicsController;
344	hrc = pGraphicsAdapter->COMGETTER(GraphicsControllerType)(&enmGraphicsController); H();
345
346	/*
347	* Devices
348	*/
349	PCFGMNODE pDevices = NULL; /* /Devices */
350	PCFGMNODE pDev = NULL; /* /Devices/Dev/ */
351	PCFGMNODE pInst = NULL; /* /Devices/Dev/0/ */
352	PCFGMNODE pCfg = NULL; /* /Devices/Dev/.../Config/ */
353	PCFGMNODE pLunL0 = NULL; /* /Devices/Dev/0/LUN#0/ */
354
355	InsertConfigNode(pRoot, "Devices", &pDevices);
356
357	InsertConfigNode(pDevices, "pci-generic-ecam-bridge", NULL);
358
359	InsertConfigNode(pDevices, "platform", &pDev);
360	InsertConfigNode(pDev, "0", &pInst);
361	InsertConfigNode(pInst, "Config", &pCfg);
362	InsertConfigNode(pInst, "LUN#0", &pLunL0);
363	InsertConfigString(pLunL0, "Driver", "ResourceStore");
364
365	/* Add the resources. */
366	PCFGMNODE pResources = NULL; /* /Devices/efi-armv8/Config/Resources */
367	PCFGMNODE pRes = NULL; /* /Devices/efi-armv8/Config/Resources/<Resource> */
368	InsertConfigString(pCfg, "ResourceNamespace", "resources");
369	InsertConfigNode(pCfg, "Resources", &pResources);
370	InsertConfigNode(pResources, "EfiRom", &pRes);
371	InsertConfigInteger(pRes, "RegisterAsRom", 1);
372	InsertConfigInteger(pRes, "GCPhysLoadAddress", 0);
373
374	/** @todo r=aeichner 32-bit guests and query the firmware type from VBoxSVC. */
375	/*
376	* Firmware.
377	*/
378	FirmwareType_T eFwType = FirmwareType_EFI64;
379	#ifdef VBOX_WITH_EFI_IN_DD2
380	const char *pszEfiRomFile = eFwType == FirmwareType_EFIDUAL ? "<INVALID>"
381	: eFwType == FirmwareType_EFI32 ? "VBoxEFIAArch32.fd"
382	: "VBoxEFIAArch64.fd";
383	const char *pszKey = "ResourceId";
384	#else
385	Utf8Str efiRomFile;
386	vrc = findEfiRom(virtualBox, PlatformArchitecture_ARM, eFwType, &efiRomFile);
387	AssertRCReturn(vrc, vrc);
388	const char *pszEfiRomFile = efiRomFile.c_str();
389	const char *pszKey = "Filename";
390	#endif
391	InsertConfigString(pRes, pszKey, pszEfiRomFile);
392
393	InsertConfigNode(pResources, "ArmV8Desc", &pRes);
394	InsertConfigInteger(pRes, "RegisterAsRom", 1);
395	InsertConfigInteger(pRes, "GCPhysLoadAddress", UINT64_MAX); /* End of physical address space. */
396	InsertConfigString(pRes, "ResourceId", "VBoxArmV8Desc");
397
398	vrc = RTFdtNodeAddF(hFdt, "platform-bus@%RX32", 0x0c000000); VRC();
399	vrc = RTFdtNodePropertyAddU32( hFdt, "interrupt-parent", idPHandleIntCtrl); VRC();
400	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "ranges", 4, 0, 0, 0x0c000000, 0x02000000); VRC();
401	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 1); VRC();
402	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 1); VRC();
403	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
404	"qemu,platform", "simple-bus"); VRC();
405	vrc = RTFdtNodeFinalize(hFdt); VRC();
406
407	InsertConfigNode(pDevices, "gic", &pDev);
408	InsertConfigNode(pDev, "0", &pInst);
409	InsertConfigInteger(pInst, "Trusted", 1);
410	InsertConfigNode(pInst, "Config", &pCfg);
411	InsertConfigInteger(pCfg, "DistributorMmioBase", 0x08000000);
412	InsertConfigInteger(pCfg, "RedistributorMmioBase", 0x080a0000);
413
414	vrc = RTFdtNodeAddF(hFdt, "intc@%RX32", 0x08000000); VRC();
415	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleIntCtrl); VRC();
416	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 8,
417	0, 0x08000000, 0, 0x10000,
418	0, 0x080a0000, 0, 0xf60000); VRC();
419	vrc = RTFdtNodePropertyAddU32( hFdt, "#redistributor-regions", 1); VRC();
420	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,gic-v3"); VRC();
421	vrc = RTFdtNodePropertyAddEmpty( hFdt, "ranges"); VRC();
422	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
423	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 2); VRC();
424	vrc = RTFdtNodePropertyAddEmpty( hFdt, "interrupt-controller"); VRC();
425	vrc = RTFdtNodePropertyAddU32( hFdt, "#interrupt-cells", 3); VRC();
426
427	#if 0
428	vrc = RTFdtNodeAddF(hFdt, "its@%RX32", 0x08080000); VRC();
429	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleIntCtrlMsi); VRC();
430	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4, 0, 0x08080000, 0, 0x20000); VRC();
431	vrc = RTFdtNodePropertyAddU32( hFdt, "#msi-cells", 1); VRC();
432	vrc = RTFdtNodePropertyAddEmpty( hFdt, "msi-controller"); VRC();
433	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,gic-v3-its"); VRC();
434	vrc = RTFdtNodeFinalize(hFdt); VRC();
435	#endif
436
437	vrc = RTFdtNodeFinalize(hFdt); VRC();
438
439
440	InsertConfigNode(pDevices, "qemu-fw-cfg", &pDev);
441	InsertConfigNode(pDev, "0", &pInst);
442	InsertConfigNode(pInst, "Config", &pCfg);
443	InsertConfigInteger(pCfg, "MmioSize", 4096);
444	InsertConfigInteger(pCfg, "MmioBase", 0x09020000);
445	InsertConfigInteger(pCfg, "DmaEnabled", 1);
446	InsertConfigInteger(pCfg, "QemuRamfbSupport", enmGraphicsController == GraphicsControllerType_QemuRamFB ? 1 : 0);
447	if (enmGraphicsController == GraphicsControllerType_QemuRamFB)
448	{
449	InsertConfigNode(pInst, "LUN#0", &pLunL0);
450	InsertConfigString(pLunL0, "Driver", "MainDisplay");
451	}
452
453	vrc = RTFdtNodeAddF(hFdt, "fw-cfg@%RX32", 0x09020000); VRC();
454	vrc = RTFdtNodePropertyAddEmpty( hFdt, "dma-coherent"); VRC();
455	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4, 0, 0x09020000, 0, 0x18); VRC();
456	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "qemu,fw-cfg-mmio"); VRC();
457	vrc = RTFdtNodeFinalize(hFdt); VRC();
458
459
460	InsertConfigNode(pDevices, "flash-cfi", &pDev);
461	InsertConfigNode(pDev, "0", &pInst);
462	InsertConfigNode(pInst, "Config", &pCfg);
463	InsertConfigInteger(pCfg, "BaseAddress", 64 * _1M);
464	InsertConfigInteger(pCfg, "Size", 768 * _1K);
465	InsertConfigString(pCfg, "FlashFile", "nvram");
466	/* Attach the NVRAM storage driver. */
467	InsertConfigNode(pInst, "LUN#0", &pLunL0);
468	InsertConfigString(pLunL0, "Driver", "NvramStore");
469
470	vrc = RTFdtNodeAddF(hFdt, "flash@%RX32", 0); VRC();
471	vrc = RTFdtNodePropertyAddU32( hFdt, "bank-width", 4); VRC();
472	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 8,
473	0, 0, 0, 0x04000000,
474	0, 0x04000000, 0, 0x04000000); VRC();
475	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "cfi-flash"); VRC();
476	vrc = RTFdtNodeFinalize(hFdt); VRC();
477
478	InsertConfigNode(pDevices, "arm-pl011", &pDev);
479	for (ULONG ulInstance = 0; ulInstance < 1 /** @todo SchemaDefs::SerialPortCount*/; ++ulInstance)
480	{
481	ComPtr<ISerialPort> serialPort;
482	hrc = pMachine->GetSerialPort(ulInstance, serialPort.asOutParam()); H();
483	BOOL fEnabledSerPort = FALSE;
484	if (serialPort)
485	{
486	hrc = serialPort->COMGETTER(Enabled)(&fEnabledSerPort); H();
487	}
488	if (!fEnabledSerPort)
489	{
490	m_aeSerialPortMode[ulInstance] = PortMode_Disconnected;
491	continue;
492	}
493
494	InsertConfigNode(pDev, Utf8StrFmt("%u", ulInstance).c_str(), &pInst);
495	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
496	InsertConfigNode(pInst, "Config", &pCfg);
497
498	InsertConfigInteger(pCfg, "Irq", 1);
499	InsertConfigInteger(pCfg, "MmioBase", 0x09000000);
500
501	vrc = RTFdtNodeAddF(hFdt, "pl011@%RX32", 0x09000000); VRC();
502	vrc = RTFdtNodePropertyAddStringList(hFdt, "clock-names", 2, "uartclk", "apb_pclk"); VRC();
503	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "clocks", 2,
504	idPHandleAbpPClk, idPHandleAbpPClk); VRC();
505	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, 0x01, 0x04); VRC();
506	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4, 0, 0x09000000, 0, 0x1000); VRC();
507	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
508	"arm,pl011", "arm,primecell"); VRC();
509	vrc = RTFdtNodeFinalize(hFdt); VRC();
510
511	BOOL fServer;
512	hrc = serialPort->COMGETTER(Server)(&fServer); H();
513	hrc = serialPort->COMGETTER(Path)(bstr.asOutParam()); H();
514
515	PortMode_T eHostMode;
516	hrc = serialPort->COMGETTER(HostMode)(&eHostMode); H();
517
518	m_aeSerialPortMode[ulInstance] = eHostMode;
519	if (eHostMode != PortMode_Disconnected)
520	{
521	vrc = i_configSerialPort(pInst, eHostMode, Utf8Str(bstr).c_str(), RT_BOOL(fServer));
522	if (RT_FAILURE(vrc))
523	return vrc;
524	}
525	}
526
527	InsertConfigNode(pDevices, "arm-pl031-rtc", &pDev);
528	InsertConfigNode(pDev, "0", &pInst);
529	InsertConfigNode(pInst, "Config", &pCfg);
530	InsertConfigInteger(pCfg, "Irq", 2);
531	InsertConfigInteger(pCfg, "MmioBase", 0x09010000);
532	vrc = RTFdtNodeAddF(hFdt, "pl032@%RX32", 0x09010000); VRC();
533	vrc = RTFdtNodePropertyAddString( hFdt, "clock-names", "apb_pclk"); VRC();
534	vrc = RTFdtNodePropertyAddU32( hFdt, "clocks", idPHandleAbpPClk); VRC();
535	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, 0x02, 0x04); VRC();
536	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4, 0, 0x09010000, 0, 0x1000); VRC();
537	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
538	"arm,pl031", "arm,primecell"); VRC();
539	vrc = RTFdtNodeFinalize(hFdt); VRC();
540
541	InsertConfigNode(pDevices, "arm-pl061-gpio",&pDev);
542	InsertConfigNode(pDev, "0", &pInst);
543	InsertConfigNode(pInst, "Config", &pCfg);
544	InsertConfigInteger(pCfg, "Irq", 7);
545	InsertConfigInteger(pCfg, "MmioBase", 0x09030000);
546	vrc = RTFdtNodeAddF(hFdt, "pl061@%RX32", 0x09030000); VRC();
547	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleGpio); VRC();
548	vrc = RTFdtNodePropertyAddString( hFdt, "clock-names", "apb_pclk"); VRC();
549	vrc = RTFdtNodePropertyAddU32( hFdt, "clocks", idPHandleAbpPClk); VRC();
550	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, 0x07, 0x04); VRC();
551	vrc = RTFdtNodePropertyAddEmpty( hFdt, "gpio-controller"); VRC();
552	vrc = RTFdtNodePropertyAddU32( hFdt, "#gpio-cells", 2); VRC();
553	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
554	"arm,pl061", "arm,primecell"); VRC();
555	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4, 0, 0x09030000, 0, 0x1000); VRC();
556	vrc = RTFdtNodeFinalize(hFdt); VRC();
557
558	uint32_t aPinIrqs[] = { 3, 4, 5, 6 };
559	InsertConfigNode(pDevices, "pci-generic-ecam", &pDev);
560	InsertConfigNode(pDev, "0", &pInst);
561	InsertConfigNode(pInst, "Config", &pCfg);
562	InsertConfigInteger(pCfg, "MmioEcamBase", 0x3f000000);
563	InsertConfigInteger(pCfg, "MmioEcamLength", 0x01000000);
564	InsertConfigInteger(pCfg, "MmioPioBase", 0x3eff0000);
565	InsertConfigInteger(pCfg, "MmioPioSize", 0x0000ffff);
566	InsertConfigInteger(pCfg, "IntPinA", aPinIrqs[0]);
567	InsertConfigInteger(pCfg, "IntPinB", aPinIrqs[1]);
568	InsertConfigInteger(pCfg, "IntPinC", aPinIrqs[2]);
569	InsertConfigInteger(pCfg, "IntPinD", aPinIrqs[3]);
570	vrc = RTFdtNodeAddF(hFdt, "pcie@%RX32", 0x10000000); VRC();
571	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupt-map-mask", 4, 0xf800, 0, 0, 7); VRC();
572
573	uint32_t aIrqCells[32 * 4 * 10]; RT_ZERO(aIrqCells); /* Maximum of 32 devices on the root bus, each supporting 4 interrupts (INTA# ... INTD#). */
574	uint32_t *pau32IrqCell = &aIrqCells[0];
575	uint32_t iIrqPinSwizzle = 0;
576
577	for (uint32_t i = 0; i < 32; i++)
578	{
579	for (uint32_t iIrqPin = 0; iIrqPin < 4; iIrqPin++)
580	{
581	pau32IrqCell[0] = i << 11; /* The dev part, composed as dev.fn. */
582	pau32IrqCell[1] = 0;
583	pau32IrqCell[2] = 0;
584	pau32IrqCell[3] = iIrqPin + 1;
585	pau32IrqCell[4] = idPHandleIntCtrl;
586	pau32IrqCell[5] = 0;
587	pau32IrqCell[6] = 0;
588	pau32IrqCell[7] = 0;
589	pau32IrqCell[8] = aPinIrqs[(iIrqPinSwizzle + iIrqPin) % RT_ELEMENTS(aPinIrqs)];
590	pau32IrqCell[9] = 0x04;
591	pau32IrqCell += 10;
592	}
593
594	iIrqPinSwizzle++;
595	}
596
597	vrc = RTFdtNodePropertyAddCellsU32AsArray(hFdt, "interrupt-map", RT_ELEMENTS(aIrqCells), &aIrqCells[0]);
598	vrc = RTFdtNodePropertyAddU32( hFdt, "#interrupt-cells", 1); VRC();
599	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "ranges", 14,
600	0x1000000, 0, 0, 0, 0x3eff0000, 0, 0x10000,
601	0x2000000, 0, 0x10000000, 0, 0x10000000, 0,
602	0x2eff0000); VRC();
603	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4, 0, 0x3f000000, 0, 0x1000000); VRC();
604	/** @todo msi-map */
605	vrc = RTFdtNodePropertyAddEmpty( hFdt, "dma-coherent"); VRC();
606	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "bus-range", 2, 0, 0xf); VRC();
607	vrc = RTFdtNodePropertyAddU32( hFdt, "linux,pci-domain", 0); VRC();
608	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
609	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 3); VRC();
610	vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "pci"); VRC();
611	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "pci-host-ecam-generic"); VRC();
612	vrc = RTFdtNodeFinalize(hFdt); VRC();
613
614	/*
615	* VMSVGA compliant graphics controller.
616	*/
617	if ( enmGraphicsController != GraphicsControllerType_QemuRamFB
618	&& enmGraphicsController != GraphicsControllerType_Null)
619	{
620	vrc = i_configGraphicsController(pDevices, enmGraphicsController, pBusMgr, pMachine,
621	pGraphicsAdapter, firmwareSettings,
622	true /fForceVmSvga3/, false /fExposeLegacyVga/); VRC();
623	}
624
625	/*
626	* The USB Controllers and input devices.
627	*/
628	#if 0 /** @todo Make us of this and disallow PS/2 for ARM VMs for now. */
629	KeyboardHIDType_T aKbdHID;
630	hrc = pMachine->COMGETTER(KeyboardHIDType)(&aKbdHID); H();
631	#endif
632
633	PointingHIDType_T aPointingHID;
634	hrc = pMachine->COMGETTER(PointingHIDType)(&aPointingHID); H();
635
636	PCFGMNODE pUsbDevices = NULL;
637	vrc = i_configUsb(pMachine, pBusMgr, pRoot, pDevices, KeyboardHIDType_USBKeyboard, aPointingHID, &pUsbDevices);
638
639	/*
640	* Storage controllers.
641	*/
642	bool fFdcEnabled = false;
643	vrc = i_configStorageCtrls(pMachine, pBusMgr, pVMM, pUVM,
644	pDevices, pUsbDevices, NULL /pBiosCfg/, &fFdcEnabled); VRC();
645
646	/*
647	* Network adapters
648	*/
649	std::list<BootNic> llBootNics;
650	vrc = i_configNetworkCtrls(pMachine, pPlatformProperties, chipsetType, pBusMgr,
651	pVMM, pUVM, pDevices, llBootNics); VRC();
652
653	/*
654	* The VMM device.
655	*/
656	vrc = i_configVmmDev(pMachine, pBusMgr, pDevices, true /fMmioReq/); VRC();
657
658	/*
659	* Audio configuration.
660	*/
661	bool fAudioEnabled = false;
662	vrc = i_configAudioCtrl(virtualBox, pMachine, pBusMgr, pDevices,
663	false /fOsXGuest/, &fAudioEnabled); VRC();
664	}
665	catch (ConfigError &x)
666	{
667	RTFdtDestroy(hFdt);
668
669	// InsertConfig threw something:
670	pVMM->pfnVMR3SetError(pUVM, x.m_vrc, RT_SRC_POS, "Caught ConfigError: %Rrc - %s", x.m_vrc, x.what());
671	return x.m_vrc;
672	}
673	catch (HRESULT hrcXcpt)
674	{
675	RTFdtDestroy(hFdt);
676	AssertLogRelMsgFailedReturn(("hrc=%Rhrc\n", hrcXcpt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR);
677	}
678
679	#ifdef VBOX_WITH_EXTPACK
680	/*
681	* Call the extension pack hooks if everything went well thus far.
682	*/
683	if (RT_SUCCESS(vrc))
684	{
685	pAlock->release();
686	vrc = mptrExtPackManager->i_callAllVmConfigureVmmHooks(this, pVM, pVMM);
687	pAlock->acquire();
688	}
689	#endif
690
691	vrc = RTFdtNodeAdd(hFdt, "chosen"); VRC();
692	vrc = RTFdtNodePropertyAddString( hFdt, "stdout-path", "pl011@9000000"); VRC();
693	vrc = RTFdtNodePropertyAddString( hFdt, "stdin-path", "pl011@9000000"); VRC();
694	vrc = RTFdtNodeFinalize(hFdt);
695
696	/* Finalize the FDT and add it to the resource store. */
697	vrc = RTFdtFinalize(hFdt);
698	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
699
700	RTVFSFILE hVfsFileDesc = NIL_RTVFSFILE;
701	vrc = RTVfsMemFileCreate(NIL_RTVFSIOSTREAM, 0 /cbEstimate/, &hVfsFileDesc);
702	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
703	RTVFSIOSTREAM hVfsIosDesc = RTVfsFileToIoStream(hVfsFileDesc);
704	AssertRelease(hVfsIosDesc != NIL_RTVFSIOSTREAM);
705
706	/* Initialize the VBox platform descriptor. */
707	VBOXPLATFORMARMV8 ArmV8Platform; RT_ZERO(ArmV8Platform);
708
709	vrc = RTFdtDumpToVfsIoStrm(hFdt, RTFDTTYPE_DTB, 0 /fFlags/, hVfsIosDesc, NULL /pErrInfo/);
710	if (RT_SUCCESS(vrc))
711	vrc = RTVfsFileQuerySize(hVfsFileDesc, &ArmV8Platform.cbFdt);
712	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
713
714	vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, (RTFOFF)(RT_ALIGN_64(ArmV8Platform.cbFdt, _64K) - ArmV8Platform.cbFdt));
715	AssertRCReturn(vrc, vrc);
716
717	ArmV8Platform.u32Magic = VBOXPLATFORMARMV8_MAGIC;
718	ArmV8Platform.u32Version = VBOXPLATFORMARMV8_VERSION;
719	ArmV8Platform.cbDesc = sizeof(ArmV8Platform);
720	ArmV8Platform.fFlags = 0;
721	ArmV8Platform.u64PhysAddrRamBase = UINT64_C(0x40000000);
722	ArmV8Platform.cbRamBase = cbRam;
723	ArmV8Platform.u64OffBackFdt = RT_ALIGN_64(ArmV8Platform.cbFdt, _64K);
724	ArmV8Platform.cbFdt = RT_ALIGN_64(ArmV8Platform.cbFdt, _64K);
725	ArmV8Platform.u64OffBackAcpiXsdp = 0;
726	ArmV8Platform.cbAcpiXsdp = 0;
727	ArmV8Platform.u64OffBackUefiRom = GCPhysTopOfAddrSpace - sizeof(ArmV8Platform);
728	ArmV8Platform.cbUefiRom = _64M; /** @todo Fixed reservation but the ROM region is usually much smaller. */
729	ArmV8Platform.u64OffBackMmio = GCPhysTopOfAddrSpace - sizeof(ArmV8Platform) - 0x08000000; /** @todo Start of generic MMIO area containing the GIC,UART,RTC, etc. Will be changed soon */
730	ArmV8Platform.cbMmio = _128M;
731
732	/* Add the VBox platform descriptor to the resource store. */
733	vrc = RTVfsIoStrmWrite(hVfsIosDesc, &ArmV8Platform, sizeof(ArmV8Platform), true /fBlocking/, NULL /pcbWritten/);
734	RTVfsIoStrmRelease(hVfsIosDesc);
735	vrc = mptrResourceStore->i_addItem("resources", "VBoxArmV8Desc", hVfsFileDesc);
736	RTVfsFileRelease(hVfsFileDesc);
737	AssertRCReturn(vrc, vrc);
738
739	/* Dump the DTB for debugging purposes if requested. */
740	Bstr DtbDumpVal;
741	hrc = mMachine->GetExtraData(Bstr("VBoxInternal2/DumpDtb").raw(),
742	DtbDumpVal.asOutParam());
743	if ( hrc == S_OK
744	&& DtbDumpVal.isNotEmpty())
745	{
746	vrc = RTFdtDumpToFile(hFdt, RTFDTTYPE_DTB, 0 /fFlags/, Utf8Str(DtbDumpVal).c_str(), NULL /pErrInfo/);
747	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
748	}
749
750
751	/*
752	* Apply the CFGM overlay.
753	*/
754	if (RT_SUCCESS(vrc))
755	vrc = i_configCfgmOverlay(pRoot, virtualBox, pMachine);
756
757	/*
758	* Dump all extradata API settings tweaks, both global and per VM.
759	*/
760	if (RT_SUCCESS(vrc))
761	vrc = i_configDumpAPISettingsTweaks(virtualBox, pMachine);
762
763	#undef H
764
765	pAlock->release(); /* Avoid triggering the lock order inversion check. */
766
767	/*
768	* Register VM state change handler.
769	*/
770	int vrc2 = pVMM->pfnVMR3AtStateRegister(pUVM, Console::i_vmstateChangeCallback, this);
771	AssertRC(vrc2);
772	if (RT_SUCCESS(vrc))
773	vrc = vrc2;
774
775	/*
776	* Register VM runtime error handler.
777	*/
778	vrc2 = pVMM->pfnVMR3AtRuntimeErrorRegister(pUVM, Console::i_atVMRuntimeErrorCallback, this);
779	AssertRC(vrc2);
780	if (RT_SUCCESS(vrc))
781	vrc = vrc2;
782
783	pAlock->acquire();
784
785	LogFlowFunc(("vrc = %Rrc\n", vrc));
786	LogFlowFuncLeave();
787
788	return vrc;
789	}
790	#endif /* !VBOX_WITH_VIRT_ARMV8 */
791

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source: vbox/trunk/src/VBox/Main/src-client/ConsoleImplConfigArmV8.cpp@ 101481

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