1 | /* $Id: BusAssignmentManager.cpp 68371 2017-08-10 13:52:23Z vboxsync $ */
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2 | /** @file
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3 | * VirtualBox bus slots assignment manager
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2010-2016 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | */
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17 |
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18 | #define LOG_GROUP LOG_GROUP_MAIN
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19 | #include "LoggingNew.h"
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20 |
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21 | #include "BusAssignmentManager.h"
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22 |
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23 | #include <iprt/asm.h>
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24 | #include <iprt/string.h>
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25 |
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26 | #include <VBox/vmm/cfgm.h>
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27 | #include <VBox/com/array.h>
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28 |
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29 | #include <map>
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30 | #include <vector>
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31 | #include <algorithm>
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32 |
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33 | struct DeviceAssignmentRule
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34 | {
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35 | const char* pszName;
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36 | int iBus;
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37 | int iDevice;
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38 | int iFn;
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39 | int iPriority;
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40 | };
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41 |
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42 | struct DeviceAliasRule
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43 | {
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44 | const char* pszDevName;
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45 | const char* pszDevAlias;
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46 | };
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47 |
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48 | /* Those rules define PCI slots assignment */
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49 | /** @note
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50 | * The EFI takes assumptions about PCI slot assignments which are different
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51 | * from the following tables in certain cases, for example the IDE device
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52 | * is assumed to be 00:01.1! */
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53 |
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54 | /* Device Bus Device Function Priority */
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55 |
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56 | /* Generic rules */
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57 | static const DeviceAssignmentRule aGenericRules[] =
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58 | {
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59 | /* VGA controller */
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60 | {"vga", 0, 2, 0, 0},
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61 |
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62 | /* VMM device */
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63 | {"VMMDev", 0, 4, 0, 0},
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64 |
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65 | /* Audio controllers */
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66 | {"ichac97", 0, 5, 0, 0},
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67 | {"hda", 0, 5, 0, 0},
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68 |
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69 | /* Storage controllers */
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70 | {"lsilogic", 0, 20, 0, 1},
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71 | {"buslogic", 0, 21, 0, 1},
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72 | {"lsilogicsas", 0, 22, 0, 1},
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73 | {"nvme", 0, 14, 0, 1},
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74 |
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75 | /* USB controllers */
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76 | {"usb-ohci", 0, 6, 0, 0},
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77 | {"usb-ehci", 0, 11, 0, 0},
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78 | {"usb-xhci", 0, 12, 0, 0},
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79 |
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80 | /* ACPI controller */
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81 | {"acpi", 0, 7, 0, 0},
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82 |
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83 | /* Network controllers */
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84 | /* the first network card gets the PCI ID 3, the next 3 gets 8..10,
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85 | * next 4 get 16..19. In "VMWare compatibility" mode the IDs 3 and 17
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86 | * swap places, i.e. the first card goes to ID 17=0x11. */
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87 | {"nic", 0, 3, 0, 1},
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88 | {"nic", 0, 8, 0, 1},
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89 | {"nic", 0, 9, 0, 1},
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90 | {"nic", 0, 10, 0, 1},
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91 | {"nic", 0, 16, 0, 1},
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92 | {"nic", 0, 17, 0, 1},
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93 | {"nic", 0, 18, 0, 1},
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94 | {"nic", 0, 19, 0, 1},
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95 |
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96 | /* ISA/LPC controller */
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97 | {"lpc", 0, 31, 0, 0},
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98 |
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99 | { NULL, -1, -1, -1, 0}
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100 | };
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101 |
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102 | /* PIIX3 chipset rules */
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103 | static const DeviceAssignmentRule aPiix3Rules[] =
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104 | {
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105 | {"piix3ide", 0, 1, 1, 0},
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106 | {"ahci", 0, 13, 0, 1},
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107 | {"pcibridge", 0, 24, 0, 0},
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108 | {"pcibridge", 0, 25, 0, 0},
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109 | { NULL, -1, -1, -1, 0}
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110 | };
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111 |
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112 |
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113 | /* ICH9 chipset rules */
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114 | static const DeviceAssignmentRule aIch9Rules[] =
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115 | {
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116 | /* Host Controller */
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117 | {"i82801", 0, 30, 0, 0},
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118 |
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119 | /* Those are functions of LPC at 00:1e:00 */
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120 | /**
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121 | * Please note, that for devices being functions, like we do here, device 0
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122 | * must be multifunction, i.e. have header type 0x80. Our LPC device is.
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123 | * Alternative approach is to assign separate slot to each device.
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124 | */
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125 | {"piix3ide", 0, 31, 1, 2},
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126 | {"ahci", 0, 31, 2, 2},
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127 | {"smbus", 0, 31, 3, 2},
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128 | {"usb-ohci", 0, 31, 4, 2},
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129 | {"usb-ehci", 0, 31, 5, 2},
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130 | {"thermal", 0, 31, 6, 2},
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131 |
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132 | /* to make sure rule never used before rules assigning devices on it */
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133 | {"ich9pcibridge", 0, 24, 0, 10},
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134 | {"ich9pcibridge", 0, 25, 0, 10},
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135 | {"ich9pcibridge", 1, 24, 0, 9},
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136 | {"ich9pcibridge", 1, 25, 0, 9},
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137 | {"ich9pcibridge", 2, 24, 0, 8},
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138 | {"ich9pcibridge", 2, 25, 0, 8},
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139 | {"ich9pcibridge", 3, 24, 0, 7},
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140 | {"ich9pcibridge", 3, 25, 0, 7},
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141 | {"ich9pcibridge", 4, 24, 0, 6},
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142 | {"ich9pcibridge", 4, 25, 0, 6},
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143 | {"ich9pcibridge", 5, 24, 0, 5},
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144 | {"ich9pcibridge", 5, 25, 0, 5},
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145 |
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146 | /* Storage controllers */
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147 | {"ahci", 1, 0, 0, 0},
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148 | {"ahci", 1, 1, 0, 0},
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149 | {"ahci", 1, 2, 0, 0},
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150 | {"ahci", 1, 3, 0, 0},
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151 | {"ahci", 1, 4, 0, 0},
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152 | {"ahci", 1, 5, 0, 0},
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153 | {"ahci", 1, 6, 0, 0},
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154 | {"lsilogic", 1, 7, 0, 0},
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155 | {"lsilogic", 1, 8, 0, 0},
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156 | {"lsilogic", 1, 9, 0, 0},
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157 | {"lsilogic", 1, 10, 0, 0},
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158 | {"lsilogic", 1, 11, 0, 0},
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159 | {"lsilogic", 1, 12, 0, 0},
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160 | {"lsilogic", 1, 13, 0, 0},
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161 | {"buslogic", 1, 14, 0, 0},
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162 | {"buslogic", 1, 15, 0, 0},
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163 | {"buslogic", 1, 16, 0, 0},
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164 | {"buslogic", 1, 17, 0, 0},
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165 | {"buslogic", 1, 18, 0, 0},
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166 | {"buslogic", 1, 19, 0, 0},
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167 | {"buslogic", 1, 20, 0, 0},
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168 | {"lsilogicsas", 1, 21, 0, 0},
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169 | {"lsilogicsas", 1, 26, 0, 0},
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170 | {"lsilogicsas", 1, 27, 0, 0},
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171 | {"lsilogicsas", 1, 28, 0, 0},
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172 | {"lsilogicsas", 1, 29, 0, 0},
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173 | {"lsilogicsas", 1, 30, 0, 0},
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174 | {"lsilogicsas", 1, 31, 0, 0},
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175 |
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176 | /* NICs */
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177 | {"nic", 2, 0, 0, 0},
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178 | {"nic", 2, 1, 0, 0},
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179 | {"nic", 2, 2, 0, 0},
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180 | {"nic", 2, 3, 0, 0},
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181 | {"nic", 2, 4, 0, 0},
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182 | {"nic", 2, 5, 0, 0},
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183 | {"nic", 2, 6, 0, 0},
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184 | {"nic", 2, 7, 0, 0},
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185 | {"nic", 2, 8, 0, 0},
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186 | {"nic", 2, 9, 0, 0},
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187 | {"nic", 2, 10, 0, 0},
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188 | {"nic", 2, 11, 0, 0},
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189 | {"nic", 2, 12, 0, 0},
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190 | {"nic", 2, 13, 0, 0},
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191 | {"nic", 2, 14, 0, 0},
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192 | {"nic", 2, 15, 0, 0},
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193 | {"nic", 2, 16, 0, 0},
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194 | {"nic", 2, 17, 0, 0},
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195 | {"nic", 2, 18, 0, 0},
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196 | {"nic", 2, 19, 0, 0},
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197 | {"nic", 2, 20, 0, 0},
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198 | {"nic", 2, 21, 0, 0},
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199 | {"nic", 2, 26, 0, 0},
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200 | {"nic", 2, 27, 0, 0},
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201 | {"nic", 2, 28, 0, 0},
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202 | {"nic", 2, 29, 0, 0},
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203 | {"nic", 2, 30, 0, 0},
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204 | {"nic", 2, 31, 0, 0},
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205 |
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206 | /* Storage controller #2 (NVMe) */
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207 | {"nvme", 3, 0, 0, 0},
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208 | {"nvme", 3, 1, 0, 0},
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209 | {"nvme", 3, 2, 0, 0},
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210 | {"nvme", 3, 3, 0, 0},
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211 | {"nvme", 3, 4, 0, 0},
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212 | {"nvme", 3, 5, 0, 0},
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213 | {"nvme", 3, 6, 0, 0},
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214 |
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215 | { NULL, -1, -1, -1, 0}
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216 | };
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217 |
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218 | /* Aliasing rules */
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219 | static const DeviceAliasRule aDeviceAliases[] =
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220 | {
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221 | {"e1000", "nic"},
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222 | {"pcnet", "nic"},
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223 | {"virtio-net", "nic"},
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224 | {"ahci", "storage"},
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225 | {"lsilogic", "storage"},
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226 | {"buslogic", "storage"},
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227 | {"lsilogicsas", "storage"},
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228 | {"nvme", "storage"}
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229 | };
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230 |
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231 | struct BusAssignmentManager::State
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232 | {
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233 | struct PCIDeviceRecord
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234 | {
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235 | char szDevName[32];
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236 | PCIBusAddress HostAddress;
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237 |
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238 | PCIDeviceRecord(const char* pszName, PCIBusAddress aHostAddress)
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239 | {
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240 | RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
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241 | this->HostAddress = aHostAddress;
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242 | }
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243 |
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244 | PCIDeviceRecord(const char* pszName)
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245 | {
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246 | RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
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247 | }
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248 |
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249 | bool operator<(const PCIDeviceRecord &a) const
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250 | {
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251 | return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) < 0;
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252 | }
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253 |
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254 | bool operator==(const PCIDeviceRecord &a) const
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255 | {
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256 | return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) == 0;
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257 | }
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258 | };
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259 |
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260 | typedef std::map<PCIBusAddress,PCIDeviceRecord> PCIMap;
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261 | typedef std::vector<PCIBusAddress> PCIAddrList;
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262 | typedef std::vector<const DeviceAssignmentRule *> PCIRulesList;
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263 | typedef std::map<PCIDeviceRecord,PCIAddrList> ReversePCIMap;
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264 |
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265 | volatile int32_t cRefCnt;
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266 | ChipsetType_T mChipsetType;
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267 | PCIMap mPCIMap;
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268 | ReversePCIMap mReversePCIMap;
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269 |
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270 | State()
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271 | : cRefCnt(1), mChipsetType(ChipsetType_Null)
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272 | {}
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273 | ~State()
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274 | {}
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275 |
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276 | HRESULT init(ChipsetType_T chipsetType);
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277 |
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278 | HRESULT record(const char* pszName, PCIBusAddress& GuestAddress, PCIBusAddress HostAddress);
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279 | HRESULT autoAssign(const char* pszName, PCIBusAddress& Address);
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280 | bool checkAvailable(PCIBusAddress& Address);
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281 | bool findPCIAddress(const char* pszDevName, int iInstance, PCIBusAddress& Address);
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282 |
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283 | const char* findAlias(const char* pszName);
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284 | void addMatchingRules(const char* pszName, PCIRulesList& aList);
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285 | void listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached);
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286 | };
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287 |
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288 | HRESULT BusAssignmentManager::State::init(ChipsetType_T chipsetType)
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289 | {
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290 | mChipsetType = chipsetType;
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291 | return S_OK;
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292 | }
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293 |
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294 | HRESULT BusAssignmentManager::State::record(const char* pszName, PCIBusAddress& Address, PCIBusAddress HostAddress)
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295 | {
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296 | PCIDeviceRecord devRec(pszName, HostAddress);
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297 |
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298 | /* Remember address -> device mapping */
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299 | mPCIMap.insert(PCIMap::value_type(Address, devRec));
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300 |
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301 | ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
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302 | if (it == mReversePCIMap.end())
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303 | {
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304 | mReversePCIMap.insert(ReversePCIMap::value_type(devRec, PCIAddrList()));
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305 | it = mReversePCIMap.find(devRec);
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306 | }
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307 |
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308 | /* Remember device name -> addresses mapping */
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309 | it->second.push_back(Address);
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310 |
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311 | return S_OK;
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312 | }
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313 |
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314 | bool BusAssignmentManager::State::findPCIAddress(const char* pszDevName, int iInstance, PCIBusAddress& Address)
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315 | {
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316 | PCIDeviceRecord devRec(pszDevName);
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317 |
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318 | ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
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319 | if (it == mReversePCIMap.end())
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320 | return false;
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321 |
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322 | if (iInstance >= (int)it->second.size())
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323 | return false;
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324 |
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325 | Address = it->second[iInstance];
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326 | return true;
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327 | }
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328 |
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329 | void BusAssignmentManager::State::addMatchingRules(const char* pszName, PCIRulesList& aList)
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330 | {
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331 | size_t iRuleset, iRule;
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332 | const DeviceAssignmentRule* aArrays[2] = {aGenericRules, NULL};
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333 |
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334 | switch (mChipsetType)
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335 | {
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336 | case ChipsetType_PIIX3:
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337 | aArrays[1] = aPiix3Rules;
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338 | break;
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339 | case ChipsetType_ICH9:
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340 | aArrays[1] = aIch9Rules;
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341 | break;
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342 | default:
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343 | Assert(false);
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344 | break;
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345 | }
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346 |
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347 | for (iRuleset = 0; iRuleset < RT_ELEMENTS(aArrays); iRuleset++)
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348 | {
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349 | if (aArrays[iRuleset] == NULL)
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350 | continue;
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351 |
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352 | for (iRule = 0; aArrays[iRuleset][iRule].pszName != NULL; iRule++)
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353 | {
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354 | if (RTStrCmp(pszName, aArrays[iRuleset][iRule].pszName) == 0)
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355 | aList.push_back(&aArrays[iRuleset][iRule]);
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356 | }
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357 | }
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358 | }
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359 |
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360 | const char* BusAssignmentManager::State::findAlias(const char* pszDev)
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361 | {
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362 | for (size_t iAlias = 0; iAlias < RT_ELEMENTS(aDeviceAliases); iAlias++)
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363 | {
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364 | if (strcmp(pszDev, aDeviceAliases[iAlias].pszDevName) == 0)
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365 | return aDeviceAliases[iAlias].pszDevAlias;
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366 | }
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367 | return NULL;
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368 | }
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369 |
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370 | static bool RuleComparator(const DeviceAssignmentRule* r1, const DeviceAssignmentRule* r2)
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371 | {
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372 | return (r1->iPriority > r2->iPriority);
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373 | }
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374 |
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375 | HRESULT BusAssignmentManager::State::autoAssign(const char* pszName, PCIBusAddress& Address)
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376 | {
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377 | PCIRulesList matchingRules;
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378 |
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379 | addMatchingRules(pszName, matchingRules);
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380 | const char* pszAlias = findAlias(pszName);
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381 | if (pszAlias)
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382 | addMatchingRules(pszAlias, matchingRules);
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383 |
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384 | AssertMsg(matchingRules.size() > 0, ("No rule for %s(%s)\n", pszName, pszAlias));
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385 |
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386 | stable_sort(matchingRules.begin(), matchingRules.end(), RuleComparator);
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387 |
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388 | for (size_t iRule = 0; iRule < matchingRules.size(); iRule++)
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389 | {
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390 | const DeviceAssignmentRule* rule = matchingRules[iRule];
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391 |
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392 | Address.miBus = rule->iBus;
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393 | Address.miDevice = rule->iDevice;
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394 | Address.miFn = rule->iFn;
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395 |
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396 | if (checkAvailable(Address))
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397 | return S_OK;
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398 | }
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399 | AssertMsgFailed(("All possible candidate positions for %s exhausted\n", pszName));
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400 |
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401 | return E_INVALIDARG;
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402 | }
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403 |
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404 | bool BusAssignmentManager::State::checkAvailable(PCIBusAddress& Address)
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405 | {
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406 | PCIMap::const_iterator it = mPCIMap.find(Address);
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407 |
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408 | return (it == mPCIMap.end());
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409 | }
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410 |
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411 | void BusAssignmentManager::State::listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached)
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412 | {
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413 | aAttached.resize(mPCIMap.size());
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414 |
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415 | size_t i = 0;
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416 | PCIDeviceInfo dev;
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417 | for (PCIMap::const_iterator it = mPCIMap.begin(); it != mPCIMap.end(); ++it, ++i)
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418 | {
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419 | dev.strDeviceName = it->second.szDevName;
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420 | dev.guestAddress = it->first;
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421 | dev.hostAddress = it->second.HostAddress;
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422 | aAttached[i] = dev;
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423 | }
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424 | }
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425 |
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426 | BusAssignmentManager::BusAssignmentManager()
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427 | : pState(NULL)
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428 | {
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429 | pState = new State();
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430 | Assert(pState);
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431 | }
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432 |
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433 | BusAssignmentManager::~BusAssignmentManager()
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434 | {
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435 | if (pState)
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436 | {
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437 | delete pState;
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438 | pState = NULL;
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439 | }
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440 | }
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441 |
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442 | BusAssignmentManager* BusAssignmentManager::createInstance(ChipsetType_T chipsetType)
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443 | {
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444 | BusAssignmentManager* pInstance = new BusAssignmentManager();
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445 | pInstance->pState->init(chipsetType);
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446 | Assert(pInstance);
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447 | return pInstance;
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448 | }
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449 |
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450 | void BusAssignmentManager::AddRef()
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451 | {
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452 | ASMAtomicIncS32(&pState->cRefCnt);
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453 | }
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454 | void BusAssignmentManager::Release()
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455 | {
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456 | if (ASMAtomicDecS32(&pState->cRefCnt) == 0)
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457 | delete this;
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458 | }
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459 |
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460 | DECLINLINE(HRESULT) InsertConfigInteger(PCFGMNODE pCfg, const char* pszName, uint64_t u64)
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461 | {
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462 | int vrc = CFGMR3InsertInteger(pCfg, pszName, u64);
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463 | if (RT_FAILURE(vrc))
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464 | return E_INVALIDARG;
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465 |
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466 | return S_OK;
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467 | }
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468 |
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469 | HRESULT BusAssignmentManager::assignPCIDeviceImpl(const char* pszDevName,
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470 | PCFGMNODE pCfg,
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471 | PCIBusAddress& GuestAddress,
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472 | PCIBusAddress HostAddress,
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473 | bool fGuestAddressRequired)
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474 | {
|
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475 | HRESULT rc = S_OK;
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476 |
|
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477 | if (!GuestAddress.valid())
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478 | rc = pState->autoAssign(pszDevName, GuestAddress);
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479 | else
|
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480 | {
|
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481 | bool fAvailable = pState->checkAvailable(GuestAddress);
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482 |
|
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483 | if (!fAvailable)
|
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484 | {
|
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485 | if (fGuestAddressRequired)
|
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486 | rc = E_ACCESSDENIED;
|
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487 | else
|
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488 | rc = pState->autoAssign(pszDevName, GuestAddress);
|
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489 | }
|
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490 | }
|
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491 |
|
---|
492 | if (FAILED(rc))
|
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493 | return rc;
|
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494 |
|
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495 | Assert(GuestAddress.valid() && pState->checkAvailable(GuestAddress));
|
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496 |
|
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497 | rc = pState->record(pszDevName, GuestAddress, HostAddress);
|
---|
498 | if (FAILED(rc))
|
---|
499 | return rc;
|
---|
500 |
|
---|
501 | rc = InsertConfigInteger(pCfg, "PCIBusNo", GuestAddress.miBus);
|
---|
502 | if (FAILED(rc))
|
---|
503 | return rc;
|
---|
504 | rc = InsertConfigInteger(pCfg, "PCIDeviceNo", GuestAddress.miDevice);
|
---|
505 | if (FAILED(rc))
|
---|
506 | return rc;
|
---|
507 | rc = InsertConfigInteger(pCfg, "PCIFunctionNo", GuestAddress.miFn);
|
---|
508 | if (FAILED(rc))
|
---|
509 | return rc;
|
---|
510 |
|
---|
511 | return S_OK;
|
---|
512 | }
|
---|
513 |
|
---|
514 |
|
---|
515 | bool BusAssignmentManager::findPCIAddress(const char* pszDevName, int iInstance, PCIBusAddress& Address)
|
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516 | {
|
---|
517 | return pState->findPCIAddress(pszDevName, iInstance, Address);
|
---|
518 | }
|
---|
519 | void BusAssignmentManager::listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached)
|
---|
520 | {
|
---|
521 | pState->listAttachedPCIDevices(aAttached);
|
---|
522 | }
|
---|