BusAssignmentManager.cpp@ 88311

Last change on this file since 88311 was 87242, checked in by vboxsync, 4 years ago
AMD IOMMU: bugref:9654 Main/API: Adjusted BusAssignmentManager and ConsoleImpl2 to use the newly added API methods.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 19.3 KB

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1	/* $Id: BusAssignmentManager.cpp 87242 2021-01-13 16:02:24Z vboxsync $ */
2	/** @file
3	* VirtualBox bus slots assignment manager
4	*/
5
6	/*
7	* Copyright (C) 2010-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#define LOG_GROUP LOG_GROUP_MAIN
19	#include "LoggingNew.h"
20
21	#include "BusAssignmentManager.h"
22
23	#include <iprt/asm.h>
24	#include <iprt/string.h>
25
26	#include <VBox/vmm/cfgm.h>
27	#include <VBox/com/array.h>
28
29	#include <map>
30	#include <vector>
31	#include <algorithm>
32
33	struct DeviceAssignmentRule
34	{
35	const char *pszName;
36	int iBus;
37	int iDevice;
38	int iFn;
39	int iPriority;
40	};
41
42	struct DeviceAliasRule
43	{
44	const char *pszDevName;
45	const char *pszDevAlias;
46	};
47
48	/* Those rules define PCI slots assignment */
49	/** @note
50	* The EFI takes assumptions about PCI slot assignments which are different
51	* from the following tables in certain cases, for example the IDE device
52	* is assumed to be 00:01.1! */
53
54	/* Device Bus Device Function Priority */
55
56	/* Generic rules */
57	static const DeviceAssignmentRule g_aGenericRules[] =
58	{
59	/* VGA controller */
60	{"vga", 0, 2, 0, 0},
61
62	/* VMM device */
63	{"VMMDev", 0, 4, 0, 0},
64
65	/* Audio controllers */
66	{"ichac97", 0, 5, 0, 0},
67	{"hda", 0, 5, 0, 0},
68
69	/* Storage controllers */
70	{"buslogic", 0, 21, 0, 1},
71	{"lsilogicsas", 0, 22, 0, 1},
72	{"nvme", 0, 14, 0, 1},
73	{"virtio-scsi", 0, 15, 0, 1},
74
75	/* USB controllers */
76	{"usb-ohci", 0, 6, 0, 0},
77	{"usb-ehci", 0, 11, 0, 0},
78	{"usb-xhci", 0, 12, 0, 0},
79
80	/* ACPI controller */
81	#if 0
82	// It really should be this for 440FX chipset (part of PIIX4 actually)
83	{"acpi", 0, 1, 3, 0},
84	#else
85	{"acpi", 0, 7, 0, 0},
86	#endif
87
88	/* Network controllers */
89	/* the first network card gets the PCI ID 3, the next 3 gets 8..10,
90	* next 4 get 16..19. In "VMWare compatibility" mode the IDs 3 and 17
91	* swap places, i.e. the first card goes to ID 17=0x11. */
92	{"nic", 0, 3, 0, 1},
93	{"nic", 0, 8, 0, 1},
94	{"nic", 0, 9, 0, 1},
95	{"nic", 0, 10, 0, 1},
96	{"nic", 0, 16, 0, 1},
97	{"nic", 0, 17, 0, 1},
98	{"nic", 0, 18, 0, 1},
99	{"nic", 0, 19, 0, 1},
100
101	/* ISA/LPC controller */
102	{"lpc", 0, 31, 0, 0},
103
104	{ NULL, -1, -1, -1, 0}
105	};
106
107	/* PIIX3 chipset rules */
108	static const DeviceAssignmentRule g_aPiix3Rules[] =
109	{
110	{"piix3ide", 0, 1, 1, 0},
111	{"ahci", 0, 13, 0, 1},
112	{"lsilogic", 0, 20, 0, 1},
113	{"pcibridge", 0, 24, 0, 0},
114	{"pcibridge", 0, 25, 0, 0},
115	{ NULL, -1, -1, -1, 0}
116	};
117
118
119	/* ICH9 chipset rules */
120	static const DeviceAssignmentRule g_aIch9Rules[] =
121	{
122	/* Host Controller */
123	{"i82801", 0, 30, 0, 0},
124
125	/* Those are functions of LPC at 00:1e:00 */
126	/**
127	* Please note, that for devices being functions, like we do here, device 0
128	* must be multifunction, i.e. have header type 0x80. Our LPC device is.
129	* Alternative approach is to assign separate slot to each device.
130	*/
131	{"piix3ide", 0, 31, 1, 2},
132	{"ahci", 0, 31, 2, 2},
133	{"smbus", 0, 31, 3, 2},
134	{"usb-ohci", 0, 31, 4, 2},
135	{"usb-ehci", 0, 31, 5, 2},
136	{"thermal", 0, 31, 6, 2},
137
138	/* to make sure rule never used before rules assigning devices on it */
139	{"ich9pcibridge", 0, 24, 0, 10},
140	{"ich9pcibridge", 0, 25, 0, 10},
141	{"ich9pcibridge", 2, 24, 0, 9}, /* Bridges must be instantiated depth */
142	{"ich9pcibridge", 2, 25, 0, 9}, /* first (assumption in PDM and other */
143	{"ich9pcibridge", 4, 24, 0, 8}, /* places), so make sure that nested */
144	{"ich9pcibridge", 4, 25, 0, 8}, /* bridges are added to the last bridge */
145	{"ich9pcibridge", 6, 24, 0, 7}, /* only, avoiding the need to re-sort */
146	{"ich9pcibridge", 6, 25, 0, 7}, /* everything before starting the VM. */
147	{"ich9pcibridge", 8, 24, 0, 6},
148	{"ich9pcibridge", 8, 25, 0, 6},
149	{"ich9pcibridge", 10, 24, 0, 5},
150	{"ich9pcibridge", 10, 25, 0, 5},
151
152	/* Storage controllers */
153	{"ahci", 1, 0, 0, 0},
154	{"ahci", 1, 1, 0, 0},
155	{"ahci", 1, 2, 0, 0},
156	{"ahci", 1, 3, 0, 0},
157	{"ahci", 1, 4, 0, 0},
158	{"ahci", 1, 5, 0, 0},
159	{"ahci", 1, 6, 0, 0},
160	{"lsilogic", 1, 7, 0, 0},
161	{"lsilogic", 1, 8, 0, 0},
162	{"lsilogic", 1, 9, 0, 0},
163	{"lsilogic", 1, 10, 0, 0},
164	{"lsilogic", 1, 11, 0, 0},
165	{"lsilogic", 1, 12, 0, 0},
166	{"lsilogic", 1, 13, 0, 0},
167	{"buslogic", 1, 14, 0, 0},
168	{"buslogic", 1, 15, 0, 0},
169	{"buslogic", 1, 16, 0, 0},
170	{"buslogic", 1, 17, 0, 0},
171	{"buslogic", 1, 18, 0, 0},
172	{"buslogic", 1, 19, 0, 0},
173	{"buslogic", 1, 20, 0, 0},
174	{"lsilogicsas", 1, 21, 0, 0},
175	{"lsilogicsas", 1, 26, 0, 0},
176	{"lsilogicsas", 1, 27, 0, 0},
177	{"lsilogicsas", 1, 28, 0, 0},
178	{"lsilogicsas", 1, 29, 0, 0},
179	{"lsilogicsas", 1, 30, 0, 0},
180	{"lsilogicsas", 1, 31, 0, 0},
181
182	/* NICs */
183	{"nic", 2, 0, 0, 0},
184	{"nic", 2, 1, 0, 0},
185	{"nic", 2, 2, 0, 0},
186	{"nic", 2, 3, 0, 0},
187	{"nic", 2, 4, 0, 0},
188	{"nic", 2, 5, 0, 0},
189	{"nic", 2, 6, 0, 0},
190	{"nic", 2, 7, 0, 0},
191	{"nic", 2, 8, 0, 0},
192	{"nic", 2, 9, 0, 0},
193	{"nic", 2, 10, 0, 0},
194	{"nic", 2, 11, 0, 0},
195	{"nic", 2, 12, 0, 0},
196	{"nic", 2, 13, 0, 0},
197	{"nic", 2, 14, 0, 0},
198	{"nic", 2, 15, 0, 0},
199	{"nic", 2, 16, 0, 0},
200	{"nic", 2, 17, 0, 0},
201	{"nic", 2, 18, 0, 0},
202	{"nic", 2, 19, 0, 0},
203	{"nic", 2, 20, 0, 0},
204	{"nic", 2, 21, 0, 0},
205	{"nic", 2, 26, 0, 0},
206	{"nic", 2, 27, 0, 0},
207	{"nic", 2, 28, 0, 0},
208	{"nic", 2, 29, 0, 0},
209	{"nic", 2, 30, 0, 0},
210	{"nic", 2, 31, 0, 0},
211
212	/* Storage controller #2 (NVMe, virtio-scsi) */
213	{"nvme", 3, 0, 0, 0},
214	{"nvme", 3, 1, 0, 0},
215	{"nvme", 3, 2, 0, 0},
216	{"nvme", 3, 3, 0, 0},
217	{"nvme", 3, 4, 0, 0},
218	{"nvme", 3, 5, 0, 0},
219	{"nvme", 3, 6, 0, 0},
220	{"virtio-scsi", 3, 7, 0, 0},
221	{"virtio-scsi", 3, 8, 0, 0},
222	{"virtio-scsi", 3, 9, 0, 0},
223	{"virtio-scsi", 3, 10, 0, 0},
224	{"virtio-scsi", 3, 11, 0, 0},
225	{"virtio-scsi", 3, 12, 0, 0},
226	{"virtio-scsi", 3, 13, 0, 0},
227
228	{ NULL, -1, -1, -1, 0}
229	};
230
231
232	#ifdef VBOX_WITH_IOMMU_AMD
233	/*
234	* AMD IOMMU and LSI Logic controller rules.
235	*
236	* Since the PCI slot (BDF=00:20.0) of the LSI Logic controller
237	* conflicts with the SB I/O APIC, we assign the LSI Logic controller
238	* to device number 23 when the VM is configured for an AMD IOMMU.
239	*/
240	static const DeviceAssignmentRule g_aIch9IommuLsiRules[] =
241	{
242	/* AMD IOMMU. */
243	{"iommu-amd", 0, 0, 0, 0},
244	/* AMD IOMMU: Reserved for southbridge I/O APIC. */
245	{"sb-ioapic", 0, 20, 0, 0},
246
247	/* Storage controller */
248	{"lsilogic", 0, 23, 0, 1},
249	{ NULL, -1, -1, -1, 0}
250	};
251	#endif
252
253	/* LSI Logic Controller. */
254	static const DeviceAssignmentRule g_aIch9LsiRules[] =
255	{
256	/* Storage controller */
257	{"lsilogic", 0, 20, 0, 1},
258	{ NULL, -1, -1, -1, 0}
259	};
260
261	/* Aliasing rules */
262	static const DeviceAliasRule g_aDeviceAliases[] =
263	{
264	{"e1000", "nic"},
265	{"pcnet", "nic"},
266	{"virtio-net", "nic"},
267	{"ahci", "storage"},
268	{"lsilogic", "storage"},
269	{"buslogic", "storage"},
270	{"lsilogicsas", "storage"},
271	{"nvme", "storage"},
272	{"virtio-scsi", "storage"}
273	};
274
275	struct BusAssignmentManager::State
276	{
277	struct PCIDeviceRecord
278	{
279	char szDevName[32];
280	PCIBusAddress HostAddress;
281
282	PCIDeviceRecord(const char *pszName, PCIBusAddress aHostAddress)
283	{
284	RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
285	this->HostAddress = aHostAddress;
286	}
287
288	PCIDeviceRecord(const char *pszName)
289	{
290	RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
291	}
292
293	bool operator<(const PCIDeviceRecord &a) const
294	{
295	return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) < 0;
296	}
297
298	bool operator==(const PCIDeviceRecord &a) const
299	{
300	return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) == 0;
301	}
302	};
303
304	typedef std::map<PCIBusAddress,PCIDeviceRecord> PCIMap;
305	typedef std::vector<PCIBusAddress> PCIAddrList;
306	typedef std::vector<const DeviceAssignmentRule *> PCIRulesList;
307	typedef std::map<PCIDeviceRecord,PCIAddrList> ReversePCIMap;
308
309	volatile int32_t cRefCnt;
310	ChipsetType_T mChipsetType;
311	const char * mpszBridgeName;
312	IommuType_T mIommuType;
313	PCIMap mPCIMap;
314	ReversePCIMap mReversePCIMap;
315
316	State()
317	: cRefCnt(1), mChipsetType(ChipsetType_Null), mpszBridgeName("unknownbridge")
318	{}
319	~State()
320	{}
321
322	HRESULT init(ChipsetType_T chipsetType, IommuType_T iommuType);
323
324	HRESULT record(const char *pszName, PCIBusAddress& GuestAddress, PCIBusAddress HostAddress);
325	HRESULT autoAssign(const char *pszName, PCIBusAddress& Address);
326	bool checkAvailable(PCIBusAddress& Address);
327	bool findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address);
328
329	const char findAlias(const char pszName);
330	void addMatchingRules(const char *pszName, PCIRulesList& aList);
331	void listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached);
332	};
333
334	HRESULT BusAssignmentManager::State::init(ChipsetType_T chipsetType, IommuType_T iommuType)
335	{
336	/* Currently we only support AMD IOMMU. */
337	Assert(iommuType == IommuType_None \|\| iommuType == IommuType_AMD);
338
339	mChipsetType = chipsetType;
340	mIommuType = iommuType;
341	switch (chipsetType)
342	{
343	case ChipsetType_PIIX3:
344	mpszBridgeName = "pcibridge";
345	break;
346	case ChipsetType_ICH9:
347	mpszBridgeName = "ich9pcibridge";
348	break;
349	default:
350	mpszBridgeName = "unknownbridge";
351	AssertFailed();
352	break;
353	}
354	return S_OK;
355	}
356
357	HRESULT BusAssignmentManager::State::record(const char *pszName, PCIBusAddress& Address, PCIBusAddress HostAddress)
358	{
359	PCIDeviceRecord devRec(pszName, HostAddress);
360
361	/* Remember address -> device mapping */
362	mPCIMap.insert(PCIMap::value_type(Address, devRec));
363
364	ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
365	if (it == mReversePCIMap.end())
366	{
367	mReversePCIMap.insert(ReversePCIMap::value_type(devRec, PCIAddrList()));
368	it = mReversePCIMap.find(devRec);
369	}
370
371	/* Remember device name -> addresses mapping */
372	it->second.push_back(Address);
373
374	return S_OK;
375	}
376
377	bool BusAssignmentManager::State::findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address)
378	{
379	PCIDeviceRecord devRec(pszDevName);
380
381	ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
382	if (it == mReversePCIMap.end())
383	return false;
384
385	if (iInstance >= (int)it->second.size())
386	return false;
387
388	Address = it->second[iInstance];
389	return true;
390	}
391
392	void BusAssignmentManager::State::addMatchingRules(const char *pszName, PCIRulesList& aList)
393	{
394	size_t iRuleset, iRule;
395	const DeviceAssignmentRule *aArrays[3] = {g_aGenericRules, NULL, NULL};
396
397	switch (mChipsetType)
398	{
399	case ChipsetType_PIIX3:
400	aArrays[1] = g_aPiix3Rules;
401	break;
402	case ChipsetType_ICH9:
403	{
404	aArrays[1] = g_aIch9Rules;
405	#ifdef VBOX_WITH_IOMMU_AMD
406	if (mIommuType == IommuType_AMD)
407	aArrays[2] = g_aIch9IommuLsiRules;
408	else
409	#endif
410	{
411	aArrays[2] = g_aIch9LsiRules;
412	}
413	break;
414	}
415	default:
416	AssertFailed();
417	break;
418	}
419
420	for (iRuleset = 0; iRuleset < RT_ELEMENTS(aArrays); iRuleset++)
421	{
422	if (aArrays[iRuleset] == NULL)
423	continue;
424
425	for (iRule = 0; aArrays[iRuleset][iRule].pszName != NULL; iRule++)
426	{
427	if (RTStrCmp(pszName, aArrays[iRuleset][iRule].pszName) == 0)
428	aList.push_back(&aArrays[iRuleset][iRule]);
429	}
430	}
431	}
432
433	const char BusAssignmentManager::State::findAlias(const char pszDev)
434	{
435	for (size_t iAlias = 0; iAlias < RT_ELEMENTS(g_aDeviceAliases); iAlias++)
436	{
437	if (strcmp(pszDev, g_aDeviceAliases[iAlias].pszDevName) == 0)
438	return g_aDeviceAliases[iAlias].pszDevAlias;
439	}
440	return NULL;
441	}
442
443	static bool RuleComparator(const DeviceAssignmentRule r1, const DeviceAssignmentRule r2)
444	{
445	return (r1->iPriority > r2->iPriority);
446	}
447
448	HRESULT BusAssignmentManager::State::autoAssign(const char *pszName, PCIBusAddress& Address)
449	{
450	PCIRulesList matchingRules;
451
452	addMatchingRules(pszName, matchingRules);
453	const char *pszAlias = findAlias(pszName);
454	if (pszAlias)
455	addMatchingRules(pszAlias, matchingRules);
456
457	AssertMsg(matchingRules.size() > 0, ("No rule for %s(%s)\n", pszName, pszAlias));
458
459	stable_sort(matchingRules.begin(), matchingRules.end(), RuleComparator);
460
461	for (size_t iRule = 0; iRule < matchingRules.size(); iRule++)
462	{
463	const DeviceAssignmentRule *rule = matchingRules[iRule];
464
465	Address.miBus = rule->iBus;
466	Address.miDevice = rule->iDevice;
467	Address.miFn = rule->iFn;
468
469	if (checkAvailable(Address))
470	return S_OK;
471	}
472	AssertLogRelMsgFailed(("BusAssignmentManager: All possible candidate positions for %s exhausted\n", pszName));
473
474	return E_INVALIDARG;
475	}
476
477	bool BusAssignmentManager::State::checkAvailable(PCIBusAddress& Address)
478	{
479	PCIMap::const_iterator it = mPCIMap.find(Address);
480
481	return (it == mPCIMap.end());
482	}
483
484	void BusAssignmentManager::State::listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached)
485	{
486	aAttached.resize(mPCIMap.size());
487
488	size_t i = 0;
489	PCIDeviceInfo dev;
490	for (PCIMap::const_iterator it = mPCIMap.begin(); it != mPCIMap.end(); ++it, ++i)
491	{
492	dev.strDeviceName = it->second.szDevName;
493	dev.guestAddress = it->first;
494	dev.hostAddress = it->second.HostAddress;
495	aAttached[i] = dev;
496	}
497	}
498
499	BusAssignmentManager::BusAssignmentManager()
500	: pState(NULL)
501	{
502	pState = new State();
503	Assert(pState);
504	}
505
506	BusAssignmentManager::~BusAssignmentManager()
507	{
508	if (pState)
509	{
510	delete pState;
511	pState = NULL;
512	}
513	}
514
515	BusAssignmentManager *BusAssignmentManager::createInstance(ChipsetType_T chipsetType, IommuType_T iommuType)
516	{
517	BusAssignmentManager *pInstance = new BusAssignmentManager();
518	pInstance->pState->init(chipsetType, iommuType);
519	Assert(pInstance);
520	return pInstance;
521	}
522
523	void BusAssignmentManager::AddRef()
524	{
525	ASMAtomicIncS32(&pState->cRefCnt);
526	}
527	void BusAssignmentManager::Release()
528	{
529	if (ASMAtomicDecS32(&pState->cRefCnt) == 0)
530	delete this;
531	}
532
533	DECLINLINE(HRESULT) InsertConfigInteger(PCFGMNODE pCfg, const char *pszName, uint64_t u64)
534	{
535	int vrc = CFGMR3InsertInteger(pCfg, pszName, u64);
536	if (RT_FAILURE(vrc))
537	return E_INVALIDARG;
538
539	return S_OK;
540	}
541
542	DECLINLINE(HRESULT) InsertConfigNode(PCFGMNODE pNode, const char pcszName, PCFGMNODE ppChild)
543	{
544	int vrc = CFGMR3InsertNode(pNode, pcszName, ppChild);
545	if (RT_FAILURE(vrc))
546	return E_INVALIDARG;
547
548	return S_OK;
549	}
550
551
552	HRESULT BusAssignmentManager::assignPCIDeviceImpl(const char *pszDevName,
553	PCFGMNODE pCfg,
554	PCIBusAddress& GuestAddress,
555	PCIBusAddress HostAddress,
556	bool fGuestAddressRequired)
557	{
558	HRESULT rc = S_OK;
559
560	if (!GuestAddress.valid())
561	rc = pState->autoAssign(pszDevName, GuestAddress);
562	else
563	{
564	bool fAvailable = pState->checkAvailable(GuestAddress);
565
566	if (!fAvailable)
567	{
568	if (fGuestAddressRequired)
569	rc = E_ACCESSDENIED;
570	else
571	rc = pState->autoAssign(pszDevName, GuestAddress);
572	}
573	}
574
575	if (FAILED(rc))
576	return rc;
577
578	Assert(GuestAddress.valid() && pState->checkAvailable(GuestAddress));
579
580	rc = pState->record(pszDevName, GuestAddress, HostAddress);
581	if (FAILED(rc))
582	return rc;
583
584	if (pCfg)
585	{
586	rc = InsertConfigInteger(pCfg, "PCIBusNo", GuestAddress.miBus);
587	if (FAILED(rc))
588	return rc;
589	rc = InsertConfigInteger(pCfg, "PCIDeviceNo", GuestAddress.miDevice);
590	if (FAILED(rc))
591	return rc;
592	rc = InsertConfigInteger(pCfg, "PCIFunctionNo", GuestAddress.miFn);
593	if (FAILED(rc))
594	return rc;
595	}
596
597	/* Check if the bus is still unknown, i.e. the bridge to it is missing */
598	if ( GuestAddress.miBus > 0
599	&& !hasPCIDevice(pState->mpszBridgeName, GuestAddress.miBus - 1))
600	{
601	PCFGMNODE pDevices = CFGMR3GetParent(CFGMR3GetParent(pCfg));
602	AssertLogRelMsgReturn(pDevices, ("BusAssignmentManager: cannot find base device configuration\n"), E_UNEXPECTED);
603	PCFGMNODE pBridges = CFGMR3GetChild(pDevices, "ich9pcibridge");
604	AssertLogRelMsgReturn(pBridges, ("BusAssignmentManager: cannot find bridge configuration base\n"), E_UNEXPECTED);
605
606	/* Device should be on a not yet existing bus, add it automatically */
607	for (int iBridge = 0; iBridge <= GuestAddress.miBus - 1; iBridge++)
608	{
609	if (!hasPCIDevice(pState->mpszBridgeName, iBridge))
610	{
611	PCIBusAddress BridgeGuestAddress;
612	rc = pState->autoAssign(pState->mpszBridgeName, BridgeGuestAddress);
613	if (FAILED(rc))
614	return rc;
615	if (BridgeGuestAddress.miBus > iBridge)
616	AssertLogRelMsgFailedReturn(("BusAssignmentManager: cannot create bridge for bus %i because the possible parent bus positions are exhausted\n", iBridge + 1), E_UNEXPECTED);
617
618	PCFGMNODE pInst;
619	InsertConfigNode(pBridges, Utf8StrFmt("%d", iBridge).c_str(), &pInst);
620	InsertConfigInteger(pInst, "Trusted", 1);
621	rc = assignPCIDevice(pState->mpszBridgeName, pInst);
622	if (FAILED(rc))
623	return rc;
624	}
625	}
626	}
627
628	return S_OK;
629	}
630
631
632	bool BusAssignmentManager::findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address)
633	{
634	return pState->findPCIAddress(pszDevName, iInstance, Address);
635	}
636	void BusAssignmentManager::listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached)
637	{
638	pState->listAttachedPCIDevices(aAttached);
639	}

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source: vbox/trunk/src/VBox/Main/src-client/BusAssignmentManager.cpp@ 88311

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