VirtualBox

source: vbox/trunk/src/VBox/Main/src-client/BusAssignmentManager.cpp@ 47148

Last change on this file since 47148 was 42826, checked in by vboxsync, 12 years ago

Main: Put AHCI to 0:13:0 only for old chipset.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 14.7 KB
Line 
1/* $Id: BusAssignmentManager.cpp 42826 2012-08-15 15:17:55Z vboxsync $ */
2
3/** @file
4 *
5 * VirtualBox bus slots assignment manager
6 */
7
8/*
9 * Copyright (C) 2010-2012 Oracle Corporation
10 *
11 * This file is part of VirtualBox Open Source Edition (OSE), as
12 * available from http://www.virtualbox.org. This file is free software;
13 * you can redistribute it and/or modify it under the terms of the GNU
14 * General Public License (GPL) as published by the Free Software
15 * Foundation, in version 2 as it comes in the "COPYING" file of the
16 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18 */
19#include "BusAssignmentManager.h"
20
21#include <iprt/asm.h>
22#include <iprt/string.h>
23
24#include <VBox/vmm/cfgm.h>
25#include <VBox/com/array.h>
26
27
28#include "PCIDeviceAttachmentImpl.h"
29
30#include <map>
31#include <vector>
32#include <algorithm>
33
34struct DeviceAssignmentRule
35{
36 const char* pszName;
37 int iBus;
38 int iDevice;
39 int iFn;
40 int iPriority;
41};
42
43struct DeviceAliasRule
44{
45 const char* pszDevName;
46 const char* pszDevAlias;
47};
48
49/* Those rules define PCI slots assignment */
50
51/* Device Bus Device Function Priority */
52
53/* Generic rules */
54static const DeviceAssignmentRule aGenericRules[] =
55{
56 /* VGA controller */
57 {"vga", 0, 2, 0, 0},
58
59 /* VMM device */
60 {"VMMDev", 0, 4, 0, 0},
61
62 /* Audio controllers */
63 {"ichac97", 0, 5, 0, 0},
64 {"hda", 0, 5, 0, 0},
65
66 /* Storage controllers */
67 {"lsilogic", 0, 20, 0, 1},
68 {"buslogic", 0, 21, 0, 1},
69 {"lsilogicsas", 0, 22, 0, 1},
70
71 /* USB controllers */
72 {"usb-ohci", 0, 6, 0, 0},
73 {"usb-ehci", 0, 11, 0, 0},
74
75 /* ACPI controller */
76 {"acpi", 0, 7, 0, 0},
77
78 /* Network controllers */
79 /* the first network card gets the PCI ID 3, the next 3 gets 8..10,
80 * next 4 get 16..19. */
81 {"nic", 0, 3, 0, 1},
82 {"nic", 0, 8, 0, 1},
83 {"nic", 0, 9, 0, 1},
84 {"nic", 0, 10, 0, 1},
85 {"nic", 0, 16, 0, 1},
86 {"nic", 0, 17, 0, 1},
87 {"nic", 0, 18, 0, 1},
88 {"nic", 0, 19, 0, 1},
89 /* VMWare assigns first NIC to slot 11 */
90 {"nic-vmware", 0, 11, 0, 1},
91
92 /* ISA/LPC controller */
93 {"lpc", 0, 31, 0, 0},
94
95 { NULL, -1, -1, -1, 0}
96};
97
98/* PIIX3 chipset rules */
99static const DeviceAssignmentRule aPiix3Rules[] =
100{
101 {"piix3ide", 0, 1, 1, 0},
102 {"ahci", 0, 13, 0, 1},
103 {"pcibridge", 0, 24, 0, 0},
104 {"pcibridge", 0, 25, 0, 0},
105 { NULL, -1, -1, -1, 0}
106};
107
108
109/* ICH9 chipset rules */
110static const DeviceAssignmentRule aIch9Rules[] =
111{
112 /* Host Controller */
113 {"i82801", 0, 30, 0, 0},
114
115 /* Those are functions of LPC at 00:1e:00 */
116 /**
117 * Please note, that for devices being functions, like we do here, device 0
118 * must be multifunction, i.e. have header type 0x80. Our LPC device is.
119 * Alternative approach is to assign separate slot to each device.
120 */
121 {"piix3ide", 0, 31, 1, 2},
122 {"ahci", 0, 31, 2, 2},
123 {"smbus", 0, 31, 3, 2},
124 {"usb-ohci", 0, 31, 4, 2},
125 {"usb-ehci", 0, 31, 5, 2},
126 {"thermal", 0, 31, 6, 2},
127
128 /* to make sure rule never used before rules assigning devices on it */
129 {"ich9pcibridge", 0, 24, 0, 10},
130 {"ich9pcibridge", 0, 25, 0, 10},
131 {"ich9pcibridge", 1, 24, 0, 9},
132 {"ich9pcibridge", 1, 25, 0, 9},
133 {"ich9pcibridge", 2, 24, 0, 8},
134 {"ich9pcibridge", 2, 25, 0, 8},
135 {"ich9pcibridge", 3, 24, 0, 7},
136 {"ich9pcibridge", 3, 25, 0, 7},
137 {"ich9pcibridge", 4, 24, 0, 6},
138 {"ich9pcibridge", 4, 25, 0, 6},
139 {"ich9pcibridge", 5, 24, 0, 5},
140 {"ich9pcibridge", 5, 25, 0, 5},
141
142 /* Storage controllers */
143 {"ahci", 1, 0, 0, 0},
144 {"ahci", 1, 1, 0, 0},
145 {"ahci", 1, 2, 0, 0},
146 {"ahci", 1, 3, 0, 0},
147 {"ahci", 1, 4, 0, 0},
148 {"ahci", 1, 5, 0, 0},
149 {"ahci", 1, 6, 0, 0},
150 {"lsilogic", 1, 7, 0, 0},
151 {"lsilogic", 1, 8, 0, 0},
152 {"lsilogic", 1, 9, 0, 0},
153 {"lsilogic", 1, 10, 0, 0},
154 {"lsilogic", 1, 11, 0, 0},
155 {"lsilogic", 1, 12, 0, 0},
156 {"lsilogic", 1, 13, 0, 0},
157 {"buslogic", 1, 14, 0, 0},
158 {"buslogic", 1, 15, 0, 0},
159 {"buslogic", 1, 16, 0, 0},
160 {"buslogic", 1, 17, 0, 0},
161 {"buslogic", 1, 18, 0, 0},
162 {"buslogic", 1, 19, 0, 0},
163 {"buslogic", 1, 20, 0, 0},
164 {"lsilogicsas", 1, 21, 0, 0},
165 {"lsilogicsas", 1, 26, 0, 0},
166 {"lsilogicsas", 1, 27, 0, 0},
167 {"lsilogicsas", 1, 28, 0, 0},
168 {"lsilogicsas", 1, 29, 0, 0},
169 {"lsilogicsas", 1, 30, 0, 0},
170 {"lsilogicsas", 1, 31, 0, 0},
171
172 /* NICs */
173 {"nic", 2, 0, 0, 0},
174 {"nic", 2, 1, 0, 0},
175 {"nic", 2, 2, 0, 0},
176 {"nic", 2, 3, 0, 0},
177 {"nic", 2, 4, 0, 0},
178 {"nic", 2, 5, 0, 0},
179 {"nic", 2, 6, 0, 0},
180 {"nic", 2, 7, 0, 0},
181 {"nic", 2, 8, 0, 0},
182 {"nic", 2, 9, 0, 0},
183 {"nic", 2, 10, 0, 0},
184 {"nic", 2, 11, 0, 0},
185 {"nic", 2, 12, 0, 0},
186 {"nic", 2, 13, 0, 0},
187 {"nic", 2, 14, 0, 0},
188 {"nic", 2, 15, 0, 0},
189 {"nic", 2, 16, 0, 0},
190 {"nic", 2, 17, 0, 0},
191 {"nic", 2, 18, 0, 0},
192 {"nic", 2, 19, 0, 0},
193 {"nic", 2, 20, 0, 0},
194 {"nic", 2, 21, 0, 0},
195 {"nic", 2, 26, 0, 0},
196 {"nic", 2, 27, 0, 0},
197 {"nic", 2, 28, 0, 0},
198 {"nic", 2, 29, 0, 0},
199 {"nic", 2, 30, 0, 0},
200 {"nic", 2, 31, 0, 0},
201
202 { NULL, -1, -1, -1, 0}
203};
204
205/* Aliasing rules */
206static const DeviceAliasRule aDeviceAliases[] =
207{
208 {"e1000", "nic"},
209 {"pcnet", "nic"},
210 {"virtio-net", "nic"},
211 {"ahci", "storage"},
212 {"lsilogic", "storage"},
213 {"buslogic", "storage"},
214 {"lsilogicsas", "storage"}
215};
216
217struct BusAssignmentManager::State
218{
219 struct PCIDeviceRecord
220 {
221 char szDevName[32];
222 PCIBusAddress HostAddress;
223
224 PCIDeviceRecord(const char* pszName, PCIBusAddress aHostAddress)
225 {
226 RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
227 this->HostAddress = aHostAddress;
228 }
229
230 PCIDeviceRecord(const char* pszName)
231 {
232 RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
233 }
234
235 bool operator<(const PCIDeviceRecord &a) const
236 {
237 return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) < 0;
238 }
239
240 bool operator==(const PCIDeviceRecord &a) const
241 {
242 return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) == 0;
243 }
244 };
245
246 typedef std::map <PCIBusAddress,PCIDeviceRecord > PCIMap;
247 typedef std::vector<PCIBusAddress> PCIAddrList;
248 typedef std::vector<const DeviceAssignmentRule*> PCIRulesList;
249 typedef std::map <PCIDeviceRecord,PCIAddrList > ReversePCIMap;
250
251 volatile int32_t cRefCnt;
252 ChipsetType_T mChipsetType;
253 PCIMap mPCIMap;
254 ReversePCIMap mReversePCIMap;
255
256 State()
257 : cRefCnt(1), mChipsetType(ChipsetType_Null)
258 {}
259 ~State()
260 {}
261
262 HRESULT init(ChipsetType_T chipsetType);
263
264 HRESULT record(const char* pszName, PCIBusAddress& GuestAddress, PCIBusAddress HostAddress);
265 HRESULT autoAssign(const char* pszName, PCIBusAddress& Address);
266 bool checkAvailable(PCIBusAddress& Address);
267 bool findPCIAddress(const char* pszDevName, int iInstance, PCIBusAddress& Address);
268
269 const char* findAlias(const char* pszName);
270 void addMatchingRules(const char* pszName, PCIRulesList& aList);
271 void listAttachedPCIDevices(ComSafeArrayOut(IPCIDeviceAttachment*, aAttached));
272};
273
274HRESULT BusAssignmentManager::State::init(ChipsetType_T chipsetType)
275{
276 mChipsetType = chipsetType;
277 return S_OK;
278}
279
280HRESULT BusAssignmentManager::State::record(const char* pszName, PCIBusAddress& Address, PCIBusAddress HostAddress)
281{
282 PCIDeviceRecord devRec(pszName, HostAddress);
283
284 /* Remember address -> device mapping */
285 mPCIMap.insert(PCIMap::value_type(Address, devRec));
286
287 ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
288 if (it == mReversePCIMap.end())
289 {
290 mReversePCIMap.insert(ReversePCIMap::value_type(devRec, PCIAddrList()));
291 it = mReversePCIMap.find(devRec);
292 }
293
294 /* Remember device name -> addresses mapping */
295 it->second.push_back(Address);
296
297 return S_OK;
298}
299
300bool BusAssignmentManager::State::findPCIAddress(const char* pszDevName, int iInstance, PCIBusAddress& Address)
301{
302 PCIDeviceRecord devRec(pszDevName);
303
304 ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
305 if (it == mReversePCIMap.end())
306 return false;
307
308 if (iInstance >= (int)it->second.size())
309 return false;
310
311 Address = it->second[iInstance];
312 return true;
313}
314
315void BusAssignmentManager::State::addMatchingRules(const char* pszName, PCIRulesList& aList)
316{
317 size_t iRuleset, iRule;
318 const DeviceAssignmentRule* aArrays[2] = {aGenericRules, NULL};
319
320 switch (mChipsetType)
321 {
322 case ChipsetType_PIIX3:
323 aArrays[1] = aPiix3Rules;
324 break;
325 case ChipsetType_ICH9:
326 aArrays[1] = aIch9Rules;
327 break;
328 default:
329 Assert(false);
330 break;
331 }
332
333 for (iRuleset = 0; iRuleset < RT_ELEMENTS(aArrays); iRuleset++)
334 {
335 if (aArrays[iRuleset] == NULL)
336 continue;
337
338 for (iRule = 0; aArrays[iRuleset][iRule].pszName != NULL; iRule++)
339 {
340 if (RTStrCmp(pszName, aArrays[iRuleset][iRule].pszName) == 0)
341 aList.push_back(&aArrays[iRuleset][iRule]);
342 }
343 }
344}
345
346const char* BusAssignmentManager::State::findAlias(const char* pszDev)
347{
348 for (size_t iAlias = 0; iAlias < RT_ELEMENTS(aDeviceAliases); iAlias++)
349 {
350 if (strcmp(pszDev, aDeviceAliases[iAlias].pszDevName) == 0)
351 return aDeviceAliases[iAlias].pszDevAlias;
352 }
353 return NULL;
354}
355
356static bool RuleComparator(const DeviceAssignmentRule* r1, const DeviceAssignmentRule* r2)
357{
358 return (r1->iPriority > r2->iPriority);
359}
360
361HRESULT BusAssignmentManager::State::autoAssign(const char* pszName, PCIBusAddress& Address)
362{
363 PCIRulesList matchingRules;
364
365 addMatchingRules(pszName, matchingRules);
366 const char* pszAlias = findAlias(pszName);
367 if (pszAlias)
368 addMatchingRules(pszAlias, matchingRules);
369
370 AssertMsg(matchingRules.size() > 0, ("No rule for %s(%s)\n", pszName, pszAlias));
371
372 stable_sort(matchingRules.begin(), matchingRules.end(), RuleComparator);
373
374 for (size_t iRule = 0; iRule < matchingRules.size(); iRule++)
375 {
376 const DeviceAssignmentRule* rule = matchingRules[iRule];
377
378 Address.miBus = rule->iBus;
379 Address.miDevice = rule->iDevice;
380 Address.miFn = rule->iFn;
381
382 if (checkAvailable(Address))
383 return S_OK;
384 }
385 AssertMsgFailed(("All possible candidate positions for %s exhausted\n", pszName));
386
387 return E_INVALIDARG;
388}
389
390bool BusAssignmentManager::State::checkAvailable(PCIBusAddress& Address)
391{
392 PCIMap::const_iterator it = mPCIMap.find(Address);
393
394 return (it == mPCIMap.end());
395}
396
397
398void BusAssignmentManager::State::listAttachedPCIDevices(ComSafeArrayOut(IPCIDeviceAttachment*, aAttached))
399{
400 com::SafeIfaceArray<IPCIDeviceAttachment> result(mPCIMap.size());
401
402 size_t iIndex = 0;
403 ComObjPtr<PCIDeviceAttachment> dev;
404 for (PCIMap::const_iterator it = mPCIMap.begin(); it != mPCIMap.end(); ++it)
405 {
406 dev.createObject();
407 com::Bstr devname(it->second.szDevName);
408 dev->init(NULL, devname,
409 it->second.HostAddress.valid() ? it->second.HostAddress.asLong() : -1,
410 it->first.asLong(), it->second.HostAddress.valid());
411 result.setElement(iIndex++, dev);
412 }
413
414 result.detachTo(ComSafeArrayOutArg(aAttached));
415}
416
417BusAssignmentManager::BusAssignmentManager()
418 : pState(NULL)
419{
420 pState = new State();
421 Assert(pState);
422}
423
424BusAssignmentManager::~BusAssignmentManager()
425{
426 if (pState)
427 {
428 delete pState;
429 pState = NULL;
430 }
431}
432
433BusAssignmentManager* BusAssignmentManager::createInstance(ChipsetType_T chipsetType)
434{
435 BusAssignmentManager* pInstance = new BusAssignmentManager();
436 pInstance->pState->init(chipsetType);
437 Assert(pInstance);
438 return pInstance;
439}
440
441void BusAssignmentManager::AddRef()
442{
443 ASMAtomicIncS32(&pState->cRefCnt);
444}
445void BusAssignmentManager::Release()
446{
447 if (ASMAtomicDecS32(&pState->cRefCnt) == 0)
448 delete this;
449}
450
451DECLINLINE(HRESULT) InsertConfigInteger(PCFGMNODE pCfg, const char* pszName, uint64_t u64)
452{
453 int vrc = CFGMR3InsertInteger(pCfg, pszName, u64);
454 if (RT_FAILURE(vrc))
455 return E_INVALIDARG;
456
457 return S_OK;
458}
459
460HRESULT BusAssignmentManager::assignPCIDeviceImpl(const char* pszDevName,
461 PCFGMNODE pCfg,
462 PCIBusAddress& GuestAddress,
463 PCIBusAddress HostAddress,
464 bool fGuestAddressRequired)
465{
466 HRESULT rc = S_OK;
467
468 if (!GuestAddress.valid())
469 rc = pState->autoAssign(pszDevName, GuestAddress);
470 else
471 {
472 bool fAvailable = pState->checkAvailable(GuestAddress);
473
474 if (!fAvailable)
475 {
476 if (fGuestAddressRequired)
477 rc = E_ACCESSDENIED;
478 else
479 rc = pState->autoAssign(pszDevName, GuestAddress);
480 }
481 }
482
483 if (FAILED(rc))
484 return rc;
485
486 Assert(GuestAddress.valid() && pState->checkAvailable(GuestAddress));
487
488 rc = pState->record(pszDevName, GuestAddress, HostAddress);
489 if (FAILED(rc))
490 return rc;
491
492 rc = InsertConfigInteger(pCfg, "PCIBusNo", GuestAddress.miBus);
493 if (FAILED(rc))
494 return rc;
495 rc = InsertConfigInteger(pCfg, "PCIDeviceNo", GuestAddress.miDevice);
496 if (FAILED(rc))
497 return rc;
498 rc = InsertConfigInteger(pCfg, "PCIFunctionNo", GuestAddress.miFn);
499 if (FAILED(rc))
500 return rc;
501
502 return S_OK;
503}
504
505
506bool BusAssignmentManager::findPCIAddress(const char* pszDevName, int iInstance, PCIBusAddress& Address)
507{
508 return pState->findPCIAddress(pszDevName, iInstance, Address);
509}
510
511void BusAssignmentManager::listAttachedPCIDevices(ComSafeArrayOut(IPCIDeviceAttachment*, aAttached))
512{
513 pState->listAttachedPCIDevices(ComSafeArrayOutArg(aAttached));
514}
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