VirtualBox

source: vbox/trunk/src/VBox/HostDrivers/Support/testcase/tstGIP-2.cpp@ 90520

Last change on this file since 90520 was 82968, checked in by vboxsync, 5 years ago

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1/* $Id: tstGIP-2.cpp 82968 2020-02-04 10:35:17Z vboxsync $ */
2/** @file
3 * SUP Testcase - Global Info Page interface (ring 3).
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * The contents of this file may alternatively be used under the terms
18 * of the Common Development and Distribution License Version 1.0
19 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20 * VirtualBox OSE distribution, in which case the provisions of the
21 * CDDL are applicable instead of those of the GPL.
22 *
23 * You may elect to license modified versions of this file under the
24 * terms and conditions of either the GPL or the CDDL or both.
25 */
26
27
28/*********************************************************************************************************************************
29* Header Files *
30*********************************************************************************************************************************/
31#include <VBox/sup.h>
32#include <iprt/errcore.h>
33#include <VBox/param.h>
34#include <iprt/asm.h>
35#include <iprt/assert.h>
36#include <iprt/alloc.h>
37#include <iprt/thread.h>
38#include <iprt/stream.h>
39#include <iprt/string.h>
40#include <iprt/initterm.h>
41#include <iprt/getopt.h>
42#include <iprt/x86.h>
43
44
45/**
46 * Entry point.
47 */
48extern "C" DECLEXPORT(int) TrustedMain(int argc, char **argv)
49{
50 RTR3InitExe(argc, &argv, 0);
51
52 /*
53 * Parse args
54 */
55 static const RTGETOPTDEF g_aOptions[] =
56 {
57 { "--iterations", 'i', RTGETOPT_REQ_INT32 },
58 { "--hex", 'h', RTGETOPT_REQ_NOTHING },
59 { "--decimal", 'd', RTGETOPT_REQ_NOTHING },
60 { "--spin", 's', RTGETOPT_REQ_NOTHING },
61 { "--reference", 'r', RTGETOPT_REQ_UINT64 }, /* reference value of CpuHz, display the
62 * CpuHz deviation in a separate column. */
63 { "--notestmode", 't', RTGETOPT_REQ_NOTHING } /* don't run GIP in test-mode (atm, test-mode
64 * implies updating GIP CpuHz even when invariant) */
65 };
66
67 bool fHex = true;
68 bool fSpin = false;
69 bool fCompat = true;
70 bool fTestMode = true;
71 int ch;
72 uint32_t cIterations = 40;
73 uint64_t uCpuHzRef = UINT64_MAX;
74 RTGETOPTUNION ValueUnion;
75 RTGETOPTSTATE GetState;
76 RTGetOptInit(&GetState, argc, argv, g_aOptions, RT_ELEMENTS(g_aOptions), 1, RTGETOPTINIT_FLAGS_NO_STD_OPTS);
77 while ((ch = RTGetOpt(&GetState, &ValueUnion)))
78 {
79 switch (ch)
80 {
81 case 'i':
82 cIterations = ValueUnion.u32;
83 break;
84
85 case 'd':
86 fHex = false;
87 break;
88
89 case 'h':
90 fHex = true;
91 break;
92
93 case 's':
94 fSpin = true;
95 break;
96
97 case 'r':
98 uCpuHzRef = ValueUnion.u64;
99 break;
100
101 case 't':
102 fTestMode = false;
103 break;
104
105 default:
106 return RTGetOptPrintError(ch, &ValueUnion);
107 }
108 }
109
110 /*
111 * Init
112 */
113 PSUPDRVSESSION pSession = NIL_RTR0PTR;
114 int rc = SUPR3Init(&pSession);
115 if (RT_SUCCESS(rc))
116 {
117 if (g_pSUPGlobalInfoPage)
118 {
119 uint64_t uCpuHzOverallDeviation = 0;
120 uint32_t cCpuHzNotCompat = 0;
121 int64_t iCpuHzMaxDeviation = 0;
122 int32_t cCpuHzOverallDevCnt = 0;
123 uint32_t cCpuHzChecked = 0;
124
125 /* Pick current CpuHz as the reference if none was specified. */
126 if (uCpuHzRef == UINT64_MAX)
127 uCpuHzRef = SUPGetCpuHzFromGip(g_pSUPGlobalInfoPage);
128
129 if ( fTestMode
130 && g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_INVARIANT_TSC)
131 SUPR3GipSetFlags(SUPGIP_FLAGS_TESTING_ENABLE, UINT32_MAX);
132
133 RTPrintf("tstGIP-2: u32Mode=%d (%s) fTestMode=%RTbool u32Version=%#x fGetGipCpu=%#RX32 cPages=%#RX32\n",
134 g_pSUPGlobalInfoPage->u32Mode,
135 SUPGetGIPModeName(g_pSUPGlobalInfoPage),
136 fTestMode,
137 g_pSUPGlobalInfoPage->u32Version,
138 g_pSUPGlobalInfoPage->fGetGipCpu,
139 g_pSUPGlobalInfoPage->cPages);
140 RTPrintf("tstGIP-2: cCpus=%d cPossibleCpus=%d cPossibleCpuGroups=%d cPresentCpus=%d cOnlineCpus=%d idCpuMax=%#x\n",
141 g_pSUPGlobalInfoPage->cCpus,
142 g_pSUPGlobalInfoPage->cPossibleCpus,
143 g_pSUPGlobalInfoPage->cPossibleCpuGroups,
144 g_pSUPGlobalInfoPage->cPresentCpus,
145 g_pSUPGlobalInfoPage->cOnlineCpus,
146 g_pSUPGlobalInfoPage->idCpuMax);
147 RTPrintf("tstGIP-2: u32UpdateHz=%RU32 u32UpdateIntervalNS=%RU32 u64NanoTSLastUpdateHz=%RX64 u64CpuHz=%RU64 uCpuHzRef=%RU64\n",
148 g_pSUPGlobalInfoPage->u32UpdateHz,
149 g_pSUPGlobalInfoPage->u32UpdateIntervalNS,
150 g_pSUPGlobalInfoPage->u64NanoTSLastUpdateHz,
151 g_pSUPGlobalInfoPage->u64CpuHz,
152 uCpuHzRef);
153 for (uint32_t iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
154 if (g_pSUPGlobalInfoPage->aCPUs[iCpu].enmState != SUPGIPCPUSTATE_INVALID)
155 {
156 SUPGIPCPU const *pGipCpu = &g_pSUPGlobalInfoPage->aCPUs[iCpu];
157 RTPrintf("tstGIP-2: aCPU[%3u]: enmState=%d iCpuSet=%-3u idCpu=%#010x iCpuGroup=%-2u iCpuGroupMember=%-3u idApic=%#06x\n",
158 iCpu, pGipCpu->enmState, pGipCpu->iCpuSet, pGipCpu->idCpu, pGipCpu->iCpuGroup,
159 pGipCpu->iCpuGroupMember, pGipCpu->idApic);
160 }
161
162 RTPrintf(fHex
163 ? "tstGIP-2: it: u64NanoTS delta u64TSC UpIntTSC H TransId CpuHz %sTSC Interval History...\n"
164 : "tstGIP-2: it: u64NanoTS delta u64TSC UpIntTSC H TransId CpuHz %sTSC Interval History...\n",
165 uCpuHzRef ? " CpuHz deviation Compat " : "");
166 static SUPGIPCPU s_aaCPUs[2][RTCPUSET_MAX_CPUS];
167 for (uint32_t i = 0; i < cIterations; i++)
168 {
169 /* Copy the data. */
170 memcpy(&s_aaCPUs[i & 1][0], &g_pSUPGlobalInfoPage->aCPUs[0], g_pSUPGlobalInfoPage->cCpus * sizeof(g_pSUPGlobalInfoPage->aCPUs[0]));
171
172 /* Display it & find something to spin on. */
173 uint32_t u32TransactionId = 0;
174 uint32_t volatile *pu32TransactionId = NULL;
175 for (unsigned iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
176 if (g_pSUPGlobalInfoPage->aCPUs[iCpu].enmState == SUPGIPCPUSTATE_ONLINE)
177 {
178 char szCpuHzDeviation[32];
179 PSUPGIPCPU pPrevCpu = &s_aaCPUs[!(i & 1)][iCpu];
180 PSUPGIPCPU pCpu = &s_aaCPUs[i & 1][iCpu];
181 if (uCpuHzRef)
182 {
183 /* Only CPU 0 is updated for invariant & sync modes, see supdrvGipUpdate(). */
184 if ( iCpu == 0
185 || g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_ASYNC_TSC)
186 {
187 /* Wait until the history validation code takes effect. */
188 if (pCpu->u32TransactionId > 23 + (8 * 2) + 1)
189 {
190 int64_t iCpuHzDeviation = pCpu->u64CpuHz - uCpuHzRef;
191 uint64_t uCpuHzDeviation = RT_ABS(iCpuHzDeviation);
192 bool fCurHzCompat = SUPIsTscFreqCompatibleEx(uCpuHzRef, pCpu->u64CpuHz, false /*fRelax*/);
193 if (uCpuHzDeviation <= 999999999)
194 {
195 if (RT_ABS(iCpuHzDeviation) > RT_ABS(iCpuHzMaxDeviation))
196 iCpuHzMaxDeviation = iCpuHzDeviation;
197 uCpuHzOverallDeviation += uCpuHzDeviation;
198 cCpuHzOverallDevCnt++;
199 uint32_t uPct = (uint32_t)(uCpuHzDeviation * 100000 / uCpuHzRef + 5);
200 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%10RI64%3d.%02d%% %RTbool ",
201 iCpuHzDeviation, uPct / 1000, (uPct % 1000) / 10, fCurHzCompat);
202 }
203 else
204 {
205 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%17s %RTbool ", "?",
206 fCurHzCompat);
207 }
208
209 if (!fCurHzCompat)
210 ++cCpuHzNotCompat;
211 fCompat &= fCurHzCompat;
212 ++cCpuHzChecked;
213 }
214 else
215 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%25s ", "priming");
216 }
217 else
218 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%25s ", "");
219 }
220 else
221 szCpuHzDeviation[0] = '\0';
222 RTPrintf(fHex
223 ? "tstGIP-2: %4d/%d: %016llx %09llx %016llx %08x %d %08x %15llu %s%08x %08x %08x %08x %08x %08x %08x %08x (%d)\n"
224 : "tstGIP-2: %4d/%d: %016llu %09llu %016llu %010u %d %010u %15llu %s%08x %08x %08x %08x %08x %08x %08x %08x (%d)\n",
225 i, iCpu,
226 pCpu->u64NanoTS,
227 i ? pCpu->u64NanoTS - pPrevCpu->u64NanoTS : 0,
228 pCpu->u64TSC,
229 pCpu->u32UpdateIntervalTSC,
230 pCpu->iTSCHistoryHead,
231 pCpu->u32TransactionId,
232 pCpu->u64CpuHz,
233 szCpuHzDeviation,
234 pCpu->au32TSCHistory[0],
235 pCpu->au32TSCHistory[1],
236 pCpu->au32TSCHistory[2],
237 pCpu->au32TSCHistory[3],
238 pCpu->au32TSCHistory[4],
239 pCpu->au32TSCHistory[5],
240 pCpu->au32TSCHistory[6],
241 pCpu->au32TSCHistory[7],
242 pCpu->cErrors);
243 if (!pu32TransactionId)
244 {
245 pu32TransactionId = &g_pSUPGlobalInfoPage->aCPUs[iCpu].u32TransactionId;
246 u32TransactionId = pCpu->u32TransactionId;
247 }
248 }
249
250 /* Wait a bit / spin. */
251 if (!fSpin)
252 RTThreadSleep(9);
253 else
254 {
255 if (pu32TransactionId)
256 {
257 uint32_t uTmp;
258 while ( u32TransactionId == (uTmp = *pu32TransactionId)
259 || (uTmp & 1))
260 ASMNopPause();
261 }
262 else
263 RTThreadSleep(1);
264 }
265 }
266
267 /*
268 * Display TSC deltas.
269 *
270 * First iterative over the APIC ID array to get mostly consistent CPUID to APIC ID mapping.
271 * Then iterate over the offline CPUs. It is possible that there's a race between the online/offline
272 * states between the two iterations, but that cannot be helped from ring-3 anyway and not a biggie.
273 */
274 RTPrintf("tstGIP-2: TSC deltas:\n");
275 RTPrintf("tstGIP-2: idApic: i64TSCDelta\n");
276 for (uint32_t i = 0; i < RT_ELEMENTS(g_pSUPGlobalInfoPage->aiCpuFromApicId); i++)
277 {
278 uint16_t iCpu = g_pSUPGlobalInfoPage->aiCpuFromApicId[i];
279 if (iCpu != UINT16_MAX)
280 RTPrintf("tstGIP-2: %#7x: %6lld (grp=%#04x mbr=%#05x set=%d cpu=%#05x)\n",
281 g_pSUPGlobalInfoPage->aCPUs[iCpu].idApic, g_pSUPGlobalInfoPage->aCPUs[iCpu].i64TSCDelta,
282 g_pSUPGlobalInfoPage->aCPUs[iCpu].iCpuGroup, g_pSUPGlobalInfoPage->aCPUs[iCpu].iCpuGroupMember,
283 g_pSUPGlobalInfoPage->aCPUs[iCpu].iCpuSet, iCpu);
284 }
285
286 for (uint32_t iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
287 if (g_pSUPGlobalInfoPage->aCPUs[iCpu].idApic == UINT16_MAX)
288 RTPrintf("tstGIP-2: offline: %6lld (grp=%#04x mbr=%#05x set=%d cpu=%#05x)\n",
289 g_pSUPGlobalInfoPage->aCPUs[iCpu].i64TSCDelta, g_pSUPGlobalInfoPage->aCPUs[iCpu].iCpuGroup,
290 g_pSUPGlobalInfoPage->aCPUs[iCpu].iCpuGroupMember, g_pSUPGlobalInfoPage->aCPUs[iCpu].iCpuSet, iCpu);
291
292 RTPrintf("tstGIP-2: enmUseTscDelta=%d fGetGipCpu=%#x\n",
293 g_pSUPGlobalInfoPage->enmUseTscDelta, g_pSUPGlobalInfoPage->fGetGipCpu);
294 if (uCpuHzRef)
295 {
296 if (cCpuHzOverallDevCnt)
297 {
298 uint32_t uPct = (uint32_t)(uCpuHzOverallDeviation * 100000 / cCpuHzOverallDevCnt / uCpuHzRef + 5);
299 RTPrintf("tstGIP-2: Average CpuHz deviation: %d.%02d%%\n",
300 uPct / 1000, (uPct % 1000) / 10);
301
302 uint32_t uMaxPct = (uint32_t)(RT_ABS(iCpuHzMaxDeviation) * 100000 / uCpuHzRef + 5);
303 RTPrintf("tstGIP-2: Maximum CpuHz deviation: %d.%02d%% (%RI64 ticks)\n",
304 uMaxPct / 1000, (uMaxPct % 1000) / 10, iCpuHzMaxDeviation);
305 }
306 else
307 {
308 RTPrintf("tstGIP-2: Average CpuHz deviation: ??.??\n");
309 RTPrintf("tstGIP-2: Average CpuHz deviation: ??.??\n");
310 }
311
312 RTPrintf("tstGIP-2: CpuHz compatibility: %RTbool (incompatible %u of %u times w/ %RU64 Hz - %s GIP)\n", fCompat,
313 cCpuHzNotCompat, cCpuHzChecked, uCpuHzRef, SUPGetGIPModeName(g_pSUPGlobalInfoPage));
314
315 if ( !fCompat
316 && g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_INVARIANT_TSC)
317 rc = -1;
318 }
319
320 /* Disable GIP test mode. */
321 if (fTestMode)
322 SUPR3GipSetFlags(0, ~SUPGIP_FLAGS_TESTING_ENABLE);
323 }
324 else
325 {
326 RTPrintf("tstGIP-2: g_pSUPGlobalInfoPage is NULL\n");
327 rc = -1;
328 }
329
330 SUPR3Term(false /*fForced*/);
331 }
332 else
333 RTPrintf("tstGIP-2: SUPR3Init failed: %Rrc\n", rc);
334 return !!rc;
335}
336
337#if !defined(VBOX_WITH_HARDENING) || !defined(RT_OS_WINDOWS)
338/**
339 * Main entry point.
340 */
341int main(int argc, char **argv)
342{
343 return TrustedMain(argc, argv);
344}
345#endif
346
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