VirtualBox

source: vbox/trunk/src/VBox/HostDrivers/Support/testcase/tstGIP-2.cpp@ 57354

Last change on this file since 57354 was 57354, checked in by vboxsync, 9 years ago

tstGIP-2: Build fix.
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1/* $Id: tstGIP-2.cpp 57354 2015-08-14 15:01:12Z vboxsync $ */
2/** @file
3 * SUP Testcase - Global Info Page interface (ring 3).
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * The contents of this file may alternatively be used under the terms
18 * of the Common Development and Distribution License Version 1.0
19 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20 * VirtualBox OSE distribution, in which case the provisions of the
21 * CDDL are applicable instead of those of the GPL.
22 *
23 * You may elect to license modified versions of this file under the
24 * terms and conditions of either the GPL or the CDDL or both.
25 */
26
27/*******************************************************************************
28* Header Files *
29*******************************************************************************/
30#include <VBox/sup.h>
31#include <VBox/err.h>
32#include <VBox/param.h>
33#include <iprt/asm.h>
34#include <iprt/assert.h>
35#include <iprt/alloc.h>
36#include <iprt/thread.h>
37#include <iprt/stream.h>
38#include <iprt/string.h>
39#include <iprt/initterm.h>
40#include <iprt/getopt.h>
41#include <iprt/x86.h>
42
43
44/**
45 * Entry point.
46 */
47extern "C" DECLEXPORT(int) TrustedMain(int argc, char **argv)
48{
49 RTR3InitExe(argc, &argv, 0);
50
51 /*
52 * Parse args
53 */
54 static const RTGETOPTDEF g_aOptions[] =
55 {
56 { "--iterations", 'i', RTGETOPT_REQ_INT32 },
57 { "--hex", 'h', RTGETOPT_REQ_NOTHING },
58 { "--decimal", 'd', RTGETOPT_REQ_NOTHING },
59 { "--spin", 's', RTGETOPT_REQ_NOTHING },
60 { "--reference", 'r', RTGETOPT_REQ_UINT64 }, /* reference value of CpuHz, display the
61 * CpuHz deviation in a separate column. */
62 { "--notestmode", 't', RTGETOPT_REQ_NOTHING } /* don't run GIP in test-mode (atm, test-mode
63 * implies updating GIP CpuHz even when invariant) */
64 };
65
66 bool fHex = true;
67 bool fSpin = false;
68 bool fCompat = true;
69 bool fTestMode = true;
70 int ch;
71 uint32_t cIterations = 40;
72 uint64_t uCpuHzRef = UINT64_MAX;
73 RTGETOPTUNION ValueUnion;
74 RTGETOPTSTATE GetState;
75 RTGetOptInit(&GetState, argc, argv, g_aOptions, RT_ELEMENTS(g_aOptions), 1, RTGETOPTINIT_FLAGS_NO_STD_OPTS);
76 while ((ch = RTGetOpt(&GetState, &ValueUnion)))
77 {
78 switch (ch)
79 {
80 case 'i':
81 cIterations = ValueUnion.u32;
82 break;
83
84 case 'd':
85 fHex = false;
86 break;
87
88 case 'h':
89 fHex = true;
90 break;
91
92 case 's':
93 fSpin = true;
94 break;
95
96 case 'r':
97 uCpuHzRef = ValueUnion.u64;
98 break;
99
100 case 't':
101 fTestMode = false;
102 break;
103
104 default:
105 return RTGetOptPrintError(ch, &ValueUnion);
106 }
107 }
108
109 /*
110 * Init
111 */
112 PSUPDRVSESSION pSession = NIL_RTR0PTR;
113 int rc = SUPR3Init(&pSession);
114 if (RT_SUCCESS(rc))
115 {
116 if (g_pSUPGlobalInfoPage)
117 {
118 uint64_t uCpuHzOverallDeviation = 0;
119 uint32_t cCpuHzNotCompat = 0;
120 int64_t iCpuHzMaxDeviation = 0;
121 int32_t cCpuHzOverallDevCnt = 0;
122 uint32_t cCpuHzChecked = 0;
123
124 /* Pick current CpuHz as the reference if none was specified. */
125 if (uCpuHzRef == UINT64_MAX)
126 uCpuHzRef = SUPGetCpuHzFromGip(g_pSUPGlobalInfoPage);
127
128 if ( fTestMode
129 && g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_INVARIANT_TSC)
130 SUPR3GipSetFlags(SUPGIP_FLAGS_TESTING_ENABLE, UINT32_MAX);
131
132 RTPrintf("tstGIP-2: cCpus=%d u32UpdateHz=%RU32 u32UpdateIntervalNS=%RU32 u64NanoTSLastUpdateHz=%RX64 u64CpuHz=%RU64 uCpuHzRef=%RU64 u32Mode=%d (%s) fTestMode=%RTbool u32Version=%#x\n",
133 g_pSUPGlobalInfoPage->cCpus,
134 g_pSUPGlobalInfoPage->u32UpdateHz,
135 g_pSUPGlobalInfoPage->u32UpdateIntervalNS,
136 g_pSUPGlobalInfoPage->u64NanoTSLastUpdateHz,
137 g_pSUPGlobalInfoPage->u64CpuHz,
138 uCpuHzRef,
139 g_pSUPGlobalInfoPage->u32Mode,
140 fTestMode,
141 SUPGetGIPModeName(g_pSUPGlobalInfoPage),
142 g_pSUPGlobalInfoPage->u32Version);
143 RTPrintf(fHex
144 ? "tstGIP-2: it: u64NanoTS delta u64TSC UpIntTSC H TransId CpuHz %sTSC Interval History...\n"
145 : "tstGIP-2: it: u64NanoTS delta u64TSC UpIntTSC H TransId CpuHz %sTSC Interval History...\n",
146 uCpuHzRef ? " CpuHz deviation Compat " : "");
147 static SUPGIPCPU s_aaCPUs[2][256];
148 for (uint32_t i = 0; i < cIterations; i++)
149 {
150 /* Copy the data. */
151 memcpy(&s_aaCPUs[i & 1][0], &g_pSUPGlobalInfoPage->aCPUs[0], g_pSUPGlobalInfoPage->cCpus * sizeof(g_pSUPGlobalInfoPage->aCPUs[0]));
152
153 /* Display it & find something to spin on. */
154 uint32_t u32TransactionId = 0;
155 uint32_t volatile *pu32TransactionId = NULL;
156 for (unsigned iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
157 if (g_pSUPGlobalInfoPage->aCPUs[iCpu].enmState == SUPGIPCPUSTATE_ONLINE)
158 {
159 char szCpuHzDeviation[32];
160 PSUPGIPCPU pPrevCpu = &s_aaCPUs[!(i & 1)][iCpu];
161 PSUPGIPCPU pCpu = &s_aaCPUs[i & 1][iCpu];
162 if (uCpuHzRef)
163 {
164 /* Only CPU 0 is updated for invariant & sync modes, see supdrvGipUpdate(). */
165 if ( iCpu == 0
166 || g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_ASYNC_TSC)
167 {
168 /* Wait until the history validation code takes effect. */
169 if (pCpu->u32TransactionId > 23 + (8 * 2) + 1)
170 {
171 int64_t iCpuHzDeviation = pCpu->u64CpuHz - uCpuHzRef;
172 uint64_t uCpuHzDeviation = RT_ABS(iCpuHzDeviation);
173 bool fCurHzCompat = SUPIsTscFreqCompatibleEx(uCpuHzRef, pCpu->u64CpuHz, false /*fRelax*/);
174 if (uCpuHzDeviation <= 999999999)
175 {
176 if (RT_ABS(iCpuHzDeviation) > RT_ABS(iCpuHzMaxDeviation))
177 iCpuHzMaxDeviation = iCpuHzDeviation;
178 uCpuHzOverallDeviation += uCpuHzDeviation;
179 cCpuHzOverallDevCnt++;
180 uint32_t uPct = (uint32_t)(uCpuHzDeviation * 100000 / uCpuHzRef + 5);
181 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%10RI64%3d.%02d%% %RTbool ",
182 iCpuHzDeviation, uPct / 1000, (uPct % 1000) / 10, fCurHzCompat);
183 }
184 else
185 {
186 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%17s %RTbool ", "?",
187 fCurHzCompat);
188 }
189
190 if (!fCurHzCompat)
191 ++cCpuHzNotCompat;
192 fCompat &= fCurHzCompat;
193 ++cCpuHzChecked;
194 }
195 else
196 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%25s ", "priming");
197 }
198 else
199 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%25s ", "");
200 }
201 else
202 szCpuHzDeviation[0] = '\0';
203 RTPrintf(fHex
204 ? "tstGIP-2: %4d/%d: %016llx %09llx %016llx %08x %d %08x %15llu %s%08x %08x %08x %08x %08x %08x %08x %08x (%d)\n"
205 : "tstGIP-2: %4d/%d: %016llu %09llu %016llu %010u %d %010u %15llu %s%08x %08x %08x %08x %08x %08x %08x %08x (%d)\n",
206 i, iCpu,
207 pCpu->u64NanoTS,
208 i ? pCpu->u64NanoTS - pPrevCpu->u64NanoTS : 0,
209 pCpu->u64TSC,
210 pCpu->u32UpdateIntervalTSC,
211 pCpu->iTSCHistoryHead,
212 pCpu->u32TransactionId,
213 pCpu->u64CpuHz,
214 szCpuHzDeviation,
215 pCpu->au32TSCHistory[0],
216 pCpu->au32TSCHistory[1],
217 pCpu->au32TSCHistory[2],
218 pCpu->au32TSCHistory[3],
219 pCpu->au32TSCHistory[4],
220 pCpu->au32TSCHistory[5],
221 pCpu->au32TSCHistory[6],
222 pCpu->au32TSCHistory[7],
223 pCpu->cErrors);
224 if (!pu32TransactionId)
225 {
226 pu32TransactionId = &g_pSUPGlobalInfoPage->aCPUs[iCpu].u32TransactionId;
227 u32TransactionId = pCpu->u32TransactionId;
228 }
229 }
230
231 /* Wait a bit / spin. */
232 if (!fSpin)
233 RTThreadSleep(9);
234 else
235 {
236 if (pu32TransactionId)
237 {
238 uint32_t uTmp;
239 while ( u32TransactionId == (uTmp = *pu32TransactionId)
240 || (uTmp & 1))
241 ASMNopPause();
242 }
243 else
244 RTThreadSleep(1);
245 }
246 }
247
248 /*
249 * Display TSC deltas.
250 *
251 * First iterative over the APIC ID array to get mostly consistent CPUID to APIC ID mapping.
252 * Then iterate over the offline CPUs. It is possible that there's a race between the online/offline
253 * states between the two iterations, but that cannot be helped from ring-3 anyway and not a biggie.
254 */
255 RTPrintf("tstGIP-2: TSC deltas:\n");
256 RTPrintf("tstGIP-2: idApic: i64TSCDelta\n");
257 for (unsigned i = 0; i < RT_ELEMENTS(g_pSUPGlobalInfoPage->aiCpuFromApicId); i++)
258 {
259 uint16_t iCpu = g_pSUPGlobalInfoPage->aiCpuFromApicId[i];
260 if (iCpu != UINT16_MAX)
261 {
262 RTPrintf("tstGIP-2: %7d: %lld\n", g_pSUPGlobalInfoPage->aCPUs[iCpu].idApic,
263 g_pSUPGlobalInfoPage->aCPUs[iCpu].i64TSCDelta);
264 }
265 }
266
267 for (unsigned iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
268 if (g_pSUPGlobalInfoPage->aCPUs[iCpu].idApic == UINT16_MAX)
269 RTPrintf("tstGIP-2: offline: %lld\n", g_pSUPGlobalInfoPage->aCPUs[iCpu].i64TSCDelta);
270
271 RTPrintf("tstGIP-2: enmUseTscDelta=%d fGetGipCpu=%#x\n",
272 g_pSUPGlobalInfoPage->enmUseTscDelta, g_pSUPGlobalInfoPage->fGetGipCpu);
273 if (uCpuHzRef)
274 {
275 if (cCpuHzOverallDevCnt)
276 {
277 uint32_t uPct = (uint32_t)(uCpuHzOverallDeviation * 100000 / cCpuHzOverallDevCnt / uCpuHzRef + 5);
278 RTPrintf("tstGIP-2: Average CpuHz deviation: %d.%02d%%\n",
279 uPct / 1000, (uPct % 1000) / 10);
280
281 uint32_t uMaxPct = (uint32_t)(RT_ABS(iCpuHzMaxDeviation) * 100000 / uCpuHzRef + 5);
282 RTPrintf("tstGIP-2: Maximum CpuHz deviation: %d.%02d%% (%RI64 ticks)\n",
283 uMaxPct / 1000, (uMaxPct % 1000) / 10, iCpuHzMaxDeviation);
284 }
285 else
286 {
287 RTPrintf("tstGIP-2: Average CpuHz deviation: ??.??\n");
288 RTPrintf("tstGIP-2: Average CpuHz deviation: ??.??\n");
289 }
290
291 RTPrintf("tstGIP-2: CpuHz compatibility: %RTbool (incompatible %u of %u times w/ %RU64 Hz - %s GIP)\n", fCompat,
292 cCpuHzNotCompat, cCpuHzChecked, uCpuHzRef, SUPGetGIPModeName(g_pSUPGlobalInfoPage));
293
294 if ( !fCompat
295 && g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_INVARIANT_TSC)
296 rc = -1;
297 }
298
299 /* Disable GIP test mode. */
300 if (fTestMode)
301 SUPR3GipSetFlags(0, ~SUPGIP_FLAGS_TESTING_ENABLE);
302 }
303 else
304 {
305 RTPrintf("tstGIP-2: g_pSUPGlobalInfoPage is NULL\n");
306 rc = -1;
307 }
308
309 SUPR3Term(false /*fForced*/);
310 }
311 else
312 RTPrintf("tstGIP-2: SUPR3Init failed: %Rrc\n", rc);
313 return !!rc;
314}
315
316#if !defined(VBOX_WITH_HARDENING) || !defined(RT_OS_WINDOWS)
317/**
318 * Main entry point.
319 */
320int main(int argc, char **argv)
321{
322 return TrustedMain(argc, argv);
323}
324#endif
325
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