SUPLibAll.cpp@ 90520

Last change on this file since 90520 was 87702, checked in by vboxsync, 4 years ago
SUP: Build fix. bugref:9937
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1	/* $Id: SUPLibAll.cpp 87702 2021-02-10 20:37:53Z vboxsync $ */
2	/** @file
3	* VirtualBox Support Library - All Contexts Code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27
28	/*********************************************************************************************************************************
29	* Header Files *
30	*********************************************************************************************************************************/
31	#include <VBox/sup.h>
32	#ifdef IN_RC
33	# include <VBox/vmm/vm.h>
34	# include <VBox/vmm/vmm.h>
35	#endif
36	#ifdef IN_RING0
37	# include <iprt/mp.h>
38	#endif
39	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
40	# include <iprt/asm-amd64-x86.h>
41	#endif
42	#include <iprt/errcore.h>
43	#if defined(IN_RING0) && defined(RT_OS_LINUX)
44	# include "SUPDrvInternal.h"
45	#endif
46
47
48
49	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
50	/**
51	* The slow case for SUPReadTsc where we need to apply deltas.
52	*
53	* Must only be called when deltas are applicable, so please do not call it
54	* directly.
55	*
56	* @returns TSC with delta applied.
57	* @param pGip Pointer to the GIP.
58	*
59	* @remarks May be called with interrupts disabled in ring-0! This is why the
60	* ring-0 code doesn't attempt to figure the delta.
61	*
62	* @internal
63	*/
64	SUPDECL(uint64_t) SUPReadTscWithDelta(PSUPGLOBALINFOPAGE pGip)
65	{
66	uint64_t uTsc;
67	uint16_t iGipCpu;
68	AssertCompile(RT_IS_POWER_OF_TWO(RTCPUSET_MAX_CPUS));
69	AssertCompile(RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx) >= RTCPUSET_MAX_CPUS);
70	Assert(pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_PRACTICALLY_ZERO);
71
72	/*
73	* Read the TSC and get the corresponding aCPUs index.
74	*/
75	#ifdef IN_RING3
76	if (pGip->fGetGipCpu & SUPGIPGETCPU_RDTSCP_MASK_MAX_SET_CPUS)
77	{
78	/* RDTSCP gives us all we need, no loops/cli. */
79	uint32_t iCpuSet;
80	uTsc = ASMReadTscWithAux(&iCpuSet);
81	iCpuSet &= RTCPUSET_MAX_CPUS - 1;
82	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
83	}
84	else if (pGip->fGetGipCpu & SUPGIPGETCPU_IDTR_LIMIT_MASK_MAX_SET_CPUS)
85	{
86	/* Storing the IDTR is normally very quick, but we need to loop. */
87	uint32_t cTries = 0;
88	for (;;)
89	{
90	uint16_t cbLim = ASMGetIdtrLimit();
91	uTsc = ASMReadTSC();
92	if (RT_LIKELY(ASMGetIdtrLimit() == cbLim))
93	{
94	uint16_t iCpuSet = cbLim - 256 * (ARCH_BITS == 64 ? 16 : 8);
95	iCpuSet &= RTCPUSET_MAX_CPUS - 1;
96	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
97	break;
98	}
99	if (cTries >= 16)
100	{
101	iGipCpu = UINT16_MAX;
102	break;
103	}
104	cTries++;
105	}
106	}
107	else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_0B)
108	{
109	/* Get APIC ID / 0x1b via the slow CPUID instruction, requires looping. */
110	uint32_t cTries = 0;
111	for (;;)
112	{
113	uint32_t idApic = ASMGetApicIdExt0B();
114	uTsc = ASMReadTSC();
115	if (RT_LIKELY(ASMGetApicIdExt0B() == idApic))
116	{
117	iGipCpu = pGip->aiCpuFromApicId[idApic];
118	break;
119	}
120	if (cTries >= 16)
121	{
122	iGipCpu = UINT16_MAX;
123	break;
124	}
125	cTries++;
126	}
127	}
128	else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_8000001E)
129	{
130	/* Get APIC ID / 0x8000001e via the slow CPUID instruction, requires looping. */
131	uint32_t cTries = 0;
132	for (;;)
133	{
134	uint32_t idApic = ASMGetApicIdExt8000001E();
135	uTsc = ASMReadTSC();
136	if (RT_LIKELY(ASMGetApicIdExt8000001E() == idApic))
137	{
138	iGipCpu = pGip->aiCpuFromApicId[idApic];
139	break;
140	}
141	if (cTries >= 16)
142	{
143	iGipCpu = UINT16_MAX;
144	break;
145	}
146	cTries++;
147	}
148	}
149	else
150	{
151	/* Get APIC ID via the slow CPUID instruction, requires looping. */
152	uint32_t cTries = 0;
153	for (;;)
154	{
155	uint8_t idApic = ASMGetApicId();
156	uTsc = ASMReadTSC();
157	if (RT_LIKELY(ASMGetApicId() == idApic))
158	{
159	iGipCpu = pGip->aiCpuFromApicId[idApic];
160	break;
161	}
162	if (cTries >= 16)
163	{
164	iGipCpu = UINT16_MAX;
165	break;
166	}
167	cTries++;
168	}
169	}
170	#elif defined(IN_RING0)
171	/* Ring-0: Use use RTMpCpuId(), no loops. */
172	RTCCUINTREG uFlags = ASMIntDisableFlags();
173	int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
174	if (RT_LIKELY((unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
175	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
176	else
177	iGipCpu = UINT16_MAX;
178	uTsc = ASMReadTSC();
179	ASMSetFlags(uFlags);
180
181	# elif defined(IN_RC)
182	/* Raw-mode context: We can get the host CPU set index via VMCPU, no loops. */
183	RTCCUINTREG uFlags = ASMIntDisableFlags(); /* Are already disable, but play safe. */
184	uint32_t iCpuSet = VMMGetCpu(&g_VM)->iHostCpuSet;
185	if (RT_LIKELY(iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
186	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
187	else
188	iGipCpu = UINT16_MAX;
189	uTsc = ASMReadTSC();
190	ASMSetFlags(uFlags);
191	#else
192	# error "IN_RING3, IN_RC or IN_RING0 must be defined!"
193	#endif
194
195	/*
196	* If the delta is valid, apply it.
197	*/
198	if (RT_LIKELY(iGipCpu < pGip->cCpus))
199	{
200	int64_t iTscDelta = pGip->aCPUs[iGipCpu].i64TSCDelta;
201	if (RT_LIKELY(iTscDelta != INT64_MAX))
202	return uTsc - iTscDelta;
203
204	# ifdef IN_RING3
205	/*
206	* The delta needs calculating, call supdrv to get the TSC.
207	*/
208	int rc = SUPR3ReadTsc(&uTsc, NULL);
209	if (RT_SUCCESS(rc))
210	return uTsc;
211	AssertMsgFailed(("SUPR3ReadTsc -> %Rrc\n", rc));
212	uTsc = ASMReadTSC();
213	# endif /* IN_RING3 */
214	}
215
216	/*
217	* This shouldn't happen, especially not in ring-3 and raw-mode context.
218	* But if it does, return something that's half useful.
219	*/
220	AssertMsgFailed(("iGipCpu=%d (%#x) cCpus=%d fGetGipCpu=%#x\n", iGipCpu, iGipCpu, pGip->cCpus, pGip->fGetGipCpu));
221	return uTsc;
222	}
223	# ifdef SUPR0_EXPORT_SYMBOL
224	SUPR0_EXPORT_SYMBOL(SUPReadTscWithDelta);
225	# endif
226	#endif /* RT_ARCH_AMD64 \|\| RT_ARCH_X86 */
227
228
229	/**
230	* Internal worker for getting the GIP CPU array index for the calling CPU.
231	*
232	* @returns Index into SUPGLOBALINFOPAGE::aCPUs or UINT16_MAX.
233	* @param pGip The GIP.
234	*/
235	DECLINLINE(uint16_t) supGetGipCpuIndex(PSUPGLOBALINFOPAGE pGip)
236	{
237	uint16_t iGipCpu;
238	#ifdef IN_RING3
239	# if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
240	if (pGip->fGetGipCpu & SUPGIPGETCPU_IDTR_LIMIT_MASK_MAX_SET_CPUS)
241	{
242	/* Storing the IDTR is normally very fast. */
243	uint16_t cbLim = ASMGetIdtrLimit();
244	uint16_t iCpuSet = cbLim - 256 * (ARCH_BITS == 64 ? 16 : 8);
245	iCpuSet &= RTCPUSET_MAX_CPUS - 1;
246	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
247	}
248	else if (pGip->fGetGipCpu & SUPGIPGETCPU_RDTSCP_MASK_MAX_SET_CPUS)
249	{
250	/* RDTSCP gives us what need need and more. */
251	uint32_t iCpuSet;
252	ASMReadTscWithAux(&iCpuSet);
253	iCpuSet &= RTCPUSET_MAX_CPUS - 1;
254	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
255	}
256	else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_0B)
257	{
258	/* Get APIC ID via the slow CPUID/0000000B instruction. */
259	uint32_t idApic = ASMGetApicIdExt0B();
260	iGipCpu = pGip->aiCpuFromApicId[idApic];
261	}
262	else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_8000001E)
263	{
264	/* Get APIC ID via the slow CPUID/8000001E instruction. */
265	uint32_t idApic = ASMGetApicIdExt8000001E();
266	iGipCpu = pGip->aiCpuFromApicId[idApic];
267	}
268	else
269	{
270	/* Get APIC ID via the slow CPUID instruction. */
271	uint8_t idApic = ASMGetApicId();
272	iGipCpu = pGip->aiCpuFromApicId[idApic];
273	}
274
275	# else
276	int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
277	if (RT_LIKELY((unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
278	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
279	else
280	iGipCpu = UINT16_MAX;
281	# endif
282
283	#elif defined(IN_RING0)
284	/* Ring-0: Use use RTMpCpuId() (disables cli to avoid host OS assertions about unsafe CPU number usage). */
285	RTCCUINTREG uFlags = ASMIntDisableFlags();
286	int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
287	if (RT_LIKELY((unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
288	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
289	else
290	iGipCpu = UINT16_MAX;
291	ASMSetFlags(uFlags);
292
293	# elif defined(IN_RC)
294	/* Raw-mode context: We can get the host CPU set index via VMCPU. */
295	uint32_t iCpuSet = VMMGetCpu(&g_VM)->iHostCpuSet;
296	if (RT_LIKELY(iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
297	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
298	else
299	iGipCpu = UINT16_MAX;
300
301	#else
302	# error "IN_RING3, IN_RC or IN_RING0 must be defined!"
303	#endif
304	return iGipCpu;
305	}
306
307
308	/**
309	* Slow path in SUPGetTscDelta, don't call directly.
310	*
311	* @returns See SUPGetTscDelta.
312	* @param pGip The GIP.
313	* @internal
314	*/
315	SUPDECL(int64_t) SUPGetTscDeltaSlow(PSUPGLOBALINFOPAGE pGip)
316	{
317	uint16_t iGipCpu = supGetGipCpuIndex(pGip);
318	if (RT_LIKELY(iGipCpu < pGip->cCpus))
319	{
320	int64_t iTscDelta = pGip->aCPUs[iGipCpu].i64TSCDelta;
321	if (iTscDelta != INT64_MAX)
322	return iTscDelta;
323	}
324	AssertFailed();
325	return 0;
326	}
327
328
329	/**
330	* Slow path in SUPGetCpuHzFromGip, don't call directly.
331	*
332	* @returns See SUPGetCpuHzFromGip.
333	* @param pGip The GIP.
334	* @internal
335	*/
336	SUPDECL(uint64_t) SUPGetCpuHzFromGipForAsyncMode(PSUPGLOBALINFOPAGE pGip)
337	{
338	uint16_t iGipCpu = supGetGipCpuIndex(pGip);
339	if (RT_LIKELY(iGipCpu < pGip->cCpus))
340	return pGip->aCPUs[iGipCpu].u64CpuHz;
341	AssertFailed();
342	return pGip->u64CpuHz;
343	}
344
345
346
347	/**
348	* Worker for SUPIsTscFreqCompatible().
349	*
350	* @returns true if it's compatible, false otherwise.
351	* @param uBaseCpuHz The reference CPU frequency of the system.
352	* @param uCpuHz The CPU frequency to compare with the base.
353	* @param fRelax Whether to use a more relaxed threshold (like
354	* for when running in a virtualized environment).
355	*
356	* @remarks Don't use directly, use SUPIsTscFreqCompatible() instead. This is
357	* to be used by tstGIP-2 or the like.
358	*/
359	SUPDECL(bool) SUPIsTscFreqCompatibleEx(uint64_t uBaseCpuHz, uint64_t uCpuHz, bool fRelax)
360	{
361	if (uBaseCpuHz != uCpuHz)
362	{
363	/* Arbitrary tolerance threshold, tweak later if required, perhaps
364	more tolerance on lower frequencies and less tolerance on higher. */
365	uint16_t uFact = !fRelax ? 666 /* 0.15% / : 125 / 0.8% */;
366	uint64_t uThr = uBaseCpuHz / uFact;
367	uint64_t uLo = uBaseCpuHz - uThr;
368	uint64_t uHi = uBaseCpuHz + uThr;
369	if ( uCpuHz < uLo
370	\|\| uCpuHz > uHi)
371	return false;
372	}
373	return true;
374	}
375
376
377	/**
378	* Checks if the provided TSC frequency is close enough to the computed TSC
379	* frequency of the host.
380	*
381	* @returns true if it's compatible, false otherwise.
382	* @param uCpuHz The TSC frequency to check.
383	* @param puGipCpuHz Where to store the GIP TSC frequency used
384	* during the compatibility test - optional.
385	* @param fRelax Whether to use a more relaxed threshold (like
386	* for when running in a virtualized environment).
387	*/
388	SUPDECL(bool) SUPIsTscFreqCompatible(uint64_t uCpuHz, uint64_t *puGipCpuHz, bool fRelax)
389	{
390	PSUPGLOBALINFOPAGE pGip = g_pSUPGlobalInfoPage;
391	bool fCompat = false;
392	uint64_t uGipCpuHz = 0;
393	if ( pGip
394	&& pGip->u32Mode != SUPGIPMODE_ASYNC_TSC)
395	{
396	uGipCpuHz = pGip->u64CpuHz;
397	fCompat = SUPIsTscFreqCompatibleEx(uGipCpuHz, uCpuHz, fRelax);
398	}
399	if (puGipCpuHz)
400	*puGipCpuHz = uGipCpuHz;
401	return fCompat;
402	}
403

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source: vbox/trunk/src/VBox/HostDrivers/Support/SUPLibAll.cpp@ 90520

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