SUPLibAll.cpp@ 107044

Last change on this file since 107044 was 106640, checked in by vboxsync, 5 weeks ago
SUPDrv: Some tiny fixes and cleanup. jiraref:VBP-1253
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1	/* $Id: SUPLibAll.cpp 106640 2024-10-24 00:31:41Z vboxsync $ */
2	/** @file
3	* VirtualBox Support Library - All Contexts Code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* The contents of this file may alternatively be used under the terms
26	* of the Common Development and Distribution License Version 1.0
27	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
28	* in the VirtualBox distribution, in which case the provisions of the
29	* CDDL are applicable instead of those of the GPL.
30	*
31	* You may elect to license modified versions of this file under the
32	* terms and conditions of either the GPL or the CDDL or both.
33	*
34	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
35	*/
36
37
38	/*********************************************************************************************************************************
39	* Header Files *
40	*********************************************************************************************************************************/
41	#include <VBox/sup.h>
42	#ifdef IN_RC
43	# include <VBox/vmm/vm.h>
44	# include <VBox/vmm/vmm.h>
45	#endif
46	#ifdef IN_RING0
47	# include <iprt/mp.h>
48	#endif
49	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
50	# include <iprt/asm-amd64-x86.h>
51	#elif defined(RT_ARCH_ARM64) \|\| defined(RT_ARCH_ARM32)
52	# include <iprt/asm-arm.h>
53	#endif
54	#include <iprt/errcore.h>
55	#if defined(IN_RING0) && defined(RT_OS_LINUX)
56	# include "SUPDrvInternal.h"
57	#endif
58
59
60
61	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(RT_ARCH_ARM64) \|\| defined(RT_ARCH_ARM32)
62	/**
63	* The slow case for SUPReadTsc where we need to apply deltas.
64	*
65	* Must only be called when deltas are applicable, so please do not call it
66	* directly.
67	*
68	* @returns TSC with delta applied.
69	* @param pGip Pointer to the GIP.
70	*
71	* @remarks May be called with interrupts disabled in ring-0! This is why the
72	* ring-0 code doesn't attempt to figure the delta.
73	*
74	* @internal
75	*/
76	SUPDECL(uint64_t) SUPReadTscWithDelta(PSUPGLOBALINFOPAGE pGip)
77	{
78	uint64_t uTsc;
79	uint16_t iGipCpu;
80	AssertCompile(RT_IS_POWER_OF_TWO(RTCPUSET_MAX_CPUS));
81	AssertCompile(RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx) >= RTCPUSET_MAX_CPUS);
82	Assert(pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_PRACTICALLY_ZERO);
83
84	/*
85	* Read the TSC and get the corresponding aCPUs index.
86	*/
87	# ifdef IN_RING3
88	# if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
89	if (pGip->fGetGipCpu & SUPGIPGETCPU_RDTSCP_MASK_MAX_SET_CPUS)
90	{
91	/* RDTSCP gives us all we need, no loops/cli. */
92	uint32_t iCpuSet;
93	uTsc = ASMReadTscWithAux(&iCpuSet);
94	iCpuSet &= RTCPUSET_MAX_CPUS - 1;
95	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
96	}
97	else if (pGip->fGetGipCpu & SUPGIPGETCPU_IDTR_LIMIT_MASK_MAX_SET_CPUS)
98	{
99	/* Storing the IDTR is normally very quick, but we need to loop. */
100	uint32_t cTries = 0;
101	for (;;)
102	{
103	uint16_t const cbLim = ASMGetIdtrLimit();
104	uTsc = ASMReadTSC();
105	if (RT_LIKELY(ASMGetIdtrLimit() == cbLim))
106	{
107	uint16_t iCpuSet = cbLim - 256 * (ARCH_BITS == 64 ? 16 : 8);
108	iCpuSet &= RTCPUSET_MAX_CPUS - 1;
109	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
110	break;
111	}
112	if (cTries >= 16)
113	{
114	iGipCpu = UINT16_MAX;
115	break;
116	}
117	cTries++;
118	}
119	}
120	else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_0B)
121	{
122	/* Get APIC ID / 0x1b via the slow CPUID instruction, requires looping. */
123	uint32_t cTries = 0;
124	for (;;)
125	{
126	uint32_t const idApic = ASMGetApicIdExt0B();
127	uTsc = ASMReadTSC();
128	if (RT_LIKELY(ASMGetApicIdExt0B() == idApic))
129	{
130	iGipCpu = pGip->aiCpuFromApicId[idApic];
131	break;
132	}
133	if (cTries >= 16)
134	{
135	iGipCpu = UINT16_MAX;
136	break;
137	}
138	cTries++;
139	}
140	}
141	else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_8000001E)
142	{
143	/* Get APIC ID / 0x8000001e via the slow CPUID instruction, requires looping. */
144	uint32_t cTries = 0;
145	for (;;)
146	{
147	uint32_t const idApic = ASMGetApicIdExt8000001E();
148	uTsc = ASMReadTSC();
149	if (RT_LIKELY(ASMGetApicIdExt8000001E() == idApic))
150	{
151	iGipCpu = pGip->aiCpuFromApicId[idApic];
152	break;
153	}
154	if (cTries >= 16)
155	{
156	iGipCpu = UINT16_MAX;
157	break;
158	}
159	cTries++;
160	}
161	}
162	else
163	{
164	/* Get APIC ID via the slow CPUID instruction, requires looping. */
165	uint32_t cTries = 0;
166	for (;;)
167	{
168	uint8_t const idApic = ASMGetApicId();
169	uTsc = ASMReadTSC();
170	if (RT_LIKELY(ASMGetApicId() == idApic))
171	{
172	iGipCpu = pGip->aiCpuFromApicId[idApic];
173	break;
174	}
175	if (cTries >= 16)
176	{
177	iGipCpu = UINT16_MAX;
178	break;
179	}
180	cTries++;
181	}
182	}
183
184	# else /* !AMD64 \|\| !X86 */
185	# if defined(RT_OS_WINDOWS)
186	/* Use TPIDRRO_EL0 (=cpu number) before and after reading the TSC. */
187	uint32_t cTries = 0;
188	for (;;)
189	{
190	RTCCUINTREG const idApic = ASMGetThreadIdRoEL0();
191	uTsc = ASMReadTSC();
192	if (RT_LIKELY(ASMGetThreadIdRoEL0() == idApic))
193	{
194	AssertBreakStmt(idApic < RT_ELEMENTS(pGip->aiCpuFromApicId), iGipCpu = UINT16_MAX);
195	iGipCpu = pGip->aiCpuFromApicId[idApic & 0xffff];
196	break;
197	}
198	if (cTries >= 16)
199	{
200	iGipCpu = UINT16_MAX;
201	break;
202	}
203	cTries++;
204	}
205	# else
206	/* Use RTMpCpuId before and after reading the TSC. */
207	uint32_t cTries = 0;
208	for (;;)
209	{
210	RTCPUID const idCpu = RTMpCpuId();
211	uTsc = ASMReadTSC();
212	if (RT_LIKELY(RTMpCpuId() == idCpu))
213	{
214	int const iCpuSet = RTMpCpuIdToSetIndex(idCpu);
215	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
216	break;
217	}
218	if (cTries >= 16)
219	{
220	iGipCpu = UINT16_MAX;
221	break;
222	}
223	cTries++;
224	}
225	# endif
226	# endif /* !AMD64 \|\| !X86 */
227
228	#elif defined(IN_RING0)
229	/* Ring-0: Use use RTMpCpuId(), no loops. */
230	RTCCUINTREG uFlags = ASMIntDisableFlags();
231	int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
232	if (RT_LIKELY((unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
233	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
234	else
235	iGipCpu = UINT16_MAX;
236	uTsc = ASMReadTSC();
237	ASMSetFlags(uFlags);
238
239	# elif defined(IN_RC)
240	/* Raw-mode context: We can get the host CPU set index via VMCPU, no loops. */
241	RTCCUINTREG uFlags = ASMIntDisableFlags(); /* Are already disable, but play safe. */
242	uint32_t iCpuSet = VMMGetCpu(&g_VM)->iHostCpuSet;
243	if (RT_LIKELY(iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
244	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
245	else
246	iGipCpu = UINT16_MAX;
247	uTsc = ASMReadTSC();
248	ASMSetFlags(uFlags);
249	#else
250	# error "IN_RING3, IN_RC or IN_RING0 must be defined!"
251	#endif
252
253	/*
254	* If the delta is valid, apply it.
255	*/
256	if (RT_LIKELY(iGipCpu < pGip->cCpus))
257	{
258	int64_t iTscDelta = pGip->aCPUs[iGipCpu].i64TSCDelta;
259	if (RT_LIKELY(iTscDelta != INT64_MAX))
260	return uTsc - iTscDelta;
261
262	# ifdef IN_RING3
263	/*
264	* The delta needs calculating, call supdrv to get the TSC.
265	*/
266	int rc = SUPR3ReadTsc(&uTsc, NULL);
267	if (RT_SUCCESS(rc))
268	return uTsc;
269	AssertMsgFailed(("SUPR3ReadTsc -> %Rrc\n", rc));
270	uTsc = ASMReadTSC();
271	# endif /* IN_RING3 */
272	}
273
274	/*
275	* This shouldn't happen, especially not in ring-3 and raw-mode context.
276	* But if it does, return something that's half useful.
277	*/
278	AssertMsgFailed(("iGipCpu=%d (%#x) cCpus=%d fGetGipCpu=%#x\n", iGipCpu, iGipCpu, pGip->cCpus, pGip->fGetGipCpu));
279	return uTsc;
280	}
281	# ifdef SUPR0_EXPORT_SYMBOL
282	SUPR0_EXPORT_SYMBOL(SUPReadTscWithDelta);
283	# endif
284	#endif /* defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(RT_ARCH_ARM64) \|\| defined(RT_ARCH_ARM32) */
285
286
287	/**
288	* Internal worker for getting the GIP CPU array index for the calling CPU.
289	*
290	* @returns Index into SUPGLOBALINFOPAGE::aCPUs or UINT16_MAX.
291	* @param pGip The GIP.
292	*/
293	DECLINLINE(uint16_t) supGetGipCpuIndex(PSUPGLOBALINFOPAGE pGip)
294	{
295	uint16_t iGipCpu;
296	#ifdef IN_RING3
297	# if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
298	if (pGip->fGetGipCpu & SUPGIPGETCPU_IDTR_LIMIT_MASK_MAX_SET_CPUS)
299	{
300	/* Storing the IDTR is normally very fast. */
301	uint16_t cbLim = ASMGetIdtrLimit();
302	uint16_t iCpuSet = cbLim - 256 * (ARCH_BITS == 64 ? 16 : 8);
303	iCpuSet &= RTCPUSET_MAX_CPUS - 1;
304	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
305	}
306	else if (pGip->fGetGipCpu & SUPGIPGETCPU_RDTSCP_MASK_MAX_SET_CPUS)
307	{
308	/* RDTSCP gives us what need need and more. */
309	uint32_t iCpuSet;
310	ASMReadTscWithAux(&iCpuSet);
311	iCpuSet &= RTCPUSET_MAX_CPUS - 1;
312	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
313	}
314	else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_0B)
315	{
316	/* Get APIC ID via the slow CPUID/0000000B instruction. */
317	uint32_t idApic = ASMGetApicIdExt0B();
318	iGipCpu = pGip->aiCpuFromApicId[idApic];
319	}
320	else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_8000001E)
321	{
322	/* Get APIC ID via the slow CPUID/8000001E instruction. */
323	uint32_t idApic = ASMGetApicIdExt8000001E();
324	iGipCpu = pGip->aiCpuFromApicId[idApic];
325	}
326	else
327	{
328	/* Get APIC ID via the slow CPUID instruction. */
329	uint8_t idApic = ASMGetApicId();
330	iGipCpu = pGip->aiCpuFromApicId[idApic];
331	}
332
333	# else
334	int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
335	if (RT_LIKELY((unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
336	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
337	else
338	iGipCpu = UINT16_MAX;
339	# endif
340
341	#elif defined(IN_RING0)
342	/* Ring-0: Use use RTMpCpuId() (disables cli to avoid host OS assertions about unsafe CPU number usage). */
343	RTCCUINTREG uFlags = ASMIntDisableFlags();
344	int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
345	if (RT_LIKELY((unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
346	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
347	else
348	iGipCpu = UINT16_MAX;
349	ASMSetFlags(uFlags);
350
351	# elif defined(IN_RC)
352	/* Raw-mode context: We can get the host CPU set index via VMCPU. */
353	uint32_t iCpuSet = VMMGetCpu(&g_VM)->iHostCpuSet;
354	if (RT_LIKELY(iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
355	iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
356	else
357	iGipCpu = UINT16_MAX;
358
359	#else
360	# error "IN_RING3, IN_RC or IN_RING0 must be defined!"
361	#endif
362	return iGipCpu;
363	}
364
365
366	/**
367	* Slow path in SUPGetTscDelta, don't call directly.
368	*
369	* @returns See SUPGetTscDelta.
370	* @param pGip The GIP.
371	* @internal
372	*/
373	SUPDECL(int64_t) SUPGetTscDeltaSlow(PSUPGLOBALINFOPAGE pGip)
374	{
375	uint16_t iGipCpu = supGetGipCpuIndex(pGip);
376	if (RT_LIKELY(iGipCpu < pGip->cCpus))
377	{
378	int64_t iTscDelta = pGip->aCPUs[iGipCpu].i64TSCDelta;
379	if (iTscDelta != INT64_MAX)
380	return iTscDelta;
381	}
382	AssertFailed();
383	return 0;
384	}
385
386
387	/**
388	* SLow path in SUPGetGipCpuPtr, don't call directly.
389	*
390	* @returns Pointer to the CPU entry for the caller, NULL on failure.
391	* @param pGip The GIP.
392	*/
393	SUPDECL(PSUPGIPCPU) SUPGetGipCpuPtrForAsyncMode(PSUPGLOBALINFOPAGE pGip)
394	{
395	uint16_t iGipCpu = supGetGipCpuIndex(pGip);
396	if (RT_LIKELY(iGipCpu < pGip->cCpus))
397	return &pGip->aCPUs[iGipCpu];
398	AssertFailed();
399	return NULL;
400	}
401
402
403	/**
404	* Slow path in SUPGetCpuHzFromGip, don't call directly.
405	*
406	* @returns See SUPGetCpuHzFromGip.
407	* @param pGip The GIP.
408	* @internal
409	*/
410	SUPDECL(uint64_t) SUPGetCpuHzFromGipForAsyncMode(PSUPGLOBALINFOPAGE pGip)
411	{
412	uint16_t iGipCpu = supGetGipCpuIndex(pGip);
413	if (RT_LIKELY(iGipCpu < pGip->cCpus))
414	return pGip->aCPUs[iGipCpu].u64CpuHz;
415	AssertFailed();
416	return pGip->u64CpuHz;
417	}
418
419
420
421	/**
422	* Worker for SUPIsTscFreqCompatible().
423	*
424	* @returns true if it's compatible, false otherwise.
425	* @param uBaseCpuHz The reference CPU frequency of the system.
426	* @param uCpuHz The CPU frequency to compare with the base.
427	* @param fRelax Whether to use a more relaxed threshold (like
428	* for when running in a virtualized environment).
429	*
430	* @remarks Don't use directly, use SUPIsTscFreqCompatible() instead. This is
431	* to be used by tstGIP-2 or the like.
432	*/
433	SUPDECL(bool) SUPIsTscFreqCompatibleEx(uint64_t uBaseCpuHz, uint64_t uCpuHz, bool fRelax)
434	{
435	if (uBaseCpuHz != uCpuHz)
436	{
437	/* Arbitrary tolerance threshold, tweak later if required, perhaps
438	more tolerance on lower frequencies and less tolerance on higher. */
439	uint16_t uFact = !fRelax ? 666 /* 0.15% / : 125 / 0.8% */;
440	uint64_t uThr = uBaseCpuHz / uFact;
441	uint64_t uLo = uBaseCpuHz - uThr;
442	uint64_t uHi = uBaseCpuHz + uThr;
443	if ( uCpuHz < uLo
444	\|\| uCpuHz > uHi)
445	return false;
446	}
447	return true;
448	}
449
450
451	/**
452	* Checks if the provided TSC frequency is close enough to the computed TSC
453	* frequency of the host.
454	*
455	* @returns true if it's compatible, false otherwise.
456	* @param uCpuHz The TSC frequency to check.
457	* @param puGipCpuHz Where to store the GIP TSC frequency used
458	* during the compatibility test - optional.
459	* @param fRelax Whether to use a more relaxed threshold (like
460	* for when running in a virtualized environment).
461	*/
462	SUPDECL(bool) SUPIsTscFreqCompatible(uint64_t uCpuHz, uint64_t *puGipCpuHz, bool fRelax)
463	{
464	PSUPGLOBALINFOPAGE pGip = g_pSUPGlobalInfoPage;
465	bool fCompat = false;
466	uint64_t uGipCpuHz = 0;
467	if ( pGip
468	&& pGip->u32Mode != SUPGIPMODE_ASYNC_TSC)
469	{
470	uGipCpuHz = pGip->u64CpuHz;
471	fCompat = SUPIsTscFreqCompatibleEx(uGipCpuHz, uCpuHz, fRelax);
472	}
473	if (puGipCpuHz)
474	*puGipCpuHz = uGipCpuHz;
475	return fCompat;
476	}
477

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