DisasmTables-armv8-a64.cpp@ 106724

Last change on this file since 106724 was 106706, checked in by vboxsync, 4 weeks ago
Disassembler: Decode 3-source register data processing instructions, bugref:10394
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1	/* $Id: DisasmTables-armv8-a64.cpp 106706 2024-10-25 15:43:05Z vboxsync $ */
2	/** @file
3	* VBox disassembler - Tables for ARMv8 A64.
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#include <VBox/dis.h>
33	#include <VBox/disopcode-armv8.h>
34	#include "DisasmInternal-armv8.h"
35
36
37	/*********************************************************************************************************************************
38	* Global Variables *
39	*********************************************************************************************************************************/
40
41	#define DIS_ARMV8_OP(a_fValue, a_szOpcode, a_uOpcode, a_fOpType) \
42	{ a_fValue, 0, NULL, OP(a_szOpcode, 0, 0, 0, a_uOpcode, 0, 0, 0, a_fOpType) }
43	#define DIS_ARMV8_OP_EX(a_fValue, a_szOpcode, a_uOpcode, a_fOpType, a_fFlags) \
44	{ a_fValue, a_fFlags, NULL, OP(a_szOpcode, 0, 0, 0, a_uOpcode, 0, 0, 0, a_fOpType) }
45	#define DIS_ARMV8_OP_ALT_DECODE(a_fValue, a_szOpcode, a_uOpcode, a_fOpType, a_aAltDecode) \
46	{ a_fValue, 0, &g_aArmV8A64Insn ## a_aAltDecode ## Decode[0], OP(a_szOpcode, 0, 0, 0, a_uOpcode, 0, 0, 0, a_fOpType) }
47
48
49	#ifndef DIS_CORE_ONLY
50	static char g_szInvalidOpcode[] = "Invalid Opcode";
51	#endif
52
53	#define INVALID_OPCODE \
54	DIS_ARMV8_OP(0, g_szInvalidOpcode, OP_ARMV8_INVALID, DISOPTYPE_INVALID)
55
56
57	/* Invalid opcode */
58	DECL_HIDDEN_CONST(DISOPCODE) g_ArmV8A64InvalidOpcode[1] =
59	{
60	OP(g_szInvalidOpcode, 0, 0, 0, 0, 0, 0, 0, DISOPTYPE_INVALID)
61	};
62
63
64	/* Include the secondary tables. */
65	#include "DisasmTables-armv8-a64-simd-fp.cpp.h"
66	#include "DisasmTables-armv8-a64-ld-st.cpp.h"
67
68	/* UDF */
69	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Rsvd)
70	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 0, 16, 0 /idxParam/),
71	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Rsvd)
72	DIS_ARMV8_OP(0x00000000, "udf" , OP_ARMV8_A64_UDF, DISOPTYPE_INVALID)
73	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Rsvd, 0xffff0000 /fFixedInsn/,
74	kDisArmV8OpcDecodeNop, 0xffff0000, 16);
75
76	/* ADR/ADRP */
77	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Adr)
78	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
79	DIS_ARMV8_INSN_DECODE(kDisParmParseImmAdr, 0, 0, 1 /idxParam/),
80	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Adr)
81	DIS_ARMV8_OP(0x10000000, "adr" , OP_ARMV8_A64_ADR, DISOPTYPE_HARMLESS),
82	DIS_ARMV8_OP(0x90000000, "adrp" , OP_ARMV8_A64_ADRP, DISOPTYPE_HARMLESS)
83	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Adr, 0x9f000000 /fFixedInsn/,
84	kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31);
85
86
87	/* ADD/ADDS/SUB/SUBS - shifted immediate variant */
88	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(AddSubImm)
89	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
90	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
91	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
92	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 10, 12, 2 /idxParam/),
93	DIS_ARMV8_INSN_DECODE(kDisParmParseSh12, 22, 1, 2 /idxParam/),
94	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(AddSubImm)
95	DIS_ARMV8_OP(0x11000000, "add" , OP_ARMV8_A64_ADD, DISOPTYPE_HARMLESS),
96	DIS_ARMV8_OP(0x31000000, "adds" , OP_ARMV8_A64_ADDS, DISOPTYPE_HARMLESS),
97	DIS_ARMV8_OP(0x51000000, "sub" , OP_ARMV8_A64_SUB, DISOPTYPE_HARMLESS),
98	DIS_ARMV8_OP(0x71000000, "subs" , OP_ARMV8_A64_SUBS, DISOPTYPE_HARMLESS),
99	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(AddSubImm, 0x7f800000 /fFixedInsn/,
100	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
101
102
103	/* ADD/ADDS/SUB/SUBS - shifted register variant */
104	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(AddSubShiftReg)
105	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
106	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
107	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
108	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
109	DIS_ARMV8_INSN_DECODE(kDisParmParseShift, 22, 2, 2 /idxParam/),
110	DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount, 10, 6, 2 /idxParam/),
111	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(AddSubShiftReg)
112	DIS_ARMV8_OP(0x0b000000, "add" , OP_ARMV8_A64_ADD, DISOPTYPE_HARMLESS),
113	DIS_ARMV8_OP(0x2b000000, "adds" , OP_ARMV8_A64_ADDS, DISOPTYPE_HARMLESS),
114	DIS_ARMV8_OP(0x4b000000, "sub" , OP_ARMV8_A64_SUB, DISOPTYPE_HARMLESS),
115	DIS_ARMV8_OP(0x6b000000, "subs" , OP_ARMV8_A64_SUBS, DISOPTYPE_HARMLESS),
116	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(AddSubShiftReg, 0x7f200000 /fFixedInsn/,
117	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
118
119
120	/* AND/ORR/EOR/ANDS */
121	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogicalImm)
122	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
123	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 0, 5, 0 /idxParam/),
124	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
125	DIS_ARMV8_INSN_DECODE(kDisParmParseImmsImmrN, 10, 13, 2 /idxParam/),
126	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogicalImm)
127	DIS_ARMV8_OP(0x12000000, "and" , OP_ARMV8_A64_AND, DISOPTYPE_HARMLESS),
128	DIS_ARMV8_OP(0x32000000, "orr" , OP_ARMV8_A64_ORR, DISOPTYPE_HARMLESS),
129	DIS_ARMV8_OP(0x52000000, "eor" , OP_ARMV8_A64_EOR, DISOPTYPE_HARMLESS),
130	DIS_ARMV8_OP(0x72000000, "ands" , OP_ARMV8_A64_ANDS, DISOPTYPE_HARMLESS),
131	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LogicalImm, 0x7f800000 /fFixedInsn/,
132	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
133
134
135	/* MOVN/MOVZ/MOVK */
136	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(MoveWide)
137	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
138	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
139	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 16, 1 /idxParam/),
140	DIS_ARMV8_INSN_DECODE(kDisParmParseHw, 21, 2, 1 /idxParam/),
141	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(MoveWide)
142	DIS_ARMV8_OP(0x12800000, "movn", OP_ARMV8_A64_MOVN, DISOPTYPE_HARMLESS),
143	INVALID_OPCODE,
144	DIS_ARMV8_OP(0x52800000, "movz" , OP_ARMV8_A64_MOVZ, DISOPTYPE_HARMLESS),
145	DIS_ARMV8_OP(0x72800000, "movk" , OP_ARMV8_A64_MOVK, DISOPTYPE_HARMLESS),
146	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(MoveWide, 0x7f800000 /fFixedInsn/,
147	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
148
149
150	/* SBFM/BFM/UBFM */
151	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Bitfield)
152	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
153	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
154	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
155	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 16, 6, 2 /idxParam/),
156	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 10, 6, 3 /idxParam/),
157	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Bitfield)
158	DIS_ARMV8_OP(0x13000000, "sbfm", OP_ARMV8_A64_SBFM, DISOPTYPE_HARMLESS),
159	DIS_ARMV8_OP(0x33000000, "bfm", OP_ARMV8_A64_BFM, DISOPTYPE_HARMLESS),
160	DIS_ARMV8_OP(0x53000000, "ubfm", OP_ARMV8_A64_UBFM, DISOPTYPE_HARMLESS),
161	INVALID_OPCODE,
162	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Bitfield, 0x7f800000 /fFixedInsn/,
163	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
164
165
166	/* EXTR */
167	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Extract) /** @todo N must match SF, and for sf == 0 -> imms<5> == 0. */
168	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
169	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
170	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
171	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
172	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 10, 6, 3 /idxParam/),
173	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Extract)
174	DIS_ARMV8_OP(0x13800000, "extr", OP_ARMV8_A64_EXTR, DISOPTYPE_HARMLESS),
175	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Extract, 0x7fa00000 /fFixedInsn/,
176	kDisArmV8OpcDecodeNop, 0, 0);
177
178
179	/*
180	* C4.1.65 of the ARMv8 architecture reference manual has the following table for the
181	* data processing (immediate) instruction classes:
182	*
183	* Bit 25 24 23
184	* +-------------------------------------------
185	* 0 0 x PC-rel. addressing.
186	* 0 1 0 Add/subtract (immediate)
187	* 0 1 1 Add/subtract (immediate, with tags)
188	* 1 0 0 Logical (immediate)
189	* 1 0 1 Move wide (immediate)
190	* 1 1 0 Bitfield
191	* 1 1 1 Extract
192	*/
193	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcessingImm)
194	DIS_ARMV8_DECODE_MAP_ENTRY(Adr),
195	DIS_ARMV8_DECODE_MAP_ENTRY(Adr),
196	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubImm),
197	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Add/subtract immediate with tags. */
198	DIS_ARMV8_DECODE_MAP_ENTRY(LogicalImm),
199	DIS_ARMV8_DECODE_MAP_ENTRY(MoveWide),
200	DIS_ARMV8_DECODE_MAP_ENTRY(Bitfield),
201	DIS_ARMV8_DECODE_MAP_ENTRY(Extract)
202	DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcessingImm, RT_BIT_32(23) \| RT_BIT_32(24) \| RT_BIT_32(25), 23);
203
204
205	/* B.cond/BC.cond */
206	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CondBr)
207	DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 0, 4, DIS_ARMV8_INSN_PARAM_UNSET),
208	DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 5, 19, 0 /idxParam/),
209	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CondBr)
210	DIS_ARMV8_OP(0x54000000, "b", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_RELATIVE_CONTROLFLOW \| DISOPTYPE_COND_CONTROLFLOW),
211	DIS_ARMV8_OP(0x54000010, "bc" , OP_ARMV8_A64_BC, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_RELATIVE_CONTROLFLOW \| DISOPTYPE_COND_CONTROLFLOW),
212	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(CondBr, 0xff000010 /fFixedInsn/,
213	kDisArmV8OpcDecodeNop, RT_BIT_32(4), 4);
214
215
216	/* SVC/HVC/SMC/BRK/HLT/TCANCEL/DCPS1/DCPS2/DCPS3 */
217	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Excp)
218	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 16, 0 /idxParam/),
219	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Excp)
220	DIS_ARMV8_OP(0xd4000001, "svc", OP_ARMV8_A64_SVC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
221	DIS_ARMV8_OP(0xd4000002, "hvc", OP_ARMV8_A64_HVC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT \| DISOPTYPE_PRIVILEGED),
222	DIS_ARMV8_OP(0xd4000003, "smc", OP_ARMV8_A64_SMC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT \| DISOPTYPE_PRIVILEGED),
223	DIS_ARMV8_OP(0xd4200000, "brk", OP_ARMV8_A64_BRK, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
224	DIS_ARMV8_OP(0xd4400000, "hlt", OP_ARMV8_A64_HLT, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
225	DIS_ARMV8_OP(0xd4600000, "tcancel", OP_ARMV8_A64_TCANCEL, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT), /* FEAT_TME */
226	DIS_ARMV8_OP(0xd4a00001, "dcps1", OP_ARMV8_A64_DCPS1, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
227	DIS_ARMV8_OP(0xd4a00002, "dcps2", OP_ARMV8_A64_DCPS2, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
228	DIS_ARMV8_OP(0xd4a00003, "dcps3", OP_ARMV8_A64_DCPS3, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
229	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Excp, 0xffe0001f /fFixedInsn/,
230	kDisArmV8OpcDecodeLookup, 0xffe0001f, 0);
231
232
233	/* WFET/WFIT */
234	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysReg)
235	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
236	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysReg)
237	DIS_ARMV8_OP(0xd5031000, "wfet", OP_ARMV8_A64_WFET, DISOPTYPE_HARMLESS), /* FEAT_WFxT */
238	DIS_ARMV8_OP(0x54000010, "wfit" , OP_ARMV8_A64_WFIT, DISOPTYPE_HARMLESS), /* FEAT_WFxT */
239	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(SysReg, 0xffffffe0 /fFixedInsn/,
240	kDisArmV8OpcDecodeNop, 0xfe0, 5);
241
242
243	/* Various hint instructions */
244	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Hints)
245	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Hints)
246	DIS_ARMV8_OP(0xd503201f, "nop", OP_ARMV8_A64_NOP, DISOPTYPE_HARMLESS),
247	DIS_ARMV8_OP(0xd503203f, "yield", OP_ARMV8_A64_YIELD, DISOPTYPE_HARMLESS),
248	DIS_ARMV8_OP(0xd503205f, "wfe", OP_ARMV8_A64_WFE, DISOPTYPE_HARMLESS),
249	DIS_ARMV8_OP(0xd503207f, "wfi", OP_ARMV8_A64_WFI, DISOPTYPE_HARMLESS),
250	DIS_ARMV8_OP(0xd503209f, "sev", OP_ARMV8_A64_SEV, DISOPTYPE_HARMLESS),
251	DIS_ARMV8_OP(0xd50320bf, "sevl", OP_ARMV8_A64_SEVL, DISOPTYPE_HARMLESS),
252	DIS_ARMV8_OP(0xd50320df, "dgh", OP_ARMV8_A64_DGH, DISOPTYPE_HARMLESS), /* FEAT_DGH */
253	DIS_ARMV8_OP(0xd50320ff, "xpaclri", OP_ARMV8_A64_XPACLRI, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
254	DIS_ARMV8_OP(0xd503211f, "pacia1716", OP_ARMV8_A64_PACIA1716, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
255	INVALID_OPCODE,
256	DIS_ARMV8_OP(0xd503215f, "pacib1716", OP_ARMV8_A64_PACIB1716, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
257	INVALID_OPCODE,
258	DIS_ARMV8_OP(0xd503219f, "autia1716", OP_ARMV8_A64_AUTIA1716, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
259	INVALID_OPCODE,
260	DIS_ARMV8_OP(0xd50321df, "autib1716", OP_ARMV8_A64_AUTIB1716, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
261	INVALID_OPCODE,
262	DIS_ARMV8_OP(0xd503221f, "esb", OP_ARMV8_A64_ESB, DISOPTYPE_HARMLESS), /* FEAT_RAS */
263	DIS_ARMV8_OP(0xd503223f, "psb csync", OP_ARMV8_A64_PSB, DISOPTYPE_HARMLESS), /* FEAT_SPE */
264	DIS_ARMV8_OP(0xd503225f, "tsb csync", OP_ARMV8_A64_TSB, DISOPTYPE_HARMLESS), /* FEAT_TRF */
265	DIS_ARMV8_OP(0xd503227f, "gcsb dsync", OP_ARMV8_A64_GCSB, DISOPTYPE_HARMLESS), /* FEAT_GCS */
266	DIS_ARMV8_OP(0xd503229f, "csdb", OP_ARMV8_A64_CSDB, DISOPTYPE_HARMLESS),
267	INVALID_OPCODE,
268	DIS_ARMV8_OP(0xd50322df, "clrbhb", OP_ARMV8_A64_CLRBHB, DISOPTYPE_HARMLESS), /* FEAT_CLRBHB */
269	INVALID_OPCODE,
270	DIS_ARMV8_OP(0xd503231f, "paciaz", OP_ARMV8_A64_PACIAZ, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
271	DIS_ARMV8_OP(0xd503233f, "paciasp", OP_ARMV8_A64_PACIASP, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
272	DIS_ARMV8_OP(0xd503235f, "pacibz", OP_ARMV8_A64_PACIBZ, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
273	DIS_ARMV8_OP(0xd503237f, "pacibsp", OP_ARMV8_A64_PACIBSP, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
274	DIS_ARMV8_OP(0xd503239f, "autiaz", OP_ARMV8_A64_AUTIAZ, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
275	DIS_ARMV8_OP(0xd50323bf, "autiasp", OP_ARMV8_A64_AUTIASP, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
276	DIS_ARMV8_OP(0xd50323df, "autibz", OP_ARMV8_A64_AUTIBZ, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
277	DIS_ARMV8_OP(0xd50323ff, "autibsp", OP_ARMV8_A64_AUTIBSP, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
278	DIS_ARMV8_OP(0xd503241f, "bti", OP_ARMV8_A64_BTI, DISOPTYPE_HARMLESS), /* FEAT_BTI */
279	INVALID_OPCODE,
280	DIS_ARMV8_OP(0xd503245f, "bti c", OP_ARMV8_A64_BTI_C, DISOPTYPE_HARMLESS), /* FEAT_BTI */
281	INVALID_OPCODE,
282	DIS_ARMV8_OP(0xd503249f, "bti j", OP_ARMV8_A64_BTI_J, DISOPTYPE_HARMLESS), /* FEAT_BTI */
283	INVALID_OPCODE,
284	DIS_ARMV8_OP(0xd50324df, "bti jc", OP_ARMV8_A64_BTI_JC, DISOPTYPE_HARMLESS), /* FEAT_BTI */
285	INVALID_OPCODE,
286	DIS_ARMV8_OP(0xd503251f, "chkfeat x16", OP_ARMV8_A64_CHKFEAT, DISOPTYPE_HARMLESS), /* FEAT_CHK */
287	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Hints, 0xffffffff /fFixedInsn/,
288	kDisArmV8OpcDecodeNop, 0xfe0, 5);
289
290
291	/* CLREX */
292	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DecBarriers)
293	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 8, 4, 0 /idxParam/),
294	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DecBarriers)
295	INVALID_OPCODE,
296	INVALID_OPCODE,
297	DIS_ARMV8_OP(0xd503304f, "clrex", OP_ARMV8_A64_CLREX, DISOPTYPE_HARMLESS),
298	INVALID_OPCODE,
299	DIS_ARMV8_OP(0xD503309f, "dsb", OP_ARMV8_A64_DSB, DISOPTYPE_HARMLESS),
300	DIS_ARMV8_OP(0xd50330bf, "dmb", OP_ARMV8_A64_DMB, DISOPTYPE_HARMLESS),
301	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(DecBarriers, 0xfffff0ff /fFixedInsn/,
302	kDisArmV8OpcDecodeNop, RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7), 5);
303
304
305	/* Barrier instructions, we divide these instructions further based on the op2 field. */
306	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DecodeBarriers)
307	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
308	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo DSB - Encoding */
309	DIS_ARMV8_DECODE_MAP_ENTRY(DecBarriers), /* CLREX */
310	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo TCOMMIT */
311	DIS_ARMV8_DECODE_MAP_ENTRY(DecBarriers), /* DSB - Encoding */
312	DIS_ARMV8_DECODE_MAP_ENTRY(DecBarriers), /* DMB */
313	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo ISB */
314	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY /** @todo SB */
315	DIS_ARMV8_DECODE_MAP_DEFINE_END(DecodeBarriers, RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7), 5);
316
317
318	/* MSR (and potentially CFINV,XAFLAG,AXFLAG) */
319	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(PState)
320	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 8, 4, 1 /idxParam/), /* CRm field encodes the immediate value, gets validated by the next decoder stage. */
321	DIS_ARMV8_INSN_DECODE(kDisParmParsePState, 0, 0, 0 /idxParam/), /* This is special for the MSR instruction. */
322	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(PState)
323	DIS_ARMV8_OP(0xd500401f, "msr", OP_ARMV8_A64_MSR, DISOPTYPE_HARMLESS),
324	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(PState, 0xfff8f01f /fFixedInsn/,
325	kDisArmV8OpcDecodeNop, 0, 0);
326
327
328	/* TSTART/TTEST */
329	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysResult)
330	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
331	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysResult)
332	DIS_ARMV8_OP(0xd5233060, "tstart", OP_ARMV8_A64_TSTART, DISOPTYPE_HARMLESS \| DISOPTYPE_PRIVILEGED), /* FEAT_TME */
333	DIS_ARMV8_OP(0xd5233160, "ttest", OP_ARMV8_A64_TTEST, DISOPTYPE_HARMLESS), /* FEAT_TME */
334	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(SysResult, 0xfffffffe /fFixedInsn/,
335	kDisArmV8OpcDecodeNop, RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11), 8);
336
337
338	/* SYS */
339	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Sys)
340	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 16, 3, 0 /idxParam/),
341	DIS_ARMV8_INSN_DECODE(kDisParmParseCRnCRm, 8, 8, 1 /idxParam/),
342	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 3, 2 /idxParam/),
343	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 3 /idxParam/),
344	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Sys)
345	DIS_ARMV8_OP(0xd5080000, "sys", OP_ARMV8_A64_SYS, DISOPTYPE_HARMLESS),
346	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Sys, 0xfff80000 /fFixedInsn/,
347	kDisArmV8OpcDecodeNop, 0, 0); /** @todo */
348
349
350	/* SYSL */
351	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysL)
352	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
353	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 16, 3, 1 /idxParam/),
354	DIS_ARMV8_INSN_DECODE(kDisParmParseCRnCRm, 8, 8, 2 /idxParam/),
355	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 3, 3 /idxParam/),
356	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysL)
357	DIS_ARMV8_OP(0xd5280000, "sysl", OP_ARMV8_A64_SYSL, DISOPTYPE_HARMLESS),
358	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(SysL, 0xfff80000 /fFixedInsn/,
359	kDisArmV8OpcDecodeNop, 0, 0); /** @todo */
360
361
362	/* MSR */
363	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Msr)
364	DIS_ARMV8_INSN_DECODE(kDisParmParseSysReg, 5, 15, 0 /idxParam/),
365	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 1 /idxParam/),
366	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Msr)
367	DIS_ARMV8_OP(0xd5100000, "msr", OP_ARMV8_A64_MSR, DISOPTYPE_PRIVILEGED \| DISOPTYPE_PRIVILEGED),
368	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Msr, 0xfff00000 /fFixedInsn/,
369	kDisArmV8OpcDecodeNop, 0, 0);
370
371
372	/* MRS */
373	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Mrs)
374	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
375	DIS_ARMV8_INSN_DECODE(kDisParmParseSysReg, 5, 15, 1 /idxParam/),
376	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Mrs)
377	DIS_ARMV8_OP(0xd5300000, "mrs", OP_ARMV8_A64_MRS, DISOPTYPE_PRIVILEGED \| DISOPTYPE_PRIVILEGED),
378	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Mrs, 0xfff00000 /fFixedInsn/,
379	kDisArmV8OpcDecodeNop, 0, 0);
380
381
382	/* BR/BRAAZ/BRABZ */
383	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Br)
384	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
385	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Br)
386	DIS_ARMV8_OP(0xd61f0000, "br", OP_ARMV8_A64_BR, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
387	INVALID_OPCODE,
388	DIS_ARMV8_OP(0xd61f081f, "braaz", OP_ARMV8_A64_BRAAZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
389	DIS_ARMV8_OP(0xd61f0c1f, "brabz", OP_ARMV8_A64_BRABZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
390	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Br, 0xfffffc1f /fFixedInsn/, kDisArmV8OpcDecodeNop,
391	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
392
393
394	/* BLR/BLRAAZ/BLRABZ */
395	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Blr)
396	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
397	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Blr)
398	DIS_ARMV8_OP(0xd63f0000, "blr", OP_ARMV8_A64_BLR, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
399	INVALID_OPCODE,
400	DIS_ARMV8_OP(0xd63f081f, "blraaz", OP_ARMV8_A64_BLRAAZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
401	DIS_ARMV8_OP(0xd63f0c1f, "blrabz", OP_ARMV8_A64_BLRAAZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
402	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Blr, 0xfffffc1f /fFixedInsn/, kDisArmV8OpcDecodeNop,
403	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
404
405
406	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Ret)
407	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
408	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(RetPAuth)
409	DIS_ARMV8_INSN_DECODE(kDisParmParseRegFixed31, 5, 5, 0 /idxParam/),
410	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Ret)
411	DIS_ARMV8_OP( 0xd65f0000, "ret", OP_ARMV8_A64_RET, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
412	INVALID_OPCODE,
413	DIS_ARMV8_OP_ALT_DECODE(0xd65f081f, "retaa", OP_ARMV8_A64_RETAA, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW, RetPAuth),
414	DIS_ARMV8_OP_ALT_DECODE(0xd65f0c1f, "retab", OP_ARMV8_A64_RETAB, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW, RetPAuth),
415	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Ret, 0xfffffc1f /fFixedInsn/, kDisArmV8OpcDecodeNop,
416	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
417
418
419	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Eret)
420	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Eret)
421	DIS_ARMV8_OP(0xd69f03e0, "eret", OP_ARMV8_A64_ERET, DISOPTYPE_PRIVILEGED \| DISOPTYPE_CONTROLFLOW),
422	INVALID_OPCODE,
423	DIS_ARMV8_OP(0xd69f0bff, "eretaa", OP_ARMV8_A64_ERETAA, DISOPTYPE_PRIVILEGED \| DISOPTYPE_CONTROLFLOW),
424	DIS_ARMV8_OP(0xd69f0fff, "eretab", OP_ARMV8_A64_ERETAB, DISOPTYPE_PRIVILEGED \| DISOPTYPE_CONTROLFLOW),
425	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Eret, 0xffffffff /fFixedInsn/, kDisArmV8OpcDecodeNop,
426	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
427
428
429	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Drps)
430	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Drps)
431	DIS_ARMV8_OP(0xd6bf03e0, "drps", OP_ARMV8_A64_DRPS, DISOPTYPE_PRIVILEGED \| DISOPTYPE_CONTROLFLOW),
432	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Drps, 0xffffffff /fFixedInsn/, kDisArmV8OpcDecodeNop,
433	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
434
435
436	/* BRAA/BRAB */
437	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(BraaBrab)
438	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
439	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 0, 5, 1 /idxParam/),
440	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(BraaBrab)
441	INVALID_OPCODE,
442	INVALID_OPCODE,
443	DIS_ARMV8_OP(0xd71f0800, "braa", OP_ARMV8_A64_BRAA, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
444	DIS_ARMV8_OP(0xd71f0c00, "brab", OP_ARMV8_A64_BRAB, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
445	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(BraaBrab, 0xfffffc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
446	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
447
448
449	/* BRAA/BRAB */
450	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(BlraaBlrab) /** @todo Could use the same decoder as for braa/brab and save a bit of table size. */
451	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
452	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 0, 5, 1 /idxParam/),
453	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(BlraaBlrab)
454	INVALID_OPCODE,
455	INVALID_OPCODE,
456	DIS_ARMV8_OP(0xd73f0800, "blraa", OP_ARMV8_A64_BLRAA, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
457	DIS_ARMV8_OP(0xd73f0c00, "blrab", OP_ARMV8_A64_BLRAB, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
458	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(BlraaBlrab, 0xfffffc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
459	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
460
461
462	/* Unconditional branch (register) instructions, we divide these instructions further based on the opc field. */
463	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(UncondBrReg)
464	DIS_ARMV8_DECODE_MAP_ENTRY(Br), /* BR/BRAAZ/BRABZ */
465	DIS_ARMV8_DECODE_MAP_ENTRY(Blr), /* BLR/BLRAA/BLRAAZ/BLRAB/BLRABZ */
466	DIS_ARMV8_DECODE_MAP_ENTRY(Ret), /* RET/RETAA/RETAB */
467	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
468	DIS_ARMV8_DECODE_MAP_ENTRY(Eret), /* ERET/ERETAA/ERETAB */
469	DIS_ARMV8_DECODE_MAP_ENTRY(Drps), /* DRPS */
470	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
471	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
472	DIS_ARMV8_DECODE_MAP_ENTRY(BraaBrab), /* BRAA/BRAB */
473	DIS_ARMV8_DECODE_MAP_ENTRY(BlraaBlrab), /* BRAA/BRAB */
474	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
475	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
476	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
477	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
478	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
479	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY
480	DIS_ARMV8_DECODE_MAP_DEFINE_END(UncondBrReg, RT_BIT_32(21) \| RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(24), 21);
481
482
483	/* B/BL */
484	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(UncondBrImm)
485	DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 0, 26, 0 /idxParam/),
486	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(UncondBrImm)
487	DIS_ARMV8_OP(0x14000000, "b", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
488	DIS_ARMV8_OP(0x94000000, "bl", OP_ARMV8_A64_BL, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
489	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(UncondBrImm, 0xfc000000 /fFixedInsn/,
490	kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31);
491
492
493	/* CBZ/CBNZ */
494	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CmpBrImm)
495	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
496	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
497	DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 5, 19, 1 /idxParam/),
498	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CmpBrImm)
499	DIS_ARMV8_OP(0x34000000, "cbz", OP_ARMV8_A64_CBZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
500	DIS_ARMV8_OP(0x35000000, "cbnz", OP_ARMV8_A64_CBNZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
501	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(CmpBrImm, 0x7f000000 /fFixedInsn/,
502	kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24);
503
504
505	/* TBZ/TBNZ */
506	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(TestBrImm)
507	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET), /* Not an SF bit but has the same meaning. */
508	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
509	DIS_ARMV8_INSN_DECODE(kDisParmParseImmTbz, 0, 0, 1 /idxParam/), /* Hardcoded bit offsets in parser. */
510	DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 5, 14, 2 /idxParam/),
511	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(TestBrImm)
512	DIS_ARMV8_OP(0x36000000, "tbz", OP_ARMV8_A64_TBZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
513	DIS_ARMV8_OP(0x37000000, "tbnz", OP_ARMV8_A64_TBNZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
514	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(TestBrImm, 0x7f000000 /fFixedInsn/,
515	kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24);
516
517
518	DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(BrExcpSys)
519	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe000000, RT_BIT_32(26) \| RT_BIT_32(28) \| RT_BIT_32(30), CondBr), /* op0: 010, op1: 0xxxxxxxxxxxxx, op2: - (including o1 from the conditional branch (immediate) class to save us one layer). */
520	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xff000000, RT_BIT_32(26) \| RT_BIT_32(28) \| RT_BIT_32(30) \| RT_BIT_32(31), Excp), /* op0: 110, op1: 00xxxxxxxxxxxx, op2: -. */
521	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff000, 0xd5031000, SysReg), /* op0: 110, op1: 01000000110001, op2: -. */
522	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503201f, Hints), /* op0: 110, op1: 01000000110010, op2: 11111. */
523	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503301f, DecodeBarriers), /* op0: 110, op1: 01000000110011, op2: - (we include Rt: 11111 from the next stage here). */
524	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff8f01f, 0xd500401f, PState), /* op0: 110, op1: 0100000xxx0100, op2: - (we include Rt: 11111 from the next stage here). */
525	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff0e0, 0xd5233060, SysResult), /* op0: 110, op1: 0100100xxxxxxx, op2: - (we include op1, CRn and op2 from the next stage here). */
526	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5080000, Sys), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */
527	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5280000, SysL), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */
528	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5100000, Msr), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */
529	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5300000, Mrs), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */
530	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe1f0000, 0xd61f0000, UncondBrReg), /* op0: 110, op1: 1xxxxxxxxxxxxx, op2: - (we include the op2 field from the next stage here as it should be always 11111). */
531	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7c000000, 0x14000000, UncondBrImm), /* op0: x00, op1: xxxxxxxxxxxxxx, op2: -. */
532	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x34000000, CmpBrImm), /* op0: x01, op1: 0xxxxxxxxxxxxx, op2: -. */
533	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x36000000, TestBrImm), /* op0: x01, op1: 1xxxxxxxxxxxxx, op2: -. */
534	DIS_ARMV8_DECODE_TBL_DEFINE_END(BrExcpSys);
535
536
537	/* AND/ORR/EOR/ANDS */
538	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogShiftRegN0)
539	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
540	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
541	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
542	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
543	DIS_ARMV8_INSN_DECODE(kDisParmParseShift, 22, 2, 2 /idxParam/),
544	DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount, 10, 6, 2 /idxParam/),
545	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogShiftRegN0)
546	DIS_ARMV8_OP(0x0a000000, "and", OP_ARMV8_A64_AND, DISOPTYPE_HARMLESS),
547	DIS_ARMV8_OP(0x2a000000, "orr", OP_ARMV8_A64_ORR, DISOPTYPE_HARMLESS),
548	DIS_ARMV8_OP(0x4a000000, "eor", OP_ARMV8_A64_EOR, DISOPTYPE_HARMLESS),
549	DIS_ARMV8_OP(0x6a000000, "ands", OP_ARMV8_A64_ANDS, DISOPTYPE_HARMLESS)
550	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LogShiftRegN0, 0x7f200000 /fFixedInsn/,
551	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
552
553
554	/* AND/ORR/EOR/ANDS */
555	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogShiftRegN1)
556	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
557	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
558	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
559	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
560	DIS_ARMV8_INSN_DECODE(kDisParmParseShift, 22, 2, 2 /idxParam/),
561	DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount, 10, 6, 2 /idxParam/),
562	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogShiftRegN1)
563	DIS_ARMV8_OP(0x0a200000, "bic", OP_ARMV8_A64_BIC, DISOPTYPE_HARMLESS),
564	DIS_ARMV8_OP(0x2a200000, "orn", OP_ARMV8_A64_ORN, DISOPTYPE_HARMLESS),
565	DIS_ARMV8_OP(0x4a200000, "eon", OP_ARMV8_A64_EON, DISOPTYPE_HARMLESS),
566	DIS_ARMV8_OP(0x6a200000, "bics", OP_ARMV8_A64_BICS, DISOPTYPE_HARMLESS)
567	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LogShiftRegN1, 0x7f200000 /fFixedInsn/,
568	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
569
570
571	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LogShiftRegN)
572	DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN0), /* Logical (shifted register) - N = 0 */
573	DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN1), /* Logical (shifted register) - N = 1 */
574	DIS_ARMV8_DECODE_MAP_DEFINE_END(LogShiftRegN, RT_BIT_32(21), 21);
575
576
577	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(AddSubExtReg)
578	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
579	DIS_ARMV8_DECODE_MAP_DEFINE_END(AddSubExtReg, RT_BIT_32(24), 24);
580
581
582	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(AddSubShiftExtReg)
583	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubShiftReg), /* Add/Subtract (shifted register) */
584	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubExtReg), /* Add/Subtract (extended register) */
585	DIS_ARMV8_DECODE_MAP_DEFINE_END(AddSubShiftExtReg, RT_BIT_32(21), 21);
586
587
588	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LogicalAddSubReg)
589	DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN), /* Logical (shifted register) */
590	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubShiftExtReg), /* Add/subtract (shifted/extended register) */
591	DIS_ARMV8_DECODE_MAP_DEFINE_END(LogicalAddSubReg, RT_BIT_32(24), 24);
592
593
594	/* CCMN/CCMP */
595	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CondCmpReg)
596	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
597	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
598	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 1 /idxParam/),
599	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 0, 4, 2 /idxParam/),
600	DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 12, 4, 3 /idxParam/),
601	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CondCmpReg)
602	DIS_ARMV8_OP(0x3a400000, "ccmn", OP_ARMV8_A64_CCMN, DISOPTYPE_HARMLESS),
603	DIS_ARMV8_OP(0x7a400000, "ccmp", OP_ARMV8_A64_CCMP, DISOPTYPE_HARMLESS)
604	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(CondCmpReg, 0x7fe00c10 /fFixedInsn/,
605	kDisArmV8OpcDecodeNop, RT_BIT_32(30), 30);
606
607
608	/**
609	* C4.1.95 - Data Processing - Register
610	*
611	* The conditional compare instructions differentiate between register and immediate
612	* variant based on the 11th bit (part of op3).
613	*/
614	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(CondCmp)
615	DIS_ARMV8_DECODE_MAP_ENTRY(CondCmpReg), /* Conditional compare register */
616	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Conditional compare immediate */
617	DIS_ARMV8_DECODE_MAP_DEFINE_END(CondCmp, RT_BIT_32(11), 11);
618
619
620	/* UDIV/SDIV/LSLV/LSRV/ASRV/RORV/CRC32.../SMAX/UMAX/SMIN/UMIN */
621	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Reg2Src32Bit)
622	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
623	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
624	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
625	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
626	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Reg2Src32Bit)
627	INVALID_OPCODE,
628	INVALID_OPCODE,
629	DIS_ARMV8_OP(0x1ac00800, "udiv", OP_ARMV8_A64_UDIV, DISOPTYPE_HARMLESS),
630	DIS_ARMV8_OP(0x1ac00c00, "sdiv", OP_ARMV8_A64_SDIV, DISOPTYPE_HARMLESS),
631	INVALID_OPCODE,
632	INVALID_OPCODE,
633	INVALID_OPCODE,
634	INVALID_OPCODE,
635	DIS_ARMV8_OP(0x1ac02000, "lslv", OP_ARMV8_A64_LSLV, DISOPTYPE_HARMLESS),
636	DIS_ARMV8_OP(0x1ac02400, "lsrv", OP_ARMV8_A64_LSRV, DISOPTYPE_HARMLESS),
637	DIS_ARMV8_OP(0x1ac02800, "asrv", OP_ARMV8_A64_ASRV, DISOPTYPE_HARMLESS),
638	DIS_ARMV8_OP(0x1ac02c00, "rorv", OP_ARMV8_A64_RORV, DISOPTYPE_HARMLESS),
639	INVALID_OPCODE,
640	INVALID_OPCODE,
641	INVALID_OPCODE,
642	INVALID_OPCODE,
643	DIS_ARMV8_OP(0x1ac04000, "crc32b", OP_ARMV8_A64_CRC32B, DISOPTYPE_HARMLESS),
644	DIS_ARMV8_OP(0x1ac04400, "crc32h", OP_ARMV8_A64_CRC32H, DISOPTYPE_HARMLESS),
645	DIS_ARMV8_OP(0x1ac04800, "crc32w", OP_ARMV8_A64_CRC32W, DISOPTYPE_HARMLESS),
646	INVALID_OPCODE,
647	DIS_ARMV8_OP(0x1ac05000, "crc32cb", OP_ARMV8_A64_CRC32CB, DISOPTYPE_HARMLESS),
648	DIS_ARMV8_OP(0x1ac05400, "crc32ch", OP_ARMV8_A64_CRC32CH, DISOPTYPE_HARMLESS),
649	DIS_ARMV8_OP(0x1ac05800, "crc32cw", OP_ARMV8_A64_CRC32CW, DISOPTYPE_HARMLESS),
650	INVALID_OPCODE,
651	DIS_ARMV8_OP(0x1ac06000, "smax", OP_ARMV8_A64_SMAX, DISOPTYPE_HARMLESS),
652	DIS_ARMV8_OP(0x1ac06400, "umax", OP_ARMV8_A64_UMAX, DISOPTYPE_HARMLESS),
653	DIS_ARMV8_OP(0x1ac06800, "smin", OP_ARMV8_A64_SMIN, DISOPTYPE_HARMLESS),
654	DIS_ARMV8_OP(0x1ac06c00, "umin", OP_ARMV8_A64_UMIN, DISOPTYPE_HARMLESS),
655	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Reg2Src32Bit, 0xffe0fc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
656	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
657
658
659	/* UDIV/SDIV/LSLV/LSRV/ASRV/RORV/CRC32.../SMAX/UMAX/SMIN/UMIN */
660	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Reg2Src64Bit)
661	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
662	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
663	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
664	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg2SrcCrc32X)
665	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 0, 5, 0 /idxParam/),
666	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 5, 5, 1 /idxParam/),
667	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 16, 5, 2 /idxParam/),
668	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg2SrcSubp)
669	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 0, 5, 0 /idxParam/),
670	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
671	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 16, 5, 2 /idxParam/),
672	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg2SrcIrg)
673	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 0, 5, 0 /idxParam/),
674	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
675	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 16, 5, 2 /idxParam/),
676	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg2SrcGmi)
677	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
678	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
679	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
680	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Reg2Src64Bit)
681	DIS_ARMV8_OP_ALT_DECODE(0x9ac00000, "subp", OP_ARMV8_A64_SUBP, DISOPTYPE_HARMLESS, Reg2SrcSubp),
682	INVALID_OPCODE,
683	DIS_ARMV8_OP( 0x9ac00800, "udiv", OP_ARMV8_A64_UDIV, DISOPTYPE_HARMLESS),
684	DIS_ARMV8_OP( 0x9ac00c00, "sdiv", OP_ARMV8_A64_SDIV, DISOPTYPE_HARMLESS),
685	DIS_ARMV8_OP_ALT_DECODE(0x9ac01000, "irg", OP_ARMV8_A64_IRG, DISOPTYPE_HARMLESS, Reg2SrcIrg),
686	DIS_ARMV8_OP_ALT_DECODE(0x9ac01400, "gmi", OP_ARMV8_A64_GMI, DISOPTYPE_HARMLESS, Reg2SrcGmi),
687	INVALID_OPCODE,
688	INVALID_OPCODE,
689	DIS_ARMV8_OP( 0x9ac02000, "lslv", OP_ARMV8_A64_LSLV, DISOPTYPE_HARMLESS),
690	DIS_ARMV8_OP( 0x9ac02400, "lsrv", OP_ARMV8_A64_LSRV, DISOPTYPE_HARMLESS),
691	DIS_ARMV8_OP( 0x9ac02800, "asrv", OP_ARMV8_A64_ASRV, DISOPTYPE_HARMLESS),
692	DIS_ARMV8_OP( 0x9ac02c00, "rorv", OP_ARMV8_A64_RORV, DISOPTYPE_HARMLESS),
693	INVALID_OPCODE, /** @todo PACGA (FEAT_PAuth). */
694	INVALID_OPCODE,
695	INVALID_OPCODE,
696	INVALID_OPCODE,
697	INVALID_OPCODE,
698	INVALID_OPCODE,
699	INVALID_OPCODE,
700	DIS_ARMV8_OP_ALT_DECODE(0x9ac04c00, "crc32x", OP_ARMV8_A64_CRC32X, DISOPTYPE_HARMLESS, Reg2SrcCrc32X),
701	INVALID_OPCODE,
702	INVALID_OPCODE,
703	INVALID_OPCODE,
704	DIS_ARMV8_OP_ALT_DECODE(0x9ac05c00, "crc32cx", OP_ARMV8_A64_CRC32CX, DISOPTYPE_HARMLESS, Reg2SrcCrc32X),
705	DIS_ARMV8_OP( 0x9ac06000, "smax", OP_ARMV8_A64_SMAX, DISOPTYPE_HARMLESS),
706	DIS_ARMV8_OP( 0x9ac06400, "umax", OP_ARMV8_A64_UMAX, DISOPTYPE_HARMLESS),
707	DIS_ARMV8_OP( 0x9ac06800, "smin", OP_ARMV8_A64_SMIN, DISOPTYPE_HARMLESS),
708	DIS_ARMV8_OP( 0x9ac06c00, "umin", OP_ARMV8_A64_UMIN, DISOPTYPE_HARMLESS)
709	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Reg2Src64Bit, 0xffe0fc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
710	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
711
712
713	/* SUBPS */
714	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Subps)
715	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
716	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
717	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 16, 5, 2 /idxParam/),
718	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Subps)
719	DIS_ARMV8_OP(0xbac00000, "subps", OP_ARMV8_A64_SUBPS, DISOPTYPE_HARMLESS),
720	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Subps, 0xffe0fc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
721	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
722
723
724	/**
725	* C4.1.95 - Data Processing - Register - 2-source
726	*
727	* Differentiate between 32-bit and 64-bit groups based on the SF bit.
728	* Not done as a general decoder step because there are different instructions in each group.
729	*/
730	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(Reg2Src)
731	DIS_ARMV8_DECODE_MAP_ENTRY(Reg2Src32Bit), /* Data-processing (2-source, 32-bit) */
732	DIS_ARMV8_DECODE_MAP_ENTRY(Reg2Src64Bit), /* Data-processing (2-source, 64-bit) */
733	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(Reg2Src, 31);
734
735
736	/**
737	* C4.1.95 - Data Processing - Register - 2-source
738	*
739	* Differentiate between SUBPS and the rest based on the S bit.
740	*/
741	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(Reg2SrcSubps)
742	DIS_ARMV8_DECODE_MAP_ENTRY(Reg2Src), /* Data-processing (2-source) */
743	DIS_ARMV8_DECODE_MAP_ENTRY(Subps), /* Subps */
744	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(Reg2SrcSubps, 29);
745
746
747	/* RBIT/REV16/REV/CLZ/CLS/CTZ/CNT/ABS/REV32 */
748	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Reg1SrcInsn)
749	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
750	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
751	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
752	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Reg1SrcInsn)
753	DIS_ARMV8_OP(0x5ac00000, "rbit", OP_ARMV8_A64_RBIT, DISOPTYPE_HARMLESS),
754	DIS_ARMV8_OP(0x5ac00400, "rev16", OP_ARMV8_A64_REV16, DISOPTYPE_HARMLESS),
755	DIS_ARMV8_OP(0x5ac00800, "rev", OP_ARMV8_A64_REV, DISOPTYPE_HARMLESS), /** @todo REV32 if SF1 is 1 (why must this be so difficult ARM?). */
756	DIS_ARMV8_OP(0x5ac00c00, "rev", OP_ARMV8_A64_REV, DISOPTYPE_HARMLESS), /** @todo SF must be 1, otherwise unallocated. */
757	DIS_ARMV8_OP(0x5ac01000, "clz", OP_ARMV8_A64_CLZ, DISOPTYPE_HARMLESS),
758	DIS_ARMV8_OP(0x5ac01400, "cls", OP_ARMV8_A64_CLS, DISOPTYPE_HARMLESS),
759	DIS_ARMV8_OP(0x5ac01800, "ctz", OP_ARMV8_A64_CTZ, DISOPTYPE_HARMLESS),
760	DIS_ARMV8_OP(0x5ac01c00, "cnt", OP_ARMV8_A64_CNT, DISOPTYPE_HARMLESS),
761	DIS_ARMV8_OP(0x5ac02000, "abs", OP_ARMV8_A64_ABS, DISOPTYPE_HARMLESS),
762	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Reg1SrcInsn, 0x7ffffc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
763	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
764
765
766	/**
767	* C4.1.95 - Data Processing - Register - 1-source
768	*
769	* Differentiate between standard and FEAT_PAuth instructions based on opcode2 field.
770	*/
771	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(Reg1Src)
772	DIS_ARMV8_DECODE_MAP_ENTRY(Reg1SrcInsn), /* Data-processing (1-source) */
773	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Data-processing (1-source, FEAT_PAuth) */
774	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(Reg1Src, 16);
775
776
777	/**
778	* C4.1.95 - Data Processing - Register - 2-source / 1-source
779	*
780	* The 2-source and 1-source instruction classes differentiate based on bit 30.
781	*/
782	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(Reg2Src1Src)
783	DIS_ARMV8_DECODE_MAP_ENTRY(Reg2SrcSubps), /* Data-processing (2-source) */
784	DIS_ARMV8_DECODE_MAP_ENTRY(Reg1Src), /* Data-processing (1-source) */
785	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(Reg2Src1Src, 30);
786
787
788	/* CSEL/CSINC/CSINV/CSNEG */
789	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CondSel)
790	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
791	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
792	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
793	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
794	DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 12, 4, 3 /idxParam/),
795	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CondSel)
796	DIS_ARMV8_OP(0x1a800000, "csel", OP_ARMV8_A64_CSEL, DISOPTYPE_HARMLESS),
797	DIS_ARMV8_OP(0x1a800400, "csinc", OP_ARMV8_A64_CSINC, DISOPTYPE_HARMLESS),
798	INVALID_OPCODE,
799	INVALID_OPCODE,
800	DIS_ARMV8_OP(0x5a800000, "csinv", OP_ARMV8_A64_CSINC, DISOPTYPE_HARMLESS),
801	DIS_ARMV8_OP(0x5a800400, "csneg", OP_ARMV8_A64_CSNEG, DISOPTYPE_HARMLESS)
802	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(CondSel, 0x7fe00c00 /fFixedInsn/, kDisArmV8OpcDecodeCollate,
803	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(30), 10);
804
805
806	/* MADD/MSUB (32-bit) */
807	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Reg3Src32)
808	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 0, 5, 0 /idxParam/),
809	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 5, 5, 1 /idxParam/),
810	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 16, 5, 2 /idxParam/),
811	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 10, 5, 3 /idxParam/),
812	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Reg3Src32)
813	DIS_ARMV8_OP(0x1b000000, "madd", OP_ARMV8_A64_MADD, DISOPTYPE_HARMLESS),
814	DIS_ARMV8_OP(0x1b008000, "msub", OP_ARMV8_A64_MSUB, DISOPTYPE_HARMLESS),
815	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Reg3Src32, 0xffe08000 /fFixedInsn/, kDisArmV8OpcDecodeNop,
816	RT_BIT_32(15), 15);
817
818
819	/* MADD/MSUB (64-bit) /SMADDL/SMSUBL/SMULH/UMADDL/UMSUBL/UMULH */
820	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Reg3Src64)
821	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 0, 5, 0 /idxParam/),
822	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 5, 5, 1 /idxParam/),
823	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 16, 5, 2 /idxParam/),
824	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 10, 5, 3 /idxParam/),
825	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg3Src64_32)
826	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 0, 5, 0 /idxParam/),
827	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 5, 5, 1 /idxParam/),
828	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 16, 5, 2 /idxParam/),
829	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 10, 5, 3 /idxParam/),
830	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg3Src64Mul) /** @todo Ra == 11111 (or is it ignored?) */
831	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 0, 5, 0 /idxParam/),
832	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 5, 5, 1 /idxParam/),
833	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 16, 5, 2 /idxParam/),
834	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Reg3Src64)
835	DIS_ARMV8_OP( 0x9b000000, "madd", OP_ARMV8_A64_MADD, DISOPTYPE_HARMLESS),
836	DIS_ARMV8_OP( 0x9b008000, "msub", OP_ARMV8_A64_MSUB, DISOPTYPE_HARMLESS),
837	DIS_ARMV8_OP_ALT_DECODE(0x9b200000, "smaddl", OP_ARMV8_A64_SMADDL, DISOPTYPE_HARMLESS, Reg3Src64_32),
838	DIS_ARMV8_OP_ALT_DECODE(0x9b208000, "smsubl", OP_ARMV8_A64_SMSUBL, DISOPTYPE_HARMLESS, Reg3Src64_32),
839	DIS_ARMV8_OP_ALT_DECODE(0x9b400000, "smulh", OP_ARMV8_A64_SMULH, DISOPTYPE_HARMLESS, Reg3Src64Mul),
840	INVALID_OPCODE,
841	INVALID_OPCODE,
842	INVALID_OPCODE,
843	INVALID_OPCODE,
844	INVALID_OPCODE,
845	DIS_ARMV8_OP_ALT_DECODE(0x9ba00000, "umaddl", OP_ARMV8_A64_UMADDL, DISOPTYPE_HARMLESS, Reg3Src64_32),
846	DIS_ARMV8_OP_ALT_DECODE(0x9ba08000, "umsubl", OP_ARMV8_A64_UMSUBL, DISOPTYPE_HARMLESS, Reg3Src64_32),
847	DIS_ARMV8_OP_ALT_DECODE(0x9bc00000, "umulh", OP_ARMV8_A64_UMULH, DISOPTYPE_HARMLESS, Reg3Src64Mul),
848	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Reg3Src64, 0xffe08000 /fFixedInsn/, kDisArmV8OpcDecodeCollate,
849	RT_BIT_32(15) \| RT_BIT_32(21) \| RT_BIT_32(22) \| RT_BIT_32(23), 15);
850
851
852	/**
853	* C4.1.95.12 - Data Processing - Register - 3-source
854	*
855	* We differentiate further based on SF because there are different instructions encoded
856	* for 32-bit and 64-bit.
857	*/
858	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(Reg3Src)
859	DIS_ARMV8_DECODE_MAP_ENTRY(Reg3Src32), /* 3-source 32-bit */
860	DIS_ARMV8_DECODE_MAP_ENTRY(Reg3Src64), /* 3-source 64-bit */
861	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(Reg3Src, 31);
862
863
864	/*
865	* C4.1.95 - Data Processing - Register
866	*
867	* The op1 field is already decoded in the previous step and is 1 when being here,
868	* leaving us with the following possible values:
869	*
870	* Bit 24 23 22 21
871	* +-------------------------------------------
872	* 0 0 0 0 Add/subtract with carry / Rotate right into flags / Evaluate into flags (depending on op3)
873	* 0 0 0 1 UNALLOC
874	* 0 0 1 0 Conditional compare (register / immediate)
875	* 0 0 1 1 UNALLOC
876	* 0 1 0 0 Conditional select
877	* 0 1 0 1 UNALLOC
878	* 0 1 1 0 Data processing (2-source or 1-source depending on op0).
879	* 0 1 1 1 UNALLOC
880	* 1 x x x Data processing 3-source
881	*/
882	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcReg)
883	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Add/subtract with carry. */
884	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
885	DIS_ARMV8_DECODE_MAP_ENTRY(CondCmp),
886	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
887	DIS_ARMV8_DECODE_MAP_ENTRY(CondSel),
888	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
889	DIS_ARMV8_DECODE_MAP_ENTRY(Reg2Src1Src),
890	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
891	DIS_ARMV8_DECODE_MAP_ENTRY(Reg3Src),
892	DIS_ARMV8_DECODE_MAP_ENTRY(Reg3Src),
893	DIS_ARMV8_DECODE_MAP_ENTRY(Reg3Src),
894	DIS_ARMV8_DECODE_MAP_ENTRY(Reg3Src),
895	DIS_ARMV8_DECODE_MAP_ENTRY(Reg3Src),
896	DIS_ARMV8_DECODE_MAP_ENTRY(Reg3Src),
897	DIS_ARMV8_DECODE_MAP_ENTRY(Reg3Src),
898	DIS_ARMV8_DECODE_MAP_ENTRY(Reg3Src),
899	DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcReg, RT_BIT_32(21) \| RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(24), 21);
900
901
902	/*
903	* C4.1 of the ARMv8 architecture reference manual has the following table for the
904	* topmost decoding level (Level 0 in our terms), x means don't care:
905	*
906	* Bit 28 27 26 25
907	* +-------------------------------------------
908	* 0 0 0 0 Reserved or SME encoding (depends on bit 31).
909	* 0 0 0 1 UNALLOC
910	* 0 0 1 0 SVE encodings
911	* 0 0 1 1 UNALLOC
912	* 1 0 0 x Data processing immediate
913	* 1 0 1 x Branch, exception generation and system instructions
914	* x 1 x 0 Loads and stores
915	* x 1 0 1 Data processing - register
916	* x 1 1 1 Data processing - SIMD and floating point
917	*
918	* In order to save us some fiddling with the don't care bits we blow up the lookup table
919	* which gives us 16 possible values (4 bits) we can use as an index into the decoder
920	* lookup table for the next level:
921	* Bit 28 27 26 25
922	* +-------------------------------------------
923	* 0 0 0 0 0 Reserved or SME encoding (depends on bit 31).
924	* 1 0 0 0 1 UNALLOC
925	* 2 0 0 1 0 SVE encodings
926	* 3 0 0 1 1 UNALLOC
927	* 4 0 1 0 0 Loads and stores
928	* 5 0 1 0 1 Data processing - register (using op1 (bit 28) from the next stage to differentiate further already)
929	* 6 0 1 1 0 Loads and stores
930	* 7 0 1 1 1 Data processing - SIMD and floating point
931	* 8 1 0 0 0 Data processing immediate
932	* 9 1 0 0 1 Data processing immediate
933	* 10 1 0 1 0 Branch, exception generation and system instructions
934	* 11 1 0 1 1 Branch, exception generation and system instructions
935	* 12 1 1 0 0 Loads and stores
936	* 13 1 1 0 1 Data processing - register (using op1 (bit 28) from the next stage to differentiate further already)
937	* 14 1 1 1 0 Loads and stores
938	* 15 1 1 1 1 Data processing - SIMD and floating point
939	*/
940	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DecodeL0)
941	DIS_ARMV8_DECODE_MAP_ENTRY(Rsvd), /* Reserved class or SME encoding (@todo). */
942	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Unallocated */
943	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo SVE */
944	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Unallocated */
945	DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
946	DIS_ARMV8_DECODE_MAP_ENTRY(LogicalAddSubReg), /* Data processing (register) (see op1 in C4.1.68). */
947	DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
948	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_0), /* Data processing (SIMD & FP) (op0<0> 0) */
949	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcessingImm), /* Data processing (immediate). */
950	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcessingImm), /* Data processing (immediate). */
951	DIS_ARMV8_DECODE_MAP_ENTRY(BrExcpSys), /* Branches / Exception generation and system instructions. */
952	DIS_ARMV8_DECODE_MAP_ENTRY(BrExcpSys), /* Branches / Exception generation and system instructions. */
953	DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
954	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcReg), /* Data processing (register) (see op1 in C4.1.68). */
955	DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
956	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1) /* Data processing (SIMD & FP) (op0<0> 1). */
957	DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(DecodeL0, RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28), 25);

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source: vbox/trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp@ 106724

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