DisasmTables-armv8-a64.cpp@ 107044

Last change on this file since 107044 was 106760, checked in by vboxsync, 5 weeks ago
Disassembler: Decode Add/Subtract (extended register) instructions, bugref:10394
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1	/* $Id: DisasmTables-armv8-a64.cpp 106760 2024-10-28 18:00:32Z vboxsync $ */
2	/** @file
3	* VBox disassembler - Tables for ARMv8 A64.
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#include <VBox/dis.h>
33	#include <VBox/disopcode-armv8.h>
34	#include "DisasmInternal-armv8.h"
35
36
37	/*********************************************************************************************************************************
38	* Global Variables *
39	*********************************************************************************************************************************/
40
41	#define DIS_ARMV8_OP(a_fValue, a_szOpcode, a_uOpcode, a_fOpType) \
42	{ a_fValue, 0, NULL, OP(a_szOpcode, 0, 0, 0, a_uOpcode, 0, 0, 0, a_fOpType) }
43	#define DIS_ARMV8_OP_EX(a_fValue, a_szOpcode, a_uOpcode, a_fOpType, a_fFlags) \
44	{ a_fValue, a_fFlags, NULL, OP(a_szOpcode, 0, 0, 0, a_uOpcode, 0, 0, 0, a_fOpType) }
45	#define DIS_ARMV8_OP_ALT_DECODE(a_fValue, a_szOpcode, a_uOpcode, a_fOpType, a_aAltDecode) \
46	{ a_fValue, 0, &g_aArmV8A64Insn ## a_aAltDecode ## Decode[0], OP(a_szOpcode, 0, 0, 0, a_uOpcode, 0, 0, 0, a_fOpType) }
47
48
49	#ifndef DIS_CORE_ONLY
50	static char g_szInvalidOpcode[] = "Invalid Opcode";
51	#endif
52
53	#define INVALID_OPCODE \
54	DIS_ARMV8_OP(0, g_szInvalidOpcode, OP_ARMV8_INVALID, DISOPTYPE_INVALID)
55
56
57	/* Invalid opcode */
58	DECL_HIDDEN_CONST(DISOPCODE) g_ArmV8A64InvalidOpcode[1] =
59	{
60	OP(g_szInvalidOpcode, 0, 0, 0, 0, 0, 0, 0, DISOPTYPE_INVALID)
61	};
62
63
64	/* Include the secondary tables. */
65	#include "DisasmTables-armv8-a64-simd-fp.cpp.h"
66	#include "DisasmTables-armv8-a64-ld-st.cpp.h"
67
68	/* UDF */
69	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Rsvd)
70	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 0, 16, 0 /idxParam/),
71	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Rsvd)
72	DIS_ARMV8_OP(0x00000000, "udf" , OP_ARMV8_A64_UDF, DISOPTYPE_INVALID)
73	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Rsvd, 0xffff0000 /fFixedInsn/,
74	kDisArmV8OpcDecodeNop, 0xffff0000, 16);
75
76	/* ADR/ADRP */
77	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Adr)
78	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
79	DIS_ARMV8_INSN_DECODE(kDisParmParseImmAdr, 0, 0, 1 /idxParam/),
80	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Adr)
81	DIS_ARMV8_OP(0x10000000, "adr" , OP_ARMV8_A64_ADR, DISOPTYPE_HARMLESS),
82	DIS_ARMV8_OP(0x90000000, "adrp" , OP_ARMV8_A64_ADRP, DISOPTYPE_HARMLESS)
83	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Adr, 0x9f000000 /fFixedInsn/,
84	kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31);
85
86
87	/* ADD/ADDS/SUB/SUBS - shifted immediate variant */
88	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(AddSubImm)
89	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
90	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
91	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
92	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 10, 12, 2 /idxParam/),
93	DIS_ARMV8_INSN_DECODE(kDisParmParseSh12, 22, 1, 2 /idxParam/),
94	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(AddSubImm)
95	DIS_ARMV8_OP(0x11000000, "add" , OP_ARMV8_A64_ADD, DISOPTYPE_HARMLESS),
96	DIS_ARMV8_OP(0x31000000, "adds" , OP_ARMV8_A64_ADDS, DISOPTYPE_HARMLESS),
97	DIS_ARMV8_OP(0x51000000, "sub" , OP_ARMV8_A64_SUB, DISOPTYPE_HARMLESS),
98	DIS_ARMV8_OP(0x71000000, "subs" , OP_ARMV8_A64_SUBS, DISOPTYPE_HARMLESS),
99	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(AddSubImm, 0x7f800000 /fFixedInsn/,
100	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
101
102
103	/* ADD/ADDS/SUB/SUBS - shifted register variant */
104	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(AddSubShiftReg)
105	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
106	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
107	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
108	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
109	DIS_ARMV8_INSN_DECODE(kDisParmParseShift, 22, 2, 2 /idxParam/),
110	DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount, 10, 6, 2 /idxParam/),
111	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(AddSubShiftReg)
112	DIS_ARMV8_OP(0x0b000000, "add" , OP_ARMV8_A64_ADD, DISOPTYPE_HARMLESS),
113	DIS_ARMV8_OP(0x2b000000, "adds" , OP_ARMV8_A64_ADDS, DISOPTYPE_HARMLESS),
114	DIS_ARMV8_OP(0x4b000000, "sub" , OP_ARMV8_A64_SUB, DISOPTYPE_HARMLESS),
115	DIS_ARMV8_OP(0x6b000000, "subs" , OP_ARMV8_A64_SUBS, DISOPTYPE_HARMLESS),
116	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(AddSubShiftReg, 0x7f200000 /fFixedInsn/,
117	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
118
119
120	/* AND/ORR/EOR/ANDS */
121	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogicalImm)
122	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
123	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 0, 5, 0 /idxParam/),
124	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
125	DIS_ARMV8_INSN_DECODE(kDisParmParseImmsImmrN, 10, 13, 2 /idxParam/),
126	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogicalImm)
127	DIS_ARMV8_OP(0x12000000, "and" , OP_ARMV8_A64_AND, DISOPTYPE_HARMLESS),
128	DIS_ARMV8_OP(0x32000000, "orr" , OP_ARMV8_A64_ORR, DISOPTYPE_HARMLESS),
129	DIS_ARMV8_OP(0x52000000, "eor" , OP_ARMV8_A64_EOR, DISOPTYPE_HARMLESS),
130	DIS_ARMV8_OP(0x72000000, "ands" , OP_ARMV8_A64_ANDS, DISOPTYPE_HARMLESS),
131	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LogicalImm, 0x7f800000 /fFixedInsn/,
132	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
133
134
135	/* MOVN/MOVZ/MOVK */
136	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(MoveWide)
137	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
138	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
139	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 16, 1 /idxParam/),
140	DIS_ARMV8_INSN_DECODE(kDisParmParseHw, 21, 2, 1 /idxParam/),
141	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(MoveWide)
142	DIS_ARMV8_OP(0x12800000, "movn", OP_ARMV8_A64_MOVN, DISOPTYPE_HARMLESS),
143	INVALID_OPCODE,
144	DIS_ARMV8_OP(0x52800000, "movz" , OP_ARMV8_A64_MOVZ, DISOPTYPE_HARMLESS),
145	DIS_ARMV8_OP(0x72800000, "movk" , OP_ARMV8_A64_MOVK, DISOPTYPE_HARMLESS),
146	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(MoveWide, 0x7f800000 /fFixedInsn/,
147	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
148
149
150	/* SBFM/BFM/UBFM */
151	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Bitfield)
152	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
153	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
154	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
155	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 16, 6, 2 /idxParam/),
156	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 10, 6, 3 /idxParam/),
157	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Bitfield)
158	DIS_ARMV8_OP(0x13000000, "sbfm", OP_ARMV8_A64_SBFM, DISOPTYPE_HARMLESS),
159	DIS_ARMV8_OP(0x33000000, "bfm", OP_ARMV8_A64_BFM, DISOPTYPE_HARMLESS),
160	DIS_ARMV8_OP(0x53000000, "ubfm", OP_ARMV8_A64_UBFM, DISOPTYPE_HARMLESS),
161	INVALID_OPCODE,
162	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Bitfield, 0x7f800000 /fFixedInsn/,
163	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
164
165
166	/* EXTR */
167	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Extract) /** @todo N must match SF, and for sf == 0 -> imms<5> == 0. */
168	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
169	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
170	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
171	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
172	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 10, 6, 3 /idxParam/),
173	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Extract)
174	DIS_ARMV8_OP(0x13800000, "extr", OP_ARMV8_A64_EXTR, DISOPTYPE_HARMLESS),
175	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Extract, 0x7fa00000 /fFixedInsn/,
176	kDisArmV8OpcDecodeNop, 0, 0);
177
178
179	/* ADD/ADDS/SUB/SUBS - shifted immediate variant */
180	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(AddSubImmTags)
181	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 0, 5, 0 /idxParam/),
182	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
183	DIS_ARMV8_INSN_DECODE(kDisParmParseImmX16, 16, 6, 2 /idxParam/),
184	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 10, 4, 3 /idxParam/),
185	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(AddSubImmTags)
186	DIS_ARMV8_OP(0x91800000, "addg", OP_ARMV8_A64_ADDG, DISOPTYPE_HARMLESS), /* FEAT_MTE */
187	DIS_ARMV8_OP(0xd1800000, "subg" , OP_ARMV8_A64_SUBG, DISOPTYPE_HARMLESS), /* FEAT_MTE */
188	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(AddSubImmTags, 0xffc0c000 /fFixedInsn/,
189	kDisArmV8OpcDecodeNop, RT_BIT_32(30), 30);
190
191
192	/*
193	* C4.1.65 of the ARMv8 architecture reference manual has the following table for the
194	* data processing (immediate) instruction classes:
195	*
196	* Bit 25 24 23
197	* +-------------------------------------------
198	* 0 0 x PC-rel. addressing.
199	* 0 1 0 Add/subtract (immediate)
200	* 0 1 1 Add/subtract (immediate, with tags)
201	* 1 0 0 Logical (immediate)
202	* 1 0 1 Move wide (immediate)
203	* 1 1 0 Bitfield
204	* 1 1 1 Extract
205	*/
206	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcessingImm)
207	DIS_ARMV8_DECODE_MAP_ENTRY(Adr),
208	DIS_ARMV8_DECODE_MAP_ENTRY(Adr),
209	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubImm),
210	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubImmTags),
211	DIS_ARMV8_DECODE_MAP_ENTRY(LogicalImm),
212	DIS_ARMV8_DECODE_MAP_ENTRY(MoveWide),
213	DIS_ARMV8_DECODE_MAP_ENTRY(Bitfield),
214	DIS_ARMV8_DECODE_MAP_ENTRY(Extract)
215	DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcessingImm, RT_BIT_32(23) \| RT_BIT_32(24) \| RT_BIT_32(25), 23);
216
217
218	/* B.cond/BC.cond */
219	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CondBr)
220	DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 0, 4, DIS_ARMV8_INSN_PARAM_UNSET),
221	DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 5, 19, 0 /idxParam/),
222	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CondBr)
223	DIS_ARMV8_OP(0x54000000, "b", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_RELATIVE_CONTROLFLOW \| DISOPTYPE_COND_CONTROLFLOW),
224	DIS_ARMV8_OP(0x54000010, "bc" , OP_ARMV8_A64_BC, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_RELATIVE_CONTROLFLOW \| DISOPTYPE_COND_CONTROLFLOW),
225	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(CondBr, 0xff000010 /fFixedInsn/,
226	kDisArmV8OpcDecodeNop, RT_BIT_32(4), 4);
227
228
229	/* SVC/HVC/SMC/BRK/HLT/TCANCEL/DCPS1/DCPS2/DCPS3 */
230	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Excp)
231	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 16, 0 /idxParam/),
232	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Excp)
233	DIS_ARMV8_OP(0xd4000001, "svc", OP_ARMV8_A64_SVC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
234	DIS_ARMV8_OP(0xd4000002, "hvc", OP_ARMV8_A64_HVC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT \| DISOPTYPE_PRIVILEGED),
235	DIS_ARMV8_OP(0xd4000003, "smc", OP_ARMV8_A64_SMC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT \| DISOPTYPE_PRIVILEGED),
236	DIS_ARMV8_OP(0xd4200000, "brk", OP_ARMV8_A64_BRK, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
237	DIS_ARMV8_OP(0xd4400000, "hlt", OP_ARMV8_A64_HLT, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
238	DIS_ARMV8_OP(0xd4600000, "tcancel", OP_ARMV8_A64_TCANCEL, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT), /* FEAT_TME */
239	DIS_ARMV8_OP(0xd4a00001, "dcps1", OP_ARMV8_A64_DCPS1, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
240	DIS_ARMV8_OP(0xd4a00002, "dcps2", OP_ARMV8_A64_DCPS2, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
241	DIS_ARMV8_OP(0xd4a00003, "dcps3", OP_ARMV8_A64_DCPS3, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
242	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Excp, 0xffe0001f /fFixedInsn/,
243	kDisArmV8OpcDecodeLookup, 0xffe0001f, 0);
244
245
246	/* WFET/WFIT */
247	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysReg)
248	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
249	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysReg)
250	DIS_ARMV8_OP(0xd5031000, "wfet", OP_ARMV8_A64_WFET, DISOPTYPE_HARMLESS), /* FEAT_WFxT */
251	DIS_ARMV8_OP(0x54000010, "wfit" , OP_ARMV8_A64_WFIT, DISOPTYPE_HARMLESS), /* FEAT_WFxT */
252	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(SysReg, 0xffffffe0 /fFixedInsn/,
253	kDisArmV8OpcDecodeNop, 0xfe0, 5);
254
255
256	/* Various hint instructions */
257	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Hints)
258	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Hints)
259	DIS_ARMV8_OP(0xd503201f, "nop", OP_ARMV8_A64_NOP, DISOPTYPE_HARMLESS),
260	DIS_ARMV8_OP(0xd503203f, "yield", OP_ARMV8_A64_YIELD, DISOPTYPE_HARMLESS),
261	DIS_ARMV8_OP(0xd503205f, "wfe", OP_ARMV8_A64_WFE, DISOPTYPE_HARMLESS),
262	DIS_ARMV8_OP(0xd503207f, "wfi", OP_ARMV8_A64_WFI, DISOPTYPE_HARMLESS),
263	DIS_ARMV8_OP(0xd503209f, "sev", OP_ARMV8_A64_SEV, DISOPTYPE_HARMLESS),
264	DIS_ARMV8_OP(0xd50320bf, "sevl", OP_ARMV8_A64_SEVL, DISOPTYPE_HARMLESS),
265	DIS_ARMV8_OP(0xd50320df, "dgh", OP_ARMV8_A64_DGH, DISOPTYPE_HARMLESS), /* FEAT_DGH */
266	DIS_ARMV8_OP(0xd50320ff, "xpaclri", OP_ARMV8_A64_XPACLRI, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
267	DIS_ARMV8_OP(0xd503211f, "pacia1716", OP_ARMV8_A64_PACIA1716, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
268	INVALID_OPCODE,
269	DIS_ARMV8_OP(0xd503215f, "pacib1716", OP_ARMV8_A64_PACIB1716, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
270	INVALID_OPCODE,
271	DIS_ARMV8_OP(0xd503219f, "autia1716", OP_ARMV8_A64_AUTIA1716, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
272	INVALID_OPCODE,
273	DIS_ARMV8_OP(0xd50321df, "autib1716", OP_ARMV8_A64_AUTIB1716, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
274	INVALID_OPCODE,
275	DIS_ARMV8_OP(0xd503221f, "esb", OP_ARMV8_A64_ESB, DISOPTYPE_HARMLESS), /* FEAT_RAS */
276	DIS_ARMV8_OP(0xd503223f, "psb csync", OP_ARMV8_A64_PSB, DISOPTYPE_HARMLESS), /* FEAT_SPE */
277	DIS_ARMV8_OP(0xd503225f, "tsb csync", OP_ARMV8_A64_TSB, DISOPTYPE_HARMLESS), /* FEAT_TRF */
278	DIS_ARMV8_OP(0xd503227f, "gcsb dsync", OP_ARMV8_A64_GCSB, DISOPTYPE_HARMLESS), /* FEAT_GCS */
279	DIS_ARMV8_OP(0xd503229f, "csdb", OP_ARMV8_A64_CSDB, DISOPTYPE_HARMLESS),
280	INVALID_OPCODE,
281	DIS_ARMV8_OP(0xd50322df, "clrbhb", OP_ARMV8_A64_CLRBHB, DISOPTYPE_HARMLESS), /* FEAT_CLRBHB */
282	INVALID_OPCODE,
283	DIS_ARMV8_OP(0xd503231f, "paciaz", OP_ARMV8_A64_PACIAZ, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
284	DIS_ARMV8_OP(0xd503233f, "paciasp", OP_ARMV8_A64_PACIASP, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
285	DIS_ARMV8_OP(0xd503235f, "pacibz", OP_ARMV8_A64_PACIBZ, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
286	DIS_ARMV8_OP(0xd503237f, "pacibsp", OP_ARMV8_A64_PACIBSP, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
287	DIS_ARMV8_OP(0xd503239f, "autiaz", OP_ARMV8_A64_AUTIAZ, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
288	DIS_ARMV8_OP(0xd50323bf, "autiasp", OP_ARMV8_A64_AUTIASP, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
289	DIS_ARMV8_OP(0xd50323df, "autibz", OP_ARMV8_A64_AUTIBZ, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
290	DIS_ARMV8_OP(0xd50323ff, "autibsp", OP_ARMV8_A64_AUTIBSP, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
291	DIS_ARMV8_OP(0xd503241f, "bti", OP_ARMV8_A64_BTI, DISOPTYPE_HARMLESS), /* FEAT_BTI */
292	INVALID_OPCODE,
293	DIS_ARMV8_OP(0xd503245f, "bti c", OP_ARMV8_A64_BTI_C, DISOPTYPE_HARMLESS), /* FEAT_BTI */
294	INVALID_OPCODE,
295	DIS_ARMV8_OP(0xd503249f, "bti j", OP_ARMV8_A64_BTI_J, DISOPTYPE_HARMLESS), /* FEAT_BTI */
296	INVALID_OPCODE,
297	DIS_ARMV8_OP(0xd50324df, "bti jc", OP_ARMV8_A64_BTI_JC, DISOPTYPE_HARMLESS), /* FEAT_BTI */
298	INVALID_OPCODE,
299	DIS_ARMV8_OP(0xd503251f, "chkfeat x16", OP_ARMV8_A64_CHKFEAT, DISOPTYPE_HARMLESS), /* FEAT_CHK */
300	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Hints, 0xffffffff /fFixedInsn/,
301	kDisArmV8OpcDecodeNop, 0xfe0, 5);
302
303
304	/* CLREX */
305	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DecBarriers)
306	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 8, 4, 0 /idxParam/),
307	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DecBarriers)
308	INVALID_OPCODE,
309	INVALID_OPCODE,
310	DIS_ARMV8_OP(0xd503304f, "clrex", OP_ARMV8_A64_CLREX, DISOPTYPE_HARMLESS),
311	INVALID_OPCODE,
312	DIS_ARMV8_OP(0xd503309f, "dsb", OP_ARMV8_A64_DSB, DISOPTYPE_HARMLESS),
313	DIS_ARMV8_OP(0xd50330bf, "dmb", OP_ARMV8_A64_DMB, DISOPTYPE_HARMLESS),
314	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(DecBarriers, 0xfffff0ff /fFixedInsn/,
315	kDisArmV8OpcDecodeNop, RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7), 5);
316
317
318	/* ISB */
319	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Isb)
320	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 8, 4, 0 /idxParam/),
321	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Isb)
322	DIS_ARMV8_OP(0xd50330df, "isb", OP_ARMV8_A64_ISB, DISOPTYPE_HARMLESS),
323	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Isb, 0xfffff0ff /fFixedInsn/,
324	kDisArmV8OpcDecodeNop, 0, 0);
325
326
327	/* SB */
328	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Sb)
329	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Sb)
330	DIS_ARMV8_OP(0xd50330ff, "sb", OP_ARMV8_A64_SB, DISOPTYPE_HARMLESS), /* FEAT_SB */
331	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Sb, 0xffffffff /fFixedInsn/,
332	kDisArmV8OpcDecodeNop, 0, 0);
333
334
335	/* TCOMMIT */
336	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(TCommit)
337	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(TCommit)
338	DIS_ARMV8_OP(0xd503307f, "tcommit", OP_ARMV8_A64_TCOMMIT, DISOPTYPE_HARMLESS), /* FEAT_TME */
339	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(TCommit, 0xffffffff /fFixedInsn/,
340	kDisArmV8OpcDecodeNop, 0, 0);
341
342
343	/* Barrier instructions, we divide these instructions further based on the op2 field. */
344	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DecodeBarriers)
345	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
346	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo DSB - Encoding (FEAT_XS) */
347	DIS_ARMV8_DECODE_MAP_ENTRY(DecBarriers), /* CLREX */
348	DIS_ARMV8_DECODE_MAP_ENTRY(TCommit),
349	DIS_ARMV8_DECODE_MAP_ENTRY(DecBarriers), /* DSB - Encoding */
350	DIS_ARMV8_DECODE_MAP_ENTRY(DecBarriers), /* DMB */
351	DIS_ARMV8_DECODE_MAP_ENTRY(Isb),
352	DIS_ARMV8_DECODE_MAP_ENTRY(Sb),
353	DIS_ARMV8_DECODE_MAP_DEFINE_END(DecodeBarriers, RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7), 5);
354
355
356	/* MSR (and potentially CFINV,XAFLAG,AXFLAG) */
357	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(PState)
358	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 8, 4, 1 /idxParam/), /* CRm field encodes the immediate value, gets validated by the next decoder stage. */
359	DIS_ARMV8_INSN_DECODE(kDisParmParsePState, 0, 0, 0 /idxParam/), /* This is special for the MSR instruction. */
360	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(PState)
361	DIS_ARMV8_OP(0xd500401f, "msr", OP_ARMV8_A64_MSR, DISOPTYPE_HARMLESS),
362	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(PState, 0xfff8f01f /fFixedInsn/,
363	kDisArmV8OpcDecodeNop, 0, 0);
364
365
366	/* TSTART/TTEST */
367	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysResult)
368	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
369	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysResult)
370	DIS_ARMV8_OP(0xd5233060, "tstart", OP_ARMV8_A64_TSTART, DISOPTYPE_HARMLESS \| DISOPTYPE_PRIVILEGED), /* FEAT_TME */
371	DIS_ARMV8_OP(0xd5233160, "ttest", OP_ARMV8_A64_TTEST, DISOPTYPE_HARMLESS), /* FEAT_TME */
372	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(SysResult, 0xfffffffe /fFixedInsn/,
373	kDisArmV8OpcDecodeNop, RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11), 8);
374
375
376	/* SYS */
377	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Sys)
378	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 16, 3, 0 /idxParam/),
379	DIS_ARMV8_INSN_DECODE(kDisParmParseCRnCRm, 8, 8, 1 /idxParam/),
380	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 3, 2 /idxParam/),
381	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 3 /idxParam/),
382	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Sys)
383	DIS_ARMV8_OP(0xd5080000, "sys", OP_ARMV8_A64_SYS, DISOPTYPE_HARMLESS),
384	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Sys, 0xfff80000 /fFixedInsn/,
385	kDisArmV8OpcDecodeNop, 0, 0); /** @todo */
386
387
388	/* SYSL */
389	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(SysL)
390	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
391	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 16, 3, 1 /idxParam/),
392	DIS_ARMV8_INSN_DECODE(kDisParmParseCRnCRm, 8, 8, 2 /idxParam/),
393	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 5, 3, 3 /idxParam/),
394	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(SysL)
395	DIS_ARMV8_OP(0xd5280000, "sysl", OP_ARMV8_A64_SYSL, DISOPTYPE_HARMLESS),
396	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(SysL, 0xfff80000 /fFixedInsn/,
397	kDisArmV8OpcDecodeNop, 0, 0); /** @todo */
398
399
400	/* MSR */
401	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Msr)
402	DIS_ARMV8_INSN_DECODE(kDisParmParseSysReg, 5, 15, 0 /idxParam/),
403	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 1 /idxParam/),
404	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Msr)
405	DIS_ARMV8_OP(0xd5100000, "msr", OP_ARMV8_A64_MSR, DISOPTYPE_PRIVILEGED \| DISOPTYPE_PRIVILEGED),
406	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Msr, 0xfff00000 /fFixedInsn/,
407	kDisArmV8OpcDecodeNop, 0, 0);
408
409
410	/* MRS */
411	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Mrs)
412	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
413	DIS_ARMV8_INSN_DECODE(kDisParmParseSysReg, 5, 15, 1 /idxParam/),
414	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Mrs)
415	DIS_ARMV8_OP(0xd5300000, "mrs", OP_ARMV8_A64_MRS, DISOPTYPE_PRIVILEGED \| DISOPTYPE_PRIVILEGED),
416	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Mrs, 0xfff00000 /fFixedInsn/,
417	kDisArmV8OpcDecodeNop, 0, 0);
418
419
420	/* BR/BRAAZ/BRABZ */
421	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Br)
422	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
423	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Br)
424	DIS_ARMV8_OP(0xd61f0000, "br", OP_ARMV8_A64_BR, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
425	INVALID_OPCODE,
426	DIS_ARMV8_OP(0xd61f081f, "braaz", OP_ARMV8_A64_BRAAZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
427	DIS_ARMV8_OP(0xd61f0c1f, "brabz", OP_ARMV8_A64_BRABZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
428	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Br, 0xfffffc1f /fFixedInsn/, kDisArmV8OpcDecodeNop,
429	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
430
431
432	/* BLR/BLRAAZ/BLRABZ */
433	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Blr)
434	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
435	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Blr)
436	DIS_ARMV8_OP(0xd63f0000, "blr", OP_ARMV8_A64_BLR, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_UNCOND_CONTROLFLOW),
437	INVALID_OPCODE,
438	DIS_ARMV8_OP(0xd63f081f, "blraaz", OP_ARMV8_A64_BLRAAZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_UNCOND_CONTROLFLOW),
439	DIS_ARMV8_OP(0xd63f0c1f, "blrabz", OP_ARMV8_A64_BLRABZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_UNCOND_CONTROLFLOW),
440	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Blr, 0xfffffc1f /fFixedInsn/, kDisArmV8OpcDecodeNop,
441	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
442
443
444	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Ret)
445	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
446	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(RetPAuth)
447	DIS_ARMV8_INSN_DECODE(kDisParmParseRegFixed31, 5, 5, 0 /idxParam/),
448	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Ret)
449	DIS_ARMV8_OP( 0xd65f0000, "ret", OP_ARMV8_A64_RET, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_UNCOND_CONTROLFLOW),
450	INVALID_OPCODE,
451	DIS_ARMV8_OP_ALT_DECODE(0xd65f081f, "retaa", OP_ARMV8_A64_RETAA, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_UNCOND_CONTROLFLOW, RetPAuth),
452	DIS_ARMV8_OP_ALT_DECODE(0xd65f0c1f, "retab", OP_ARMV8_A64_RETAB, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_UNCOND_CONTROLFLOW, RetPAuth),
453	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Ret, 0xfffffc1f /fFixedInsn/, kDisArmV8OpcDecodeNop,
454	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
455
456
457	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Eret)
458	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Eret)
459	DIS_ARMV8_OP(0xd69f03e0, "eret", OP_ARMV8_A64_ERET, DISOPTYPE_PRIVILEGED \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_UNCOND_CONTROLFLOW),
460	INVALID_OPCODE,
461	DIS_ARMV8_OP(0xd69f0bff, "eretaa", OP_ARMV8_A64_ERETAA, DISOPTYPE_PRIVILEGED \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_UNCOND_CONTROLFLOW),
462	DIS_ARMV8_OP(0xd69f0fff, "eretab", OP_ARMV8_A64_ERETAB, DISOPTYPE_PRIVILEGED \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_UNCOND_CONTROLFLOW),
463	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Eret, 0xffffffff /fFixedInsn/, kDisArmV8OpcDecodeNop,
464	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
465
466
467	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Drps)
468	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Drps)
469	DIS_ARMV8_OP(0xd6bf03e0, "drps", OP_ARMV8_A64_DRPS, DISOPTYPE_PRIVILEGED \| DISOPTYPE_CONTROLFLOW),
470	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Drps, 0xffffffff /fFixedInsn/, kDisArmV8OpcDecodeNop,
471	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
472
473
474	/* BRAA/BRAB */
475	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(BraaBrab)
476	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
477	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 0, 5, 1 /idxParam/),
478	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(BraaBrab)
479	INVALID_OPCODE,
480	INVALID_OPCODE,
481	DIS_ARMV8_OP(0xd71f0800, "braa", OP_ARMV8_A64_BRAA, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_UNCOND_CONTROLFLOW),
482	DIS_ARMV8_OP(0xd71f0c00, "brab", OP_ARMV8_A64_BRAB, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_UNCOND_CONTROLFLOW),
483	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(BraaBrab, 0xfffffc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
484	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
485
486
487	/* BRAA/BRAB */
488	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(BlraaBlrab) /** @todo Could use the same decoder as for braa/brab and save a bit of table size. */
489	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
490	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 0, 5, 1 /idxParam/),
491	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(BlraaBlrab)
492	INVALID_OPCODE,
493	INVALID_OPCODE,
494	DIS_ARMV8_OP(0xd73f0800, "blraa", OP_ARMV8_A64_BLRAA, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_UNCOND_CONTROLFLOW),
495	DIS_ARMV8_OP(0xd73f0c00, "blrab", OP_ARMV8_A64_BLRAB, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_UNCOND_CONTROLFLOW),
496	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(BlraaBlrab, 0xfffffc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
497	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
498
499
500	/* Unconditional branch (register) instructions, we divide these instructions further based on the opc field. */
501	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(UncondBrReg)
502	DIS_ARMV8_DECODE_MAP_ENTRY(Br), /* BR/BRAAZ/BRABZ */
503	DIS_ARMV8_DECODE_MAP_ENTRY(Blr), /* BLR/BLRAA/BLRAAZ/BLRAB/BLRABZ */
504	DIS_ARMV8_DECODE_MAP_ENTRY(Ret), /* RET/RETAA/RETAB */
505	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
506	DIS_ARMV8_DECODE_MAP_ENTRY(Eret), /* ERET/ERETAA/ERETAB */
507	DIS_ARMV8_DECODE_MAP_ENTRY(Drps), /* DRPS */
508	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
509	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
510	DIS_ARMV8_DECODE_MAP_ENTRY(BraaBrab), /* BRAA/BRAB */
511	DIS_ARMV8_DECODE_MAP_ENTRY(BlraaBlrab), /* BRAA/BRAB */
512	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
513	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
514	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
515	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
516	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
517	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY
518	DIS_ARMV8_DECODE_MAP_DEFINE_END(UncondBrReg, RT_BIT_32(21) \| RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(24), 21);
519
520
521	/* B/BL */
522	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(UncondBrImm)
523	DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 0, 26, 0 /idxParam/),
524	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(UncondBrImm)
525	DIS_ARMV8_OP(0x14000000, "b", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_RELATIVE_CONTROLFLOW \| DISOPTYPE_UNCOND_CONTROLFLOW),
526	DIS_ARMV8_OP(0x94000000, "bl", OP_ARMV8_A64_BL, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_RELATIVE_CONTROLFLOW \| DISOPTYPE_UNCOND_CONTROLFLOW),
527	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(UncondBrImm, 0xfc000000 /fFixedInsn/,
528	kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31);
529
530
531	/* CBZ/CBNZ */
532	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CmpBrImm)
533	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
534	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
535	DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 5, 19, 1 /idxParam/),
536	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CmpBrImm)
537	DIS_ARMV8_OP(0x34000000, "cbz", OP_ARMV8_A64_CBZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_RELATIVE_CONTROLFLOW \| DISOPTYPE_COND_CONTROLFLOW),
538	DIS_ARMV8_OP(0x35000000, "cbnz", OP_ARMV8_A64_CBNZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_RELATIVE_CONTROLFLOW \| DISOPTYPE_COND_CONTROLFLOW),
539	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(CmpBrImm, 0x7f000000 /fFixedInsn/,
540	kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24);
541
542
543	/* TBZ/TBNZ */
544	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(TestBrImm)
545	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET), /* Not an SF bit but has the same meaning. */
546	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
547	DIS_ARMV8_INSN_DECODE(kDisParmParseImmTbz, 0, 0, 1 /idxParam/), /* Hardcoded bit offsets in parser. */
548	DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel, 5, 14, 2 /idxParam/),
549	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(TestBrImm)
550	DIS_ARMV8_OP(0x36000000, "tbz", OP_ARMV8_A64_TBZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_RELATIVE_CONTROLFLOW \| DISOPTYPE_COND_CONTROLFLOW),
551	DIS_ARMV8_OP(0x37000000, "tbnz", OP_ARMV8_A64_TBNZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_RELATIVE_CONTROLFLOW \| DISOPTYPE_COND_CONTROLFLOW),
552	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(TestBrImm, 0x7f000000 /fFixedInsn/,
553	kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24);
554
555
556	DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(BrExcpSys)
557	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe000000, RT_BIT_32(26) \| RT_BIT_32(28) \| RT_BIT_32(30), CondBr), /* op0: 010, op1: 0xxxxxxxxxxxxx, op2: - (including o1 from the conditional branch (immediate) class to save us one layer). */
558	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xff000000, RT_BIT_32(26) \| RT_BIT_32(28) \| RT_BIT_32(30) \| RT_BIT_32(31), Excp), /* op0: 110, op1: 00xxxxxxxxxxxx, op2: -. */
559	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff000, 0xd5031000, SysReg), /* op0: 110, op1: 01000000110001, op2: -. */
560	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503201f, Hints), /* op0: 110, op1: 01000000110010, op2: 11111. */
561	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503301f, DecodeBarriers), /* op0: 110, op1: 01000000110011, op2: - (we include Rt: 11111 from the next stage here). */
562	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff8f01f, 0xd500401f, PState), /* op0: 110, op1: 0100000xxx0100, op2: - (we include Rt: 11111 from the next stage here). */
563	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff0e0, 0xd5233060, SysResult), /* op0: 110, op1: 0100100xxxxxxx, op2: - (we include op1, CRn and op2 from the next stage here). */
564	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5080000, Sys), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */
565	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5280000, SysL), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */
566	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5100000, Msr), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */
567	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5300000, Mrs), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */
568	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe1f0000, 0xd61f0000, UncondBrReg), /* op0: 110, op1: 1xxxxxxxxxxxxx, op2: - (we include the op2 field from the next stage here as it should be always 11111). */
569	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7c000000, 0x14000000, UncondBrImm), /* op0: x00, op1: xxxxxxxxxxxxxx, op2: -. */
570	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x34000000, CmpBrImm), /* op0: x01, op1: 0xxxxxxxxxxxxx, op2: -. */
571	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x36000000, TestBrImm), /* op0: x01, op1: 1xxxxxxxxxxxxx, op2: -. */
572	DIS_ARMV8_DECODE_TBL_DEFINE_END(BrExcpSys);
573
574
575	/* AND/ORR/EOR/ANDS */
576	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogShiftRegN0)
577	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
578	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
579	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
580	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
581	DIS_ARMV8_INSN_DECODE(kDisParmParseShift, 22, 2, 2 /idxParam/),
582	DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount, 10, 6, 2 /idxParam/),
583	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogShiftRegN0)
584	DIS_ARMV8_OP(0x0a000000, "and", OP_ARMV8_A64_AND, DISOPTYPE_HARMLESS),
585	DIS_ARMV8_OP(0x2a000000, "orr", OP_ARMV8_A64_ORR, DISOPTYPE_HARMLESS),
586	DIS_ARMV8_OP(0x4a000000, "eor", OP_ARMV8_A64_EOR, DISOPTYPE_HARMLESS),
587	DIS_ARMV8_OP(0x6a000000, "ands", OP_ARMV8_A64_ANDS, DISOPTYPE_HARMLESS)
588	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LogShiftRegN0, 0x7f200000 /fFixedInsn/,
589	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
590
591
592	/* AND/ORR/EOR/ANDS */
593	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LogShiftRegN1)
594	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
595	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
596	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
597	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
598	DIS_ARMV8_INSN_DECODE(kDisParmParseShift, 22, 2, 2 /idxParam/),
599	DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount, 10, 6, 2 /idxParam/),
600	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LogShiftRegN1)
601	DIS_ARMV8_OP(0x0a200000, "bic", OP_ARMV8_A64_BIC, DISOPTYPE_HARMLESS),
602	DIS_ARMV8_OP(0x2a200000, "orn", OP_ARMV8_A64_ORN, DISOPTYPE_HARMLESS),
603	DIS_ARMV8_OP(0x4a200000, "eon", OP_ARMV8_A64_EON, DISOPTYPE_HARMLESS),
604	DIS_ARMV8_OP(0x6a200000, "bics", OP_ARMV8_A64_BICS, DISOPTYPE_HARMLESS)
605	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LogShiftRegN1, 0x7f200000 /fFixedInsn/,
606	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
607
608
609	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LogShiftRegN)
610	DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN0), /* Logical (shifted register) - N = 0 */
611	DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN1), /* Logical (shifted register) - N = 1 */
612	DIS_ARMV8_DECODE_MAP_DEFINE_END(LogShiftRegN, RT_BIT_32(21), 21);
613
614
615	/* ADD/ADDS/SUB/SUBS */
616	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(AddSubExtReg)
617	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
618	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 0, 5, 0 /idxParam/),
619	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
620	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
621	DIS_ARMV8_INSN_DECODE(kDisParmParseOption, 13, 3, 2 /idxParam/),
622	DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount, 10, 3, 2 /idxParam/),
623	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(AddSubExtRegS)
624	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
625	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
626	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
627	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
628	DIS_ARMV8_INSN_DECODE(kDisParmParseOption, 13, 3, 2 /idxParam/),
629	DIS_ARMV8_INSN_DECODE(kDisParmParseShiftAmount, 10, 3, 2 /idxParam/),
630	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(AddSubExtReg)
631	DIS_ARMV8_OP( 0x0b200000, "add", OP_ARMV8_A64_ADD, DISOPTYPE_HARMLESS),
632	DIS_ARMV8_OP_ALT_DECODE(0x2b200000, "adds", OP_ARMV8_A64_ADDS, DISOPTYPE_HARMLESS, AddSubExtRegS),
633	DIS_ARMV8_OP( 0x4b200000, "sub", OP_ARMV8_A64_SUB, DISOPTYPE_HARMLESS),
634	DIS_ARMV8_OP_ALT_DECODE(0x6b200000, "subs", OP_ARMV8_A64_SUBS, DISOPTYPE_HARMLESS, AddSubExtRegS),
635	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(AddSubExtReg, 0x7fe00000 /fFixedInsn/,
636	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29);
637
638
639	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(AddSubShiftExtReg)
640	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubShiftReg), /* Add/Subtract (shifted register) */
641	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubExtReg), /* Add/Subtract (extended register) */
642	DIS_ARMV8_DECODE_MAP_DEFINE_END(AddSubShiftExtReg, RT_BIT_32(21), 21);
643
644
645	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LogicalAddSubReg)
646	DIS_ARMV8_DECODE_MAP_ENTRY(LogShiftRegN), /* Logical (shifted register) */
647	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubShiftExtReg), /* Add/subtract (shifted/extended register) */
648	DIS_ARMV8_DECODE_MAP_DEFINE_END(LogicalAddSubReg, RT_BIT_32(24), 24);
649
650
651	/* CCMN/CCMP */
652	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CondCmpReg)
653	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
654	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
655	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 1 /idxParam/),
656	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 0, 4, 2 /idxParam/),
657	DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 12, 4, 3 /idxParam/),
658	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CondCmpReg)
659	DIS_ARMV8_OP(0x3a400000, "ccmn", OP_ARMV8_A64_CCMN, DISOPTYPE_HARMLESS),
660	DIS_ARMV8_OP(0x7a400000, "ccmp", OP_ARMV8_A64_CCMP, DISOPTYPE_HARMLESS)
661	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(CondCmpReg, 0x7fe00c10 /fFixedInsn/,
662	kDisArmV8OpcDecodeNop, RT_BIT_32(30), 30);
663
664
665	/* CCMN/CCMP */
666	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CondCmpImm)
667	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
668	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 0 /idxParam/),
669	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 16, 5, 1 /idxParam/),
670	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 0, 4, 2 /idxParam/),
671	DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 12, 4, 3 /idxParam/),
672	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CondCmpImm)
673	DIS_ARMV8_OP(0x3a400800, "ccmn", OP_ARMV8_A64_CCMN, DISOPTYPE_HARMLESS),
674	DIS_ARMV8_OP(0x7a400800, "ccmp", OP_ARMV8_A64_CCMP, DISOPTYPE_HARMLESS)
675	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(CondCmpImm, 0x7fe00c10 /fFixedInsn/,
676	kDisArmV8OpcDecodeNop, RT_BIT_32(30), 30);
677
678
679	/**
680	* C4.1.95 - Data Processing - Register
681	*
682	* The conditional compare instructions differentiate between register and immediate
683	* variant based on the 11th bit (part of op3).
684	*/
685	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(CondCmp)
686	DIS_ARMV8_DECODE_MAP_ENTRY(CondCmpReg), /* Conditional compare register */
687	DIS_ARMV8_DECODE_MAP_ENTRY(CondCmpImm), /* Conditional compare immediate */
688	DIS_ARMV8_DECODE_MAP_DEFINE_END(CondCmp, RT_BIT_32(11), 11);
689
690
691	/* UDIV/SDIV/LSLV/LSRV/ASRV/RORV/CRC32.../SMAX/UMAX/SMIN/UMIN */
692	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Reg2Src32Bit)
693	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
694	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
695	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
696	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
697	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Reg2Src32Bit)
698	INVALID_OPCODE,
699	INVALID_OPCODE,
700	DIS_ARMV8_OP(0x1ac00800, "udiv", OP_ARMV8_A64_UDIV, DISOPTYPE_HARMLESS),
701	DIS_ARMV8_OP(0x1ac00c00, "sdiv", OP_ARMV8_A64_SDIV, DISOPTYPE_HARMLESS),
702	INVALID_OPCODE,
703	INVALID_OPCODE,
704	INVALID_OPCODE,
705	INVALID_OPCODE,
706	DIS_ARMV8_OP(0x1ac02000, "lslv", OP_ARMV8_A64_LSLV, DISOPTYPE_HARMLESS),
707	DIS_ARMV8_OP(0x1ac02400, "lsrv", OP_ARMV8_A64_LSRV, DISOPTYPE_HARMLESS),
708	DIS_ARMV8_OP(0x1ac02800, "asrv", OP_ARMV8_A64_ASRV, DISOPTYPE_HARMLESS),
709	DIS_ARMV8_OP(0x1ac02c00, "rorv", OP_ARMV8_A64_RORV, DISOPTYPE_HARMLESS),
710	INVALID_OPCODE,
711	INVALID_OPCODE,
712	INVALID_OPCODE,
713	INVALID_OPCODE,
714	DIS_ARMV8_OP(0x1ac04000, "crc32b", OP_ARMV8_A64_CRC32B, DISOPTYPE_HARMLESS),
715	DIS_ARMV8_OP(0x1ac04400, "crc32h", OP_ARMV8_A64_CRC32H, DISOPTYPE_HARMLESS),
716	DIS_ARMV8_OP(0x1ac04800, "crc32w", OP_ARMV8_A64_CRC32W, DISOPTYPE_HARMLESS),
717	INVALID_OPCODE,
718	DIS_ARMV8_OP(0x1ac05000, "crc32cb", OP_ARMV8_A64_CRC32CB, DISOPTYPE_HARMLESS),
719	DIS_ARMV8_OP(0x1ac05400, "crc32ch", OP_ARMV8_A64_CRC32CH, DISOPTYPE_HARMLESS),
720	DIS_ARMV8_OP(0x1ac05800, "crc32cw", OP_ARMV8_A64_CRC32CW, DISOPTYPE_HARMLESS),
721	INVALID_OPCODE,
722	DIS_ARMV8_OP(0x1ac06000, "smax", OP_ARMV8_A64_SMAX, DISOPTYPE_HARMLESS),
723	DIS_ARMV8_OP(0x1ac06400, "umax", OP_ARMV8_A64_UMAX, DISOPTYPE_HARMLESS),
724	DIS_ARMV8_OP(0x1ac06800, "smin", OP_ARMV8_A64_SMIN, DISOPTYPE_HARMLESS),
725	DIS_ARMV8_OP(0x1ac06c00, "umin", OP_ARMV8_A64_UMIN, DISOPTYPE_HARMLESS),
726	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Reg2Src32Bit, 0xffe0fc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
727	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
728
729
730	/* UDIV/SDIV/LSLV/LSRV/ASRV/RORV/CRC32.../SMAX/UMAX/SMIN/UMIN */
731	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Reg2Src64Bit)
732	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
733	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
734	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
735	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg2SrcCrc32X)
736	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 0, 5, 0 /idxParam/),
737	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 5, 5, 1 /idxParam/),
738	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 16, 5, 2 /idxParam/),
739	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg2SrcSubp)
740	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 0, 5, 0 /idxParam/),
741	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
742	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 16, 5, 2 /idxParam/),
743	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg2SrcIrg)
744	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 0, 5, 0 /idxParam/),
745	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
746	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 16, 5, 2 /idxParam/),
747	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg2SrcGmi)
748	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
749	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
750	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
751	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg2SrcPacga)
752	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 0, 5, 0 /idxParam/),
753	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 5, 5, 1 /idxParam/),
754	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 16, 5, 2 /idxParam/),
755	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Reg2Src64Bit)
756	DIS_ARMV8_OP_ALT_DECODE(0x9ac00000, "subp", OP_ARMV8_A64_SUBP, DISOPTYPE_HARMLESS, Reg2SrcSubp),
757	INVALID_OPCODE,
758	DIS_ARMV8_OP( 0x9ac00800, "udiv", OP_ARMV8_A64_UDIV, DISOPTYPE_HARMLESS),
759	DIS_ARMV8_OP( 0x9ac00c00, "sdiv", OP_ARMV8_A64_SDIV, DISOPTYPE_HARMLESS),
760	DIS_ARMV8_OP_ALT_DECODE(0x9ac01000, "irg", OP_ARMV8_A64_IRG, DISOPTYPE_HARMLESS, Reg2SrcIrg),
761	DIS_ARMV8_OP_ALT_DECODE(0x9ac01400, "gmi", OP_ARMV8_A64_GMI, DISOPTYPE_HARMLESS, Reg2SrcGmi),
762	INVALID_OPCODE,
763	INVALID_OPCODE,
764	DIS_ARMV8_OP( 0x9ac02000, "lslv", OP_ARMV8_A64_LSLV, DISOPTYPE_HARMLESS),
765	DIS_ARMV8_OP( 0x9ac02400, "lsrv", OP_ARMV8_A64_LSRV, DISOPTYPE_HARMLESS),
766	DIS_ARMV8_OP( 0x9ac02800, "asrv", OP_ARMV8_A64_ASRV, DISOPTYPE_HARMLESS),
767	DIS_ARMV8_OP( 0x9ac02c00, "rorv", OP_ARMV8_A64_RORV, DISOPTYPE_HARMLESS),
768	DIS_ARMV8_OP_ALT_DECODE(0x9ac03000, "pacga", OP_ARMV8_A64_PACGA, DISOPTYPE_HARMLESS, Reg2SrcPacga),
769	INVALID_OPCODE,
770	INVALID_OPCODE,
771	INVALID_OPCODE,
772	INVALID_OPCODE,
773	INVALID_OPCODE,
774	INVALID_OPCODE,
775	DIS_ARMV8_OP_ALT_DECODE(0x9ac04c00, "crc32x", OP_ARMV8_A64_CRC32X, DISOPTYPE_HARMLESS, Reg2SrcCrc32X),
776	INVALID_OPCODE,
777	INVALID_OPCODE,
778	INVALID_OPCODE,
779	DIS_ARMV8_OP_ALT_DECODE(0x9ac05c00, "crc32cx", OP_ARMV8_A64_CRC32CX, DISOPTYPE_HARMLESS, Reg2SrcCrc32X),
780	DIS_ARMV8_OP( 0x9ac06000, "smax", OP_ARMV8_A64_SMAX, DISOPTYPE_HARMLESS),
781	DIS_ARMV8_OP( 0x9ac06400, "umax", OP_ARMV8_A64_UMAX, DISOPTYPE_HARMLESS),
782	DIS_ARMV8_OP( 0x9ac06800, "smin", OP_ARMV8_A64_SMIN, DISOPTYPE_HARMLESS),
783	DIS_ARMV8_OP( 0x9ac06c00, "umin", OP_ARMV8_A64_UMIN, DISOPTYPE_HARMLESS)
784	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Reg2Src64Bit, 0xffe0fc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
785	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
786
787
788	/* SUBPS */
789	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Subps)
790	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
791	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 5, 5, 1 /idxParam/),
792	DIS_ARMV8_INSN_DECODE(kDisParmParseGprSp, 16, 5, 2 /idxParam/),
793	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Subps)
794	DIS_ARMV8_OP(0xbac00000, "subps", OP_ARMV8_A64_SUBPS, DISOPTYPE_HARMLESS),
795	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Subps, 0xffe0fc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
796	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
797
798
799	/**
800	* C4.1.95 - Data Processing - Register - 2-source
801	*
802	* Differentiate between 32-bit and 64-bit groups based on the SF bit.
803	* Not done as a general decoder step because there are different instructions in each group.
804	*/
805	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(Reg2Src)
806	DIS_ARMV8_DECODE_MAP_ENTRY(Reg2Src32Bit), /* Data-processing (2-source, 32-bit) */
807	DIS_ARMV8_DECODE_MAP_ENTRY(Reg2Src64Bit), /* Data-processing (2-source, 64-bit) */
808	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(Reg2Src, 31);
809
810
811	/**
812	* C4.1.95 - Data Processing - Register - 2-source
813	*
814	* Differentiate between SUBPS and the rest based on the S bit.
815	*/
816	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(Reg2SrcSubps)
817	DIS_ARMV8_DECODE_MAP_ENTRY(Reg2Src), /* Data-processing (2-source) */
818	DIS_ARMV8_DECODE_MAP_ENTRY(Subps), /* Subps */
819	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(Reg2SrcSubps, 29);
820
821
822	/* RBIT/REV16/REV/CLZ/CLS/CTZ/CNT/ABS/REV32 */
823	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Reg1SrcInsn)
824	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
825	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
826	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
827	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Reg1SrcInsn)
828	DIS_ARMV8_OP(0x5ac00000, "rbit", OP_ARMV8_A64_RBIT, DISOPTYPE_HARMLESS),
829	DIS_ARMV8_OP(0x5ac00400, "rev16", OP_ARMV8_A64_REV16, DISOPTYPE_HARMLESS),
830	DIS_ARMV8_OP(0x5ac00800, "rev", OP_ARMV8_A64_REV, DISOPTYPE_HARMLESS), /** @todo REV32 if SF1 is 1 (why must this be so difficult ARM?). */
831	DIS_ARMV8_OP(0x5ac00c00, "rev", OP_ARMV8_A64_REV, DISOPTYPE_HARMLESS), /** @todo SF must be 1, otherwise unallocated. */
832	DIS_ARMV8_OP(0x5ac01000, "clz", OP_ARMV8_A64_CLZ, DISOPTYPE_HARMLESS),
833	DIS_ARMV8_OP(0x5ac01400, "cls", OP_ARMV8_A64_CLS, DISOPTYPE_HARMLESS),
834	DIS_ARMV8_OP(0x5ac01800, "ctz", OP_ARMV8_A64_CTZ, DISOPTYPE_HARMLESS),
835	DIS_ARMV8_OP(0x5ac01c00, "cnt", OP_ARMV8_A64_CNT, DISOPTYPE_HARMLESS),
836	DIS_ARMV8_OP(0x5ac02000, "abs", OP_ARMV8_A64_ABS, DISOPTYPE_HARMLESS),
837	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Reg1SrcInsn, 0x7ffffc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
838	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 10);
839
840
841	/**
842	* C4.1.95 - Data Processing - Register - 1-source
843	*
844	* Differentiate between standard and FEAT_PAuth instructions based on opcode2 field.
845	*/
846	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(Reg1Src)
847	DIS_ARMV8_DECODE_MAP_ENTRY(Reg1SrcInsn), /* Data-processing (1-source) */
848	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Data-processing (1-source, FEAT_PAuth) */
849	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(Reg1Src, 16);
850
851
852	/**
853	* C4.1.95 - Data Processing - Register - 2-source / 1-source
854	*
855	* The 2-source and 1-source instruction classes differentiate based on bit 30.
856	*/
857	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(Reg2Src1Src)
858	DIS_ARMV8_DECODE_MAP_ENTRY(Reg2SrcSubps), /* Data-processing (2-source) */
859	DIS_ARMV8_DECODE_MAP_ENTRY(Reg1Src), /* Data-processing (1-source) */
860	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(Reg2Src1Src, 30);
861
862
863	/* CSEL/CSINC/CSINV/CSNEG */
864	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(CondSel)
865	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
866	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
867	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
868	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
869	DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 12, 4, 3 /idxParam/),
870	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(CondSel)
871	DIS_ARMV8_OP(0x1a800000, "csel", OP_ARMV8_A64_CSEL, DISOPTYPE_HARMLESS),
872	DIS_ARMV8_OP(0x1a800400, "csinc", OP_ARMV8_A64_CSINC, DISOPTYPE_HARMLESS),
873	INVALID_OPCODE,
874	INVALID_OPCODE,
875	DIS_ARMV8_OP(0x5a800000, "csinv", OP_ARMV8_A64_CSINC, DISOPTYPE_HARMLESS),
876	DIS_ARMV8_OP(0x5a800400, "csneg", OP_ARMV8_A64_CSNEG, DISOPTYPE_HARMLESS)
877	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(CondSel, 0x7fe00c00 /fFixedInsn/, kDisArmV8OpcDecodeCollate,
878	RT_BIT_32(10) \| RT_BIT_32(11) \| RT_BIT_32(30), 10);
879
880
881	/* MADD/MSUB (32-bit) */
882	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Reg3Src32)
883	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 0, 5, 0 /idxParam/),
884	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 5, 5, 1 /idxParam/),
885	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 16, 5, 2 /idxParam/),
886	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 10, 5, 3 /idxParam/),
887	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Reg3Src32)
888	DIS_ARMV8_OP(0x1b000000, "madd", OP_ARMV8_A64_MADD, DISOPTYPE_HARMLESS),
889	DIS_ARMV8_OP(0x1b008000, "msub", OP_ARMV8_A64_MSUB, DISOPTYPE_HARMLESS),
890	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Reg3Src32, 0xffe08000 /fFixedInsn/, kDisArmV8OpcDecodeNop,
891	RT_BIT_32(15), 15);
892
893
894	/* MADD/MSUB (64-bit) /SMADDL/SMSUBL/SMULH/UMADDL/UMSUBL/UMULH */
895	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(Reg3Src64)
896	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 0, 5, 0 /idxParam/),
897	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 5, 5, 1 /idxParam/),
898	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 16, 5, 2 /idxParam/),
899	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 10, 5, 3 /idxParam/),
900	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg3Src64_32)
901	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 0, 5, 0 /idxParam/),
902	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 5, 5, 1 /idxParam/),
903	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 16, 5, 2 /idxParam/),
904	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 10, 5, 3 /idxParam/),
905	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(Reg3Src64Mul) /** @todo Ra == 11111 (or is it ignored?) */
906	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 0, 5, 0 /idxParam/),
907	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 5, 5, 1 /idxParam/),
908	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 16, 5, 2 /idxParam/),
909	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(Reg3Src64)
910	DIS_ARMV8_OP( 0x9b000000, "madd", OP_ARMV8_A64_MADD, DISOPTYPE_HARMLESS),
911	DIS_ARMV8_OP( 0x9b008000, "msub", OP_ARMV8_A64_MSUB, DISOPTYPE_HARMLESS),
912	DIS_ARMV8_OP_ALT_DECODE(0x9b200000, "smaddl", OP_ARMV8_A64_SMADDL, DISOPTYPE_HARMLESS, Reg3Src64_32),
913	DIS_ARMV8_OP_ALT_DECODE(0x9b208000, "smsubl", OP_ARMV8_A64_SMSUBL, DISOPTYPE_HARMLESS, Reg3Src64_32),
914	DIS_ARMV8_OP_ALT_DECODE(0x9b400000, "smulh", OP_ARMV8_A64_SMULH, DISOPTYPE_HARMLESS, Reg3Src64Mul),
915	INVALID_OPCODE,
916	INVALID_OPCODE,
917	INVALID_OPCODE,
918	INVALID_OPCODE,
919	INVALID_OPCODE,
920	DIS_ARMV8_OP_ALT_DECODE(0x9ba00000, "umaddl", OP_ARMV8_A64_UMADDL, DISOPTYPE_HARMLESS, Reg3Src64_32),
921	DIS_ARMV8_OP_ALT_DECODE(0x9ba08000, "umsubl", OP_ARMV8_A64_UMSUBL, DISOPTYPE_HARMLESS, Reg3Src64_32),
922	DIS_ARMV8_OP_ALT_DECODE(0x9bc00000, "umulh", OP_ARMV8_A64_UMULH, DISOPTYPE_HARMLESS, Reg3Src64Mul),
923	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(Reg3Src64, 0xffe08000 /fFixedInsn/, kDisArmV8OpcDecodeCollate,
924	RT_BIT_32(15) \| RT_BIT_32(21) \| RT_BIT_32(22) \| RT_BIT_32(23), 15);
925
926
927	/**
928	* C4.1.95.12 - Data Processing - Register - 3-source
929	*
930	* We differentiate further based on SF because there are different instructions encoded
931	* for 32-bit and 64-bit.
932	*/
933	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(Reg3Src)
934	DIS_ARMV8_DECODE_MAP_ENTRY(Reg3Src32), /* 3-source 32-bit */
935	DIS_ARMV8_DECODE_MAP_ENTRY(Reg3Src64), /* 3-source 64-bit */
936	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(Reg3Src, 31);
937
938
939	/* ADC/ADCS/SBC/SBCS */
940	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(AddSubCarry)
941	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
942	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
943	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
944	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 16, 5, 2 /idxParam/),
945	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(AddSubCarry)
946	DIS_ARMV8_OP(0x1a000000, "adc", OP_ARMV8_A64_ADC, DISOPTYPE_HARMLESS),
947	DIS_ARMV8_OP(0x3a000000, "adcs", OP_ARMV8_A64_ADCS, DISOPTYPE_HARMLESS),
948	DIS_ARMV8_OP(0x5a000000, "sbc", OP_ARMV8_A64_SBC, DISOPTYPE_HARMLESS),
949	DIS_ARMV8_OP(0x7a000000, "sbcs", OP_ARMV8_A64_SBCS, DISOPTYPE_HARMLESS),
950	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(AddSubCarry, 0x7fe0fc00 /fFixedInsn/, kDisArmV8OpcDecodeNop,
951	RT_BIT_32(29) \| RT_BIT_32(30), 29);
952
953
954	/* RMIF */
955	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(RotateIntoFlags)
956	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64, 5, 5, 0 /idxParam/),
957	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 15, 6, 1 /idxParam/),
958	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 0, 4, 2 /idxParam/),
959	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(RotateIntoFlags)
960	INVALID_OPCODE,
961	DIS_ARMV8_OP(0xba000400, "rmif", OP_ARMV8_A64_RMIF, DISOPTYPE_HARMLESS),
962	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(RotateIntoFlags, 0xffe07c10 /fFixedInsn/, kDisArmV8OpcDecodeNop,
963	RT_BIT_32(29), 29);
964
965
966	/* SETF8/SETF16 */
967	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(EvaluateIntoFlags)
968	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32, 5, 5, 0 /idxParam/),
969	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(EvaluateIntoFlags)
970	DIS_ARMV8_OP(0x3a00080d, "setf8", OP_ARMV8_A64_SETF8, DISOPTYPE_HARMLESS),
971	DIS_ARMV8_OP(0x3a00480d, "setf16", OP_ARMV8_A64_SETF16, DISOPTYPE_HARMLESS),
972	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(EvaluateIntoFlags, 0xfffffc1f /fFixedInsn/, kDisArmV8OpcDecodeNop,
973	RT_BIT_32(14), 14);
974
975
976	/**
977	* C4.1.95 - Data Processing - Register
978	*
979	* Differentiate between add/sub (with carry) / rotate right / evaluate by op3<1:0>.
980	*/
981	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(AddSubRotateEval)
982	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubCarry),
983	DIS_ARMV8_DECODE_MAP_ENTRY(RotateIntoFlags),
984	DIS_ARMV8_DECODE_MAP_ENTRY(EvaluateIntoFlags),
985	DIS_ARMV8_DECODE_MAP_DEFINE_END(AddSubRotateEval, RT_BIT_32(10) \| RT_BIT_32(11), 10);
986
987
988	/*
989	* C4.1.95 - Data Processing - Register
990	*
991	* The op1 field is already decoded in the previous step and is 1 when being here,
992	* leaving us with the following possible values:
993	*
994	* Bit 24 23 22 21
995	* +-------------------------------------------
996	* 0 0 0 0 Add/subtract with carry / Rotate right into flags / Evaluate into flags (depending on op3)
997	* 0 0 0 1 UNALLOC
998	* 0 0 1 0 Conditional compare (register / immediate)
999	* 0 0 1 1 UNALLOC
1000	* 0 1 0 0 Conditional select
1001	* 0 1 0 1 UNALLOC
1002	* 0 1 1 0 Data processing (2-source or 1-source depending on op0).
1003	* 0 1 1 1 UNALLOC
1004	* 1 x x x Data processing 3-source
1005	*/
1006	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcReg)
1007	DIS_ARMV8_DECODE_MAP_ENTRY(AddSubRotateEval),
1008	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
1009	DIS_ARMV8_DECODE_MAP_ENTRY(CondCmp),
1010	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
1011	DIS_ARMV8_DECODE_MAP_ENTRY(CondSel),
1012	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
1013	DIS_ARMV8_DECODE_MAP_ENTRY(Reg2Src1Src),
1014	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
1015	DIS_ARMV8_DECODE_MAP_ENTRY(Reg3Src),
1016	DIS_ARMV8_DECODE_MAP_ENTRY(Reg3Src),
1017	DIS_ARMV8_DECODE_MAP_ENTRY(Reg3Src),
1018	DIS_ARMV8_DECODE_MAP_ENTRY(Reg3Src),
1019	DIS_ARMV8_DECODE_MAP_ENTRY(Reg3Src),
1020	DIS_ARMV8_DECODE_MAP_ENTRY(Reg3Src),
1021	DIS_ARMV8_DECODE_MAP_ENTRY(Reg3Src),
1022	DIS_ARMV8_DECODE_MAP_ENTRY(Reg3Src),
1023	DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcReg, RT_BIT_32(21) \| RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(24), 21);
1024
1025
1026	/*
1027	* C4.1 of the ARMv8 architecture reference manual has the following table for the
1028	* topmost decoding level (Level 0 in our terms), x means don't care:
1029	*
1030	* Bit 28 27 26 25
1031	* +-------------------------------------------
1032	* 0 0 0 0 Reserved or SME encoding (depends on bit 31).
1033	* 0 0 0 1 UNALLOC
1034	* 0 0 1 0 SVE encodings
1035	* 0 0 1 1 UNALLOC
1036	* 1 0 0 x Data processing immediate
1037	* 1 0 1 x Branch, exception generation and system instructions
1038	* x 1 x 0 Loads and stores
1039	* x 1 0 1 Data processing - register
1040	* x 1 1 1 Data processing - SIMD and floating point
1041	*
1042	* In order to save us some fiddling with the don't care bits we blow up the lookup table
1043	* which gives us 16 possible values (4 bits) we can use as an index into the decoder
1044	* lookup table for the next level:
1045	* Bit 28 27 26 25
1046	* +-------------------------------------------
1047	* 0 0 0 0 0 Reserved or SME encoding (depends on bit 31).
1048	* 1 0 0 0 1 UNALLOC
1049	* 2 0 0 1 0 SVE encodings
1050	* 3 0 0 1 1 UNALLOC
1051	* 4 0 1 0 0 Loads and stores
1052	* 5 0 1 0 1 Data processing - register (using op1 (bit 28) from the next stage to differentiate further already)
1053	* 6 0 1 1 0 Loads and stores
1054	* 7 0 1 1 1 Data processing - SIMD and floating point
1055	* 8 1 0 0 0 Data processing immediate
1056	* 9 1 0 0 1 Data processing immediate
1057	* 10 1 0 1 0 Branch, exception generation and system instructions
1058	* 11 1 0 1 1 Branch, exception generation and system instructions
1059	* 12 1 1 0 0 Loads and stores
1060	* 13 1 1 0 1 Data processing - register (using op1 (bit 28) from the next stage to differentiate further already)
1061	* 14 1 1 1 0 Loads and stores
1062	* 15 1 1 1 1 Data processing - SIMD and floating point
1063	*/
1064	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DecodeL0)
1065	DIS_ARMV8_DECODE_MAP_ENTRY(Rsvd), /* Reserved class or SME encoding (@todo). */
1066	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Unallocated */
1067	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo SVE */
1068	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Unallocated */
1069	DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
1070	DIS_ARMV8_DECODE_MAP_ENTRY(LogicalAddSubReg), /* Data processing (register) (see op1 in C4.1.68). */
1071	DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
1072	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_0), /* Data processing (SIMD & FP) (op0<0> 0) */
1073	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcessingImm), /* Data processing (immediate). */
1074	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcessingImm), /* Data processing (immediate). */
1075	DIS_ARMV8_DECODE_MAP_ENTRY(BrExcpSys), /* Branches / Exception generation and system instructions. */
1076	DIS_ARMV8_DECODE_MAP_ENTRY(BrExcpSys), /* Branches / Exception generation and system instructions. */
1077	DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
1078	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcReg), /* Data processing (register) (see op1 in C4.1.68). */
1079	DIS_ARMV8_DECODE_MAP_ENTRY(LdStOp0Lo), /* Load/Stores. */
1080	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1) /* Data processing (SIMD & FP) (op0<0> 1). */
1081	DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(DecodeL0, RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28), 25);

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source: vbox/trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp@ 107044

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