DisasmTables-armv8-a64-simd-fp.cpp.h@ 106877

Last change on this file since 106877 was 106746, checked in by vboxsync, 5 weeks ago
Disassembler: Decode SIMD ldr/str instructions, bugref:10394
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 27.3 KB

Line
1	/* $Id: DisasmTables-armv8-a64-simd-fp.cpp.h 106746 2024-10-28 13:14:22Z vboxsync $ */
2	/** @file
3	* VBox disassembler - Tables for ARMv8 A64 - SIMD & FP.
4	*/
5
6	/*
7	* Copyright (C) 2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	/*
29	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
30	*
31	* Bit 28 (op0<0>) is already fixed at 0 at this point.
32	*
33	* Differentiate further based on the op3<0> field.
34	* Splitting this up because the decoding would get insane otherwise with tables doing cross referencing...
35	*
36	* Bit 10
37	* +-------------------------------------------
38	* 0 Advanced SIMD table lookup/permute/extract/copy/three same (FP16)/two-register miscellaneous (FP16)/ three-register extension
39	* two-register miscellaneous/across lanes/three different/three same/modified immediate/shift by immediate/vector x indexed element/
40	* Cryptographic AES
41	* 1 Cryptographic three-register, imm2/three register SHA 512/four-register/two-register SHA 512
42	* XAR
43	*/
44	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_0_31_0)
45	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
46	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
47	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_0_31_0, 10);
48
49
50	/*
51	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
52	*
53	* Bit 28 (op0<0>) is already fixed at 0 at this point.
54	*
55	* Differentiate further based on the op0<3> field.
56	* Splitting this up because the decoding would get insane otherwise with tables doing cross referencing...
57	*
58	* Bit 31
59	* +-------------------------------------------
60	* 0 Advanced SIMD table lookup/permute/extract/copy/three same (FP16)/two-register miscellaneous (FP16)/ three-register extension
61	* two-register miscellaneous/across lanes/three different/three same/modified immediate/shift by immediate/vector x indexed element/
62	* Cryptographic AES
63	* 1 Cryptographic three-register, imm2/three register SHA 512/four-register/two-register SHA 512
64	* XAR
65	*/
66	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_0)
67	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_0_31_0),
68	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
69	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_0, 31);
70
71
72	/*
73	* SCVTF/UCVTF.
74	*
75	* Note: The opcode is selected based on the <opcode> field.
76	*/
77	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpFixedPConvGpr2FpReg)
78	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
79	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
80	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
81	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 5, 5, 1 /idxParam/),
82	DIS_ARMV8_INSN_DECODE(kDisParmParseFpScale, 10, 6, 2 /idxParam/),
83	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpFixedPConvGpr2FpReg)
84	INVALID_OPCODE,
85	INVALID_OPCODE,
86	DIS_ARMV8_OP(0x1e020000, "scvtf", OP_ARMV8_A64_SCVTF, DISOPTYPE_HARMLESS),
87	DIS_ARMV8_OP(0x1e030000, "ucvtf", OP_ARMV8_A64_UCVTF, DISOPTYPE_HARMLESS),
88	INVALID_OPCODE,
89	INVALID_OPCODE,
90	INVALID_OPCODE,
91	INVALID_OPCODE,
92	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(DataProcFpFixedPConvGpr2FpReg, 0x7f3f0000 /fFixedInsn/,
93	kDisArmV8OpcDecodeNop,
94	RT_BIT_32(16) \| RT_BIT_32(17) \| RT_BIT_32(18), 16);
95
96
97	/*
98	* FCVTZS/FCVTZU.
99	*
100	* Note: The opcode is selected based on the <opcode> field.
101	*/
102	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpFixedPConvFpReg2Gpr)
103	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
104	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
105	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
106	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 1 /idxParam/),
107	DIS_ARMV8_INSN_DECODE(kDisParmParseFpScale, 10, 6, 2 /idxParam/),
108	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpFixedPConvFpReg2Gpr)
109	DIS_ARMV8_OP(0x1e180000, "fcvtzs", OP_ARMV8_A64_FCVTZS, DISOPTYPE_HARMLESS),
110	DIS_ARMV8_OP(0x1e190000, "fcvtzu", OP_ARMV8_A64_FCVTZU, DISOPTYPE_HARMLESS),
111	INVALID_OPCODE,
112	INVALID_OPCODE,
113	INVALID_OPCODE,
114	INVALID_OPCODE,
115	INVALID_OPCODE,
116	INVALID_OPCODE,
117	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(DataProcFpFixedPConvFpReg2Gpr, 0x7f3f0000 /fFixedInsn/,
118	kDisArmV8OpcDecodeNop,
119	RT_BIT_32(16) \| RT_BIT_32(17) \| RT_BIT_32(18), 16);
120
121
122	/*
123	* C4.1.96.32 - Conversion between floating-point and fixed-point
124	*
125	* Bit 28 (op0<0>) is already fixed at 1 at this point.
126	* Bit 30 (op0<2>) is already fixed at 0 at this point.
127	* Bit 24 (op1<1>) is already fixed at 0 at this point.
128	* Bit 21 (op2<2>) is already fixed at 0 at this point.
129	*
130	* Differentiate further based on the rmode field.
131	*/
132	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcFpFixedPConv)
133	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpFixedPConvGpr2FpReg),
134	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
135	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
136	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpFixedPConvFpReg2Gpr),
137	DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcFpFixedPConv, RT_BIT_32(19) \| RT_BIT_32(20), 19);
138
139
140	/*
141	* C4.1.96.33 - Conversion between floating-point and integer.
142	*
143	* FCVTNS/FCVTNU/SCVTF/UCVTF/FCVTAS/FCVTAU/FMOV/FCVTPS/FCVTPU/FCVTMS/FCVTMU/FCVTZS/FCVTZU.
144	*
145	* Note: The opcode is selected based on the <rmode>:<opcode> field.
146	*/
147	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpConvInt)
148	DIS_ARMV8_INSN_DECODE(kDisParmParseSf, 31, 1, DIS_ARMV8_INSN_PARAM_UNSET),
149	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
150	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
151	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 1 /idxParam/),
152	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpConvInt) /** @todo */
153	INVALID_OPCODE,
154	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(DataProcFpConvInt, 0xff3ffc00 /fFixedInsn/,
155	kDisArmV8OpcDecodeNop,
156	RT_BIT_32(16) \| RT_BIT_32(17) \| RT_BIT_32(18) \| RT_BIT_32(19) \| RT_BIT_32(20), 16);
157
158
159	/*
160	* FCSEL.
161	*
162	* Note: The opcode is selected based on the <opcode> field.
163	*/
164	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpCondSelect)
165	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
166	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
167	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 1 /idxParam/),
168	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 16, 5, 2 /idxParam/),
169	DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 12, 4, 3 /idxParam/),
170	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpCondSelect)
171	DIS_ARMV8_OP(0x1e200c00, "fcsel", OP_ARMV8_A64_FCSEL, DISOPTYPE_HARMLESS),
172	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(DataProcFpCondSelect, 0xff200c00 /fFixedInsn/,
173	kDisArmV8OpcDecodeNop,
174	RT_BIT_32(29), 29);
175
176
177	/*
178	* FMUL/FDIV/FADD/FSUB/FMAX/FMIN/FMAXNM/FMINNM.
179	*
180	* Note: The opcode is selected based on the <opcode> field.
181	*/
182	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpDataProc2Src)
183	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
184	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
185	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 1 /idxParam/),
186	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 16, 5, 2 /idxParam/),
187	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpDataProc2Src)
188	DIS_ARMV8_OP(0x1e200800, "fmul", OP_ARMV8_A64_FMUL, DISOPTYPE_HARMLESS),
189	DIS_ARMV8_OP(0x1e201800, "fdiv", OP_ARMV8_A64_FDIV, DISOPTYPE_HARMLESS),
190	DIS_ARMV8_OP(0x1e202800, "fadd", OP_ARMV8_A64_FADD, DISOPTYPE_HARMLESS),
191	DIS_ARMV8_OP(0x1e203800, "fsub", OP_ARMV8_A64_FSUB, DISOPTYPE_HARMLESS),
192	DIS_ARMV8_OP(0x1e204800, "fmax", OP_ARMV8_A64_FMAX, DISOPTYPE_HARMLESS),
193	DIS_ARMV8_OP(0x1e205800, "fmin", OP_ARMV8_A64_FMIN, DISOPTYPE_HARMLESS),
194	DIS_ARMV8_OP(0x1e206800, "fmaxnm", OP_ARMV8_A64_FMAXNM, DISOPTYPE_HARMLESS),
195	DIS_ARMV8_OP(0x1e207800, "fminnm", OP_ARMV8_A64_FMINNM, DISOPTYPE_HARMLESS),
196	DIS_ARMV8_OP(0x1e208800, "fnmul", OP_ARMV8_A64_FNMUL, DISOPTYPE_HARMLESS),
197	/* Rest of the 4 bit block is invalid */
198	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(DataProcFpDataProc2Src, 0xff20fc00 /fFixedInsn/,
199	kDisArmV8OpcDecodeNop,
200	RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 12);
201
202
203	/*
204	* C4.1.96.34 - Floating-point data-processing (1 source).
205	*
206	* FMOV/FABS/FNEG/FSQRT/FCVT/FRINTN/FRINTP/FRINTM/FRINTZ/FRINA/FRINTX/FRINTI/FRINT32Z/FRINT32X/FRINT64Z/FRINT64X.
207	*
208	* Note: The opcode is selected based on the <opcode> field.
209	*/
210	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpDataProc1Src)
211	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
212	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
213	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 1 /idxParam/),
214	DIS_ARMV8_INSN_DECODE(kDisParmParseFpFixupFCvt, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET),
215	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpDataProc1Src)
216	DIS_ARMV8_OP(0x1e204000, "fmov", OP_ARMV8_A64_FMOV, DISOPTYPE_HARMLESS),
217	DIS_ARMV8_OP(0x1e20c000, "fabs", OP_ARMV8_A64_FABS, DISOPTYPE_HARMLESS),
218	DIS_ARMV8_OP(0x1e214000, "fneg", OP_ARMV8_A64_FNEG, DISOPTYPE_HARMLESS),
219	DIS_ARMV8_OP(0x1e21c000, "fsqrt", OP_ARMV8_A64_FSQRT, DISOPTYPE_HARMLESS),
220	DIS_ARMV8_OP(0x1e224000, "fcvt", OP_ARMV8_A64_FCVT, DISOPTYPE_HARMLESS),
221	DIS_ARMV8_OP(0x1e22c000, "fcvt", OP_ARMV8_A64_FCVT, DISOPTYPE_HARMLESS),
222	INVALID_OPCODE,
223	DIS_ARMV8_OP(0x1e23c000, "fcvt", OP_ARMV8_A64_FCVT, DISOPTYPE_HARMLESS),
224	DIS_ARMV8_OP(0x1e244000, "frintn", OP_ARMV8_A64_FRINTN, DISOPTYPE_HARMLESS),
225	DIS_ARMV8_OP(0x1e24c000, "frintp", OP_ARMV8_A64_FRINTP, DISOPTYPE_HARMLESS),
226	DIS_ARMV8_OP(0x1e254000, "frintm", OP_ARMV8_A64_FRINTM, DISOPTYPE_HARMLESS),
227	DIS_ARMV8_OP(0x1e25c000, "frintz", OP_ARMV8_A64_FRINTZ, DISOPTYPE_HARMLESS),
228	DIS_ARMV8_OP(0x1e264000, "frinta", OP_ARMV8_A64_FRINTA, DISOPTYPE_HARMLESS),
229	INVALID_OPCODE,
230	DIS_ARMV8_OP(0x1e274000, "frintx", OP_ARMV8_A64_FRINTX, DISOPTYPE_HARMLESS),
231	DIS_ARMV8_OP(0x1e27c000, "frinti", OP_ARMV8_A64_FRINTI, DISOPTYPE_HARMLESS),
232	DIS_ARMV8_OP(0x1e284000, "frint32z", OP_ARMV8_A64_FRINT32Z, DISOPTYPE_HARMLESS),
233	DIS_ARMV8_OP(0x1e28c000, "frint32x", OP_ARMV8_A64_FRINT32X, DISOPTYPE_HARMLESS),
234	DIS_ARMV8_OP(0x1e294000, "frint64z", OP_ARMV8_A64_FRINT64Z, DISOPTYPE_HARMLESS),
235	DIS_ARMV8_OP(0x1e29c000, "frint64x", OP_ARMV8_A64_FRINT64X, DISOPTYPE_HARMLESS),
236	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(DataProcFpDataProc1Src, 0xff3ffc00 /fFixedInsn/,
237	kDisArmV8OpcDecodeNop,
238	RT_BIT_32(15) \| RT_BIT_32(16) \| RT_BIT_32(17) \| RT_BIT_32(18) \| RT_BIT_32(19) \| RT_BIT_32(20), 15);
239
240
241	/*
242	* C4.1.96.35 - Floating-point compare.
243	*
244	* FCMP/FCMPE.
245	*
246	* Note: The opcode is selected based on the op2<3:4> field.
247	*/
248	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpCmpReg)
249	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
250	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 0 /idxParam/),
251	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 16, 5, 1 /idxParam/),
252	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpCmpReg)
253	DIS_ARMV8_OP(0x1e202000, "fcmp", OP_ARMV8_A64_FCMP, DISOPTYPE_HARMLESS),
254	DIS_ARMV8_OP(0x1e202010, "fcmpe", OP_ARMV8_A64_FCMPE, DISOPTYPE_HARMLESS),
255	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(DataProcFpCmpReg, 0xff20fc1f /fFixedInsn/,
256	kDisArmV8OpcDecodeNop,
257	RT_BIT_32(4), 4);
258
259
260	/*
261	* C4.1.96.35 - Floating-point compare.
262	*
263	* FCMP/FCMPE.
264	*
265	* Note: The opcode is selected based on the op2<3:4> field.
266	*/
267	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpCmpZero)
268	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
269	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 0 /idxParam/),
270	DIS_ARMV8_INSN_DECODE(kDisParmParseImmZero, 0, 0, 1 /idxParam/),
271	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpCmpZero)
272	DIS_ARMV8_OP(0x1e202008, "fcmp", OP_ARMV8_A64_FCMP, DISOPTYPE_HARMLESS),
273	DIS_ARMV8_OP(0x1e202018, "fcmpe", OP_ARMV8_A64_FCMPE, DISOPTYPE_HARMLESS),
274	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(DataProcFpCmpZero, 0xff20fc1f /fFixedInsn/,
275	kDisArmV8OpcDecodeNop,
276	RT_BIT_32(4), 4);
277
278
279	/*
280	* Floating Point compare, differentiate between register and zero variant.
281	*/
282	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcFpCmp)
283	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCmpReg),
284	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCmpZero),
285	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcFpCmp, 3);
286
287
288	/*
289	* C4.1.96.36 - Floating-point immediate.
290	*
291	* FMOV.
292	*
293	* Note: The opcode is selected based on the <op> field.
294	*/
295	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpImm)
296	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
297	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
298	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 13, 8, 1 /idxParam/),
299	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpImm)
300	DIS_ARMV8_OP(0x1e201000, "fmov", OP_ARMV8_A64_FMOV, DISOPTYPE_HARMLESS),
301	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(DataProcFpImm, 0xff201fe0 /fFixedInsn/,
302	kDisArmV8OpcDecodeNop,
303	RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7) \| RT_BIT_32(8) \| RT_BIT_32(9), 5);
304
305
306	/*
307	* C4.1.96.37 - Floating-point conditional compare.
308	*
309	* FCCMP/FCCMPE.
310	*
311	* Note: The opcode is selected based on the <op> field.
312	*/
313	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpCondCmp)
314	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
315	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 0 /idxParam/),
316	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 16, 5, 1 /idxParam/),
317	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 0, 4, 2 /idxParam/),
318	DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 12, 4, 3 /idxParam/),
319	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpCondCmp)
320	DIS_ARMV8_OP(0x1e200400, "fccmp", OP_ARMV8_A64_FCCMP, DISOPTYPE_HARMLESS),
321	DIS_ARMV8_OP(0x1e200410, "fccmpe", OP_ARMV8_A64_FCCMPE, DISOPTYPE_HARMLESS),
322	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(DataProcFpCondCmp, 0xff200c10 /fFixedInsn/,
323	kDisArmV8OpcDecodeNop,
324	RT_BIT_32(4), 4);
325
326
327	/*
328	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
329	*
330	* Bit 28 (op0<0>) is already fixed at 1 at this point.
331	* Bit 30 (op0<2>) is already fixed at 0 at this point.
332	* Bit 24 (op1<1>) is already fixed at 0 at this point.
333	* Bit 21 (op2<2>) is already fixed at 1 at this point.
334	* Bit 11 (op3<1>) is already fixed at 0 at this point.
335	* Bit 10 (op3<0>) is already fixed at 0 at this point.
336	*
337	* Differentiate further based on the op3<5:2> field.
338	*
339	* Bit 15 14 13 12
340	* +-------------------------------------------
341	* 0 0 0 0 Conversion between FP and integer
342	* 0 0 0 1 FP immediate
343	* 0 0 1 0 FP compare
344	* 0 0 1 1 FP immediate
345	* 0 1 0 0 FP data-processing (1 source)
346	* 0 1 0 1 FP immediate
347	* 0 1 1 0 FP compare
348	* 0 1 1 1 FP immediate
349	* 1 0 0 0 UNDEFINED
350	* 1 0 0 1 FP immediate
351	* 1 0 1 0 FP compare
352	* 1 0 1 1 FP immediate
353	* 1 1 0 0 FP data-processing (1 source)
354	* 1 1 0 1 FP immediate
355	* 1 1 1 0 FP compare
356	* 1 1 1 1 FP immediate
357	*/
358	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1_30_0_24_0_21_1_11_0_10_0)
359	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpConvInt),
360	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
361	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCmp),
362	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
363	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpDataProc1Src),
364	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
365	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCmp),
366	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
367	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
368	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
369	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCmp),
370	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
371	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpDataProc1Src),
372	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
373	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCmp),
374	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
375	DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcSimdFpBit28_1_30_0_24_0_21_1_11_0_10_0, RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 12);
376
377
378	/*
379	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
380	*
381	* Bit 28 (op0<0>) is already fixed at 1 at this point.
382	* Bit 30 (op0<2>) is already fixed at 0 at this point.
383	* Bit 24 (op1<1>) is already fixed at 0 at this point.
384	* Bit 21 (op2<2>) is already fixed at 1 at this point.
385	*
386	* Differentiate further based on the op3<1:0> field.
387	*
388	* Bit 11 10
389	* +-------------------------------------------
390	* 0 0 Conversion between FP and integer / FP data-processing (1 source) / compare / immediate
391	* 0 1 FP conditional compare
392	* 1 0 FP data processing (2 source)
393	* 1 1 FP conditional select
394	*/
395	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1_30_0_24_0_21_1)
396	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_0_24_0_21_1_11_0_10_0),
397	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCondCmp),
398	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpDataProc2Src),
399	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCondSelect),
400	DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcSimdFpBit28_1_30_0_24_0_21_1, RT_BIT_32(10) \| RT_BIT_32(11), 10);
401
402
403	/*
404	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
405	*
406	* Bit 28 (op0<0>) is already fixed at 1 at this point.
407	* Bit 30 (op0<2>) is already fixed at 0 at this point.
408	* Bit 24 (op1<1>) is already fixed at 0 at this point.
409	*
410	* Differentiate further based on the op2<2> field.
411	*
412	* Bit 21
413	* +-------------------------------------------
414	* 0 Conversion between FP and fixed-point
415	* 1 Conversion between FP and integer/FP data-processing (1 source) /
416	* compare / immediate / conditional compare / data-processing (2 source) / conditional select
417	*/
418	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1_30_0_24_0)
419	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpFixedPConv),
420	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_0_24_0_21_1),
421	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_1_30_0_24_0, 21);
422
423
424	/*
425	* FMADD/FMSUB/FNMADD/FNMSUB.
426	*
427	* Note: The o1,o0 bitfields are concatenated to form an index.
428	*/
429	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpDataProc3Src)
430	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
431	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
432	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 1 /idxParam/),
433	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 16, 5, 2 /idxParam/),
434	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 10, 5, 3 /idxParam/),
435	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpDataProc3Src)
436	DIS_ARMV8_OP(0x1f000000, "fmadd", OP_ARMV8_A64_FMADD, DISOPTYPE_HARMLESS),
437	DIS_ARMV8_OP(0x1f008000, "fmsub", OP_ARMV8_A64_FMSUB, DISOPTYPE_HARMLESS),
438	DIS_ARMV8_OP(0x1f200000, "fnmadd", OP_ARMV8_A64_FNMADD, DISOPTYPE_HARMLESS),
439	DIS_ARMV8_OP(0x1f208000, "fnmsub", OP_ARMV8_A64_FNMSUB, DISOPTYPE_HARMLESS),
440	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(DataProcFpDataProc3Src, 0xff208000 /fFixedInsn/,
441	kDisArmV8OpcDecodeCollate,
442	RT_BIT_32(15) \| RT_BIT_32(21), 15);
443
444
445	/*
446	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
447	*
448	* Bit 28 (op0<0>) is already fixed at 1 at this point.
449	* Bit 30 (op0<2>) is already fixed at 0 at this point.
450	*
451	* Differentiate further based on the op1<1> field.
452	*
453	* Bit 24
454	* +-------------------------------------------
455	* 0 Conversion between FP and fixed-point/Conversion between FP and integer/
456	* FP data-processing (1 source) / compare / immediate / conditional compare / data-processing (2 source) /
457	* conditional select
458	* 1 FP data-processing (3 source)
459	*/
460	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1_30_0)
461	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_0_24_0),
462	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpDataProc3Src),
463	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_1_30_0, 24);
464
465
466	/*
467	* C4.1.96.12 - Data Processing - Advanced SIMD scalar shift by immediate
468	*
469	* FMADD/FMSUB/FNMADD/FNMSUB.
470	*
471	* Note: The U,opcode bitfields are concatenated to form an index.
472	*/
473	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcSimdScalarShiftByImm)
474	DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize64, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET),
475	DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar, 0, 5, 0 /idxParam/),
476	DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar, 5, 5, 1 /idxParam/),
477	DIS_ARMV8_INSN_DECODE(kDisParmParseImmHImmB, 16, 7, 2 /idxParam/),
478	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcSimdScalarShiftByImm)
479	DIS_ARMV8_OP(0x5f000400, "sshr", OP_ARMV8_A64_SSHR, DISOPTYPE_HARMLESS),
480	INVALID_OPCODE,
481	DIS_ARMV8_OP(0x5f001400, "ssra", OP_ARMV8_A64_SSRA, DISOPTYPE_HARMLESS),
482	INVALID_OPCODE,
483	DIS_ARMV8_OP(0x5f002400, "srshr", OP_ARMV8_A64_SRSHR, DISOPTYPE_HARMLESS),
484	INVALID_OPCODE,
485	DIS_ARMV8_OP(0x5f003400, "srsra", OP_ARMV8_A64_SRSRA, DISOPTYPE_HARMLESS),
486	INVALID_OPCODE,
487	INVALID_OPCODE,
488	INVALID_OPCODE,
489	#if 0 /** @todo */
490	DIS_ARMV8_OP(0x5f005400, "shl", OP_ARMV8_A64_SHL, DISOPTYPE_HARMLESS),
491	INVALID_OPCODE,
492	DIS_ARMV8_OP(0x5f007400, "sqshl", OP_ARMV8_A64_SQSHL, DISOPTYPE_HARMLESS),
493	INVALID_OPCODE,
494	DIS_ARMV8_OP(0x5f009400, "sqshrn", OP_ARMV8_A64_SQSHRN, DISOPTYPE_HARMLESS),
495	INVALID_OPCODE,
496	DIS_ARMV8_OP(0x5f009c00, "sqrshrn", OP_ARMV8_A64_SQRSHRN, DISOPTYPE_HARMLESS),
497	#endif
498	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(DataProcSimdScalarShiftByImm, 0xff80fc00 /fFixedInsn/,
499	kDisArmV8OpcDecodeCollate,
500	/* opcode */ RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15)
501	/* U */ \| RT_BIT_32(29), 11);
502
503
504	/*
505	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
506	*
507	* Bit 28 (op0<0>) is already fixed at 1 at this point.
508	* Bit 30 (op0<2>) is already fixed at 1 at this point.
509	* Bit 10 (op3<0>) is already fixed at 1 at this point.
510	*
511	* Differentiate further based on the op1<1> field.
512	*
513	* Bit 24
514	* +-------------------------------------------
515	* 0 Advanced SIMD scalar copy / scalar three same FP16 / scalar three same /
516	* scalar three same extra
517	* 1 Advanced SIMD scalar shift by immediate
518	*/
519	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1_30_1_10_1)
520	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, //DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_1_10_0),
521	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdScalarShiftByImm),
522	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_1_30_1_10_1, 24);
523
524
525	/*
526	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
527	*
528	* Bit 28 (op0<0>) is already fixed at 1 at this point.
529	* Bit 30 (op0<2>) is already fixed at 1 at this point.
530	*
531	* Differentiate further based on the op3<0> field.
532	*
533	* Bit 10
534	* +-------------------------------------------
535	* 0 Cryptographic three-register SHA / two-register SHA
536	* Advanced SIMD scalar two-register miscellaneous FP16 / scalar two-register miscellaneous / scalar pairwise /
537	* scalar three different / scalar x indexed element
538	* 1 Advanced SIMD scalar copy / scalar three same FP16 / scalar three same /
539	* scalar shift by immediate / scalar three same extra
540	*/
541	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1_30_1)
542	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, //DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_1_10_0),
543	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_1_10_1),
544	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_1_30_1, 10);
545
546
547	/*
548	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
549	*
550	* Bit 28 (op0<0>) is already fixed at 1 at this point.
551	*
552	* Differentiate further based on the op0<2> field.
553	*
554	* Bit 30
555	* +-------------------------------------------
556	* 0 Conversion between FP and fixed-point/Conversion between FP and integer/
557	* FP data-processing (1 source) / compare / immediate / conditional compare / data-processing (2 source) /
558	* conditional select / data-processing (3 source)
559	* 1 Cryptographic three-register SHA / two-register SHA
560	* Advanced SIMD scalar two-register miscellaneous FP16 / scalar two-register miscellaneous / scalar pairwise /
561	* scalar three different / scalar x indexed element / scalar copy / scalar three same FP16 / scalar three same /
562	* scalar shift by immediate / scalar three same extra
563	*/
564	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1)
565	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_0),
566	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_1),
567	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_1, 30);

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-simd-fp.cpp.h@ 106877

Download in other formats: