DisasmTables-armv8-a64-simd-fp.cpp.h@ 106129

Last change on this file since 106129 was 106004, checked in by vboxsync, 3 months ago
Disassembler/ArmV8: Updates and start on floating point and SIMD instructions, bugref:10394
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1	/* $Id: DisasmTables-armv8-a64-simd-fp.cpp.h 106004 2024-09-10 11:51:08Z vboxsync $ */
2	/** @file
3	* VBox disassembler - Tables for ARMv8 A64 - SIMD & FP.
4	*/
5
6	/*
7	* Copyright (C) 2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	/*
29	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
30	*
31	* Bit 28 (op0<0>) is already fixed at 0 at this point.
32	*
33	* Differentiate further based on the op3<0> field.
34	* Splitting this up because the decoding would get insane otherwise with tables doing cross referencing...
35	*
36	* Bit 10
37	* +-------------------------------------------
38	* 0 Advanced SIMD table lookup/permute/extract/copy/three same (FP16)/two-register miscellaneous (FP16)/ three-register extension
39	* two-register miscellaneous/across lanes/three different/three same/modified immediate/shift by immediate/vector x indexed element/
40	* Cryptographic AES
41	* 1 Cryptographic three-register, imm2/three register SHA 512/four-register/two-register SHA 512
42	* XAR
43	*/
44	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_0_31_0)
45	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
46	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
47	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_0_31_0, 10);
48
49
50	/*
51	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
52	*
53	* Bit 28 (op0<0>) is already fixed at 0 at this point.
54	*
55	* Differentiate further based on the op0<3> field.
56	* Splitting this up because the decoding would get insane otherwise with tables doing cross referencing...
57	*
58	* Bit 31
59	* +-------------------------------------------
60	* 0 Advanced SIMD table lookup/permute/extract/copy/three same (FP16)/two-register miscellaneous (FP16)/ three-register extension
61	* two-register miscellaneous/across lanes/three different/three same/modified immediate/shift by immediate/vector x indexed element/
62	* Cryptographic AES
63	* 1 Cryptographic three-register, imm2/three register SHA 512/four-register/two-register SHA 512
64	* XAR
65	*/
66	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_0)
67	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_0_31_0),
68	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
69	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_0, 31);
70
71
72	/*
73	* SCVTF/UCVTF.
74	*
75	* Note: The opcode is selected based on the <opcode> field.
76	*/
77	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpFixedPConvGpr2FpReg)
78	INVALID_OPCODE,
79	INVALID_OPCODE,
80	DIS_ARMV8_OP(0x1e020000, "scvtf", OP_ARMV8_A64_SCVTF, DISOPTYPE_HARMLESS),
81	DIS_ARMV8_OP(0x1e030000, "ucvtf", OP_ARMV8_A64_UCVTF, DISOPTYPE_HARMLESS),
82	INVALID_OPCODE,
83	INVALID_OPCODE,
84	INVALID_OPCODE,
85	INVALID_OPCODE,
86	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpFixedPConvGpr2FpReg)
87	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
88	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
89	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 5, 5, 1 /idxParam/),
90	DIS_ARMV8_INSN_DECODE(kDisParmParseFpScale, 10, 6, 2 /idxParam/),
91	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(DataProcFpFixedPConvGpr2FpReg, 0x7f3f0000 /fFixedInsn/, DISARMV8INSNCLASS_F_SF /fClass/,
92	kDisArmV8OpcDecodeNop,
93	RT_BIT_32(16) \| RT_BIT_32(17) \| RT_BIT_32(18), 16,
94	kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmImm);
95
96
97	/*
98	* FCVTZS/FCVTZU.
99	*
100	* Note: The opcode is selected based on the <opcode> field.
101	*/
102	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpFixedPConvFpReg2Gpr)
103	DIS_ARMV8_OP(0x1e180000, "fcvtzs", OP_ARMV8_A64_FCVTZS, DISOPTYPE_HARMLESS),
104	DIS_ARMV8_OP(0x1e190000, "fcvtzu", OP_ARMV8_A64_FCVTZU, DISOPTYPE_HARMLESS),
105	INVALID_OPCODE,
106	INVALID_OPCODE,
107	INVALID_OPCODE,
108	INVALID_OPCODE,
109	INVALID_OPCODE,
110	INVALID_OPCODE,
111	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpFixedPConvFpReg2Gpr)
112	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
113	DIS_ARMV8_INSN_DECODE(kDisParmParseReg, 0, 5, 0 /idxParam/),
114	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 1 /idxParam/),
115	DIS_ARMV8_INSN_DECODE(kDisParmParseFpScale, 10, 6, 2 /idxParam/),
116	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(DataProcFpFixedPConvFpReg2Gpr, 0x7f3f0000 /fFixedInsn/, DISARMV8INSNCLASS_F_SF /fClass/,
117	kDisArmV8OpcDecodeNop,
118	RT_BIT_32(16) \| RT_BIT_32(17) \| RT_BIT_32(18), 16,
119	kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmImm);
120
121
122	/*
123	* C4.1.96.32 - Conversion between floating-point and fixed-point
124	*
125	* Bit 28 (op0<0>) is already fixed at 1 at this point.
126	* Bit 30 (op0<2>) is already fixed at 0 at this point.
127	* Bit 24 (op1<1>) is already fixed at 0 at this point.
128	* Bit 21 (op2<2>) is already fixed at 0 at this point.
129	*
130	* Differentiate further based on the rmode field.
131	*/
132	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcFpFixedPConv)
133	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpFixedPConvGpr2FpReg),
134	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
135	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
136	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpFixedPConvFpReg2Gpr),
137	DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcFpFixedPConv, RT_BIT_32(19) \| RT_BIT_32(20), 19);
138
139
140	/*
141	* C4.1.96.33 - Conversion between floating-point and integer.
142	*
143	* FCVTNS/FCVTNU/SCVTF/UCVTF/FCVTAS/FCVTAU/FMOV/FCVTPS/FCVTPU/FCVTMS/FCVTMU/FCVTZS/FCVTZU.
144	*
145	* Note: The opcode is selected based on the <rmode>:<opcode> field.
146	*/
147	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpConvInt) /** @todo */
148	INVALID_OPCODE,
149	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpConvInt)
150	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
151	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
152	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 1 /idxParam/),
153	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(DataProcFpConvInt, 0xff3ffc00 /fFixedInsn/, DISARMV8INSNCLASS_F_SF /fClass/,
154	kDisArmV8OpcDecodeNop,
155	RT_BIT_32(16) \| RT_BIT_32(17) \| RT_BIT_32(18) \| RT_BIT_32(19) \| RT_BIT_32(20), 16,
156	kDisArmv8OpParmReg, kDisArmv8OpParmReg);
157
158
159	/*
160	* FCSEL.
161	*
162	* Note: The opcode is selected based on the <opcode> field.
163	*/
164	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpCondSelect)
165	DIS_ARMV8_OP(0x1e200c00, "fcsel", OP_ARMV8_A64_FCSEL, DISOPTYPE_HARMLESS),
166	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpCondSelect)
167	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
168	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
169	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 1 /idxParam/),
170	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 16, 5, 2 /idxParam/),
171	DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 12, 4, 3 /idxParam/),
172	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(DataProcFpCondSelect, 0xff200c00 /fFixedInsn/, 0 /fClass/,
173	kDisArmV8OpcDecodeNop,
174	RT_BIT_32(29), 29,
175	kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmCond);
176
177
178	/*
179	* FMUL/FDIV/FADD/FSUB/FMAX/FMIN/FMAXNM/FMINNM.
180	*
181	* Note: The opcode is selected based on the <opcode> field.
182	*/
183	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpDataProc2Src)
184	DIS_ARMV8_OP(0x1e200800, "fmul", OP_ARMV8_A64_FMUL, DISOPTYPE_HARMLESS),
185	DIS_ARMV8_OP(0x1e201800, "fdiv", OP_ARMV8_A64_FDIV, DISOPTYPE_HARMLESS),
186	DIS_ARMV8_OP(0x1e202800, "fadd", OP_ARMV8_A64_FADD, DISOPTYPE_HARMLESS),
187	DIS_ARMV8_OP(0x1e203800, "fsub", OP_ARMV8_A64_FSUB, DISOPTYPE_HARMLESS),
188	DIS_ARMV8_OP(0x1e204800, "fmax", OP_ARMV8_A64_FMAX, DISOPTYPE_HARMLESS),
189	DIS_ARMV8_OP(0x1e205800, "fmin", OP_ARMV8_A64_FMIN, DISOPTYPE_HARMLESS),
190	DIS_ARMV8_OP(0x1e206800, "fmaxnm", OP_ARMV8_A64_FMAXNM, DISOPTYPE_HARMLESS),
191	DIS_ARMV8_OP(0x1e207800, "fminnm", OP_ARMV8_A64_FMINNM, DISOPTYPE_HARMLESS),
192	DIS_ARMV8_OP(0x1e208800, "fnmul", OP_ARMV8_A64_FNMUL, DISOPTYPE_HARMLESS),
193	/* Rest of the 4 bit block is invalid */
194	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpDataProc2Src)
195	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
196	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
197	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 1 /idxParam/),
198	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 16, 5, 2 /idxParam/),
199	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(DataProcFpDataProc2Src, 0xff20fc00 /fFixedInsn/, 0 /fClass/,
200	kDisArmV8OpcDecodeNop,
201	RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 12,
202	kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmReg);
203
204
205	/*
206	* C4.1.96.34 - Floating-point data-processing (1 source).
207	*
208	* FMOV/FABS/FNEG/FSQRT/FCVT/FRINTN/FRINTP/FRINTM/FRINTZ/FRINA/FRINTX/FRINTI/FRINT32Z/FRINT32X/FRINT64Z/FRINT64X.
209	*
210	* Note: The opcode is selected based on the <opcode> field.
211	*/
212	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpDataProc1Src)
213	DIS_ARMV8_OP(0x1e204000, "fmov", OP_ARMV8_A64_FMOV, DISOPTYPE_HARMLESS),
214	DIS_ARMV8_OP(0x1e20c000, "fabs", OP_ARMV8_A64_FABS, DISOPTYPE_HARMLESS),
215	DIS_ARMV8_OP(0x1e214000, "fneg", OP_ARMV8_A64_FNEG, DISOPTYPE_HARMLESS),
216	DIS_ARMV8_OP(0x1e21c000, "fsqrt", OP_ARMV8_A64_FSQRT, DISOPTYPE_HARMLESS),
217	DIS_ARMV8_OP(0x1e224000, "fcvt", OP_ARMV8_A64_FCVT, DISOPTYPE_HARMLESS),
218	DIS_ARMV8_OP(0x1e22c000, "fcvt", OP_ARMV8_A64_FCVT, DISOPTYPE_HARMLESS),
219	INVALID_OPCODE,
220	DIS_ARMV8_OP(0x1e23c000, "fcvt", OP_ARMV8_A64_FCVT, DISOPTYPE_HARMLESS),
221	DIS_ARMV8_OP(0x1e244000, "frintn", OP_ARMV8_A64_FRINTN, DISOPTYPE_HARMLESS),
222	DIS_ARMV8_OP(0x1e24c000, "frintp", OP_ARMV8_A64_FRINTP, DISOPTYPE_HARMLESS),
223	DIS_ARMV8_OP(0x1e254000, "frintm", OP_ARMV8_A64_FRINTM, DISOPTYPE_HARMLESS),
224	DIS_ARMV8_OP(0x1e25c000, "frintz", OP_ARMV8_A64_FRINTZ, DISOPTYPE_HARMLESS),
225	DIS_ARMV8_OP(0x1e264000, "frinta", OP_ARMV8_A64_FRINTA, DISOPTYPE_HARMLESS),
226	INVALID_OPCODE,
227	DIS_ARMV8_OP(0x1e274000, "frintx", OP_ARMV8_A64_FRINTX, DISOPTYPE_HARMLESS),
228	DIS_ARMV8_OP(0x1e27c000, "frinti", OP_ARMV8_A64_FRINTI, DISOPTYPE_HARMLESS),
229	DIS_ARMV8_OP(0x1e284000, "frint32z", OP_ARMV8_A64_FRINT32Z, DISOPTYPE_HARMLESS),
230	DIS_ARMV8_OP(0x1e28c000, "frint32x", OP_ARMV8_A64_FRINT32X, DISOPTYPE_HARMLESS),
231	DIS_ARMV8_OP(0x1e294000, "frint64z", OP_ARMV8_A64_FRINT64Z, DISOPTYPE_HARMLESS),
232	DIS_ARMV8_OP(0x1e29c000, "frint64x", OP_ARMV8_A64_FRINT64X, DISOPTYPE_HARMLESS),
233	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpDataProc1Src)
234	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
235	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
236	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 1 /idxParam/),
237	DIS_ARMV8_INSN_DECODE(kDisParmParseFpFixupFCvt, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET),
238	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(DataProcFpDataProc1Src, 0xff3ffc00 /fFixedInsn/, 0 /fClass/,
239	kDisArmV8OpcDecodeNop,
240	RT_BIT_32(15) \| RT_BIT_32(16) \| RT_BIT_32(17) \| RT_BIT_32(18) \| RT_BIT_32(19) \| RT_BIT_32(20), 15,
241	kDisArmv8OpParmReg, kDisArmv8OpParmReg);
242
243
244	/*
245	* C4.1.96.35 - Floating-point compare.
246	*
247	* FCMP/FCMPE.
248	*
249	* Note: The opcode is selected based on the op2<3:4> field.
250	*/
251	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpCmpReg)
252	DIS_ARMV8_OP(0x1e202000, "fcmp", OP_ARMV8_A64_FCMP, DISOPTYPE_HARMLESS),
253	DIS_ARMV8_OP(0x1e202010, "fcmpe", OP_ARMV8_A64_FCMPE, DISOPTYPE_HARMLESS),
254	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpCmpReg)
255	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
256	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 0 /idxParam/),
257	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 16, 5, 1 /idxParam/),
258	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(DataProcFpCmpReg, 0xff20fc1f /fFixedInsn/, 0 /fClass/,
259	kDisArmV8OpcDecodeNop,
260	RT_BIT_32(4), 4,
261	kDisArmv8OpParmReg, kDisArmv8OpParmReg);
262
263
264	/*
265	* C4.1.96.35 - Floating-point compare.
266	*
267	* FCMP/FCMPE.
268	*
269	* Note: The opcode is selected based on the op2<3:4> field.
270	*/
271	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpCmpZero)
272	DIS_ARMV8_OP(0x1e202008, "fcmp", OP_ARMV8_A64_FCMP, DISOPTYPE_HARMLESS),
273	DIS_ARMV8_OP(0x1e202018, "fcmpe", OP_ARMV8_A64_FCMPE, DISOPTYPE_HARMLESS),
274	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpCmpZero)
275	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
276	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 0 /idxParam/),
277	DIS_ARMV8_INSN_DECODE(kDisParmParseImmZero, 0, 0, 1 /idxParam/),
278	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(DataProcFpCmpZero, 0xff20fc1f /fFixedInsn/, 0 /fClass/,
279	kDisArmV8OpcDecodeNop,
280	RT_BIT_32(4), 4,
281	kDisArmv8OpParmReg, kDisArmv8OpParmImm);
282
283
284	/*
285	* Floating Point compare, differentiate between register and zero variant.
286	*/
287	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcFpCmp)
288	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCmpReg),
289	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCmpZero),
290	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcFpCmp, 3);
291
292
293	/*
294	* C4.1.96.36 - Floating-point immediate.
295	*
296	* FMOV.
297	*
298	* Note: The opcode is selected based on the <op> field.
299	*/
300	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpImm)
301	DIS_ARMV8_OP(0x1e201000, "fmov", OP_ARMV8_A64_FMOV, DISOPTYPE_HARMLESS),
302	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpImm)
303	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
304	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
305	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 13, 8, 1 /idxParam/),
306	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_2(DataProcFpImm, 0xff201fe0 /fFixedInsn/, 0 /fClass/,
307	kDisArmV8OpcDecodeNop,
308	RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7) \| RT_BIT_32(8) \| RT_BIT_32(9), 5,
309	kDisArmv8OpParmReg, kDisArmv8OpParmImm);
310
311
312	/*
313	* C4.1.96.37 - Floating-point conditional compare.
314	*
315	* FCCMP/FCCMPE.
316	*
317	* Note: The opcode is selected based on the <op> field.
318	*/
319	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpCondCmp)
320	DIS_ARMV8_OP(0x1e200400, "fccmp", OP_ARMV8_A64_FCCMP, DISOPTYPE_HARMLESS),
321	DIS_ARMV8_OP(0x1e200410, "fccmpe", OP_ARMV8_A64_FCCMPE, DISOPTYPE_HARMLESS),
322	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpCondCmp)
323	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
324	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 0 /idxParam/),
325	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 16, 5, 1 /idxParam/),
326	DIS_ARMV8_INSN_DECODE(kDisParmParseImm, 0, 4, 2 /idxParam/),
327	DIS_ARMV8_INSN_DECODE(kDisParmParseCond, 12, 4, 3 /idxParam/),
328	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(DataProcFpCondCmp, 0xff200c10 /fFixedInsn/, 0 /fClass/,
329	kDisArmV8OpcDecodeNop,
330	RT_BIT_32(4), 4,
331	kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmImm, kDisArmv8OpParmCond);
332
333
334	/*
335	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
336	*
337	* Bit 28 (op0<0>) is already fixed at 1 at this point.
338	* Bit 30 (op0<2>) is already fixed at 0 at this point.
339	* Bit 24 (op1<1>) is already fixed at 0 at this point.
340	* Bit 21 (op2<2>) is already fixed at 1 at this point.
341	* Bit 11 (op3<1>) is already fixed at 0 at this point.
342	* Bit 10 (op3<0>) is already fixed at 0 at this point.
343	*
344	* Differentiate further based on the op3<5:2> field.
345	*
346	* Bit 15 14 13 12
347	* +-------------------------------------------
348	* 0 0 0 0 Conversion between FP and integer
349	* 0 0 0 1 FP immediate
350	* 0 0 1 0 FP compare
351	* 0 0 1 1 FP immediate
352	* 0 1 0 0 FP data-processing (1 source)
353	* 0 1 0 1 FP immediate
354	* 0 1 1 0 FP compare
355	* 0 1 1 1 FP immediate
356	* 1 0 0 0 UNDEFINED
357	* 1 0 0 1 FP immediate
358	* 1 0 1 0 FP compare
359	* 1 0 1 1 FP immediate
360	* 1 1 0 0 FP data-processing (1 source)
361	* 1 1 0 1 FP immediate
362	* 1 1 1 0 FP compare
363	* 1 1 1 1 FP immediate
364	*/
365	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1_30_0_24_0_21_1_11_0_10_0)
366	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpConvInt),
367	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
368	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCmp),
369	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
370	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpDataProc1Src),
371	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
372	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCmp),
373	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
374	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
375	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
376	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCmp),
377	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
378	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpDataProc1Src),
379	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
380	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCmp),
381	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpImm),
382	DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcSimdFpBit28_1_30_0_24_0_21_1_11_0_10_0, RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15), 12);
383
384
385	/*
386	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
387	*
388	* Bit 28 (op0<0>) is already fixed at 1 at this point.
389	* Bit 30 (op0<2>) is already fixed at 0 at this point.
390	* Bit 24 (op1<1>) is already fixed at 0 at this point.
391	* Bit 21 (op2<2>) is already fixed at 1 at this point.
392	*
393	* Differentiate further based on the op3<1:0> field.
394	*
395	* Bit 11 10
396	* +-------------------------------------------
397	* 0 0 Conversion between FP and integer / FP data-processing (1 source) / compare / immediate
398	* 0 1 FP conditional compare
399	* 1 0 FP data processing (2 source)
400	* 1 1 FP conditional select
401	*/
402	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1_30_0_24_0_21_1)
403	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_0_24_0_21_1_11_0_10_0),
404	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCondCmp),
405	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpDataProc2Src),
406	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpCondSelect),
407	DIS_ARMV8_DECODE_MAP_DEFINE_END(DataProcSimdFpBit28_1_30_0_24_0_21_1, RT_BIT_32(10) \| RT_BIT_32(11), 10);
408
409
410	/*
411	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
412	*
413	* Bit 28 (op0<0>) is already fixed at 1 at this point.
414	* Bit 30 (op0<2>) is already fixed at 0 at this point.
415	* Bit 24 (op1<1>) is already fixed at 0 at this point.
416	*
417	* Differentiate further based on the op2<2> field.
418	*
419	* Bit 21
420	* +-------------------------------------------
421	* 0 Conversion between FP and fixed-point
422	* 1 Conversion between FP and integer/FP data-processing (1 source) /
423	* compare / immediate / conditional compare / data-processing (2 source) / conditional select
424	*/
425	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1_30_0_24_0)
426	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpFixedPConv),
427	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_0_24_0_21_1),
428	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_1_30_0_24_0, 21);
429
430
431	/*
432	* FMADD/FMSUB/FNMADD/FNMSUB.
433	*
434	* Note: The o1,o0 bitfields are concatenated to form an index.
435	*/
436	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcFpDataProc3Src)
437	DIS_ARMV8_OP(0x1f000000, "fmadd", OP_ARMV8_A64_FMADD, DISOPTYPE_HARMLESS),
438	DIS_ARMV8_OP(0x1f008000, "fmsub", OP_ARMV8_A64_FMSUB, DISOPTYPE_HARMLESS),
439	DIS_ARMV8_OP(0x1f200000, "fnmadd", OP_ARMV8_A64_FNMADD, DISOPTYPE_HARMLESS),
440	DIS_ARMV8_OP(0x1f208000, "fnmsub", OP_ARMV8_A64_FNMSUB, DISOPTYPE_HARMLESS),
441	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcFpDataProc3Src)
442	DIS_ARMV8_INSN_DECODE(kDisParmParseFpType, 22, 2, DIS_ARMV8_INSN_PARAM_UNSET),
443	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 0, 5, 0 /idxParam/),
444	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 5, 5, 1 /idxParam/),
445	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 16, 5, 2 /idxParam/),
446	DIS_ARMV8_INSN_DECODE(kDisParmParseFpReg, 10, 5, 3 /idxParam/),
447	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_4(DataProcFpDataProc3Src, 0xff208000 /fFixedInsn/, 0 /fClass/,
448	kDisArmV8OpcDecodeCollate,
449	RT_BIT_32(15) \| RT_BIT_32(21), 15,
450	kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmReg);
451
452
453	/*
454	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
455	*
456	* Bit 28 (op0<0>) is already fixed at 1 at this point.
457	* Bit 30 (op0<2>) is already fixed at 0 at this point.
458	*
459	* Differentiate further based on the op1<1> field.
460	*
461	* Bit 24
462	* +-------------------------------------------
463	* 0 Conversion between FP and fixed-point/Conversion between FP and integer/
464	* FP data-processing (1 source) / compare / immediate / conditional compare / data-processing (2 source) /
465	* conditional select
466	* 1 FP data-processing (3 source)
467	*/
468	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1_30_0)
469	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_0_24_0),
470	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcFpDataProc3Src),
471	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_1_30_0, 24);
472
473
474	/*
475	* C4.1.96.12 - Data Processing - Advanced SIMD scalar shift by immediate
476	*
477	* FMADD/FMSUB/FNMADD/FNMSUB.
478	*
479	* Note: The U,opcode bitfields are concatenated to form an index.
480	*/
481	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(DataProcSimdScalarShiftByImm)
482	DIS_ARMV8_OP(0x5f000400, "sshr", OP_ARMV8_A64_SSHR, DISOPTYPE_HARMLESS),
483	INVALID_OPCODE,
484	DIS_ARMV8_OP(0x5f001400, "ssra", OP_ARMV8_A64_SSRA, DISOPTYPE_HARMLESS),
485	INVALID_OPCODE,
486	DIS_ARMV8_OP(0x5f002400, "srshr", OP_ARMV8_A64_SRSHR, DISOPTYPE_HARMLESS),
487	INVALID_OPCODE,
488	DIS_ARMV8_OP(0x5f003400, "srsra", OP_ARMV8_A64_SRSRA, DISOPTYPE_HARMLESS),
489	INVALID_OPCODE,
490	INVALID_OPCODE,
491	INVALID_OPCODE,
492	#if 0 /** @todo */
493	DIS_ARMV8_OP(0x5f005400, "shl", OP_ARMV8_A64_SHL, DISOPTYPE_HARMLESS),
494	INVALID_OPCODE,
495	DIS_ARMV8_OP(0x5f007400, "sqshl", OP_ARMV8_A64_SQSHL, DISOPTYPE_HARMLESS),
496	INVALID_OPCODE,
497	DIS_ARMV8_OP(0x5f009400, "sqshrn", OP_ARMV8_A64_SQSHRN, DISOPTYPE_HARMLESS),
498	INVALID_OPCODE,
499	DIS_ARMV8_OP(0x5f009c00, "sqrshrn", OP_ARMV8_A64_SQRSHRN, DISOPTYPE_HARMLESS),
500	#endif
501	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(DataProcSimdScalarShiftByImm)
502	DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar, 0, 5, 0 /idxParam/),
503	DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar, 5, 5, 1 /idxParam/),
504	DIS_ARMV8_INSN_DECODE(kDisParmParseImmHImmB, 16, 7, 2 /idxParam/),
505	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END_PARAMS_3(DataProcSimdScalarShiftByImm, 0xff80fc00 /fFixedInsn/, 0 /fClass/,
506	kDisArmV8OpcDecodeCollate,
507	/* opcode */ RT_BIT_32(11) \| RT_BIT_32(12) \| RT_BIT_32(13) \| RT_BIT_32(14) \| RT_BIT_32(15)
508	/* U */ \| RT_BIT_32(29), 11,
509	kDisArmv8OpParmReg, kDisArmv8OpParmReg, kDisArmv8OpParmImm);
510
511
512	/*
513	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
514	*
515	* Bit 28 (op0<0>) is already fixed at 1 at this point.
516	* Bit 30 (op0<2>) is already fixed at 1 at this point.
517	* Bit 10 (op3<0>) is already fixed at 1 at this point.
518	*
519	* Differentiate further based on the op1<1> field.
520	*
521	* Bit 24
522	* +-------------------------------------------
523	* 0 Advanced SIMD scalar copy / scalar three same FP16 / scalar three same /
524	* scalar three same extra
525	* 1 Advanced SIMD scalar shift by immediate
526	*/
527	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1_30_1_10_1)
528	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, //DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_1_10_0),
529	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdScalarShiftByImm),
530	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_1_30_1_10_1, 24);
531
532
533	/*
534	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
535	*
536	* Bit 28 (op0<0>) is already fixed at 1 at this point.
537	* Bit 30 (op0<2>) is already fixed at 1 at this point.
538	*
539	* Differentiate further based on the op3<0> field.
540	*
541	* Bit 10
542	* +-------------------------------------------
543	* 0 Cryptographic three-register SHA / two-register SHA
544	* Advanced SIMD scalar two-register miscellaneous FP16 / scalar two-register miscellaneous / scalar pairwise /
545	* scalar three different / scalar x indexed element
546	* 1 Advanced SIMD scalar copy / scalar three same FP16 / scalar three same /
547	* scalar shift by immediate / scalar three same extra
548	*/
549	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1_30_1)
550	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, //DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_1_10_0),
551	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_1_10_1),
552	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_1_30_1, 10);
553
554
555	/*
556	* C4.1.96 - Data Processing - Scalar Floating-Point and Advanced SIMD
557	*
558	* Bit 28 (op0<0>) is already fixed at 1 at this point.
559	*
560	* Differentiate further based on the op0<2> field.
561	*
562	* Bit 30
563	* +-------------------------------------------
564	* 0 Conversion between FP and fixed-point/Conversion between FP and integer/
565	* FP data-processing (1 source) / compare / immediate / conditional compare / data-processing (2 source) /
566	* conditional select / data-processing (3 source)
567	* 1 Cryptographic three-register SHA / two-register SHA
568	* Advanced SIMD scalar two-register miscellaneous FP16 / scalar two-register miscellaneous / scalar pairwise /
569	* scalar three different / scalar x indexed element / scalar copy / scalar three same FP16 / scalar three same /
570	* scalar shift by immediate / scalar three same extra
571	*/
572	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(DataProcSimdFpBit28_1)
573	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_0),
574	DIS_ARMV8_DECODE_MAP_ENTRY(DataProcSimdFpBit28_1_30_1),
575	DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(DataProcSimdFpBit28_1, 30);

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source: vbox/trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-simd-fp.cpp.h@ 106129

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