DisasmTables-armv8-a64-ld-st.cpp.h@ 106695

Last change on this file since 106695 was 106694, checked in by vboxsync, 5 weeks ago
Disassembler: Decode ldnp/stnp non temporal hint load/store instructions, bugref:10394
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1	/* $Id: DisasmTables-armv8-a64-ld-st.cpp.h 106694 2024-10-25 12:55:26Z vboxsync $ */
2	/** @file
3	* VBox disassembler - Tables for ARMv8 A64 - Lods & Stores.
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/* STRB/LDRB/LDRSB/STR/LDR/STRH/LDRH/LDRSH/LDRSW/PRFM
30	*
31	* Note: The size,opc bitfields are concatenated to form an index.
32	*/
33	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUImmGpr)
34	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
35	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
36	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
37	DIS_ARMV8_INSN_DECODE(kDisParmParseImmMemOff, 10, 12, 1 /idxParam/),
38	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUImmGpr)
39	DIS_ARMV8_OP(0x39000000, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
40	DIS_ARMV8_OP(0x39400000, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
41	DIS_ARMV8_OP_EX(0x39800000, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
42	DIS_ARMV8_OP(0x39c00000, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS),
43	DIS_ARMV8_OP(0x79000000, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
44	DIS_ARMV8_OP(0x79400000, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
45	DIS_ARMV8_OP_EX(0x79800000, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
46	DIS_ARMV8_OP(0x79c00000, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS),
47	DIS_ARMV8_OP(0xb9000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
48	DIS_ARMV8_OP(0xb9400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
49	DIS_ARMV8_OP_EX(0xb9800000, "ldrsw", OP_ARMV8_A64_LDRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
50	INVALID_OPCODE,
51	DIS_ARMV8_OP(0xf9000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
52	DIS_ARMV8_OP(0xf9400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
53	INVALID_OPCODE, /** @todo PRFM */
54	INVALID_OPCODE,
55	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUImmGpr, 0xffc00000 /fFixedInsn/,
56	kDisArmV8OpcDecodeCollate,
57	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
58
59
60	/*
61	* C4.1.94 - Loads and Stores - Load/Store register variants
62	*
63	* Differentiate further based on the VR field.
64	*
65	* Bit 26
66	* +-------------------------------------------
67	* 0 GPR variants.
68	* 1 SIMD/FP variants
69	*/
70	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegUImm)
71	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUImmGpr),
72	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
73	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegUImm, RT_BIT_32(26), 26);
74
75
76	/*
77	* STRB/LDRB/LDRSB/STR/LDR/STRH/LDRH/LDRSH/LDRSW/PRFM
78	*
79	* Note: The size,opc bitfields are concatenated to form an index.
80	*/
81	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegOffGpr)
82	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
83	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
84	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
85	DIS_ARMV8_INSN_DECODE(kDisParmParseGprOff, 16, 5, 1 /idxParam/),
86	DIS_ARMV8_INSN_DECODE(kDisParmParseOption, 13, 3, 1 /idxParam/),
87	DIS_ARMV8_INSN_DECODE(kDisParmParseS, 12, 1, 1 /idxParam/),
88	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegOffGpr)
89	DIS_ARMV8_OP(0x38200800, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
90	DIS_ARMV8_OP(0x38600800, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
91	DIS_ARMV8_OP_EX(0x38a00800, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
92	DIS_ARMV8_OP(0x38e00800, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS),
93	DIS_ARMV8_OP(0x78200800, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
94	DIS_ARMV8_OP(0x78600800, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
95	DIS_ARMV8_OP_EX(0x78a00800, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
96	DIS_ARMV8_OP(0x78e00800, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS),
97	DIS_ARMV8_OP(0xb8200800, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
98	DIS_ARMV8_OP(0xb8600800, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
99	DIS_ARMV8_OP_EX(0xb8a00800, "ldrsw", OP_ARMV8_A64_LDRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT ),
100	INVALID_OPCODE,
101	DIS_ARMV8_OP(0xf8200800, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
102	DIS_ARMV8_OP(0xf8600800, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
103	INVALID_OPCODE, /** @todo PRFM */
104	INVALID_OPCODE,
105	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegOffGpr, 0xffe00c00 /fFixedInsn/,
106	kDisArmV8OpcDecodeCollate,
107	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
108
109
110	/*
111	* C4.1.94 - Loads and Stores - Load/Store register (register offset) variants
112	*
113	* Differentiate further based on the VR field.
114	*
115	* Bit 26
116	* +-------------------------------------------
117	* 0 GPR variants.
118	* 1 SIMD/FP variants
119	*/
120	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOff)
121	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOffGpr),
122	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
123	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOff, RT_BIT_32(26), 26);
124
125
126	/*
127	* C4.1.94 - Loads and Stores - Load/Store register variants
128	*
129	* Differentiate further based on the op2<1:0> field.
130	*
131	* Bit 11 10
132	* +-------------------------------------------
133	* 0 0 Atomic memory operations
134	* 0 1 Load/store register (pac)
135	* 1 0 Load/store register (register offset)
136	* 1 1 Load/store register (pac)
137	*/
138	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11_1)
139	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
140	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
141	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOff),
142	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
143	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11_1, RT_BIT_32(10) \| RT_BIT_32(11), 10);
144
145
146	/*
147	* STURB/LDURB/LDURSB/STURH/LDURH/LDURSH/STUR/LDUR/LDURSW/PRFUM
148	*
149	* Note: The size,opc bitfields are concatenated to form an index.
150	*/
151	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUnscaledImmGpr)
152	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
153	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
154	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
155	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /idxParam/),
156	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUnscaledImmGpr)
157	DIS_ARMV8_OP(0x38000000, "sturb", OP_ARMV8_A64_STURB, DISOPTYPE_HARMLESS),
158	DIS_ARMV8_OP(0x38400000, "ldurb", OP_ARMV8_A64_LDURB, DISOPTYPE_HARMLESS),
159	DIS_ARMV8_OP_EX(0x38800000, "ldursb", OP_ARMV8_A64_LDURSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
160	DIS_ARMV8_OP(0x38c00000, "ldursb", OP_ARMV8_A64_LDURSB, DISOPTYPE_HARMLESS),
161	DIS_ARMV8_OP(0x78000000, "sturh", OP_ARMV8_A64_STURH, DISOPTYPE_HARMLESS),
162	DIS_ARMV8_OP(0x78400000, "ldurh", OP_ARMV8_A64_LDURH, DISOPTYPE_HARMLESS),
163	DIS_ARMV8_OP_EX(0x78800000, "ldursh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
164	DIS_ARMV8_OP(0x78c00000, "ldursh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS),
165	DIS_ARMV8_OP(0xb8000000, "stur", OP_ARMV8_A64_STUR, DISOPTYPE_HARMLESS),
166	DIS_ARMV8_OP(0xb8400000, "ldur", OP_ARMV8_A64_LDUR, DISOPTYPE_HARMLESS),
167	DIS_ARMV8_OP_EX(0xb8800000, "ldursw", OP_ARMV8_A64_LDURSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
168	INVALID_OPCODE,
169	DIS_ARMV8_OP(0xf8000000, "stur", OP_ARMV8_A64_STUR, DISOPTYPE_HARMLESS),
170	DIS_ARMV8_OP(0xf8400000, "ldur", OP_ARMV8_A64_LDUR, DISOPTYPE_HARMLESS),
171	INVALID_OPCODE, /** @todo PRFUM */
172	INVALID_OPCODE,
173	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUnscaledImmGpr, 0xffe00c00 /fFixedInsn/,
174	kDisArmV8OpcDecodeCollate,
175	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
176
177
178	/*
179	* C4.1.94 - Loads and Stores - Load/Store register (register offset) variants
180	*
181	* Differentiate further based on the VR field.
182	*
183	* Bit 26
184	* +-------------------------------------------
185	* 0 GPR variants.
186	* 1 SIMD/FP variants
187	*/
188	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegUnscaledImm)
189	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnscaledImmGpr),
190	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
191	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegUnscaledImm, RT_BIT_32(26), 26);
192
193
194	/*
195	* STRB/LDRB/LDRSB/STRH/LDRH/LDRSH/STR/LDR/LDRSW/STR/LDR
196	*
197	* Note: The size,opc bitfields are concatenated to form an index.
198	*/
199	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegImmPreIndexGpr)
200	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
201	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
202	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
203	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /idxParam/),
204	DIS_ARMV8_INSN_DECODE(kDisParmParseSetPreIndexed, 0, 0, 1 /idxParam/),
205	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegImmPreIndexGpr)
206	DIS_ARMV8_OP(0x38000c00, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
207	DIS_ARMV8_OP(0x38400c00, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
208	DIS_ARMV8_OP_EX(0x38800c00, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
209	DIS_ARMV8_OP_EX(0x38c00c00, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
210	DIS_ARMV8_OP(0x78000c00, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
211	DIS_ARMV8_OP(0x78400c00, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
212	DIS_ARMV8_OP_EX(0x78800c00, "ldrsh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
213	DIS_ARMV8_OP_EX(0x78c00c00, "ldrsh", OP_ARMV8_A64_LDURSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
214	DIS_ARMV8_OP(0xb8000c00, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
215	DIS_ARMV8_OP(0xb8400c00, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
216	DIS_ARMV8_OP_EX(0xb8800c00, "ldrsw", OP_ARMV8_A64_LDURSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
217	INVALID_OPCODE,
218	DIS_ARMV8_OP(0xf8000c00, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
219	DIS_ARMV8_OP(0xf8400c00, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
220	INVALID_OPCODE,
221	INVALID_OPCODE,
222	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegImmPreIndexGpr, 0xffe00c00 /fFixedInsn/,
223	kDisArmV8OpcDecodeCollate,
224	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
225
226
227	/*
228	* C4.1.94.28 - Loads and Stores - Load/Store register (immediate pre-indexed) variants
229	*
230	* Differentiate further based on the VR field.
231	*
232	* Bit 26
233	* +-------------------------------------------
234	* 0 GPR variants.
235	* 1 SIMD/FP variants
236	*/
237	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegImmPreIndex)
238	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPreIndexGpr),
239	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
240	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegImmPreIndex, RT_BIT_32(26), 26);
241
242
243	/*
244	* STRB/LDRB/LDRSB/STRH/LDRH/LDRSH/STR/LDR/LDRSW/STR/LDR
245	*
246	* Note: The size,opc bitfields are concatenated to form an index.
247	*/
248	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegImmPostIndexGpr)
249	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
250	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
251	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
252	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /idxParam/),
253	DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed, 0, 0, 1 /idxParam/),
254	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegImmPostIndexGpr)
255	DIS_ARMV8_OP(0x38000400, "strb", OP_ARMV8_A64_STRB, DISOPTYPE_HARMLESS),
256	DIS_ARMV8_OP(0x38400400, "ldrb", OP_ARMV8_A64_LDRB, DISOPTYPE_HARMLESS),
257	DIS_ARMV8_OP_EX(0x38800400, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
258	DIS_ARMV8_OP_EX(0x38c00400, "ldrsb", OP_ARMV8_A64_LDRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
259	DIS_ARMV8_OP(0x78000400, "strh", OP_ARMV8_A64_STRH, DISOPTYPE_HARMLESS),
260	DIS_ARMV8_OP(0x78400400, "ldrh", OP_ARMV8_A64_LDRH, DISOPTYPE_HARMLESS),
261	DIS_ARMV8_OP_EX(0x78800400, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
262	DIS_ARMV8_OP_EX(0x78c00400, "ldrsh", OP_ARMV8_A64_LDRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
263	DIS_ARMV8_OP(0xb8000400, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
264	DIS_ARMV8_OP(0xb8400400, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
265	DIS_ARMV8_OP_EX(0xb8800400, "ldrsw", OP_ARMV8_A64_LDRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
266	INVALID_OPCODE,
267	DIS_ARMV8_OP(0xf8000400, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS),
268	DIS_ARMV8_OP(0xf8400400, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS),
269	INVALID_OPCODE,
270	INVALID_OPCODE,
271	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegImmPostIndexGpr, 0xffe00c00 /fFixedInsn/,
272	kDisArmV8OpcDecodeCollate,
273	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
274
275
276	/*
277	* C4.1.94.26 - Loads and Stores - Load/Store register (immediate post-indexed) variants
278	*
279	* Differentiate further based on the VR field.
280	*
281	* Bit 26
282	* +-------------------------------------------
283	* 0 GPR variants.
284	* 1 SIMD/FP variants
285	*/
286	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegImmPostIndex)
287	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPostIndexGpr),
288	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
289	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegImmPostIndex, RT_BIT_32(26), 26);
290
291
292	/*
293	* STTRB/LDTRB/LDTRSB/STTRH/LDTRH/LDTRSH/LDTRSH/STTR/LDTR/LDTRSW/STTR/LDTR
294	*
295	* Note: The size,opc bitfields are concatenated to form an index.
296	*/
297	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUnpriv)
298	DIS_ARMV8_INSN_DECODE(kDisParmParseSize, 30, 2, DIS_ARMV8_INSN_PARAM_UNSET),
299	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
300	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /idxParam/),
301	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12, 9, 1 /idxParam/),
302	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUnpriv)
303	DIS_ARMV8_OP(0x38000800, "sttrb", OP_ARMV8_A64_STTRB, DISOPTYPE_HARMLESS),
304	DIS_ARMV8_OP(0x38400800, "ldtrb", OP_ARMV8_A64_LDTRB, DISOPTYPE_HARMLESS),
305	DIS_ARMV8_OP_EX(0x38800800, "ldtrsb", OP_ARMV8_A64_LDTRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
306	DIS_ARMV8_OP_EX(0x38c00800, "ldtrsb", OP_ARMV8_A64_LDTRSB, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
307	DIS_ARMV8_OP(0x78000800, "sttrh", OP_ARMV8_A64_STTRH, DISOPTYPE_HARMLESS),
308	DIS_ARMV8_OP(0x78400800, "ldtrh", OP_ARMV8_A64_LDTRH, DISOPTYPE_HARMLESS),
309	DIS_ARMV8_OP_EX(0x78800800, "ldtrsh", OP_ARMV8_A64_LDTRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
310	DIS_ARMV8_OP_EX(0x78c00800, "ldtrsh", OP_ARMV8_A64_LDTRSH, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
311	DIS_ARMV8_OP(0xb8000800, "sttr", OP_ARMV8_A64_STTR, DISOPTYPE_HARMLESS),
312	DIS_ARMV8_OP(0xb8400800, "ldtr", OP_ARMV8_A64_LDTR, DISOPTYPE_HARMLESS),
313	DIS_ARMV8_OP_EX(0xb8800800, "ldtrsw", OP_ARMV8_A64_LDTRSW, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
314	INVALID_OPCODE,
315	DIS_ARMV8_OP(0xf8000800, "sttr", OP_ARMV8_A64_STTR, DISOPTYPE_HARMLESS),
316	DIS_ARMV8_OP(0xf8400800, "ldtr", OP_ARMV8_A64_LDTR, DISOPTYPE_HARMLESS),
317	INVALID_OPCODE,
318	INVALID_OPCODE,
319	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUnpriv, 0xffe00c00 /fFixedInsn/,
320	kDisArmV8OpcDecodeCollate,
321	RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
322
323
324	/*
325	* C4.1.94 - Loads and Stores - Load/Store register variants
326	*
327	* Differentiate further based on the op2<1:0> field.
328	*
329	* Bit 11 10
330	* +-------------------------------------------
331	* 0 0 Load/store register (unscaled immediate)
332	* 0 1 Load/store register (immediate post-indexed)
333	* 1 0 Load/store register (unprivileged)
334	* 1 1 Load/store register (immediate pre-indexed)
335	*/
336	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11_0)
337	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnscaledImm),
338	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPostIndex),
339	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnpriv), /* No vector variants. */
340	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPreIndex),
341	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11_0, RT_BIT_32(10) \| RT_BIT_32(11), 10);
342
343
344	/*
345	* C4.1.94 - Loads and Stores - Load/Store register variants
346	*
347	* Differentiate further based on the op2<11> field.
348	*
349	* Bit 21
350	* +-------------------------------------------
351	* 0 Load/store register (unscaled immediate) / Load/store register (immediate post-indexed) / Load/store register (unprivileged) / Load/store register (immediate pre-indexed)
352	* 1 Atomic memory operations / Load/store register (register offset) / Load/store register (pac).
353	*/
354	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegOp2_11)
355	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11_0),
356	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11_1),
357	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegOp2_11, RT_BIT_32(21), 21);
358
359
360	/*
361	* C4.1.94 - Loads and Stores - Load/Store register variants
362	*
363	* Differentiate further based on the op2<14> field.
364	*
365	* Bit 24
366	* +-------------------------------------------
367	* 0 All the other Load/store register variants and Atomic memory operations.
368	* 1 Load/store register (unsigned immediate).
369	*/
370	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStReg)
371	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegOp2_11),
372	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUImm),
373	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStReg, RT_BIT_32(24), 24);
374
375
376	/*
377	* STP/LDP/STGP/LDPSW
378	*
379	* Note: The opc,L bitfields are concatenated to form an index.
380	*/
381	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairOff)
382	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
383	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /idxParam/),
384	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /idxParam/),
385	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /idxParam/),
386	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairOff)
387	DIS_ARMV8_OP_EX(0x29000000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
388	DIS_ARMV8_OP_EX(0x29400000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
389	INVALID_OPCODE,
390	INVALID_OPCODE,
391	DIS_ARMV8_OP_EX(0xa9000000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
392	DIS_ARMV8_OP_EX(0xa9400000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
393	INVALID_OPCODE,
394	INVALID_OPCODE,
395	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairOff, 0xffc00000 /fFixedInsn/,
396	kDisArmV8OpcDecodeCollate,
397	RT_BIT_32(22) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
398
399
400	/*
401	* STP/LDP/STGP/LDPSW - pre-indexed variant.
402	*
403	* Note: The opc,L bitfields are concatenated to form an index.
404	*/
405	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairPreIndex)
406	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
407	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /idxParam/),
408	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /idxParam/),
409	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /idxParam/),
410	DIS_ARMV8_INSN_DECODE(kDisParmParseSetPreIndexed, 0, 0, 2 /idxParam/),
411	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairPreIndex)
412	DIS_ARMV8_OP_EX(0x29800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
413	DIS_ARMV8_OP_EX(0x29c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
414	INVALID_OPCODE,
415	INVALID_OPCODE,
416	DIS_ARMV8_OP_EX(0xa9800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
417	DIS_ARMV8_OP_EX(0xa9c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
418	INVALID_OPCODE,
419	INVALID_OPCODE,
420	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairPreIndex, 0xffc00000 /fFixedInsn/,
421	kDisArmV8OpcDecodeCollate,
422	RT_BIT_32(22) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
423
424
425	/*
426	* STP/LDP/STGP/LDPSW - post-indexed variant.
427	*
428	* Note: The opc,L bitfields are concatenated to form an index.
429	*/
430	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairPostIndex)
431	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
432	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /idxParam/),
433	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /idxParam/),
434	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /idxParam/),
435	DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed, 0, 0, 2 /idxParam/),
436	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairPostIndex)
437	DIS_ARMV8_OP_EX(0x28800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
438	DIS_ARMV8_OP_EX(0x28c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
439	INVALID_OPCODE,
440	INVALID_OPCODE,
441	DIS_ARMV8_OP_EX(0xa8800000, "stp", OP_ARMV8_A64_STP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
442	DIS_ARMV8_OP_EX(0xa8c00000, "ldp", OP_ARMV8_A64_LDP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
443	INVALID_OPCODE,
444	INVALID_OPCODE,
445	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairPostIndex, 0xffc00000 /fFixedInsn/,
446	kDisArmV8OpcDecodeCollate,
447	RT_BIT_32(22) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
448
449
450	/*
451	* stnp/LDNP - no-allocate variant.
452	*
453	* Note: The opc,L bitfields are concatenated to form an index.
454	*/
455	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegPairNoAllocGpr)
456	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 0, 5, 0 /idxParam/),
457	DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr, 10, 5, 1 /idxParam/),
458	DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 2 /idxParam/),
459	DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOff, 15, 7, 2 /idxParam/),
460	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegPairNoAllocGpr)
461	DIS_ARMV8_OP_EX(0x28000000, "stnp", OP_ARMV8_A64_STNP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
462	DIS_ARMV8_OP_EX(0x28400000, "ldnp", OP_ARMV8_A64_LDNP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
463	INVALID_OPCODE,
464	INVALID_OPCODE,
465	DIS_ARMV8_OP_EX(0xa8000000, "stnp", OP_ARMV8_A64_STNP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
466	DIS_ARMV8_OP_EX(0xa8400000, "ldnp", OP_ARMV8_A64_LDNP, DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
467	INVALID_OPCODE,
468	INVALID_OPCODE,
469	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegPairNoAllocGpr, 0xffc00000 /fFixedInsn/,
470	kDisArmV8OpcDecodeCollate,
471	RT_BIT_32(22) \| RT_BIT_32(30) \| RT_BIT_32(31), 22);
472
473
474	/*
475	* C4.1.94.21 - Loads and Stores - Load/Store register (immediate post-indexed) variants
476	*
477	* Differentiate further based on the VR field.
478	*
479	* Bit 26
480	* +-------------------------------------------
481	* 0 GPR variants.
482	* 1 SIMD/FP variants
483	*/
484	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegPairNoAlloc)
485	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairNoAllocGpr),
486	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
487	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegPairNoAlloc, RT_BIT_32(26), 26);
488
489
490	/*
491	* C4.1.94 - Loads and Stores - Load/Store register pair variants
492	*
493	* Differentiate further based on the op2<14:13> field.
494	*
495	* Bit 24 23
496	* +-------------------------------------------
497	* 0 0 Load/store no-allocate pair (offset)
498	* 0 1 Load/store register pair (post-indexed)
499	* 1 0 Load/store register pair (offset).
500	* 1 1 Load/store register pair (pre-indexed).
501	*/
502	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegPair)
503	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairNoAlloc),
504	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairPostIndex),
505	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairOff),
506	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPairPreIndex),
507	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegPair, RT_BIT_32(23) \| RT_BIT_32(24), 23);
508
509
510	/*
511	* C4.1.94 - Loads and Stores
512	*
513	* Differentiate further based on the op0<1:0> field.
514	* Splitting this up because the decoding would get insane otherwise with tables doing cross referencing...
515	*
516	* Bit 29 28
517	* +-------------------------------------------
518	* 0 0 Compare and swap pair / Advanced SIMD loads/stores / Load/store exclusive pair / Load/store exclusive register
519	* Load/store ordered / Compare and swap
520	* 0 1 RCW compare and swap / 128-bit atomic memory instructions / GCS load/store / Load/store memory tags /
521	* LDIAPP/STILP / LDAPR/STLR / Load register (literal) / Memory Copy and Set
522	* 1 0 Load/store no-allocate pair / Load/store register pair /
523	* 1 1 Load/store register / Atomic memory operations
524	*/
525	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStOp0Lo)
526	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
527	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo */
528	DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPair),
529	DIS_ARMV8_DECODE_MAP_ENTRY(LdStReg),
530	DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStOp0Lo, RT_BIT_32(28) \| RT_BIT_32(29), 28);

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source: vbox/trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-ld-st.cpp.h@ 106695

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