DisasmReg.cpp@ 69288

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1	/* $Id: DisasmReg.cpp 69111 2017-10-17 14:26:02Z vboxsync $ */
2	/** @file
3	* VBox disassembler- Register Info Helpers.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DIS
23	#include <VBox/dis.h>
24	#include <VBox/disopcode.h>
25	#include <VBox/err.h>
26	#include <VBox/log.h>
27	#include <VBox/vmm/cpum.h>
28	#include <iprt/assert.h>
29	#include <iprt/string.h>
30	#include <iprt/stdarg.h>
31	#include "DisasmInternal.h"
32
33
34	/*********************************************************************************************************************************
35	* Global Variables *
36	*********************************************************************************************************************************/
37
38	/**
39	* Array for accessing 64-bit general registers in VMMREGFRAME structure
40	* by register's index from disasm.
41	*/
42	static const unsigned g_aReg64Index[] =
43	{
44	RT_OFFSETOF(CPUMCTXCORE, rax), /* DISGREG_RAX */
45	RT_OFFSETOF(CPUMCTXCORE, rcx), /* DISGREG_RCX */
46	RT_OFFSETOF(CPUMCTXCORE, rdx), /* DISGREG_RDX */
47	RT_OFFSETOF(CPUMCTXCORE, rbx), /* DISGREG_RBX */
48	RT_OFFSETOF(CPUMCTXCORE, rsp), /* DISGREG_RSP */
49	RT_OFFSETOF(CPUMCTXCORE, rbp), /* DISGREG_RBP */
50	RT_OFFSETOF(CPUMCTXCORE, rsi), /* DISGREG_RSI */
51	RT_OFFSETOF(CPUMCTXCORE, rdi), /* DISGREG_RDI */
52	RT_OFFSETOF(CPUMCTXCORE, r8), /* DISGREG_R8 */
53	RT_OFFSETOF(CPUMCTXCORE, r9), /* DISGREG_R9 */
54	RT_OFFSETOF(CPUMCTXCORE, r10), /* DISGREG_R10 */
55	RT_OFFSETOF(CPUMCTXCORE, r11), /* DISGREG_R11 */
56	RT_OFFSETOF(CPUMCTXCORE, r12), /* DISGREG_R12 */
57	RT_OFFSETOF(CPUMCTXCORE, r13), /* DISGREG_R13 */
58	RT_OFFSETOF(CPUMCTXCORE, r14), /* DISGREG_R14 */
59	RT_OFFSETOF(CPUMCTXCORE, r15) /* DISGREG_R15 */
60	};
61
62	/**
63	* Macro for accessing 64-bit general purpose registers in CPUMCTXCORE structure.
64	*/
65	#define DIS_READ_REG64(p, idx) ((uint64_t )((char *)(p) + g_aReg64Index[idx]))
66	#define DIS_WRITE_REG64(p, idx, val) ((uint64_t )((char *)(p) + g_aReg64Index[idx]) = val)
67	#define DIS_PTR_REG64(p, idx) ( (uint64_t )((char )(p) + g_aReg64Index[idx]))
68
69	/**
70	* Array for accessing 32-bit general registers in VMMREGFRAME structure
71	* by register's index from disasm.
72	*/
73	static const unsigned g_aReg32Index[] =
74	{
75	RT_OFFSETOF(CPUMCTXCORE, eax), /* DISGREG_EAX */
76	RT_OFFSETOF(CPUMCTXCORE, ecx), /* DISGREG_ECX */
77	RT_OFFSETOF(CPUMCTXCORE, edx), /* DISGREG_EDX */
78	RT_OFFSETOF(CPUMCTXCORE, ebx), /* DISGREG_EBX */
79	RT_OFFSETOF(CPUMCTXCORE, esp), /* DISGREG_ESP */
80	RT_OFFSETOF(CPUMCTXCORE, ebp), /* DISGREG_EBP */
81	RT_OFFSETOF(CPUMCTXCORE, esi), /* DISGREG_ESI */
82	RT_OFFSETOF(CPUMCTXCORE, edi), /* DISGREG_EDI */
83	RT_OFFSETOF(CPUMCTXCORE, r8), /* DISGREG_R8D */
84	RT_OFFSETOF(CPUMCTXCORE, r9), /* DISGREG_R9D */
85	RT_OFFSETOF(CPUMCTXCORE, r10), /* DISGREG_R1D */
86	RT_OFFSETOF(CPUMCTXCORE, r11), /* DISGREG_R11D */
87	RT_OFFSETOF(CPUMCTXCORE, r12), /* DISGREG_R12D */
88	RT_OFFSETOF(CPUMCTXCORE, r13), /* DISGREG_R13D */
89	RT_OFFSETOF(CPUMCTXCORE, r14), /* DISGREG_R14D */
90	RT_OFFSETOF(CPUMCTXCORE, r15) /* DISGREG_R15D */
91	};
92
93	/**
94	* Macro for accessing 32-bit general purpose registers in CPUMCTXCORE structure.
95	*/
96	#define DIS_READ_REG32(p, idx) ((uint32_t )((char *)(p) + g_aReg32Index[idx]))
97	/* From http://www.cs.cmu.edu/~fp/courses/15213-s06/misc/asm64-handout.pdf:
98	* ``Perhaps unexpectedly, instructions that move or generate 32-bit register
99	* values also set the upper 32 bits of the register to zero. Consequently
100	* there is no need for an instruction movzlq.''
101	*/
102	#define DIS_WRITE_REG32(p, idx, val) ((uint64_t )((char *)(p) + g_aReg32Index[idx]) = (uint32_t)val)
103	#define DIS_PTR_REG32(p, idx) ( (uint32_t )((char )(p) + g_aReg32Index[idx]))
104
105	/**
106	* Array for accessing 16-bit general registers in CPUMCTXCORE structure
107	* by register's index from disasm.
108	*/
109	static const unsigned g_aReg16Index[] =
110	{
111	RT_OFFSETOF(CPUMCTXCORE, eax), /* DISGREG_AX */
112	RT_OFFSETOF(CPUMCTXCORE, ecx), /* DISGREG_CX */
113	RT_OFFSETOF(CPUMCTXCORE, edx), /* DISGREG_DX */
114	RT_OFFSETOF(CPUMCTXCORE, ebx), /* DISGREG_BX */
115	RT_OFFSETOF(CPUMCTXCORE, esp), /* DISGREG_SP */
116	RT_OFFSETOF(CPUMCTXCORE, ebp), /* DISGREG_BP */
117	RT_OFFSETOF(CPUMCTXCORE, esi), /* DISGREG_SI */
118	RT_OFFSETOF(CPUMCTXCORE, edi), /* DISGREG_DI */
119	RT_OFFSETOF(CPUMCTXCORE, r8), /* DISGREG_R8W */
120	RT_OFFSETOF(CPUMCTXCORE, r9), /* DISGREG_R9W */
121	RT_OFFSETOF(CPUMCTXCORE, r10), /* DISGREG_R10W */
122	RT_OFFSETOF(CPUMCTXCORE, r11), /* DISGREG_R11W */
123	RT_OFFSETOF(CPUMCTXCORE, r12), /* DISGREG_R12W */
124	RT_OFFSETOF(CPUMCTXCORE, r13), /* DISGREG_R13W */
125	RT_OFFSETOF(CPUMCTXCORE, r14), /* DISGREG_R14W */
126	RT_OFFSETOF(CPUMCTXCORE, r15) /* DISGREG_R15W */
127	};
128
129	/**
130	* Macro for accessing 16-bit general purpose registers in CPUMCTXCORE structure.
131	*/
132	#define DIS_READ_REG16(p, idx) ((uint16_t )((char *)(p) + g_aReg16Index[idx]))
133	#define DIS_WRITE_REG16(p, idx, val) ((uint16_t )((char *)(p) + g_aReg16Index[idx]) = val)
134	#define DIS_PTR_REG16(p, idx) ( (uint16_t )((char )(p) + g_aReg16Index[idx]))
135
136	/**
137	* Array for accessing 8-bit general registers in CPUMCTXCORE structure
138	* by register's index from disasm.
139	*/
140	static const unsigned g_aReg8Index[] =
141	{
142	RT_OFFSETOF(CPUMCTXCORE, eax), /* DISGREG_AL */
143	RT_OFFSETOF(CPUMCTXCORE, ecx), /* DISGREG_CL */
144	RT_OFFSETOF(CPUMCTXCORE, edx), /* DISGREG_DL */
145	RT_OFFSETOF(CPUMCTXCORE, ebx), /* DISGREG_BL */
146	RT_OFFSETOF_ADD(CPUMCTXCORE, eax, 1), /* DISGREG_AH */
147	RT_OFFSETOF_ADD(CPUMCTXCORE, ecx, 1), /* DISGREG_CH */
148	RT_OFFSETOF_ADD(CPUMCTXCORE, edx, 1), /* DISGREG_DH */
149	RT_OFFSETOF_ADD(CPUMCTXCORE, ebx, 1), /* DISGREG_BH */
150	RT_OFFSETOF(CPUMCTXCORE, r8), /* DISGREG_R8B */
151	RT_OFFSETOF(CPUMCTXCORE, r9), /* DISGREG_R9B */
152	RT_OFFSETOF(CPUMCTXCORE, r10), /* DISGREG_R10B*/
153	RT_OFFSETOF(CPUMCTXCORE, r11), /* DISGREG_R11B */
154	RT_OFFSETOF(CPUMCTXCORE, r12), /* DISGREG_R12B */
155	RT_OFFSETOF(CPUMCTXCORE, r13), /* DISGREG_R13B */
156	RT_OFFSETOF(CPUMCTXCORE, r14), /* DISGREG_R14B */
157	RT_OFFSETOF(CPUMCTXCORE, r15), /* DISGREG_R15B */
158	RT_OFFSETOF(CPUMCTXCORE, esp), /* DISGREG_SPL; with REX prefix only */
159	RT_OFFSETOF(CPUMCTXCORE, ebp), /* DISGREG_BPL; with REX prefix only */
160	RT_OFFSETOF(CPUMCTXCORE, esi), /* DISGREG_SIL; with REX prefix only */
161	RT_OFFSETOF(CPUMCTXCORE, edi) /* DISGREG_DIL; with REX prefix only */
162	};
163
164	/**
165	* Macro for accessing 8-bit general purpose registers in CPUMCTXCORE structure.
166	*/
167	#define DIS_READ_REG8(p, idx) ((uint8_t )((char *)(p) + g_aReg8Index[idx]))
168	#define DIS_WRITE_REG8(p, idx, val) ((uint8_t )((char *)(p) + g_aReg8Index[idx]) = val)
169	#define DIS_PTR_REG8(p, idx) ( (uint8_t )((char )(p) + g_aReg8Index[idx]))
170
171	/**
172	* Array for accessing segment registers in CPUMCTXCORE structure
173	* by register's index from disasm.
174	*/
175	static const unsigned g_aRegSegIndex[] =
176	{
177	RT_OFFSETOF(CPUMCTXCORE, es), /* DISSELREG_ES */
178	RT_OFFSETOF(CPUMCTXCORE, cs), /* DISSELREG_CS */
179	RT_OFFSETOF(CPUMCTXCORE, ss), /* DISSELREG_SS */
180	RT_OFFSETOF(CPUMCTXCORE, ds), /* DISSELREG_DS */
181	RT_OFFSETOF(CPUMCTXCORE, fs), /* DISSELREG_FS */
182	RT_OFFSETOF(CPUMCTXCORE, gs) /* DISSELREG_GS */
183	};
184
185	static const unsigned g_aRegHidSegIndex[] =
186	{
187	RT_OFFSETOF(CPUMCTXCORE, es), /* DISSELREG_ES */
188	RT_OFFSETOF(CPUMCTXCORE, cs), /* DISSELREG_CS */
189	RT_OFFSETOF(CPUMCTXCORE, ss), /* DISSELREG_SS */
190	RT_OFFSETOF(CPUMCTXCORE, ds), /* DISSELREG_DS */
191	RT_OFFSETOF(CPUMCTXCORE, fs), /* DISSELREG_FS */
192	RT_OFFSETOF(CPUMCTXCORE, gs) /* DISSELREG_GS */
193	};
194
195	/**
196	* Macro for accessing segment registers in CPUMCTXCORE structure.
197	*/
198	#define DIS_READ_REGSEG(p, idx) (((uint16_t )((char *)(p) + g_aRegSegIndex[idx])))
199	#define DIS_WRITE_REGSEG(p, idx, val) (((uint16_t )((char *)(p) + g_aRegSegIndex[idx])) = val)
200
201	//*****************************************************************************
202	//*****************************************************************************
203	DISDECL(int) DISGetParamSize(PCDISSTATE pDis, PCDISOPPARAM pParam)
204	{
205	unsigned subtype = OP_PARM_VSUBTYPE(pParam->fParam);
206	switch (subtype)
207	{
208	case OP_PARM_v:
209	switch (pDis->uOpMode)
210	{
211	case DISCPUMODE_32BIT:
212	return 4;
213	case DISCPUMODE_64BIT:
214	return 8;
215	case DISCPUMODE_16BIT:
216	return 2;
217	default: AssertFailed(); /* make gcc happy */ return 4;
218	}
219	break;
220
221	case OP_PARM_b:
222	return 1;
223
224	case OP_PARM_w:
225	return 2;
226
227	case OP_PARM_d:
228	return 4;
229
230	case OP_PARM_q:
231	return 8;
232
233	case OP_PARM_dq:
234	return 16;
235
236	case OP_PARM_qq:
237	return 32;
238
239	case 0: /* nop, pause, lea, wrmsr, rdmsr, etc. Most of these due to DISOPPARAM::cb being initialized in the wrong place
240	(disParseInstruction) where it will be called on intermediate stuff like IDX_ParseTwoByteEsc. The parameter
241	parsers should do it instead, though I see the potential filtering issue. */
242	//Assert( pDis->pCurInstr
243	// && ( pDis->pCurInstr->uOpcode == OP_NOP
244	// \|\| pDis->pCurInstr->uOpcode == OP_LEA ));
245	return 0;
246
247	case OP_PARM_p: /* far pointer */
248	if (pDis->uAddrMode == DISCPUMODE_32BIT)
249	return 6; /* 16:32 */
250	if (pDis->uAddrMode == DISCPUMODE_64BIT)
251	return 12; /* 16:64 */
252	return 4; /* 16:16 */
253
254	case OP_PARM_s: /* lgdt, sgdt, lidt, sidt */
255	return pDis->uCpuMode == DISCPUMODE_64BIT ? 2 + 8 : 2 + 4;
256
257	case OP_PARM_a:
258	return pDis->uOpMode == DISCPUMODE_16BIT ? 2 + 2 : 4 + 4;
259
260	case OP_PARM_pi:
261	return 8;
262
263	case OP_PARM_sd:
264	case OP_PARM_ss:
265	return 16;
266
267	case OP_PARM_x:
268	case OP_PARM_pd:
269	case OP_PARM_ps:
270	return VEXREG_IS256B(pDis->bVexDestReg) ? 32 : 16; //??
271
272	case OP_PARM_y:
273	return pDis->uOpMode == DISCPUMODE_64BIT ? 4 : 8; //??
274
275	case OP_PARM_z:
276	if (pParam->cb)
277	return pParam->cb;
278	return pDis->uOpMode == DISCPUMODE_16BIT ? 2 : 4; //??
279
280	default:
281	if (pParam->cb)
282	return pParam->cb;
283	/// @todo dangerous!!!
284	AssertMsgFailed(("subtype=%#x fParam=%#x fUse=%#RX64 op=%#x\n", subtype, pParam->fParam, pParam->fUse,
285	pDis->pCurInstr ? pDis->pCurInstr->uOpcode : 0));
286	return 4;
287	}
288	}
289	//*****************************************************************************
290	//*****************************************************************************
291	DISDECL(DISSELREG) DISDetectSegReg(PCDISSTATE pDis, PCDISOPPARAM pParam)
292	{
293	if (pDis->fPrefix & DISPREFIX_SEG)
294	/* Use specified SEG: prefix. */
295	return (DISSELREG)pDis->idxSegPrefix;
296
297	/* Guess segment register by parameter type. */
298	if (pParam->fUse & (DISUSE_REG_GEN32\|DISUSE_REG_GEN64\|DISUSE_REG_GEN16))
299	{
300	AssertCompile(DISGREG_ESP == DISGREG_RSP);
301	AssertCompile(DISGREG_EBP == DISGREG_RBP);
302	AssertCompile(DISGREG_ESP == DISGREG_SP);
303	AssertCompile(DISGREG_EBP == DISGREG_BP);
304	if (pParam->Base.idxGenReg == DISGREG_ESP \|\| pParam->Base.idxGenReg == DISGREG_EBP)
305	return DISSELREG_SS;
306	}
307	/* Default is use DS: for data access. */
308	return DISSELREG_DS;
309	}
310	//*****************************************************************************
311	//*****************************************************************************
312	DISDECL(uint8_t) DISQuerySegPrefixByte(PCDISSTATE pDis)
313	{
314	Assert(pDis->fPrefix & DISPREFIX_SEG);
315	switch (pDis->idxSegPrefix)
316	{
317	case DISSELREG_ES:
318	return 0x26;
319	case DISSELREG_CS:
320	return 0x2E;
321	case DISSELREG_SS:
322	return 0x36;
323	case DISSELREG_DS:
324	return 0x3E;
325	case DISSELREG_FS:
326	return 0x64;
327	case DISSELREG_GS:
328	return 0x65;
329	default:
330	AssertFailed();
331	return 0;
332	}
333	}
334
335
336	/**
337	* Returns the value of the specified 8 bits general purpose register
338	*
339	*/
340	DISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal)
341	{
342	AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
343
344	*pVal = DIS_READ_REG8(pCtx, reg8);
345	return VINF_SUCCESS;
346	}
347
348	/**
349	* Returns the value of the specified 16 bits general purpose register
350	*
351	*/
352	DISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal)
353	{
354	AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
355
356	*pVal = DIS_READ_REG16(pCtx, reg16);
357	return VINF_SUCCESS;
358	}
359
360	/**
361	* Returns the value of the specified 32 bits general purpose register
362	*
363	*/
364	DISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal)
365	{
366	AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
367
368	*pVal = DIS_READ_REG32(pCtx, reg32);
369	return VINF_SUCCESS;
370	}
371
372	/**
373	* Returns the value of the specified 64 bits general purpose register
374	*
375	*/
376	DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal)
377	{
378	AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
379
380	*pVal = DIS_READ_REG64(pCtx, reg64);
381	return VINF_SUCCESS;
382	}
383
384	/**
385	* Returns the pointer to the specified 8 bits general purpose register
386	*
387	*/
388	DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg)
389	{
390	AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
391
392	*ppReg = DIS_PTR_REG8(pCtx, reg8);
393	return VINF_SUCCESS;
394	}
395
396	/**
397	* Returns the pointer to the specified 16 bits general purpose register
398	*
399	*/
400	DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg)
401	{
402	AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
403
404	*ppReg = DIS_PTR_REG16(pCtx, reg16);
405	return VINF_SUCCESS;
406	}
407
408	/**
409	* Returns the pointer to the specified 32 bits general purpose register
410	*
411	*/
412	DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg)
413	{
414	AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
415
416	*ppReg = DIS_PTR_REG32(pCtx, reg32);
417	return VINF_SUCCESS;
418	}
419
420	/**
421	* Returns the pointer to the specified 64 bits general purpose register
422	*
423	*/
424	DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg)
425	{
426	AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
427
428	*ppReg = DIS_PTR_REG64(pCtx, reg64);
429	return VINF_SUCCESS;
430	}
431
432	/**
433	* Returns the value of the specified segment register
434	*
435	*/
436	DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal)
437	{
438	AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
439
440	AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
441	*pVal = DIS_READ_REGSEG(pCtx, sel);
442	return VINF_SUCCESS;
443	}
444
445	/**
446	* Returns the value of the specified segment register including a pointer to the hidden register in the supplied cpu context
447	*
448	*/
449	DISDECL(int) DISFetchRegSegEx(PCPUMCTXCORE pCtx, DISSELREG sel, PCPUMSELREG *ppSelReg)
450	{
451	AssertReturnStmt((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), *ppSelReg = NULL, VERR_INVALID_PARAMETER);
452	ppSelReg = (CPUMSELREG )((uintptr_t)pCtx + g_aRegHidSegIndex[sel]);
453	return VINF_SUCCESS;
454	}
455
456	/**
457	* Updates the value of the specified 64 bits general purpose register
458	*
459	*/
460	DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64)
461	{
462	AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
463
464	DIS_WRITE_REG64(pRegFrame, reg64, val64);
465	return VINF_SUCCESS;
466	}
467
468	/**
469	* Updates the value of the specified 32 bits general purpose register
470	*
471	*/
472	DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32)
473	{
474	AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
475
476	DIS_WRITE_REG32(pRegFrame, reg32, val32);
477	return VINF_SUCCESS;
478	}
479
480	/**
481	* Updates the value of the specified 16 bits general purpose register
482	*
483	*/
484	DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg16, uint16_t val16)
485	{
486	AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
487
488	DIS_WRITE_REG16(pRegFrame, reg16, val16);
489	return VINF_SUCCESS;
490	}
491
492	/**
493	* Updates the specified 8 bits general purpose register
494	*
495	*/
496	DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8)
497	{
498	AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
499
500	DIS_WRITE_REG8(pRegFrame, reg8, val8);
501	return VINF_SUCCESS;
502	}
503
504	/**
505	* Updates the specified segment register
506	*
507	*/
508	DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DISSELREG sel, RTSEL val)
509	{
510	AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
511
512	AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
513	DIS_WRITE_REGSEG(pCtx, sel, val);
514	return VINF_SUCCESS;
515	}
516
517	/**
518	* Returns the value of the parameter in pParam
519	*
520	* @returns VBox error code
521	* @param pCtx CPU context structure pointer
522	* @param pDis Pointer to the disassembler state.
523	* @param pParam Pointer to the parameter to parse
524	* @param pParamVal Pointer to parameter value (OUT)
525	* @param parmtype Parameter type
526	*
527	* @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
528	*
529	*/
530	DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PCDISSTATE pDis, PCDISOPPARAM pParam, PDISQPVPARAMVAL pParamVal, DISQPVWHICH parmtype)
531	{
532	memset(pParamVal, 0, sizeof(*pParamVal));
533
534	if (DISUSE_IS_EFFECTIVE_ADDR(pParam->fUse))
535	{
536	// Effective address
537	pParamVal->type = DISQPV_TYPE_ADDRESS;
538	pParamVal->size = pParam->cb;
539
540	if (pParam->fUse & DISUSE_BASE)
541	{
542	if (pParam->fUse & DISUSE_REG_GEN8)
543	{
544	pParamVal->flags \|= DISQPV_FLAG_8;
545	if (RT_FAILURE(DISFetchReg8(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
546	}
547	else
548	if (pParam->fUse & DISUSE_REG_GEN16)
549	{
550	pParamVal->flags \|= DISQPV_FLAG_16;
551	if (RT_FAILURE(DISFetchReg16(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
552	}
553	else
554	if (pParam->fUse & DISUSE_REG_GEN32)
555	{
556	pParamVal->flags \|= DISQPV_FLAG_32;
557	if (RT_FAILURE(DISFetchReg32(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
558	}
559	else
560	if (pParam->fUse & DISUSE_REG_GEN64)
561	{
562	pParamVal->flags \|= DISQPV_FLAG_64;
563	if (RT_FAILURE(DISFetchReg64(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
564	}
565	else
566	{
567	AssertFailed();
568	return VERR_INVALID_PARAMETER;
569	}
570	}
571	// Note that scale implies index (SIB byte)
572	if (pParam->fUse & DISUSE_INDEX)
573	{
574	if (pParam->fUse & DISUSE_REG_GEN16)
575	{
576	uint16_t val16;
577
578	pParamVal->flags \|= DISQPV_FLAG_16;
579	if (RT_FAILURE(DISFetchReg16(pCtx, pParam->Index.idxGenReg, &val16))) return VERR_INVALID_PARAMETER;
580
581	Assert(!(pParam->fUse & DISUSE_SCALE)); /* shouldn't be possible in 16 bits mode */
582
583	pParamVal->val.val16 += val16;
584	}
585	else
586	if (pParam->fUse & DISUSE_REG_GEN32)
587	{
588	uint32_t val32;
589
590	pParamVal->flags \|= DISQPV_FLAG_32;
591	if (RT_FAILURE(DISFetchReg32(pCtx, pParam->Index.idxGenReg, &val32))) return VERR_INVALID_PARAMETER;
592
593	if (pParam->fUse & DISUSE_SCALE)
594	val32 *= pParam->uScale;
595
596	pParamVal->val.val32 += val32;
597	}
598	else
599	if (pParam->fUse & DISUSE_REG_GEN64)
600	{
601	uint64_t val64;
602
603	pParamVal->flags \|= DISQPV_FLAG_64;
604	if (RT_FAILURE(DISFetchReg64(pCtx, pParam->Index.idxGenReg, &val64))) return VERR_INVALID_PARAMETER;
605
606	if (pParam->fUse & DISUSE_SCALE)
607	val64 *= pParam->uScale;
608
609	pParamVal->val.val64 += val64;
610	}
611	else
612	AssertFailed();
613	}
614
615	if (pParam->fUse & DISUSE_DISPLACEMENT8)
616	{
617	if (pDis->uCpuMode == DISCPUMODE_32BIT)
618	pParamVal->val.val32 += (int32_t)pParam->uDisp.i8;
619	else
620	if (pDis->uCpuMode == DISCPUMODE_64BIT)
621	pParamVal->val.val64 += (int64_t)pParam->uDisp.i8;
622	else
623	pParamVal->val.val16 += (int16_t)pParam->uDisp.i8;
624	}
625	else
626	if (pParam->fUse & DISUSE_DISPLACEMENT16)
627	{
628	if (pDis->uCpuMode == DISCPUMODE_32BIT)
629	pParamVal->val.val32 += (int32_t)pParam->uDisp.i16;
630	else
631	if (pDis->uCpuMode == DISCPUMODE_64BIT)
632	pParamVal->val.val64 += (int64_t)pParam->uDisp.i16;
633	else
634	pParamVal->val.val16 += pParam->uDisp.i16;
635	}
636	else
637	if (pParam->fUse & DISUSE_DISPLACEMENT32)
638	{
639	if (pDis->uCpuMode == DISCPUMODE_32BIT)
640	pParamVal->val.val32 += pParam->uDisp.i32;
641	else
642	pParamVal->val.val64 += pParam->uDisp.i32;
643	}
644	else
645	if (pParam->fUse & DISUSE_DISPLACEMENT64)
646	{
647	Assert(pDis->uCpuMode == DISCPUMODE_64BIT);
648	pParamVal->val.val64 += pParam->uDisp.i64;
649	}
650	else
651	if (pParam->fUse & DISUSE_RIPDISPLACEMENT32)
652	{
653	Assert(pDis->uCpuMode == DISCPUMODE_64BIT);
654	/* Relative to the RIP of the next instruction. */
655	pParamVal->val.val64 += pParam->uDisp.i32 + pCtx->rip + pDis->cbInstr;
656	}
657	return VINF_SUCCESS;
658	}
659
660	if (pParam->fUse & (DISUSE_REG_GEN8\|DISUSE_REG_GEN16\|DISUSE_REG_GEN32\|DISUSE_REG_GEN64\|DISUSE_REG_FP\|DISUSE_REG_MMX\|DISUSE_REG_XMM\|DISUSE_REG_CR\|DISUSE_REG_DBG\|DISUSE_REG_SEG\|DISUSE_REG_TEST))
661	{
662	if (parmtype == DISQPVWHICH_DST)
663	{
664	// Caller needs to interpret the register according to the instruction (source/target, special value etc)
665	pParamVal->type = DISQPV_TYPE_REGISTER;
666	pParamVal->size = pParam->cb;
667	return VINF_SUCCESS;
668	}
669	//else DISQPVWHICH_SRC
670
671	pParamVal->type = DISQPV_TYPE_IMMEDIATE;
672
673	if (pParam->fUse & DISUSE_REG_GEN8)
674	{
675	pParamVal->flags \|= DISQPV_FLAG_8;
676	pParamVal->size = sizeof(uint8_t);
677	if (RT_FAILURE(DISFetchReg8(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
678	}
679	else
680	if (pParam->fUse & DISUSE_REG_GEN16)
681	{
682	pParamVal->flags \|= DISQPV_FLAG_16;
683	pParamVal->size = sizeof(uint16_t);
684	if (RT_FAILURE(DISFetchReg16(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
685	}
686	else
687	if (pParam->fUse & DISUSE_REG_GEN32)
688	{
689	pParamVal->flags \|= DISQPV_FLAG_32;
690	pParamVal->size = sizeof(uint32_t);
691	if (RT_FAILURE(DISFetchReg32(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
692	}
693	else
694	if (pParam->fUse & DISUSE_REG_GEN64)
695	{
696	pParamVal->flags \|= DISQPV_FLAG_64;
697	pParamVal->size = sizeof(uint64_t);
698	if (RT_FAILURE(DISFetchReg64(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
699	}
700	else
701	{
702	// Caller needs to interpret the register according to the instruction (source/target, special value etc)
703	pParamVal->type = DISQPV_TYPE_REGISTER;
704	}
705	Assert(!(pParam->fUse & DISUSE_IMMEDIATE));
706	return VINF_SUCCESS;
707	}
708
709	if (pParam->fUse & DISUSE_IMMEDIATE)
710	{
711	pParamVal->type = DISQPV_TYPE_IMMEDIATE;
712	if (pParam->fUse & (DISUSE_IMMEDIATE8\|DISUSE_IMMEDIATE8_REL))
713	{
714	pParamVal->flags \|= DISQPV_FLAG_8;
715	if (pParam->cb == 2)
716	{
717	pParamVal->size = sizeof(uint16_t);
718	pParamVal->val.val16 = (uint8_t)pParam->uValue;
719	}
720	else
721	{
722	pParamVal->size = sizeof(uint8_t);
723	pParamVal->val.val8 = (uint8_t)pParam->uValue;
724	}
725	}
726	else
727	if (pParam->fUse & (DISUSE_IMMEDIATE16\|DISUSE_IMMEDIATE16_REL\|DISUSE_IMMEDIATE_ADDR_0_16\|DISUSE_IMMEDIATE16_SX8))
728	{
729	pParamVal->flags \|= DISQPV_FLAG_16;
730	pParamVal->size = sizeof(uint16_t);
731	pParamVal->val.val16 = (uint16_t)pParam->uValue;
732	AssertMsg(pParamVal->size == pParam->cb \|\| ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE16_SX8)), ("pParamVal->size %d vs %d EIP=%RX32\n", pParamVal->size, pParam->cb, pCtx->eip) );
733	}
734	else
735	if (pParam->fUse & (DISUSE_IMMEDIATE32\|DISUSE_IMMEDIATE32_REL\|DISUSE_IMMEDIATE_ADDR_0_32\|DISUSE_IMMEDIATE32_SX8))
736	{
737	pParamVal->flags \|= DISQPV_FLAG_32;
738	pParamVal->size = sizeof(uint32_t);
739	pParamVal->val.val32 = (uint32_t)pParam->uValue;
740	Assert(pParamVal->size == pParam->cb \|\| ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE32_SX8)) );
741	}
742	else
743	if (pParam->fUse & (DISUSE_IMMEDIATE64 \| DISUSE_IMMEDIATE64_REL \| DISUSE_IMMEDIATE64_SX8))
744	{
745	pParamVal->flags \|= DISQPV_FLAG_64;
746	pParamVal->size = sizeof(uint64_t);
747	pParamVal->val.val64 = pParam->uValue;
748	Assert(pParamVal->size == pParam->cb \|\| ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE64_SX8)) );
749	}
750	else
751	if (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16))
752	{
753	pParamVal->flags \|= DISQPV_FLAG_FARPTR16;
754	pParamVal->size = sizeof(uint16_t)*2;
755	pParamVal->val.farptr.sel = (uint16_t)RT_LOWORD(pParam->uValue >> 16);
756	pParamVal->val.farptr.offset = (uint32_t)RT_LOWORD(pParam->uValue);
757	Assert(pParamVal->size == pParam->cb);
758	}
759	else
760	if (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_32))
761	{
762	pParamVal->flags \|= DISQPV_FLAG_FARPTR32;
763	pParamVal->size = sizeof(uint16_t) + sizeof(uint32_t);
764	pParamVal->val.farptr.sel = (uint16_t)RT_LOWORD(pParam->uValue >> 32);
765	pParamVal->val.farptr.offset = (uint32_t)(pParam->uValue & 0xFFFFFFFF);
766	Assert(pParam->cb == 8);
767	}
768	}
769	return VINF_SUCCESS;
770	}
771
772	/**
773	* Returns the pointer to a register of the parameter in pParam. We need this
774	* pointer when an interpreted instruction updates a register as a side effect.
775	* In CMPXCHG we know that only [r/e]ax is updated, but with XADD this could
776	* be every register.
777	*
778	* @returns VBox error code
779	* @param pCtx CPU context structure pointer
780	* @param pDis Pointer to the disassembler state.
781	* @param pParam Pointer to the parameter to parse
782	* @param pReg Pointer to parameter value (OUT)
783	* @param cbsize Parameter size (OUT)
784	*
785	* @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
786	*
787	*/
788	DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PCDISSTATE pDis, PCDISOPPARAM pParam, void *ppReg, size_t pcbSize)
789	{
790	NOREF(pDis);
791	if (pParam->fUse & (DISUSE_REG_GEN8\|DISUSE_REG_GEN16\|DISUSE_REG_GEN32\|DISUSE_REG_FP\|DISUSE_REG_MMX\|DISUSE_REG_XMM\|DISUSE_REG_CR\|DISUSE_REG_DBG\|DISUSE_REG_SEG\|DISUSE_REG_TEST))
792	{
793	if (pParam->fUse & DISUSE_REG_GEN8)
794	{
795	uint8_t *pu8Reg;
796	if (RT_SUCCESS(DISPtrReg8(pCtx, pParam->Base.idxGenReg, &pu8Reg)))
797	{
798	*pcbSize = sizeof(uint8_t);
799	ppReg = (void )pu8Reg;
800	return VINF_SUCCESS;
801	}
802	}
803	else
804	if (pParam->fUse & DISUSE_REG_GEN16)
805	{
806	uint16_t *pu16Reg;
807	if (RT_SUCCESS(DISPtrReg16(pCtx, pParam->Base.idxGenReg, &pu16Reg)))
808	{
809	*pcbSize = sizeof(uint16_t);
810	ppReg = (void )pu16Reg;
811	return VINF_SUCCESS;
812	}
813	}
814	else
815	if (pParam->fUse & DISUSE_REG_GEN32)
816	{
817	uint32_t *pu32Reg;
818	if (RT_SUCCESS(DISPtrReg32(pCtx, pParam->Base.idxGenReg, &pu32Reg)))
819	{
820	*pcbSize = sizeof(uint32_t);
821	ppReg = (void )pu32Reg;
822	return VINF_SUCCESS;
823	}
824	}
825	else
826	if (pParam->fUse & DISUSE_REG_GEN64)
827	{
828	uint64_t *pu64Reg;
829	if (RT_SUCCESS(DISPtrReg64(pCtx, pParam->Base.idxGenReg, &pu64Reg)))
830	{
831	*pcbSize = sizeof(uint64_t);
832	ppReg = (void )pu64Reg;
833	return VINF_SUCCESS;
834	}
835	}
836	}
837	return VERR_INVALID_PARAMETER;
838	}
839

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source: vbox/trunk/src/VBox/Disassembler/DisasmReg.cpp@ 69288

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