VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmReg.cpp@ 17610

Last change on this file since 17610 was 16433, checked in by vboxsync, 16 years ago

DisasmReg.cpp: Use RT_OFFSETOF_ADD instead of RT_OFFSETOF() + 1, g++ 4.2.1 on darwin/amd64 generates static initialization code otherwise.
  • Property svn:eol-style set to native
  • Property svn:sync_process set to export
File size: 29.0 KB
Line 
1/** @file
2 *
3 * VBox disassembler:
4 * Core components
5 */
6
7/*
8 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
19 * Clara, CA 95054 USA or visit http://www.sun.com if you need
20 * additional information or have any questions.
21 */
22
23
24/*******************************************************************************
25* Header Files *
26*******************************************************************************/
27#define LOG_GROUP LOG_GROUP_DIS
28#ifdef USING_VISUAL_STUDIO
29# include <stdafx.h>
30#endif
31
32#include <VBox/dis.h>
33#include <VBox/disopcode.h>
34#include <VBox/cpum.h>
35#include <VBox/err.h>
36#include <VBox/log.h>
37#include <iprt/assert.h>
38#include <iprt/string.h>
39#include <iprt/stdarg.h>
40#include "DisasmInternal.h"
41#include "DisasmTables.h"
42
43#if !defined(DIS_CORE_ONLY) && defined(LOG_ENABLED)
44# include <stdlib.h>
45# include <stdio.h>
46#endif
47
48
49/*******************************************************************************
50* Global Variables *
51*******************************************************************************/
52
53/**
54 * Array for accessing 64-bit general registers in VMMREGFRAME structure
55 * by register's index from disasm.
56 */
57static const unsigned g_aReg64Index[] =
58{
59 RT_OFFSETOF(CPUMCTXCORE, rax), /* USE_REG_RAX */
60 RT_OFFSETOF(CPUMCTXCORE, rcx), /* USE_REG_RCX */
61 RT_OFFSETOF(CPUMCTXCORE, rdx), /* USE_REG_RDX */
62 RT_OFFSETOF(CPUMCTXCORE, rbx), /* USE_REG_RBX */
63 RT_OFFSETOF(CPUMCTXCORE, rsp), /* USE_REG_RSP */
64 RT_OFFSETOF(CPUMCTXCORE, rbp), /* USE_REG_RBP */
65 RT_OFFSETOF(CPUMCTXCORE, rsi), /* USE_REG_RSI */
66 RT_OFFSETOF(CPUMCTXCORE, rdi), /* USE_REG_RDI */
67 RT_OFFSETOF(CPUMCTXCORE, r8), /* USE_REG_R8 */
68 RT_OFFSETOF(CPUMCTXCORE, r9), /* USE_REG_R9 */
69 RT_OFFSETOF(CPUMCTXCORE, r10), /* USE_REG_R10 */
70 RT_OFFSETOF(CPUMCTXCORE, r11), /* USE_REG_R11 */
71 RT_OFFSETOF(CPUMCTXCORE, r12), /* USE_REG_R12 */
72 RT_OFFSETOF(CPUMCTXCORE, r13), /* USE_REG_R13 */
73 RT_OFFSETOF(CPUMCTXCORE, r14), /* USE_REG_R14 */
74 RT_OFFSETOF(CPUMCTXCORE, r15) /* USE_REG_R15 */
75};
76
77/**
78 * Macro for accessing 64-bit general purpose registers in CPUMCTXCORE structure.
79 */
80#define DIS_READ_REG64(p, idx) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]))
81#define DIS_WRITE_REG64(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]) = val)
82#define DIS_PTR_REG64(p, idx) ( (uint64_t *)((char *)(p) + g_aReg64Index[idx]))
83
84/**
85 * Array for accessing 32-bit general registers in VMMREGFRAME structure
86 * by register's index from disasm.
87 */
88static const unsigned g_aReg32Index[] =
89{
90 RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_EAX */
91 RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_ECX */
92 RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_EDX */
93 RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_EBX */
94 RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_ESP */
95 RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_EBP */
96 RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_ESI */
97 RT_OFFSETOF(CPUMCTXCORE, edi), /* USE_REG_EDI */
98 RT_OFFSETOF(CPUMCTXCORE, r8), /* USE_REG_R8D */
99 RT_OFFSETOF(CPUMCTXCORE, r9), /* USE_REG_R9D */
100 RT_OFFSETOF(CPUMCTXCORE, r10), /* USE_REG_R10D */
101 RT_OFFSETOF(CPUMCTXCORE, r11), /* USE_REG_R11D */
102 RT_OFFSETOF(CPUMCTXCORE, r12), /* USE_REG_R12D */
103 RT_OFFSETOF(CPUMCTXCORE, r13), /* USE_REG_R13D */
104 RT_OFFSETOF(CPUMCTXCORE, r14), /* USE_REG_R14D */
105 RT_OFFSETOF(CPUMCTXCORE, r15) /* USE_REG_R15D */
106};
107
108/**
109 * Macro for accessing 32-bit general purpose registers in CPUMCTXCORE structure.
110 */
111#define DIS_READ_REG32(p, idx) (*(uint32_t *)((char *)(p) + g_aReg32Index[idx]))
112/* From http://www.cs.cmu.edu/~fp/courses/15213-s06/misc/asm64-handout.pdf:
113 * ``Perhaps unexpectedly, instructions that move or generate 32-bit register
114 * values also set the upper 32 bits of the register to zero. Consequently
115 * there is no need for an instruction movzlq.''
116 */
117#define DIS_WRITE_REG32(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg32Index[idx]) = (uint32_t)val)
118#define DIS_PTR_REG32(p, idx) ( (uint32_t *)((char *)(p) + g_aReg32Index[idx]))
119
120/**
121 * Array for accessing 16-bit general registers in CPUMCTXCORE structure
122 * by register's index from disasm.
123 */
124static const unsigned g_aReg16Index[] =
125{
126 RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_AX */
127 RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_CX */
128 RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_DX */
129 RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_BX */
130 RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_SP */
131 RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_BP */
132 RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_SI */
133 RT_OFFSETOF(CPUMCTXCORE, edi), /* USE_REG_DI */
134 RT_OFFSETOF(CPUMCTXCORE, r8), /* USE_REG_R8W */
135 RT_OFFSETOF(CPUMCTXCORE, r9), /* USE_REG_R9W */
136 RT_OFFSETOF(CPUMCTXCORE, r10), /* USE_REG_R10W */
137 RT_OFFSETOF(CPUMCTXCORE, r11), /* USE_REG_R11W */
138 RT_OFFSETOF(CPUMCTXCORE, r12), /* USE_REG_R12W */
139 RT_OFFSETOF(CPUMCTXCORE, r13), /* USE_REG_R13W */
140 RT_OFFSETOF(CPUMCTXCORE, r14), /* USE_REG_R14W */
141 RT_OFFSETOF(CPUMCTXCORE, r15) /* USE_REG_R15W */
142};
143
144/**
145 * Macro for accessing 16-bit general purpose registers in CPUMCTXCORE structure.
146 */
147#define DIS_READ_REG16(p, idx) (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]))
148#define DIS_WRITE_REG16(p, idx, val) (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]) = val)
149#define DIS_PTR_REG16(p, idx) ( (uint16_t *)((char *)(p) + g_aReg16Index[idx]))
150
151/**
152 * Array for accessing 8-bit general registers in CPUMCTXCORE structure
153 * by register's index from disasm.
154 */
155static const unsigned g_aReg8Index[] =
156{
157 RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_AL */
158 RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_CL */
159 RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_DL */
160 RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_BL */
161 RT_OFFSETOF_ADD(CPUMCTXCORE, eax, 1), /* USE_REG_AH */
162 RT_OFFSETOF_ADD(CPUMCTXCORE, ecx, 1), /* USE_REG_CH */
163 RT_OFFSETOF_ADD(CPUMCTXCORE, edx, 1), /* USE_REG_DH */
164 RT_OFFSETOF_ADD(CPUMCTXCORE, ebx, 1), /* USE_REG_BH */
165 RT_OFFSETOF(CPUMCTXCORE, r8), /* USE_REG_R8B */
166 RT_OFFSETOF(CPUMCTXCORE, r9), /* USE_REG_R9B */
167 RT_OFFSETOF(CPUMCTXCORE, r10), /* USE_REG_R10B*/
168 RT_OFFSETOF(CPUMCTXCORE, r11), /* USE_REG_R11B */
169 RT_OFFSETOF(CPUMCTXCORE, r12), /* USE_REG_R12B */
170 RT_OFFSETOF(CPUMCTXCORE, r13), /* USE_REG_R13B */
171 RT_OFFSETOF(CPUMCTXCORE, r14), /* USE_REG_R14B */
172 RT_OFFSETOF(CPUMCTXCORE, r15), /* USE_REG_R15B */
173 RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_SPL; with REX prefix only */
174 RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_BPL; with REX prefix only */
175 RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_SIL; with REX prefix only */
176 RT_OFFSETOF(CPUMCTXCORE, edi) /* USE_REG_DIL; with REX prefix only */
177};
178
179/**
180 * Macro for accessing 8-bit general purpose registers in CPUMCTXCORE structure.
181 */
182#define DIS_READ_REG8(p, idx) (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]))
183#define DIS_WRITE_REG8(p, idx, val) (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]) = val)
184#define DIS_PTR_REG8(p, idx) ( (uint8_t *)((char *)(p) + g_aReg8Index[idx]))
185
186/**
187 * Array for accessing segment registers in CPUMCTXCORE structure
188 * by register's index from disasm.
189 */
190static const unsigned g_aRegSegIndex[] =
191{
192 RT_OFFSETOF(CPUMCTXCORE, es), /* DIS_SELREG_ES */
193 RT_OFFSETOF(CPUMCTXCORE, cs), /* DIS_SELREG_CS */
194 RT_OFFSETOF(CPUMCTXCORE, ss), /* DIS_SELREG_SS */
195 RT_OFFSETOF(CPUMCTXCORE, ds), /* DIS_SELREG_DS */
196 RT_OFFSETOF(CPUMCTXCORE, fs), /* DIS_SELREG_FS */
197 RT_OFFSETOF(CPUMCTXCORE, gs) /* DIS_SELREG_GS */
198};
199
200static const unsigned g_aRegHidSegIndex[] =
201{
202 RT_OFFSETOF(CPUMCTXCORE, esHid), /* DIS_SELREG_ES */
203 RT_OFFSETOF(CPUMCTXCORE, csHid), /* DIS_SELREG_CS */
204 RT_OFFSETOF(CPUMCTXCORE, ssHid), /* DIS_SELREG_SS */
205 RT_OFFSETOF(CPUMCTXCORE, dsHid), /* DIS_SELREG_DS */
206 RT_OFFSETOF(CPUMCTXCORE, fsHid), /* DIS_SELREG_FS */
207 RT_OFFSETOF(CPUMCTXCORE, gsHid) /* DIS_SELREG_GS */
208};
209
210/**
211 * Macro for accessing segment registers in CPUMCTXCORE structure.
212 */
213#define DIS_READ_REGSEG(p, idx) (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])))
214#define DIS_WRITE_REGSEG(p, idx, val) (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])) = val)
215
216//*****************************************************************************
217//*****************************************************************************
218DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, POP_PARAMETER pParam)
219{
220 int subtype = OP_PARM_VSUBTYPE(pParam->param);
221
222 if (subtype == OP_PARM_v)
223 {
224 switch(pCpu->opmode)
225 {
226 case CPUMODE_32BIT:
227 subtype = OP_PARM_d;
228 break;
229 case CPUMODE_64BIT:
230 subtype = OP_PARM_q;
231 break;
232 case CPUMODE_16BIT:
233 subtype = OP_PARM_w;
234 break;
235 default:
236 /* make gcc happy */
237 break;
238 }
239 }
240
241 switch(subtype)
242 {
243 case OP_PARM_b:
244 return 1;
245
246 case OP_PARM_w:
247 return 2;
248
249 case OP_PARM_d:
250 return 4;
251
252 case OP_PARM_q:
253 case OP_PARM_dq:
254 return 8;
255
256 case OP_PARM_p: /* far pointer */
257 if (pCpu->addrmode == CPUMODE_32BIT)
258 return 6; /* 16:32 */
259 else
260 if (pCpu->addrmode == CPUMODE_64BIT)
261 return 12; /* 16:64 */
262 else
263 return 4; /* 16:16 */
264
265 default:
266 if (pParam->size)
267 return pParam->size;
268 else //@todo dangerous!!!
269 return 4;
270 }
271}
272//*****************************************************************************
273//*****************************************************************************
274DISDECL(DIS_SELREG) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam)
275{
276 if (pCpu->prefix & PREFIX_SEG)
277 {
278 /* Use specified SEG: prefix. */
279 return pCpu->enmPrefixSeg;
280 }
281 else
282 {
283 /* Guess segment register by parameter type. */
284 if (pParam->flags & (USE_REG_GEN32|USE_REG_GEN64|USE_REG_GEN16))
285 {
286 AssertCompile(USE_REG_ESP == USE_REG_RSP);
287 AssertCompile(USE_REG_EBP == USE_REG_RBP);
288 AssertCompile(USE_REG_ESP == USE_REG_SP);
289 AssertCompile(USE_REG_EBP == USE_REG_BP);
290 if (pParam->base.reg_gen == USE_REG_ESP || pParam->base.reg_gen == USE_REG_EBP)
291 return DIS_SELREG_SS;
292 }
293 /* Default is use DS: for data access. */
294 return DIS_SELREG_DS;
295 }
296}
297//*****************************************************************************
298//*****************************************************************************
299DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu)
300{
301 Assert(pCpu->prefix & PREFIX_SEG);
302 switch(pCpu->enmPrefixSeg)
303 {
304 case DIS_SELREG_ES:
305 return 0x26;
306 case DIS_SELREG_CS:
307 return 0x2E;
308 case DIS_SELREG_SS:
309 return 0x36;
310 case DIS_SELREG_DS:
311 return 0x3E;
312 case DIS_SELREG_FS:
313 return 0x64;
314 case DIS_SELREG_GS:
315 return 0x65;
316 default:
317 AssertFailed();
318 return 0;
319 }
320}
321
322
323/**
324 * Returns the value of the specified 8 bits general purpose register
325 *
326 */
327DISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal)
328{
329 AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
330
331 *pVal = DIS_READ_REG8(pCtx, reg8);
332 return VINF_SUCCESS;
333}
334
335/**
336 * Returns the value of the specified 16 bits general purpose register
337 *
338 */
339DISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal)
340{
341 AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
342
343 *pVal = DIS_READ_REG16(pCtx, reg16);
344 return VINF_SUCCESS;
345}
346
347/**
348 * Returns the value of the specified 32 bits general purpose register
349 *
350 */
351DISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal)
352{
353 AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
354
355 *pVal = DIS_READ_REG32(pCtx, reg32);
356 return VINF_SUCCESS;
357}
358
359/**
360 * Returns the value of the specified 64 bits general purpose register
361 *
362 */
363DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal)
364{
365 AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
366
367 *pVal = DIS_READ_REG64(pCtx, reg64);
368 return VINF_SUCCESS;
369}
370
371/**
372 * Returns the pointer to the specified 8 bits general purpose register
373 *
374 */
375DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg)
376{
377 AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
378
379 *ppReg = DIS_PTR_REG8(pCtx, reg8);
380 return VINF_SUCCESS;
381}
382
383/**
384 * Returns the pointer to the specified 16 bits general purpose register
385 *
386 */
387DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg)
388{
389 AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
390
391 *ppReg = DIS_PTR_REG16(pCtx, reg16);
392 return VINF_SUCCESS;
393}
394
395/**
396 * Returns the pointer to the specified 32 bits general purpose register
397 *
398 */
399DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg)
400{
401 AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
402
403 *ppReg = DIS_PTR_REG32(pCtx, reg32);
404 return VINF_SUCCESS;
405}
406
407/**
408 * Returns the pointer to the specified 64 bits general purpose register
409 *
410 */
411DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg)
412{
413 AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
414
415 *ppReg = DIS_PTR_REG64(pCtx, reg64);
416 return VINF_SUCCESS;
417}
418
419/**
420 * Returns the value of the specified segment register
421 *
422 */
423DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal)
424{
425 AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
426
427 AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
428 *pVal = DIS_READ_REGSEG(pCtx, sel);
429 return VINF_SUCCESS;
430}
431
432/**
433 * Returns the value of the specified segment register including a pointer to the hidden register in the supplied cpu context
434 *
435 */
436DISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal, CPUMSELREGHID **ppSelHidReg)
437{
438 AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
439
440 AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
441 *pVal = DIS_READ_REGSEG(pCtx, sel);
442 *ppSelHidReg = (CPUMSELREGHID *)((char *)pCtx + g_aRegHidSegIndex[sel]);
443 return VINF_SUCCESS;
444}
445
446/**
447 * Updates the value of the specified 64 bits general purpose register
448 *
449 */
450DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64)
451{
452 AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
453
454 DIS_WRITE_REG64(pRegFrame, reg64, val64);
455 return VINF_SUCCESS;
456}
457
458/**
459 * Updates the value of the specified 32 bits general purpose register
460 *
461 */
462DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32)
463{
464 AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
465
466 DIS_WRITE_REG32(pRegFrame, reg32, val32);
467 return VINF_SUCCESS;
468}
469
470/**
471 * Updates the value of the specified 16 bits general purpose register
472 *
473 */
474DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg16, uint16_t val16)
475{
476 AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
477
478 DIS_WRITE_REG16(pRegFrame, reg16, val16);
479 return VINF_SUCCESS;
480}
481
482/**
483 * Updates the specified 8 bits general purpose register
484 *
485 */
486DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8)
487{
488 AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
489
490 DIS_WRITE_REG8(pRegFrame, reg8, val8);
491 return VINF_SUCCESS;
492}
493
494/**
495 * Updates the specified segment register
496 *
497 */
498DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL val)
499{
500 AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
501
502 AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
503 DIS_WRITE_REGSEG(pCtx, sel, val);
504 return VINF_SUCCESS;
505}
506
507/**
508 * Returns the value of the parameter in pParam
509 *
510 * @returns VBox error code
511 * @param pCtx CPU context structure pointer
512 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
513 * set correctly.
514 * @param pParam Pointer to the parameter to parse
515 * @param pParamVal Pointer to parameter value (OUT)
516 * @param parmtype Parameter type
517 *
518 * @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
519 *
520 */
521DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype)
522{
523 memset(pParamVal, 0, sizeof(*pParamVal));
524
525 if (DIS_IS_EFFECTIVE_ADDR(pParam->flags))
526 {
527 // Effective address
528 pParamVal->type = PARMTYPE_ADDRESS;
529 pParamVal->size = pParam->size;
530
531 if (pParam->flags & USE_BASE)
532 {
533 if (pParam->flags & USE_REG_GEN8)
534 {
535 pParamVal->flags |= PARAM_VAL8;
536 if (RT_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
537 }
538 else
539 if (pParam->flags & USE_REG_GEN16)
540 {
541 pParamVal->flags |= PARAM_VAL16;
542 if (RT_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
543 }
544 else
545 if (pParam->flags & USE_REG_GEN32)
546 {
547 pParamVal->flags |= PARAM_VAL32;
548 if (RT_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
549 }
550 else
551 if (pParam->flags & USE_REG_GEN64)
552 {
553 pParamVal->flags |= PARAM_VAL64;
554 if (RT_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
555 }
556 else
557 {
558 AssertFailed();
559 return VERR_INVALID_PARAMETER;
560 }
561 }
562 // Note that scale implies index (SIB byte)
563 if (pParam->flags & USE_INDEX)
564 {
565 if (pParam->flags & USE_REG_GEN16)
566 {
567 uint16_t val16;
568
569 pParamVal->flags |= PARAM_VAL16;
570 if (RT_FAILURE(DISFetchReg16(pCtx, pParam->index.reg_gen, &val16))) return VERR_INVALID_PARAMETER;
571
572 Assert(!(pParam->flags & USE_SCALE)); /* shouldn't be possible in 16 bits mode */
573
574 pParamVal->val.val16 += val16;
575 }
576 else
577 if (pParam->flags & USE_REG_GEN32)
578 {
579 uint32_t val32;
580
581 pParamVal->flags |= PARAM_VAL32;
582 if (RT_FAILURE(DISFetchReg32(pCtx, pParam->index.reg_gen, &val32))) return VERR_INVALID_PARAMETER;
583
584 if (pParam->flags & USE_SCALE)
585 val32 *= pParam->scale;
586
587 pParamVal->val.val32 += val32;
588 }
589 else
590 if (pParam->flags & USE_REG_GEN64)
591 {
592 uint64_t val64;
593
594 pParamVal->flags |= PARAM_VAL64;
595 if (RT_FAILURE(DISFetchReg64(pCtx, pParam->index.reg_gen, &val64))) return VERR_INVALID_PARAMETER;
596
597 if (pParam->flags & USE_SCALE)
598 val64 *= pParam->scale;
599
600 pParamVal->val.val64 += val64;
601 }
602 else
603 AssertFailed();
604 }
605
606 if (pParam->flags & USE_DISPLACEMENT8)
607 {
608 if (pCpu->mode == CPUMODE_32BIT)
609 pParamVal->val.val32 += (int32_t)pParam->disp8;
610 else
611 if (pCpu->mode == CPUMODE_64BIT)
612 pParamVal->val.val64 += (int64_t)pParam->disp8;
613 else
614 pParamVal->val.val16 += (int16_t)pParam->disp8;
615 }
616 else
617 if (pParam->flags & USE_DISPLACEMENT16)
618 {
619 if (pCpu->mode == CPUMODE_32BIT)
620 pParamVal->val.val32 += (int32_t)pParam->disp16;
621 else
622 if (pCpu->mode == CPUMODE_64BIT)
623 pParamVal->val.val64 += (int64_t)pParam->disp16;
624 else
625 pParamVal->val.val16 += pParam->disp16;
626 }
627 else
628 if (pParam->flags & USE_DISPLACEMENT32)
629 {
630 if (pCpu->mode == CPUMODE_32BIT)
631 pParamVal->val.val32 += pParam->disp32;
632 else
633 pParamVal->val.val64 += pParam->disp32;
634 }
635 else
636 if (pParam->flags & USE_DISPLACEMENT64)
637 {
638 Assert(pCpu->mode == CPUMODE_64BIT);
639 pParamVal->val.val64 += (int64_t)pParam->disp64;
640 }
641 else
642 if (pParam->flags & USE_RIPDISPLACEMENT32)
643 {
644 Assert(pCpu->mode == CPUMODE_64BIT);
645 /* Relative to the RIP of the next instruction. */
646 pParamVal->val.val64 += pParam->disp32 + pCtx->rip + pCpu->opsize;
647 }
648 return VINF_SUCCESS;
649 }
650
651 if (pParam->flags & (USE_REG_GEN8|USE_REG_GEN16|USE_REG_GEN32|USE_REG_GEN64|USE_REG_FP|USE_REG_MMX|USE_REG_XMM|USE_REG_CR|USE_REG_DBG|USE_REG_SEG|USE_REG_TEST))
652 {
653 if (parmtype == PARAM_DEST)
654 {
655 // Caller needs to interpret the register according to the instruction (source/target, special value etc)
656 pParamVal->type = PARMTYPE_REGISTER;
657 pParamVal->size = pParam->size;
658 return VINF_SUCCESS;
659 }
660 //else PARAM_SOURCE
661
662 pParamVal->type = PARMTYPE_IMMEDIATE;
663
664 if (pParam->flags & USE_REG_GEN8)
665 {
666 pParamVal->flags |= PARAM_VAL8;
667 pParamVal->size = sizeof(uint8_t);
668 if (RT_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
669 }
670 else
671 if (pParam->flags & USE_REG_GEN16)
672 {
673 pParamVal->flags |= PARAM_VAL16;
674 pParamVal->size = sizeof(uint16_t);
675 if (RT_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
676 }
677 else
678 if (pParam->flags & USE_REG_GEN32)
679 {
680 pParamVal->flags |= PARAM_VAL32;
681 pParamVal->size = sizeof(uint32_t);
682 if (RT_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
683 }
684 else
685 if (pParam->flags & USE_REG_GEN64)
686 {
687 pParamVal->flags |= PARAM_VAL64;
688 pParamVal->size = sizeof(uint64_t);
689 if (RT_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
690 }
691 else
692 {
693 // Caller needs to interpret the register according to the instruction (source/target, special value etc)
694 pParamVal->type = PARMTYPE_REGISTER;
695 }
696 Assert(!(pParam->flags & USE_IMMEDIATE));
697 return VINF_SUCCESS;
698 }
699
700 if (pParam->flags & USE_IMMEDIATE)
701 {
702 pParamVal->type = PARMTYPE_IMMEDIATE;
703 if (pParam->flags & (USE_IMMEDIATE8|USE_IMMEDIATE8_REL))
704 {
705 pParamVal->flags |= PARAM_VAL8;
706 if (pParam->size == 2)
707 {
708 pParamVal->size = sizeof(uint16_t);
709 pParamVal->val.val16 = (uint8_t)pParam->parval;
710 }
711 else
712 {
713 pParamVal->size = sizeof(uint8_t);
714 pParamVal->val.val8 = (uint8_t)pParam->parval;
715 }
716 }
717 else
718 if (pParam->flags & (USE_IMMEDIATE16|USE_IMMEDIATE16_REL|USE_IMMEDIATE_ADDR_0_16|USE_IMMEDIATE16_SX8))
719 {
720 pParamVal->flags |= PARAM_VAL16;
721 pParamVal->size = sizeof(uint16_t);
722 pParamVal->val.val16 = (uint16_t)pParam->parval;
723 AssertMsg(pParamVal->size == pParam->size || ((pParam->size == 1) && (pParam->flags & USE_IMMEDIATE16_SX8)), ("pParamVal->size %d vs %d EIP=%RX32\n", pParamVal->size, pParam->size, pCtx->eip) );
724 }
725 else
726 if (pParam->flags & (USE_IMMEDIATE32|USE_IMMEDIATE32_REL|USE_IMMEDIATE_ADDR_0_32|USE_IMMEDIATE32_SX8))
727 {
728 pParamVal->flags |= PARAM_VAL32;
729 pParamVal->size = sizeof(uint32_t);
730 pParamVal->val.val32 = (uint32_t)pParam->parval;
731 Assert(pParamVal->size == pParam->size || ((pParam->size == 1) && (pParam->flags & USE_IMMEDIATE32_SX8)) );
732 }
733 else
734 if (pParam->flags & (USE_IMMEDIATE64 | USE_IMMEDIATE64_REL | USE_IMMEDIATE64_SX8))
735 {
736 pParamVal->flags |= PARAM_VAL64;
737 pParamVal->size = sizeof(uint64_t);
738 pParamVal->val.val64 = pParam->parval;
739 Assert(pParamVal->size == pParam->size || ((pParam->size == 1) && (pParam->flags & USE_IMMEDIATE64_SX8)) );
740 }
741 else
742 if (pParam->flags & (USE_IMMEDIATE_ADDR_16_16))
743 {
744 pParamVal->flags |= PARAM_VALFARPTR16;
745 pParamVal->size = sizeof(uint16_t)*2;
746 pParamVal->val.farptr.sel = (uint16_t)RT_LOWORD(pParam->parval >> 16);
747 pParamVal->val.farptr.offset = (uint32_t)RT_LOWORD(pParam->parval);
748 Assert(pParamVal->size == pParam->size);
749 }
750 else
751 if (pParam->flags & (USE_IMMEDIATE_ADDR_16_32))
752 {
753 pParamVal->flags |= PARAM_VALFARPTR32;
754 pParamVal->size = sizeof(uint16_t) + sizeof(uint32_t);
755 pParamVal->val.farptr.sel = (uint16_t)RT_LOWORD(pParam->parval >> 32);
756 pParamVal->val.farptr.offset = (uint32_t)(pParam->parval & 0xFFFFFFFF);
757 Assert(pParam->size == 8);
758 }
759 }
760 return VINF_SUCCESS;
761}
762
763/**
764 * Returns the pointer to a register of the parameter in pParam. We need this
765 * pointer when an interpreted instruction updates a register as a side effect.
766 * In CMPXCHG we know that only [r/e]ax is updated, but with XADD this could
767 * be every register.
768 *
769 * @returns VBox error code
770 * @param pCtx CPU context structure pointer
771 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
772 * set correctly.
773 * @param pParam Pointer to the parameter to parse
774 * @param pReg Pointer to parameter value (OUT)
775 * @param cbsize Parameter size (OUT)
776 *
777 * @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
778 *
779 */
780DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, void **ppReg, size_t *pcbSize)
781{
782 if (pParam->flags & (USE_REG_GEN8|USE_REG_GEN16|USE_REG_GEN32|USE_REG_FP|USE_REG_MMX|USE_REG_XMM|USE_REG_CR|USE_REG_DBG|USE_REG_SEG|USE_REG_TEST))
783 {
784 if (pParam->flags & USE_REG_GEN8)
785 {
786 uint8_t *pu8Reg;
787 if (RT_SUCCESS(DISPtrReg8(pCtx, pParam->base.reg_gen, &pu8Reg)))
788 {
789 *pcbSize = sizeof(uint8_t);
790 *ppReg = (void *)pu8Reg;
791 return VINF_SUCCESS;
792 }
793 }
794 else
795 if (pParam->flags & USE_REG_GEN16)
796 {
797 uint16_t *pu16Reg;
798 if (RT_SUCCESS(DISPtrReg16(pCtx, pParam->base.reg_gen, &pu16Reg)))
799 {
800 *pcbSize = sizeof(uint16_t);
801 *ppReg = (void *)pu16Reg;
802 return VINF_SUCCESS;
803 }
804 }
805 else
806 if (pParam->flags & USE_REG_GEN32)
807 {
808 uint32_t *pu32Reg;
809 if (RT_SUCCESS(DISPtrReg32(pCtx, pParam->base.reg_gen, &pu32Reg)))
810 {
811 *pcbSize = sizeof(uint32_t);
812 *ppReg = (void *)pu32Reg;
813 return VINF_SUCCESS;
814 }
815 }
816 else
817 if (pParam->flags & USE_REG_GEN64)
818 {
819 uint64_t *pu64Reg;
820 if (RT_SUCCESS(DISPtrReg64(pCtx, pParam->base.reg_gen, &pu64Reg)))
821 {
822 *pcbSize = sizeof(uint64_t);
823 *ppReg = (void *)pu64Reg;
824 return VINF_SUCCESS;
825 }
826 }
827 }
828 return VERR_INVALID_PARAMETER;
829}
830//*****************************************************************************
831//*****************************************************************************
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