VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmReg.cpp@ 77807

Last change on this file since 77807 was 76553, checked in by vboxsync, 6 years ago

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[41668]1/* $Id: DisasmReg.cpp 76553 2019-01-01 01:45:53Z vboxsync $ */
[11111]2/** @file
[41668]3 * VBox disassembler- Register Info Helpers.
[11111]4 */
5
6/*
[76553]7 * Copyright (C) 2006-2019 Oracle Corporation
[11111]8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
[57358]19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
[11111]22#define LOG_GROUP LOG_GROUP_DIS
23#include <VBox/dis.h>
24#include <VBox/disopcode.h>
[76455]25#include <iprt/errcore.h>
[11111]26#include <VBox/log.h>
[35346]27#include <VBox/vmm/cpum.h>
[11111]28#include <iprt/assert.h>
29#include <iprt/string.h>
30#include <iprt/stdarg.h>
31#include "DisasmInternal.h"
32
33
[57358]34/*********************************************************************************************************************************
35* Global Variables *
36*********************************************************************************************************************************/
[11111]37
38/**
39 * Array for accessing 64-bit general registers in VMMREGFRAME structure
40 * by register's index from disasm.
41 */
42static const unsigned g_aReg64Index[] =
43{
[41727]44 RT_OFFSETOF(CPUMCTXCORE, rax), /* DISGREG_RAX */
45 RT_OFFSETOF(CPUMCTXCORE, rcx), /* DISGREG_RCX */
46 RT_OFFSETOF(CPUMCTXCORE, rdx), /* DISGREG_RDX */
47 RT_OFFSETOF(CPUMCTXCORE, rbx), /* DISGREG_RBX */
48 RT_OFFSETOF(CPUMCTXCORE, rsp), /* DISGREG_RSP */
49 RT_OFFSETOF(CPUMCTXCORE, rbp), /* DISGREG_RBP */
50 RT_OFFSETOF(CPUMCTXCORE, rsi), /* DISGREG_RSI */
51 RT_OFFSETOF(CPUMCTXCORE, rdi), /* DISGREG_RDI */
52 RT_OFFSETOF(CPUMCTXCORE, r8), /* DISGREG_R8 */
53 RT_OFFSETOF(CPUMCTXCORE, r9), /* DISGREG_R9 */
54 RT_OFFSETOF(CPUMCTXCORE, r10), /* DISGREG_R10 */
55 RT_OFFSETOF(CPUMCTXCORE, r11), /* DISGREG_R11 */
56 RT_OFFSETOF(CPUMCTXCORE, r12), /* DISGREG_R12 */
57 RT_OFFSETOF(CPUMCTXCORE, r13), /* DISGREG_R13 */
58 RT_OFFSETOF(CPUMCTXCORE, r14), /* DISGREG_R14 */
59 RT_OFFSETOF(CPUMCTXCORE, r15) /* DISGREG_R15 */
[11111]60};
61
62/**
63 * Macro for accessing 64-bit general purpose registers in CPUMCTXCORE structure.
64 */
65#define DIS_READ_REG64(p, idx) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]))
66#define DIS_WRITE_REG64(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]) = val)
67#define DIS_PTR_REG64(p, idx) ( (uint64_t *)((char *)(p) + g_aReg64Index[idx]))
68
69/**
70 * Array for accessing 32-bit general registers in VMMREGFRAME structure
71 * by register's index from disasm.
72 */
73static const unsigned g_aReg32Index[] =
74{
[41727]75 RT_OFFSETOF(CPUMCTXCORE, eax), /* DISGREG_EAX */
76 RT_OFFSETOF(CPUMCTXCORE, ecx), /* DISGREG_ECX */
77 RT_OFFSETOF(CPUMCTXCORE, edx), /* DISGREG_EDX */
78 RT_OFFSETOF(CPUMCTXCORE, ebx), /* DISGREG_EBX */
79 RT_OFFSETOF(CPUMCTXCORE, esp), /* DISGREG_ESP */
80 RT_OFFSETOF(CPUMCTXCORE, ebp), /* DISGREG_EBP */
81 RT_OFFSETOF(CPUMCTXCORE, esi), /* DISGREG_ESI */
82 RT_OFFSETOF(CPUMCTXCORE, edi), /* DISGREG_EDI */
83 RT_OFFSETOF(CPUMCTXCORE, r8), /* DISGREG_R8D */
84 RT_OFFSETOF(CPUMCTXCORE, r9), /* DISGREG_R9D */
85 RT_OFFSETOF(CPUMCTXCORE, r10), /* DISGREG_R1D */
86 RT_OFFSETOF(CPUMCTXCORE, r11), /* DISGREG_R11D */
87 RT_OFFSETOF(CPUMCTXCORE, r12), /* DISGREG_R12D */
88 RT_OFFSETOF(CPUMCTXCORE, r13), /* DISGREG_R13D */
89 RT_OFFSETOF(CPUMCTXCORE, r14), /* DISGREG_R14D */
90 RT_OFFSETOF(CPUMCTXCORE, r15) /* DISGREG_R15D */
[11111]91};
92
93/**
94 * Macro for accessing 32-bit general purpose registers in CPUMCTXCORE structure.
95 */
96#define DIS_READ_REG32(p, idx) (*(uint32_t *)((char *)(p) + g_aReg32Index[idx]))
97/* From http://www.cs.cmu.edu/~fp/courses/15213-s06/misc/asm64-handout.pdf:
98 * ``Perhaps unexpectedly, instructions that move or generate 32-bit register
99 * values also set the upper 32 bits of the register to zero. Consequently
100 * there is no need for an instruction movzlq.''
101 */
102#define DIS_WRITE_REG32(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg32Index[idx]) = (uint32_t)val)
103#define DIS_PTR_REG32(p, idx) ( (uint32_t *)((char *)(p) + g_aReg32Index[idx]))
104
105/**
106 * Array for accessing 16-bit general registers in CPUMCTXCORE structure
107 * by register's index from disasm.
108 */
109static const unsigned g_aReg16Index[] =
110{
[41727]111 RT_OFFSETOF(CPUMCTXCORE, eax), /* DISGREG_AX */
112 RT_OFFSETOF(CPUMCTXCORE, ecx), /* DISGREG_CX */
113 RT_OFFSETOF(CPUMCTXCORE, edx), /* DISGREG_DX */
114 RT_OFFSETOF(CPUMCTXCORE, ebx), /* DISGREG_BX */
115 RT_OFFSETOF(CPUMCTXCORE, esp), /* DISGREG_SP */
116 RT_OFFSETOF(CPUMCTXCORE, ebp), /* DISGREG_BP */
117 RT_OFFSETOF(CPUMCTXCORE, esi), /* DISGREG_SI */
118 RT_OFFSETOF(CPUMCTXCORE, edi), /* DISGREG_DI */
119 RT_OFFSETOF(CPUMCTXCORE, r8), /* DISGREG_R8W */
120 RT_OFFSETOF(CPUMCTXCORE, r9), /* DISGREG_R9W */
121 RT_OFFSETOF(CPUMCTXCORE, r10), /* DISGREG_R10W */
122 RT_OFFSETOF(CPUMCTXCORE, r11), /* DISGREG_R11W */
123 RT_OFFSETOF(CPUMCTXCORE, r12), /* DISGREG_R12W */
124 RT_OFFSETOF(CPUMCTXCORE, r13), /* DISGREG_R13W */
125 RT_OFFSETOF(CPUMCTXCORE, r14), /* DISGREG_R14W */
126 RT_OFFSETOF(CPUMCTXCORE, r15) /* DISGREG_R15W */
[11111]127};
128
129/**
130 * Macro for accessing 16-bit general purpose registers in CPUMCTXCORE structure.
131 */
132#define DIS_READ_REG16(p, idx) (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]))
133#define DIS_WRITE_REG16(p, idx, val) (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]) = val)
134#define DIS_PTR_REG16(p, idx) ( (uint16_t *)((char *)(p) + g_aReg16Index[idx]))
135
136/**
137 * Array for accessing 8-bit general registers in CPUMCTXCORE structure
138 * by register's index from disasm.
139 */
140static const unsigned g_aReg8Index[] =
141{
[41727]142 RT_OFFSETOF(CPUMCTXCORE, eax), /* DISGREG_AL */
143 RT_OFFSETOF(CPUMCTXCORE, ecx), /* DISGREG_CL */
144 RT_OFFSETOF(CPUMCTXCORE, edx), /* DISGREG_DL */
145 RT_OFFSETOF(CPUMCTXCORE, ebx), /* DISGREG_BL */
146 RT_OFFSETOF_ADD(CPUMCTXCORE, eax, 1), /* DISGREG_AH */
147 RT_OFFSETOF_ADD(CPUMCTXCORE, ecx, 1), /* DISGREG_CH */
148 RT_OFFSETOF_ADD(CPUMCTXCORE, edx, 1), /* DISGREG_DH */
149 RT_OFFSETOF_ADD(CPUMCTXCORE, ebx, 1), /* DISGREG_BH */
150 RT_OFFSETOF(CPUMCTXCORE, r8), /* DISGREG_R8B */
151 RT_OFFSETOF(CPUMCTXCORE, r9), /* DISGREG_R9B */
152 RT_OFFSETOF(CPUMCTXCORE, r10), /* DISGREG_R10B*/
153 RT_OFFSETOF(CPUMCTXCORE, r11), /* DISGREG_R11B */
154 RT_OFFSETOF(CPUMCTXCORE, r12), /* DISGREG_R12B */
155 RT_OFFSETOF(CPUMCTXCORE, r13), /* DISGREG_R13B */
156 RT_OFFSETOF(CPUMCTXCORE, r14), /* DISGREG_R14B */
157 RT_OFFSETOF(CPUMCTXCORE, r15), /* DISGREG_R15B */
158 RT_OFFSETOF(CPUMCTXCORE, esp), /* DISGREG_SPL; with REX prefix only */
159 RT_OFFSETOF(CPUMCTXCORE, ebp), /* DISGREG_BPL; with REX prefix only */
160 RT_OFFSETOF(CPUMCTXCORE, esi), /* DISGREG_SIL; with REX prefix only */
161 RT_OFFSETOF(CPUMCTXCORE, edi) /* DISGREG_DIL; with REX prefix only */
[11111]162};
163
164/**
165 * Macro for accessing 8-bit general purpose registers in CPUMCTXCORE structure.
166 */
167#define DIS_READ_REG8(p, idx) (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]))
168#define DIS_WRITE_REG8(p, idx, val) (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]) = val)
169#define DIS_PTR_REG8(p, idx) ( (uint8_t *)((char *)(p) + g_aReg8Index[idx]))
170
171/**
172 * Array for accessing segment registers in CPUMCTXCORE structure
173 * by register's index from disasm.
174 */
175static const unsigned g_aRegSegIndex[] =
176{
[41727]177 RT_OFFSETOF(CPUMCTXCORE, es), /* DISSELREG_ES */
178 RT_OFFSETOF(CPUMCTXCORE, cs), /* DISSELREG_CS */
179 RT_OFFSETOF(CPUMCTXCORE, ss), /* DISSELREG_SS */
180 RT_OFFSETOF(CPUMCTXCORE, ds), /* DISSELREG_DS */
181 RT_OFFSETOF(CPUMCTXCORE, fs), /* DISSELREG_FS */
182 RT_OFFSETOF(CPUMCTXCORE, gs) /* DISSELREG_GS */
[11111]183};
184
185static const unsigned g_aRegHidSegIndex[] =
186{
[41906]187 RT_OFFSETOF(CPUMCTXCORE, es), /* DISSELREG_ES */
188 RT_OFFSETOF(CPUMCTXCORE, cs), /* DISSELREG_CS */
189 RT_OFFSETOF(CPUMCTXCORE, ss), /* DISSELREG_SS */
190 RT_OFFSETOF(CPUMCTXCORE, ds), /* DISSELREG_DS */
191 RT_OFFSETOF(CPUMCTXCORE, fs), /* DISSELREG_FS */
192 RT_OFFSETOF(CPUMCTXCORE, gs) /* DISSELREG_GS */
[11111]193};
194
195/**
196 * Macro for accessing segment registers in CPUMCTXCORE structure.
197 */
198#define DIS_READ_REGSEG(p, idx) (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])))
199#define DIS_WRITE_REGSEG(p, idx, val) (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])) = val)
200
201//*****************************************************************************
202//*****************************************************************************
[41790]203DISDECL(int) DISGetParamSize(PCDISSTATE pDis, PCDISOPPARAM pParam)
[11111]204{
[41740]205 unsigned subtype = OP_PARM_VSUBTYPE(pParam->fParam);
[61135]206 switch (subtype)
[11111]207 {
[61135]208 case OP_PARM_v:
209 switch (pDis->uOpMode)
210 {
211 case DISCPUMODE_32BIT:
212 return 4;
213 case DISCPUMODE_64BIT:
214 return 8;
215 case DISCPUMODE_16BIT:
216 return 2;
217 default: AssertFailed(); /* make gcc happy */ return 4;
218 }
[11111]219 break;
220
[61135]221 case OP_PARM_b:
222 return 1;
[11111]223
[61135]224 case OP_PARM_w:
225 return 2;
[11111]226
[61135]227 case OP_PARM_d:
228 return 4;
[11111]229
[61135]230 case OP_PARM_q:
231 return 8;
[11111]232
[61135]233 case OP_PARM_dq:
234 return 16;
[11111]235
[61135]236 case OP_PARM_qq:
237 return 32;
238
239 case 0: /* nop, pause, lea, wrmsr, rdmsr, etc. Most of these due to DISOPPARAM::cb being initialized in the wrong place
240 (disParseInstruction) where it will be called on intermediate stuff like IDX_ParseTwoByteEsc. The parameter
241 parsers should do it instead, though I see the potential filtering issue. */
242 //Assert( pDis->pCurInstr
243 // && ( pDis->pCurInstr->uOpcode == OP_NOP
244 // || pDis->pCurInstr->uOpcode == OP_LEA ));
245 return 0;
246
247 case OP_PARM_p: /* far pointer */
248 if (pDis->uAddrMode == DISCPUMODE_32BIT)
249 return 6; /* 16:32 */
250 if (pDis->uAddrMode == DISCPUMODE_64BIT)
251 return 12; /* 16:64 */
252 return 4; /* 16:16 */
253
254 case OP_PARM_s: /* lgdt, sgdt, lidt, sidt */
255 return pDis->uCpuMode == DISCPUMODE_64BIT ? 2 + 8 : 2 + 4;
256
257 case OP_PARM_a:
258 return pDis->uOpMode == DISCPUMODE_16BIT ? 2 + 2 : 4 + 4;
259
260 case OP_PARM_pi:
261 return 8;
262
263 case OP_PARM_sd:
264 case OP_PARM_ss:
265 return 16;
266
267 case OP_PARM_x:
268 case OP_PARM_pd:
269 case OP_PARM_ps:
270 return VEXREG_IS256B(pDis->bVexDestReg) ? 32 : 16; //??
271
272 case OP_PARM_y:
273 return pDis->uOpMode == DISCPUMODE_64BIT ? 4 : 8; //??
274
275 case OP_PARM_z:
[61136]276 if (pParam->cb)
277 return pParam->cb;
[61135]278 return pDis->uOpMode == DISCPUMODE_16BIT ? 2 : 4; //??
279
280 default:
281 if (pParam->cb)
282 return pParam->cb;
283 /// @todo dangerous!!!
284 AssertMsgFailed(("subtype=%#x fParam=%#x fUse=%#RX64 op=%#x\n", subtype, pParam->fParam, pParam->fUse,
285 pDis->pCurInstr ? pDis->pCurInstr->uOpcode : 0));
[11111]286 return 4;
287 }
288}
289//*****************************************************************************
290//*****************************************************************************
[41790]291DISDECL(DISSELREG) DISDetectSegReg(PCDISSTATE pDis, PCDISOPPARAM pParam)
[11111]292{
[41789]293 if (pDis->fPrefix & DISPREFIX_SEG)
[11111]294 /* Use specified SEG: prefix. */
[41789]295 return (DISSELREG)pDis->idxSegPrefix;
[41692]296
297 /* Guess segment register by parameter type. */
298 if (pParam->fUse & (DISUSE_REG_GEN32|DISUSE_REG_GEN64|DISUSE_REG_GEN16))
[11111]299 {
[41727]300 AssertCompile(DISGREG_ESP == DISGREG_RSP);
301 AssertCompile(DISGREG_EBP == DISGREG_RBP);
302 AssertCompile(DISGREG_ESP == DISGREG_SP);
303 AssertCompile(DISGREG_EBP == DISGREG_BP);
[41744]304 if (pParam->Base.idxGenReg == DISGREG_ESP || pParam->Base.idxGenReg == DISGREG_EBP)
[41727]305 return DISSELREG_SS;
[11111]306 }
[41692]307 /* Default is use DS: for data access. */
[41727]308 return DISSELREG_DS;
[11111]309}
310//*****************************************************************************
311//*****************************************************************************
[41790]312DISDECL(uint8_t) DISQuerySegPrefixByte(PCDISSTATE pDis)
[11111]313{
[41789]314 Assert(pDis->fPrefix & DISPREFIX_SEG);
315 switch (pDis->idxSegPrefix)
[11111]316 {
[41727]317 case DISSELREG_ES:
[11111]318 return 0x26;
[41727]319 case DISSELREG_CS:
[11111]320 return 0x2E;
[41727]321 case DISSELREG_SS:
[11111]322 return 0x36;
[41727]323 case DISSELREG_DS:
[11111]324 return 0x3E;
[41727]325 case DISSELREG_FS:
[11111]326 return 0x64;
[41727]327 case DISSELREG_GS:
[11111]328 return 0x65;
329 default:
330 AssertFailed();
331 return 0;
332 }
333}
334
335
336/**
337 * Returns the value of the specified 8 bits general purpose register
338 *
339 */
340DISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal)
341{
[73514]342 AssertReturnStmt(reg8 < RT_ELEMENTS(g_aReg8Index), *pVal = 0, VERR_INVALID_PARAMETER);
[11111]343
344 *pVal = DIS_READ_REG8(pCtx, reg8);
345 return VINF_SUCCESS;
346}
347
348/**
349 * Returns the value of the specified 16 bits general purpose register
350 *
351 */
352DISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal)
353{
[73508]354 AssertReturnStmt(reg16 < RT_ELEMENTS(g_aReg16Index), *pVal = 0, VERR_INVALID_PARAMETER);
[11111]355
356 *pVal = DIS_READ_REG16(pCtx, reg16);
357 return VINF_SUCCESS;
358}
359
360/**
361 * Returns the value of the specified 32 bits general purpose register
362 *
363 */
364DISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal)
365{
[73508]366 AssertReturnStmt(reg32 < RT_ELEMENTS(g_aReg32Index), *pVal = 0, VERR_INVALID_PARAMETER);
[11111]367
368 *pVal = DIS_READ_REG32(pCtx, reg32);
369 return VINF_SUCCESS;
370}
371
372/**
373 * Returns the value of the specified 64 bits general purpose register
374 *
375 */
376DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal)
377{
[73508]378 AssertReturnStmt(reg64 < RT_ELEMENTS(g_aReg64Index), *pVal = 0, VERR_INVALID_PARAMETER);
[11111]379
380 *pVal = DIS_READ_REG64(pCtx, reg64);
381 return VINF_SUCCESS;
382}
383
384/**
385 * Returns the pointer to the specified 8 bits general purpose register
386 *
387 */
388DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg)
389{
[73508]390 AssertReturnStmt(reg8 < RT_ELEMENTS(g_aReg8Index), *ppReg = NULL, VERR_INVALID_PARAMETER);
[11111]391
392 *ppReg = DIS_PTR_REG8(pCtx, reg8);
393 return VINF_SUCCESS;
394}
395
396/**
397 * Returns the pointer to the specified 16 bits general purpose register
398 *
399 */
400DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg)
401{
[73508]402 AssertReturnStmt(reg16 < RT_ELEMENTS(g_aReg16Index), *ppReg = NULL, VERR_INVALID_PARAMETER);
[11111]403
404 *ppReg = DIS_PTR_REG16(pCtx, reg16);
405 return VINF_SUCCESS;
406}
407
408/**
409 * Returns the pointer to the specified 32 bits general purpose register
410 */
411DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg)
412{
[73508]413 AssertReturnStmt(reg32 < RT_ELEMENTS(g_aReg32Index), *ppReg = NULL, VERR_INVALID_PARAMETER);
[11111]414
415 *ppReg = DIS_PTR_REG32(pCtx, reg32);
416 return VINF_SUCCESS;
417}
418
419/**
420 * Returns the pointer to the specified 64 bits general purpose register
421 */
422DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg)
423{
[73508]424 AssertReturnStmt(reg64 < RT_ELEMENTS(g_aReg64Index), *ppReg = NULL, VERR_INVALID_PARAMETER);
[11111]425
426 *ppReg = DIS_PTR_REG64(pCtx, reg64);
427 return VINF_SUCCESS;
428}
429
430/**
431 * Returns the value of the specified segment register
432 */
[41727]433DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal)
[11111]434{
[13836]435 AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
[11111]436
437 AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
438 *pVal = DIS_READ_REGSEG(pCtx, sel);
439 return VINF_SUCCESS;
440}
441
442/**
443 * Returns the value of the specified segment register including a pointer to the hidden register in the supplied cpu context
444 *
445 */
[42186]446DISDECL(int) DISFetchRegSegEx(PCPUMCTXCORE pCtx, DISSELREG sel, PCPUMSELREG *ppSelReg)
[11111]447{
[42186]448 AssertReturnStmt((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), *ppSelReg = NULL, VERR_INVALID_PARAMETER);
449 *ppSelReg = (CPUMSELREG *)((uintptr_t)pCtx + g_aRegHidSegIndex[sel]);
[11111]450 return VINF_SUCCESS;
451}
452
453/**
454 * Updates the value of the specified 64 bits general purpose register
455 *
456 */
457DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64)
458{
[13836]459 AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
[11111]460
461 DIS_WRITE_REG64(pRegFrame, reg64, val64);
462 return VINF_SUCCESS;
463}
464
465/**
466 * Updates the value of the specified 32 bits general purpose register
467 *
468 */
469DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32)
470{
[13836]471 AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
[11111]472
473 DIS_WRITE_REG32(pRegFrame, reg32, val32);
474 return VINF_SUCCESS;
475}
476
477/**
478 * Updates the value of the specified 16 bits general purpose register
479 *
480 */
481DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg16, uint16_t val16)
482{
[13836]483 AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
[11111]484
485 DIS_WRITE_REG16(pRegFrame, reg16, val16);
486 return VINF_SUCCESS;
487}
488
489/**
490 * Updates the specified 8 bits general purpose register
491 *
492 */
493DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8)
494{
[13836]495 AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
[11111]496
497 DIS_WRITE_REG8(pRegFrame, reg8, val8);
498 return VINF_SUCCESS;
499}
500
501/**
502 * Updates the specified segment register
503 *
504 */
[41727]505DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DISSELREG sel, RTSEL val)
[11111]506{
[13836]507 AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
[11111]508
509 AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
510 DIS_WRITE_REGSEG(pCtx, sel, val);
511 return VINF_SUCCESS;
512}
513
514/**
515 * Returns the value of the parameter in pParam
516 *
517 * @returns VBox error code
518 * @param pCtx CPU context structure pointer
[41789]519 * @param pDis Pointer to the disassembler state.
[11111]520 * @param pParam Pointer to the parameter to parse
521 * @param pParamVal Pointer to parameter value (OUT)
522 * @param parmtype Parameter type
523 *
524 * @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
525 *
526 */
[41790]527DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PCDISSTATE pDis, PCDISOPPARAM pParam, PDISQPVPARAMVAL pParamVal, DISQPVWHICH parmtype)
[11111]528{
529 memset(pParamVal, 0, sizeof(*pParamVal));
530
[41678]531 if (DISUSE_IS_EFFECTIVE_ADDR(pParam->fUse))
[11111]532 {
533 // Effective address
[41729]534 pParamVal->type = DISQPV_TYPE_ADDRESS;
[41663]535 pParamVal->size = pParam->cb;
[11111]536
[41678]537 if (pParam->fUse & DISUSE_BASE)
[11111]538 {
[41678]539 if (pParam->fUse & DISUSE_REG_GEN8)
[11111]540 {
[41729]541 pParamVal->flags |= DISQPV_FLAG_8;
[41744]542 if (RT_FAILURE(DISFetchReg8(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
[11111]543 }
544 else
[41678]545 if (pParam->fUse & DISUSE_REG_GEN16)
[11111]546 {
[41729]547 pParamVal->flags |= DISQPV_FLAG_16;
[41744]548 if (RT_FAILURE(DISFetchReg16(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
[11111]549 }
550 else
[41678]551 if (pParam->fUse & DISUSE_REG_GEN32)
[11111]552 {
[41729]553 pParamVal->flags |= DISQPV_FLAG_32;
[41744]554 if (RT_FAILURE(DISFetchReg32(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
[11111]555 }
556 else
[41678]557 if (pParam->fUse & DISUSE_REG_GEN64)
[11111]558 {
[41729]559 pParamVal->flags |= DISQPV_FLAG_64;
[41744]560 if (RT_FAILURE(DISFetchReg64(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
[11111]561 }
[13835]562 else
[11111]563 {
564 AssertFailed();
565 return VERR_INVALID_PARAMETER;
566 }
567 }
568 // Note that scale implies index (SIB byte)
[41678]569 if (pParam->fUse & DISUSE_INDEX)
[11111]570 {
[41678]571 if (pParam->fUse & DISUSE_REG_GEN16)
[11111]572 {
573 uint16_t val16;
574
[41729]575 pParamVal->flags |= DISQPV_FLAG_16;
[41743]576 if (RT_FAILURE(DISFetchReg16(pCtx, pParam->Index.idxGenReg, &val16))) return VERR_INVALID_PARAMETER;
[13835]577
[41678]578 Assert(!(pParam->fUse & DISUSE_SCALE)); /* shouldn't be possible in 16 bits mode */
[13835]579
[11111]580 pParamVal->val.val16 += val16;
581 }
582 else
[41678]583 if (pParam->fUse & DISUSE_REG_GEN32)
[11111]584 {
585 uint32_t val32;
586
[41729]587 pParamVal->flags |= DISQPV_FLAG_32;
[41743]588 if (RT_FAILURE(DISFetchReg32(pCtx, pParam->Index.idxGenReg, &val32))) return VERR_INVALID_PARAMETER;
[11111]589
[41678]590 if (pParam->fUse & DISUSE_SCALE)
[41742]591 val32 *= pParam->uScale;
[11111]592
593 pParamVal->val.val32 += val32;
594 }
595 else
[41678]596 if (pParam->fUse & DISUSE_REG_GEN64)
[11111]597 {
598 uint64_t val64;
599
[41729]600 pParamVal->flags |= DISQPV_FLAG_64;
[41743]601 if (RT_FAILURE(DISFetchReg64(pCtx, pParam->Index.idxGenReg, &val64))) return VERR_INVALID_PARAMETER;
[11111]602
[41678]603 if (pParam->fUse & DISUSE_SCALE)
[41742]604 val64 *= pParam->uScale;
[11111]605
606 pParamVal->val.val64 += val64;
607 }
608 else
609 AssertFailed();
610 }
611
[41678]612 if (pParam->fUse & DISUSE_DISPLACEMENT8)
[11111]613 {
[41789]614 if (pDis->uCpuMode == DISCPUMODE_32BIT)
[41662]615 pParamVal->val.val32 += (int32_t)pParam->uDisp.i8;
[11111]616 else
[41789]617 if (pDis->uCpuMode == DISCPUMODE_64BIT)
[41662]618 pParamVal->val.val64 += (int64_t)pParam->uDisp.i8;
[11111]619 else
[41662]620 pParamVal->val.val16 += (int16_t)pParam->uDisp.i8;
[11111]621 }
622 else
[41678]623 if (pParam->fUse & DISUSE_DISPLACEMENT16)
[11111]624 {
[41789]625 if (pDis->uCpuMode == DISCPUMODE_32BIT)
[41662]626 pParamVal->val.val32 += (int32_t)pParam->uDisp.i16;
[11111]627 else
[41789]628 if (pDis->uCpuMode == DISCPUMODE_64BIT)
[41662]629 pParamVal->val.val64 += (int64_t)pParam->uDisp.i16;
[11111]630 else
[41662]631 pParamVal->val.val16 += pParam->uDisp.i16;
[11111]632 }
633 else
[41678]634 if (pParam->fUse & DISUSE_DISPLACEMENT32)
[11111]635 {
[41789]636 if (pDis->uCpuMode == DISCPUMODE_32BIT)
[41662]637 pParamVal->val.val32 += pParam->uDisp.i32;
[11111]638 else
[41662]639 pParamVal->val.val64 += pParam->uDisp.i32;
[11111]640 }
641 else
[41678]642 if (pParam->fUse & DISUSE_DISPLACEMENT64)
[11111]643 {
[41789]644 Assert(pDis->uCpuMode == DISCPUMODE_64BIT);
[41662]645 pParamVal->val.val64 += pParam->uDisp.i64;
[11111]646 }
647 else
[41678]648 if (pParam->fUse & DISUSE_RIPDISPLACEMENT32)
[11111]649 {
[41789]650 Assert(pDis->uCpuMode == DISCPUMODE_64BIT);
[11504]651 /* Relative to the RIP of the next instruction. */
[41789]652 pParamVal->val.val64 += pParam->uDisp.i32 + pCtx->rip + pDis->cbInstr;
[11111]653 }
654 return VINF_SUCCESS;
655 }
656
[41678]657 if (pParam->fUse & (DISUSE_REG_GEN8|DISUSE_REG_GEN16|DISUSE_REG_GEN32|DISUSE_REG_GEN64|DISUSE_REG_FP|DISUSE_REG_MMX|DISUSE_REG_XMM|DISUSE_REG_CR|DISUSE_REG_DBG|DISUSE_REG_SEG|DISUSE_REG_TEST))
[11111]658 {
[41729]659 if (parmtype == DISQPVWHICH_DST)
[11111]660 {
661 // Caller needs to interpret the register according to the instruction (source/target, special value etc)
[41729]662 pParamVal->type = DISQPV_TYPE_REGISTER;
[41663]663 pParamVal->size = pParam->cb;
[11111]664 return VINF_SUCCESS;
665 }
[41729]666 //else DISQPVWHICH_SRC
[11111]667
[41729]668 pParamVal->type = DISQPV_TYPE_IMMEDIATE;
[11111]669
[41678]670 if (pParam->fUse & DISUSE_REG_GEN8)
[11111]671 {
[41729]672 pParamVal->flags |= DISQPV_FLAG_8;
[11111]673 pParamVal->size = sizeof(uint8_t);
[41744]674 if (RT_FAILURE(DISFetchReg8(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
[11111]675 }
676 else
[41678]677 if (pParam->fUse & DISUSE_REG_GEN16)
[11111]678 {
[41729]679 pParamVal->flags |= DISQPV_FLAG_16;
[11111]680 pParamVal->size = sizeof(uint16_t);
[41744]681 if (RT_FAILURE(DISFetchReg16(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
[11111]682 }
683 else
[41678]684 if (pParam->fUse & DISUSE_REG_GEN32)
[11111]685 {
[41729]686 pParamVal->flags |= DISQPV_FLAG_32;
[11111]687 pParamVal->size = sizeof(uint32_t);
[41744]688 if (RT_FAILURE(DISFetchReg32(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
[11111]689 }
690 else
[41678]691 if (pParam->fUse & DISUSE_REG_GEN64)
[11111]692 {
[41729]693 pParamVal->flags |= DISQPV_FLAG_64;
[11111]694 pParamVal->size = sizeof(uint64_t);
[41744]695 if (RT_FAILURE(DISFetchReg64(pCtx, pParam->Base.idxGenReg, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
[11111]696 }
697 else
698 {
699 // Caller needs to interpret the register according to the instruction (source/target, special value etc)
[41729]700 pParamVal->type = DISQPV_TYPE_REGISTER;
[11111]701 }
[41678]702 Assert(!(pParam->fUse & DISUSE_IMMEDIATE));
[11111]703 return VINF_SUCCESS;
704 }
705
[41678]706 if (pParam->fUse & DISUSE_IMMEDIATE)
[11111]707 {
[41729]708 pParamVal->type = DISQPV_TYPE_IMMEDIATE;
[41678]709 if (pParam->fUse & (DISUSE_IMMEDIATE8|DISUSE_IMMEDIATE8_REL))
[11111]710 {
[41729]711 pParamVal->flags |= DISQPV_FLAG_8;
[41663]712 if (pParam->cb == 2)
[11111]713 {
714 pParamVal->size = sizeof(uint16_t);
[41741]715 pParamVal->val.val16 = (uint8_t)pParam->uValue;
[11111]716 }
717 else
718 {
719 pParamVal->size = sizeof(uint8_t);
[41741]720 pParamVal->val.val8 = (uint8_t)pParam->uValue;
[11111]721 }
722 }
723 else
[41678]724 if (pParam->fUse & (DISUSE_IMMEDIATE16|DISUSE_IMMEDIATE16_REL|DISUSE_IMMEDIATE_ADDR_0_16|DISUSE_IMMEDIATE16_SX8))
[11111]725 {
[41729]726 pParamVal->flags |= DISQPV_FLAG_16;
[11111]727 pParamVal->size = sizeof(uint16_t);
[41741]728 pParamVal->val.val16 = (uint16_t)pParam->uValue;
[41678]729 AssertMsg(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE16_SX8)), ("pParamVal->size %d vs %d EIP=%RX32\n", pParamVal->size, pParam->cb, pCtx->eip) );
[11111]730 }
731 else
[41678]732 if (pParam->fUse & (DISUSE_IMMEDIATE32|DISUSE_IMMEDIATE32_REL|DISUSE_IMMEDIATE_ADDR_0_32|DISUSE_IMMEDIATE32_SX8))
[11111]733 {
[41729]734 pParamVal->flags |= DISQPV_FLAG_32;
[11111]735 pParamVal->size = sizeof(uint32_t);
[41741]736 pParamVal->val.val32 = (uint32_t)pParam->uValue;
[41678]737 Assert(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE32_SX8)) );
[11111]738 }
739 else
[41678]740 if (pParam->fUse & (DISUSE_IMMEDIATE64 | DISUSE_IMMEDIATE64_REL | DISUSE_IMMEDIATE64_SX8))
[11111]741 {
[41729]742 pParamVal->flags |= DISQPV_FLAG_64;
[11111]743 pParamVal->size = sizeof(uint64_t);
[41741]744 pParamVal->val.val64 = pParam->uValue;
[41678]745 Assert(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE64_SX8)) );
[11111]746 }
747 else
[41678]748 if (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16))
[11111]749 {
[41729]750 pParamVal->flags |= DISQPV_FLAG_FARPTR16;
[11111]751 pParamVal->size = sizeof(uint16_t)*2;
[41741]752 pParamVal->val.farptr.sel = (uint16_t)RT_LOWORD(pParam->uValue >> 16);
753 pParamVal->val.farptr.offset = (uint32_t)RT_LOWORD(pParam->uValue);
[41663]754 Assert(pParamVal->size == pParam->cb);
[11111]755 }
756 else
[41678]757 if (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_32))
[11111]758 {
[41729]759 pParamVal->flags |= DISQPV_FLAG_FARPTR32;
[11111]760 pParamVal->size = sizeof(uint16_t) + sizeof(uint32_t);
[41741]761 pParamVal->val.farptr.sel = (uint16_t)RT_LOWORD(pParam->uValue >> 32);
762 pParamVal->val.farptr.offset = (uint32_t)(pParam->uValue & 0xFFFFFFFF);
[41663]763 Assert(pParam->cb == 8);
[11111]764 }
765 }
766 return VINF_SUCCESS;
767}
768
769/**
770 * Returns the pointer to a register of the parameter in pParam. We need this
771 * pointer when an interpreted instruction updates a register as a side effect.
772 * In CMPXCHG we know that only [r/e]ax is updated, but with XADD this could
773 * be every register.
774 *
775 * @returns VBox error code
776 * @param pCtx CPU context structure pointer
[41789]777 * @param pDis Pointer to the disassembler state.
[11111]778 * @param pParam Pointer to the parameter to parse
779 * @param pReg Pointer to parameter value (OUT)
780 * @param cbsize Parameter size (OUT)
781 *
782 * @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
783 *
784 */
[41790]785DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PCDISSTATE pDis, PCDISOPPARAM pParam, void **ppReg, size_t *pcbSize)
[11111]786{
[41789]787 NOREF(pDis);
[41678]788 if (pParam->fUse & (DISUSE_REG_GEN8|DISUSE_REG_GEN16|DISUSE_REG_GEN32|DISUSE_REG_FP|DISUSE_REG_MMX|DISUSE_REG_XMM|DISUSE_REG_CR|DISUSE_REG_DBG|DISUSE_REG_SEG|DISUSE_REG_TEST))
[11111]789 {
[41678]790 if (pParam->fUse & DISUSE_REG_GEN8)
[11111]791 {
792 uint8_t *pu8Reg;
[41744]793 if (RT_SUCCESS(DISPtrReg8(pCtx, pParam->Base.idxGenReg, &pu8Reg)))
[11111]794 {
795 *pcbSize = sizeof(uint8_t);
796 *ppReg = (void *)pu8Reg;
797 return VINF_SUCCESS;
798 }
799 }
800 else
[41678]801 if (pParam->fUse & DISUSE_REG_GEN16)
[11111]802 {
803 uint16_t *pu16Reg;
[41744]804 if (RT_SUCCESS(DISPtrReg16(pCtx, pParam->Base.idxGenReg, &pu16Reg)))
[11111]805 {
806 *pcbSize = sizeof(uint16_t);
807 *ppReg = (void *)pu16Reg;
808 return VINF_SUCCESS;
809 }
810 }
811 else
[41678]812 if (pParam->fUse & DISUSE_REG_GEN32)
[11111]813 {
814 uint32_t *pu32Reg;
[41744]815 if (RT_SUCCESS(DISPtrReg32(pCtx, pParam->Base.idxGenReg, &pu32Reg)))
[11111]816 {
817 *pcbSize = sizeof(uint32_t);
818 *ppReg = (void *)pu32Reg;
819 return VINF_SUCCESS;
820 }
821 }
822 else
[41678]823 if (pParam->fUse & DISUSE_REG_GEN64)
[11111]824 {
825 uint64_t *pu64Reg;
[41744]826 if (RT_SUCCESS(DISPtrReg64(pCtx, pParam->Base.idxGenReg, &pu64Reg)))
[11111]827 {
828 *pcbSize = sizeof(uint64_t);
829 *ppReg = (void *)pu64Reg;
830 return VINF_SUCCESS;
831 }
832 }
833 }
834 return VERR_INVALID_PARAMETER;
835}
[41668]836
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