VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmInternal-armv8.h@ 106877

Last change on this file since 106877 was 106817, checked in by vboxsync, 4 weeks ago

Disassembler: Decode SIMD load/store multiple structures (post-indexed) instructions immediate, bugref:10394
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File size: 11.0 KB
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1/* $Id: DisasmInternal-armv8.h 106817 2024-11-01 10:06:53Z vboxsync $ */
2/** @file
3 * VBox disassembler - Internal header.
4 */
5
6/*
7 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
29#define VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/types.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38
39#include <iprt/param.h>
40#include "DisasmInternal.h"
41
42
43/** @addtogroup grp_dis_int Internals.
44 * @ingroup grp_dis
45 * @{
46 */
47
48/** @name Index into g_apfnFullDisasm.
49 * @{ */
50typedef enum DISPARMPARSEIDX
51{
52 kDisParmParseNop = 0,
53 kDisParmParseSize,
54 kDisParmParseImm,
55 kDisParmParseImmRel,
56 kDisParmParseImmAdr,
57 kDisParmParseImmZero,
58 kDisParmParseGprZr,
59 kDisParmParseGprZr32,
60 kDisParmParseGprZr64,
61 kDisParmParseGprSp,
62 kDisParmParseGprOff,
63 kDisParmParseVecReg,
64 kDisParmParseAddrGprSp,
65 kDisParmParseRegFixed31,
66 kDisParmParseGprCount,
67 kDisParmParseImmsImmrN,
68 kDisParmParseHw,
69 kDisParmParseCond,
70 kDisParmParsePState,
71 kDisParmParseCRnCRm,
72 kDisParmParseSysReg,
73 kDisParmParseSh12,
74 kDisParmParseImmTbz,
75 kDisParmParseShift,
76 kDisParmParseShiftAmount,
77 kDisParmParseImmMemOff,
78 kDisParmParseSImmMemOff,
79 kDisParmParseSImmMemOffUnscaled,
80 kDisParmParseOption,
81 kDisParmParseS,
82 kDisParmParseSetPreIndexed,
83 kDisParmParseSetPostIndexed,
84 kDisParmParseFpType,
85 kDisParmParseFpReg,
86 kDisParmParseFpScale,
87 kDisParmParseFpFixupFCvt,
88 kDisParmParseSimdRegSize,
89 kDisParmParseSimdRegSize32,
90 kDisParmParseSimdRegSize64,
91 kDisParmParseSimdRegSize128,
92 kDisParmParseSimdRegScalar,
93 kDisParmParseImmHImmB,
94 kDisParmParseSf,
95 kDisParmParseImmX16,
96 kDisParmParseSImmTags,
97 kDisParmParseLdrPacImm,
98 kDisParmParseLdrPacW,
99 kDisParmParseVecRegElemSize,
100 kDisParmParseVecQ,
101 kDisParmParseVecGrp,
102 kDisParmParseSimdLdStPostIndexImm,
103 kDisParmParseMax
104} DISPARMPARSEIDX;
105/** @} */
106
107
108/**
109 * Decoder step.
110 */
111typedef struct DISARMV8INSNPARAM
112{
113 /** The parser to use for the decode step. */
114 DISPARMPARSEIDX idxParse;
115 /** Bit index at which the field starts. */
116 uint8_t idxBitStart;
117 /** Size of the bit field. */
118 uint8_t cBits;
119 /** The parameter this decoder param contributes to. */
120 uint8_t idxParam;
121} DISARMV8INSNPARAM;
122typedef DISARMV8INSNPARAM *PDISARMV8INSNPARAM;
123typedef const DISARMV8INSNPARAM *PCDISARMV8INSNPARAM;
124
125#define DIS_ARMV8_INSN_DECODE_TERM { kDisParmParseNop, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET }
126#define DIS_ARMV8_INSN_DECODE(a_idxParse, a_idxBitStart, a_cBits, a_idxParam) \
127 { a_idxParse, a_idxBitStart, a_cBits, a_idxParam }
128
129#define DIS_ARMV8_INSN_PARAM_UNSET UINT8_MAX
130
131
132/**
133 * Opcode structure.
134 */
135typedef struct DISARMV8OPCODE
136{
137 /** The value of the fixed bits of the instruction. */
138 uint32_t fValue;
139 /** Special flags for the opcode. */
140 uint32_t fFlags;
141 /** Pointer to an alternative decoder overriding the default one for the instruction class. */
142 PCDISARMV8INSNPARAM paDecode;
143 /** The generic opcode structure. */
144 DISOPCODE Opc;
145} DISARMV8OPCODE;
146/** Pointer to a const opcode. */
147typedef const DISARMV8OPCODE *PCDISARMV8OPCODE;
148
149
150/**
151 * Opcode decode index.
152 */
153typedef enum DISARMV8OPCDECODE
154{
155 kDisArmV8OpcDecodeNop = 0,
156 kDisArmV8OpcDecodeLookup,
157 kDisArmV8OpcDecodeCollate,
158 kDisArmV8OpcDecodeMax
159} DISARMV8OPCDECODE;
160
161
162/**
163 * Decoder stage type.
164 */
165typedef enum kDisArmV8DecodeType
166{
167 kDisArmV8DecodeType_Invalid = 0,
168 kDisArmV8DecodeType_Map,
169 kDisArmV8DecodeType_Table,
170 kDisArmV8DecodeType_InsnClass,
171 kDisArmV8DecodeType_32Bit_Hack = 0x7fffffff
172} kDisArmV8DecodeType;
173
174
175/**
176 * Decode header.
177 */
178typedef struct DISARMV8DECODEHDR
179{
180 /** Next stage decoding type. */
181 kDisArmV8DecodeType enmDecodeType;
182 /** Number of entries in the next decoder stage or
183 * opcodes in the instruction class. */
184 uint32_t cDecode;
185} DISARMV8DECODEHDR;
186/** Pointer to a decode header. */
187typedef DISARMV8DECODEHDR *PDISARMV8DECODEHDR;
188/** Pointer to a const decode header. */
189typedef const DISARMV8DECODEHDR *PCDISARMV8DECODEHDR;
190typedef const PCDISARMV8DECODEHDR *PPCDISARMV8DECODEHDR;
191
192
193/**
194 * Instruction class descriptor.
195 */
196typedef struct DISARMV8INSNCLASS
197{
198 /** Decoder header. */
199 DISARMV8DECODEHDR Hdr;
200 /** Pointer to the arry of opcodes. */
201 PCDISARMV8OPCODE paOpcodes;
202 /** The mask of fixed instruction bits. */
203 uint32_t fFixedInsn;
204 /** Opcode decoder function. */
205 DISARMV8OPCDECODE enmOpcDecode;
206 /** The mask of the bits relevant for decoding. */
207 uint32_t fMask;
208 /** Number of bits to shift to get an index. */
209 uint32_t cShift;
210 /** The array of decoding steps. */
211 PCDISARMV8INSNPARAM paParms;
212} DISARMV8INSNCLASS;
213/** Pointer to a constant instruction class descriptor. */
214typedef const DISARMV8INSNCLASS *PCDISARMV8INSNCLASS;
215
216/** The N bit in an N:ImmR:ImmS bit vector must be 1 for 64-bit instruction variants. */
217#define DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT RT_BIT_32(1)
218/** The instruction class is using the 64-bit register encoding only. */
219#define DISARMV8INSNCLASS_F_FORCED_64BIT RT_BIT_32(2)
220/** The instruction class is using the 32-bit register encoding only. */
221#define DISARMV8INSNCLASS_F_FORCED_32BIT RT_BIT_32(3)
222
223
224#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(a_Name) \
225 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = {
226#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(a_Name) \
227 DIS_ARMV8_INSN_DECODE_TERM \
228 }; \
229 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = {
230#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(a_Name) \
231 DIS_ARMV8_INSN_DECODE_TERM \
232 }; \
233 static const DISARMV8OPCODE g_aArmV8A64Insn ## a_Name ## Opcodes[] = {
234#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift) \
235 }; \
236 static const DISARMV8INSNCLASS g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_InsnClass, \
237 RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## Opcodes) }, \
238 & g_aArmV8A64Insn ## a_Name ## Opcodes[0], \
239 a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
240 & g_aArmV8A64Insn ## a_Name ## Decode[0] }
241
242/**
243 * Decoder lookup table entry.
244 */
245typedef struct DISARMV8DECODETBLENTRY
246{
247 /** The mask to apply to the instruction. */
248 uint32_t fMask;
249 /** The value the masked instruction must match for the entry to match. */
250 uint32_t fValue;
251 /** The next stage followed when there is a match. */
252 PCDISARMV8DECODEHDR pHdrNext;
253} DISARMV8DECODETBLENTRY;
254typedef struct DISARMV8DECODETBLENTRY *PDISARMV8DECODETBLENTRY;
255typedef const DISARMV8DECODETBLENTRY *PCDISARMV8DECODETBLENTRY;
256
257
258#define DIS_ARMV8_DECODE_TBL_ENTRY_INIT(a_fMask, a_fValue, a_pNext) \
259 { a_fMask, a_fValue, & g_aArmV8A64Insn ## a_pNext.Hdr }
260
261
262/**
263 * Decoder lookup table using masks and values.
264 */
265typedef struct DISARMV8DECODETBL
266{
267 /** The header for the decoder lookup table. */
268 DISARMV8DECODEHDR Hdr;
269 /** Pointer to the individual entries. */
270 PCDISARMV8DECODETBLENTRY paEntries;
271} DISARMV8DECODETBL;
272/** Pointer to a const decode table. */
273typedef const struct DISARMV8DECODETBL *PCDISARMV8DECODETBL;
274
275
276#define DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(a_Name) \
277 static const DISARMV8DECODETBLENTRY g_aArmV8A64Insn ## a_Name ## TblEnt[] = {
278
279#define DIS_ARMV8_DECODE_TBL_DEFINE_END(a_Name) \
280 }; \
281 static const DISARMV8DECODETBL g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Table, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## TblEnt) }, \
282 & g_aArmV8A64Insn ## a_Name ## TblEnt[0] }
283
284
285/**
286 * Decoder map when direct indexing is possible.
287 */
288typedef struct DISARMV8DECODEMAP
289{
290 /** The header for the decoder map. */
291 DISARMV8DECODEHDR Hdr;
292 /** The bitmask used to decide where to go next. */
293 uint32_t fMask;
294 /** Amount to shift to get at the index. */
295 uint32_t cShift;
296 /** Pointer to the array of pointers to the next stage to index into. */
297 PPCDISARMV8DECODEHDR papNext;
298} DISARMV8DECODEMAP;
299/** Pointer to a const decode map. */
300typedef const struct DISARMV8DECODEMAP *PCDISARMV8DECODEMAP;
301
302#define DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(a_Name) \
303 static const PCDISARMV8DECODEHDR g_aArmV8A64Insn ## a_Name ## MapHdrs[] = {
304
305#define DIS_ARMV8_DECODE_MAP_DEFINE_END(a_Name, a_fMask, a_cShift) \
306 }; \
307 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
308 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
309
310#define DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(a_Name, a_idxBit) \
311 }; \
312 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
313 RT_BIT_32(a_idxBit), a_idxBit, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
314
315
316#define DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(a_Name, a_fMask, a_cShift) \
317 }; \
318 DECL_HIDDEN_CONST(DISARMV8DECODEMAP) g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
319 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
320
321#define DIS_ARMV8_DECODE_MAP_INVALID_ENTRY NULL
322#define DIS_ARMV8_DECODE_MAP_ENTRY(a_Next) & g_aArmV8A64Insn ## a_Next.Hdr
323
324
325/** @name Decoder maps.
326 * @{ */
327extern DECL_HIDDEN_DATA(DISOPCODE) g_ArmV8A64InvalidOpcode[1];
328
329extern DECL_HIDDEN_DATA(DISARMV8DECODEMAP) g_aArmV8A64InsnDecodeL0;
330/** @} */
331
332
333/** @} */
334#endif /* !VBOX_INCLUDED_SRC_DisasmInternal_armv8_h */
335
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