VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmInternal-armv8.h@ 106805

Last change on this file since 106805 was 106805, checked in by vboxsync, 5 months ago

Disassembler: Decode RCW compare and swap and RCW compare and swap pair instructions, bugref:10394
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1/* $Id: DisasmInternal-armv8.h 106805 2024-10-31 10:54:16Z vboxsync $ */
2/** @file
3 * VBox disassembler - Internal header.
4 */
5
6/*
7 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
29#define VBOX_INCLUDED_SRC_DisasmInternal_armv8_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/types.h>
35#include <VBox/err.h>
36#include <VBox/dis.h>
37#include <VBox/log.h>
38
39#include <iprt/param.h>
40#include "DisasmInternal.h"
41
42
43/** @addtogroup grp_dis_int Internals.
44 * @ingroup grp_dis
45 * @{
46 */
47
48/** @name Index into g_apfnFullDisasm.
49 * @{ */
50typedef enum DISPARMPARSEIDX
51{
52 kDisParmParseNop = 0,
53 kDisParmParseSize,
54 kDisParmParseImm,
55 kDisParmParseImmRel,
56 kDisParmParseImmAdr,
57 kDisParmParseImmZero,
58 kDisParmParseGprZr,
59 kDisParmParseGprZr32,
60 kDisParmParseGprZr64,
61 kDisParmParseGprSp,
62 kDisParmParseGprOff,
63 kDisParmParseVecReg,
64 kDisParmParseAddrGprSp,
65 kDisParmParseRegFixed31,
66 kDisParmParseGprCount,
67 kDisParmParseImmsImmrN,
68 kDisParmParseHw,
69 kDisParmParseCond,
70 kDisParmParsePState,
71 kDisParmParseCRnCRm,
72 kDisParmParseSysReg,
73 kDisParmParseSh12,
74 kDisParmParseImmTbz,
75 kDisParmParseShift,
76 kDisParmParseShiftAmount,
77 kDisParmParseImmMemOff,
78 kDisParmParseSImmMemOff,
79 kDisParmParseSImmMemOffUnscaled,
80 kDisParmParseOption,
81 kDisParmParseS,
82 kDisParmParseSetPreIndexed,
83 kDisParmParseSetPostIndexed,
84 kDisParmParseFpType,
85 kDisParmParseFpReg,
86 kDisParmParseFpScale,
87 kDisParmParseFpFixupFCvt,
88 kDisParmParseSimdRegSize,
89 kDisParmParseSimdRegSize32,
90 kDisParmParseSimdRegSize64,
91 kDisParmParseSimdRegSize128,
92 kDisParmParseSimdRegScalar,
93 kDisParmParseImmHImmB,
94 kDisParmParseSf,
95 kDisParmParseImmX16,
96 kDisParmParseSImmTags,
97 kDisParmParseLdrPacImm,
98 kDisParmParseLdrPacW,
99 kDisParmParseVecRegElemSize,
100 kDisParmParseVecQ,
101 kDisParmParseVecGrp,
102 kDisParmParseMax
103} DISPARMPARSEIDX;
104/** @} */
105
106
107/**
108 * Decoder step.
109 */
110typedef struct DISARMV8INSNPARAM
111{
112 /** The parser to use for the decode step. */
113 DISPARMPARSEIDX idxParse;
114 /** Bit index at which the field starts. */
115 uint8_t idxBitStart;
116 /** Size of the bit field. */
117 uint8_t cBits;
118 /** The parameter this decoder param contributes to. */
119 uint8_t idxParam;
120} DISARMV8INSNPARAM;
121typedef DISARMV8INSNPARAM *PDISARMV8INSNPARAM;
122typedef const DISARMV8INSNPARAM *PCDISARMV8INSNPARAM;
123
124#define DIS_ARMV8_INSN_DECODE_TERM { kDisParmParseNop, 0, 0, DIS_ARMV8_INSN_PARAM_UNSET }
125#define DIS_ARMV8_INSN_DECODE(a_idxParse, a_idxBitStart, a_cBits, a_idxParam) \
126 { a_idxParse, a_idxBitStart, a_cBits, a_idxParam }
127
128#define DIS_ARMV8_INSN_PARAM_UNSET UINT8_MAX
129
130
131/**
132 * Opcode structure.
133 */
134typedef struct DISARMV8OPCODE
135{
136 /** The value of the fixed bits of the instruction. */
137 uint32_t fValue;
138 /** Special flags for the opcode. */
139 uint32_t fFlags;
140 /** Pointer to an alternative decoder overriding the default one for the instruction class. */
141 PCDISARMV8INSNPARAM paDecode;
142 /** The generic opcode structure. */
143 DISOPCODE Opc;
144} DISARMV8OPCODE;
145/** Pointer to a const opcode. */
146typedef const DISARMV8OPCODE *PCDISARMV8OPCODE;
147
148
149/**
150 * Opcode decode index.
151 */
152typedef enum DISARMV8OPCDECODE
153{
154 kDisArmV8OpcDecodeNop = 0,
155 kDisArmV8OpcDecodeLookup,
156 kDisArmV8OpcDecodeCollate,
157 kDisArmV8OpcDecodeMax
158} DISARMV8OPCDECODE;
159
160
161/**
162 * Decoder stage type.
163 */
164typedef enum kDisArmV8DecodeType
165{
166 kDisArmV8DecodeType_Invalid = 0,
167 kDisArmV8DecodeType_Map,
168 kDisArmV8DecodeType_Table,
169 kDisArmV8DecodeType_InsnClass,
170 kDisArmV8DecodeType_32Bit_Hack = 0x7fffffff
171} kDisArmV8DecodeType;
172
173
174/**
175 * Decode header.
176 */
177typedef struct DISARMV8DECODEHDR
178{
179 /** Next stage decoding type. */
180 kDisArmV8DecodeType enmDecodeType;
181 /** Number of entries in the next decoder stage or
182 * opcodes in the instruction class. */
183 uint32_t cDecode;
184} DISARMV8DECODEHDR;
185/** Pointer to a decode header. */
186typedef DISARMV8DECODEHDR *PDISARMV8DECODEHDR;
187/** Pointer to a const decode header. */
188typedef const DISARMV8DECODEHDR *PCDISARMV8DECODEHDR;
189typedef const PCDISARMV8DECODEHDR *PPCDISARMV8DECODEHDR;
190
191
192/**
193 * Instruction class descriptor.
194 */
195typedef struct DISARMV8INSNCLASS
196{
197 /** Decoder header. */
198 DISARMV8DECODEHDR Hdr;
199 /** Pointer to the arry of opcodes. */
200 PCDISARMV8OPCODE paOpcodes;
201 /** The mask of fixed instruction bits. */
202 uint32_t fFixedInsn;
203 /** Opcode decoder function. */
204 DISARMV8OPCDECODE enmOpcDecode;
205 /** The mask of the bits relevant for decoding. */
206 uint32_t fMask;
207 /** Number of bits to shift to get an index. */
208 uint32_t cShift;
209 /** The array of decoding steps. */
210 PCDISARMV8INSNPARAM paParms;
211} DISARMV8INSNCLASS;
212/** Pointer to a constant instruction class descriptor. */
213typedef const DISARMV8INSNCLASS *PCDISARMV8INSNCLASS;
214
215/** The N bit in an N:ImmR:ImmS bit vector must be 1 for 64-bit instruction variants. */
216#define DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT RT_BIT_32(1)
217/** The instruction class is using the 64-bit register encoding only. */
218#define DISARMV8INSNCLASS_F_FORCED_64BIT RT_BIT_32(2)
219/** The instruction class is using the 32-bit register encoding only. */
220#define DISARMV8INSNCLASS_F_FORCED_32BIT RT_BIT_32(3)
221
222
223#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(a_Name) \
224 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = {
225#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(a_Name) \
226 DIS_ARMV8_INSN_DECODE_TERM \
227 }; \
228 static const DISARMV8INSNPARAM g_aArmV8A64Insn ## a_Name ## Decode[] = {
229#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(a_Name) \
230 DIS_ARMV8_INSN_DECODE_TERM \
231 }; \
232 static const DISARMV8OPCODE g_aArmV8A64Insn ## a_Name ## Opcodes[] = {
233#define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(a_Name, a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift) \
234 }; \
235 static const DISARMV8INSNCLASS g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_InsnClass, \
236 RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## Opcodes) }, \
237 & g_aArmV8A64Insn ## a_Name ## Opcodes[0], \
238 a_fFixedInsn, a_enmOpcDecode, a_fMask, a_cShift, \
239 & g_aArmV8A64Insn ## a_Name ## Decode[0] }
240
241/**
242 * Decoder lookup table entry.
243 */
244typedef struct DISARMV8DECODETBLENTRY
245{
246 /** The mask to apply to the instruction. */
247 uint32_t fMask;
248 /** The value the masked instruction must match for the entry to match. */
249 uint32_t fValue;
250 /** The next stage followed when there is a match. */
251 PCDISARMV8DECODEHDR pHdrNext;
252} DISARMV8DECODETBLENTRY;
253typedef struct DISARMV8DECODETBLENTRY *PDISARMV8DECODETBLENTRY;
254typedef const DISARMV8DECODETBLENTRY *PCDISARMV8DECODETBLENTRY;
255
256
257#define DIS_ARMV8_DECODE_TBL_ENTRY_INIT(a_fMask, a_fValue, a_pNext) \
258 { a_fMask, a_fValue, & g_aArmV8A64Insn ## a_pNext.Hdr }
259
260
261/**
262 * Decoder lookup table using masks and values.
263 */
264typedef struct DISARMV8DECODETBL
265{
266 /** The header for the decoder lookup table. */
267 DISARMV8DECODEHDR Hdr;
268 /** Pointer to the individual entries. */
269 PCDISARMV8DECODETBLENTRY paEntries;
270} DISARMV8DECODETBL;
271/** Pointer to a const decode table. */
272typedef const struct DISARMV8DECODETBL *PCDISARMV8DECODETBL;
273
274
275#define DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(a_Name) \
276 static const DISARMV8DECODETBLENTRY g_aArmV8A64Insn ## a_Name ## TblEnt[] = {
277
278#define DIS_ARMV8_DECODE_TBL_DEFINE_END(a_Name) \
279 }; \
280 static const DISARMV8DECODETBL g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Table, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## TblEnt) }, \
281 & g_aArmV8A64Insn ## a_Name ## TblEnt[0] }
282
283
284/**
285 * Decoder map when direct indexing is possible.
286 */
287typedef struct DISARMV8DECODEMAP
288{
289 /** The header for the decoder map. */
290 DISARMV8DECODEHDR Hdr;
291 /** The bitmask used to decide where to go next. */
292 uint32_t fMask;
293 /** Amount to shift to get at the index. */
294 uint32_t cShift;
295 /** Pointer to the array of pointers to the next stage to index into. */
296 PPCDISARMV8DECODEHDR papNext;
297} DISARMV8DECODEMAP;
298/** Pointer to a const decode map. */
299typedef const struct DISARMV8DECODEMAP *PCDISARMV8DECODEMAP;
300
301#define DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(a_Name) \
302 static const PCDISARMV8DECODEHDR g_aArmV8A64Insn ## a_Name ## MapHdrs[] = {
303
304#define DIS_ARMV8_DECODE_MAP_DEFINE_END(a_Name, a_fMask, a_cShift) \
305 }; \
306 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
307 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
308
309#define DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(a_Name, a_idxBit) \
310 }; \
311 static const DISARMV8DECODEMAP g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
312 RT_BIT_32(a_idxBit), a_idxBit, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
313
314
315#define DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(a_Name, a_fMask, a_cShift) \
316 }; \
317 DECL_HIDDEN_CONST(DISARMV8DECODEMAP) g_aArmV8A64Insn ## a_Name = { { kDisArmV8DecodeType_Map, RT_ELEMENTS(g_aArmV8A64Insn ## a_Name ## MapHdrs) }, \
318 a_fMask, a_cShift, & g_aArmV8A64Insn ## a_Name ## MapHdrs[0] }
319
320#define DIS_ARMV8_DECODE_MAP_INVALID_ENTRY NULL
321#define DIS_ARMV8_DECODE_MAP_ENTRY(a_Next) & g_aArmV8A64Insn ## a_Next.Hdr
322
323
324/** @name Decoder maps.
325 * @{ */
326extern DECL_HIDDEN_DATA(DISOPCODE) g_ArmV8A64InvalidOpcode[1];
327
328extern DECL_HIDDEN_DATA(DISARMV8DECODEMAP) g_aArmV8A64InsnDecodeL0;
329/** @} */
330
331
332/** @} */
333#endif /* !VBOX_INCLUDED_SRC_DisasmInternal_armv8_h */
334
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