DisasmFormatYasm.cpp@ 46860

Last change on this file since 46860 was 46177, checked in by vboxsync, 11 years ago
More symbols in disassembly, for PATM esp.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 62.8 KB

Line
1	/* $Id: DisasmFormatYasm.cpp 46177 2013-05-20 21:12:43Z vboxsync $ */
2	/** @file
3	* VBox Disassembler - Yasm(/Nasm) Style Formatter.
4	*/
5
6	/*
7	* Copyright (C) 2008-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#include <VBox/dis.h>
23	#include "DisasmInternal.h"
24	#include <iprt/string.h>
25	#include <iprt/assert.h>
26	#include <iprt/ctype.h>
27
28
29	/*******************************************************************************
30	* Global Variables *
31	*******************************************************************************/
32	static const char g_szSpaces[] =
33	" ";
34	static const char g_aszYasmRegGen8[20][5] =
35	{
36	"al\0\0", "cl\0\0", "dl\0\0", "bl\0\0", "ah\0\0", "ch\0\0", "dh\0\0", "bh\0\0", "r8b\0", "r9b\0", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", "spl\0", "bpl\0", "sil\0", "dil\0"
37	};
38	static const char g_aszYasmRegGen16[16][5] =
39	{
40	"ax\0\0", "cx\0\0", "dx\0\0", "bx\0\0", "sp\0\0", "bp\0\0", "si\0\0", "di\0\0", "r8w\0", "r9w\0", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
41	};
42	static const char g_aszYasmRegGen1616[8][6] =
43	{
44	"bx+si", "bx+di", "bp+si", "bp+di", "si\0\0\0", "di\0\0\0", "bp\0\0\0", "bx\0\0\0"
45	};
46	static const char g_aszYasmRegGen32[16][5] =
47	{
48	"eax\0", "ecx\0", "edx\0", "ebx\0", "esp\0", "ebp\0", "esi\0", "edi\0", "r8d\0", "r9d\0", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
49	};
50	static const char g_aszYasmRegGen64[16][4] =
51	{
52	"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8\0", "r9\0", "r10", "r11", "r12", "r13", "r14", "r15"
53	};
54	static const char g_aszYasmRegSeg[6][3] =
55	{
56	"es", "cs", "ss", "ds", "fs", "gs"
57	};
58	static const char g_aszYasmRegFP[8][4] =
59	{
60	"st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"
61	};
62	static const char g_aszYasmRegMMX[8][4] =
63	{
64	"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"
65	};
66	static const char g_aszYasmRegXMM[16][6] =
67	{
68	"xmm0\0", "xmm1\0", "xmm2\0", "xmm3\0", "xmm4\0", "xmm5\0", "xmm6\0", "xmm7\0", "xmm8\0", "xmm9\0", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
69	};
70	static const char g_aszYasmRegCRx[16][5] =
71	{
72	"cr0\0", "cr1\0", "cr2\0", "cr3\0", "cr4\0", "cr5\0", "cr6\0", "cr7\0", "cr8\0", "cr9\0", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
73	};
74	static const char g_aszYasmRegDRx[16][5] =
75	{
76	"dr0\0", "dr1\0", "dr2\0", "dr3\0", "dr4\0", "dr5\0", "dr6\0", "dr7\0", "dr8\0", "dr9\0", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
77	};
78	static const char g_aszYasmRegTRx[16][5] =
79	{
80	"tr0\0", "tr1\0", "tr2\0", "tr3\0", "tr4\0", "tr5\0", "tr6\0", "tr7\0", "tr8\0", "tr9\0", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"
81	};
82
83
84
85	/**
86	* Gets the base register name for the given parameter.
87	*
88	* @returns Pointer to the register name.
89	* @param pDis The disassembler state.
90	* @param pParam The parameter.
91	* @param pcchReg Where to store the length of the name.
92	*/
93	static const char disasmFormatYasmBaseReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t pcchReg)
94	{
95	switch (pParam->fUse & ( DISUSE_REG_GEN8 \| DISUSE_REG_GEN16 \| DISUSE_REG_GEN32 \| DISUSE_REG_GEN64
96	\| DISUSE_REG_FP \| DISUSE_REG_MMX \| DISUSE_REG_XMM \| DISUSE_REG_CR
97	\| DISUSE_REG_DBG \| DISUSE_REG_SEG \| DISUSE_REG_TEST))
98
99	{
100	case DISUSE_REG_GEN8:
101	{
102	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen8));
103	const char *psz = g_aszYasmRegGen8[pParam->Base.idxGenReg];
104	*pcchReg = 2 + !!psz[2] + !!psz[3];
105	return psz;
106	}
107
108	case DISUSE_REG_GEN16:
109	{
110	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
111	const char *psz = g_aszYasmRegGen16[pParam->Base.idxGenReg];
112	*pcchReg = 2 + !!psz[2] + !!psz[3];
113	return psz;
114	}
115
116	case DISUSE_REG_GEN32:
117	{
118	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
119	const char *psz = g_aszYasmRegGen32[pParam->Base.idxGenReg];
120	*pcchReg = 2 + !!psz[2] + !!psz[3];
121	return psz;
122	}
123
124	case DISUSE_REG_GEN64:
125	{
126	Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
127	const char *psz = g_aszYasmRegGen64[pParam->Base.idxGenReg];
128	*pcchReg = 2 + !!psz[2] + !!psz[3];
129	return psz;
130	}
131
132	case DISUSE_REG_FP:
133	{
134	Assert(pParam->Base.idxFpuReg < RT_ELEMENTS(g_aszYasmRegFP));
135	const char *psz = g_aszYasmRegFP[pParam->Base.idxFpuReg];
136	*pcchReg = 3;
137	return psz;
138	}
139
140	case DISUSE_REG_MMX:
141	{
142	Assert(pParam->Base.idxMmxReg < RT_ELEMENTS(g_aszYasmRegMMX));
143	const char *psz = g_aszYasmRegMMX[pParam->Base.idxMmxReg];
144	*pcchReg = 3;
145	return psz;
146	}
147
148	case DISUSE_REG_XMM:
149	{
150	Assert(pParam->Base.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
151	const char *psz = g_aszYasmRegXMM[pParam->Base.idxMmxReg];
152	*pcchReg = 4 + !!psz[4];
153	return psz;
154	}
155
156	case DISUSE_REG_CR:
157	{
158	Assert(pParam->Base.idxCtrlReg < RT_ELEMENTS(g_aszYasmRegCRx));
159	const char *psz = g_aszYasmRegCRx[pParam->Base.idxCtrlReg];
160	*pcchReg = 3;
161	return psz;
162	}
163
164	case DISUSE_REG_DBG:
165	{
166	Assert(pParam->Base.idxDbgReg < RT_ELEMENTS(g_aszYasmRegDRx));
167	const char *psz = g_aszYasmRegDRx[pParam->Base.idxDbgReg];
168	*pcchReg = 3;
169	return psz;
170	}
171
172	case DISUSE_REG_SEG:
173	{
174	Assert(pParam->Base.idxSegReg < RT_ELEMENTS(g_aszYasmRegCRx));
175	const char *psz = g_aszYasmRegSeg[pParam->Base.idxSegReg];
176	*pcchReg = 2;
177	return psz;
178	}
179
180	case DISUSE_REG_TEST:
181	{
182	Assert(pParam->Base.idxTestReg < RT_ELEMENTS(g_aszYasmRegTRx));
183	const char *psz = g_aszYasmRegTRx[pParam->Base.idxTestReg];
184	*pcchReg = 3;
185	return psz;
186	}
187
188	default:
189	AssertMsgFailed(("%#x\n", pParam->fUse));
190	*pcchReg = 3;
191	return "r??";
192	}
193	}
194
195
196	/**
197	* Gets the index register name for the given parameter.
198	*
199	* @returns The index register name.
200	* @param pDis The disassembler state.
201	* @param pParam The parameter.
202	* @param pcchReg Where to store the length of the name.
203	*/
204	static const char disasmFormatYasmIndexReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t pcchReg)
205	{
206	switch (pDis->uAddrMode)
207	{
208	case DISCPUMODE_16BIT:
209	{
210	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
211	const char *psz = g_aszYasmRegGen16[pParam->Index.idxGenReg];
212	*pcchReg = 2 + !!psz[2] + !!psz[3];
213	return psz;
214	}
215
216	case DISCPUMODE_32BIT:
217	{
218	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
219	const char *psz = g_aszYasmRegGen32[pParam->Index.idxGenReg];
220	*pcchReg = 2 + !!psz[2] + !!psz[3];
221	return psz;
222	}
223
224	case DISCPUMODE_64BIT:
225	{
226	Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
227	const char *psz = g_aszYasmRegGen64[pParam->Index.idxGenReg];
228	*pcchReg = 2 + !!psz[2] + !!psz[3];
229	return psz;
230	}
231
232	default:
233	AssertMsgFailed(("%#x %#x\n", pParam->fUse, pDis->uAddrMode));
234	*pcchReg = 3;
235	return "r??";
236	}
237	}
238
239
240	/**
241	* Formats the current instruction in Yasm (/ Nasm) style.
242	*
243	*
244	* @returns The number of output characters. If this is >= cchBuf, then the content
245	* of pszBuf will be truncated.
246	* @param pDis Pointer to the disassembler state.
247	* @param pszBuf The output buffer.
248	* @param cchBuf The size of the output buffer.
249	* @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
250	* @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
251	* @param pvUser User argument for pfnGetSymbol.
252	*/
253	DISDECL(size_t) DISFormatYasmEx(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags,
254	PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
255	{
256	/*
257	* Input validation and massaging.
258	*/
259	AssertPtr(pDis);
260	AssertPtrNull(pszBuf);
261	Assert(pszBuf \|\| !cchBuf);
262	AssertPtrNull(pfnGetSymbol);
263	AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
264	if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
265	fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) \| DIS_FMT_FLAGS_ADDR_RIGHT;
266	if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
267	fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) \| DIS_FMT_FLAGS_BYTES_RIGHT;
268
269	PCDISOPCODE const pOp = pDis->pCurInstr;
270
271	/*
272	* Output macros
273	*/
274	char *pszDst = pszBuf;
275	size_t cchDst = cchBuf;
276	size_t cchOutput = 0;
277	#define PUT_C(ch) \
278	do { \
279	cchOutput++; \
280	if (cchDst > 1) \
281	{ \
282	cchDst--; \
283	*pszDst++ = (ch); \
284	} \
285	} while (0)
286	#define PUT_STR(pszSrc, cchSrc) \
287	do { \
288	cchOutput += (cchSrc); \
289	if (cchDst > (cchSrc)) \
290	{ \
291	memcpy(pszDst, (pszSrc), (cchSrc)); \
292	pszDst += (cchSrc); \
293	cchDst -= (cchSrc); \
294	} \
295	else if (cchDst > 1) \
296	{ \
297	memcpy(pszDst, (pszSrc), cchDst - 1); \
298	pszDst += cchDst - 1; \
299	cchDst = 1; \
300	} \
301	} while (0)
302	#define PUT_SZ(sz) \
303	PUT_STR((sz), sizeof(sz) - 1)
304	#define PUT_SZ_STRICT(szStrict, szRelaxed) \
305	do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
306	#define PUT_PSZ(psz) \
307	do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
308	#define PUT_NUM(cch, fmt, num) \
309	do { \
310	cchOutput += (cch); \
311	if (cchDst > 1) \
312	{ \
313	const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
314	pszDst += cchTmp; \
315	cchDst -= cchTmp; \
316	Assert(cchTmp == (cch) \|\| cchDst == 1); \
317	} \
318	} while (0)
319	/** @todo add two flags for choosing between %X / %x and h / 0x. */
320	#define PUT_NUM_8(num) PUT_NUM(4, "0%02xh", (uint8_t)(num))
321	#define PUT_NUM_16(num) PUT_NUM(6, "0%04xh", (uint16_t)(num))
322	#define PUT_NUM_32(num) PUT_NUM(10, "0%08xh", (uint32_t)(num))
323	#define PUT_NUM_64(num) PUT_NUM(18, "0%016RX64h", (uint64_t)(num))
324
325	#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
326	do { \
327	if ((stype)(num) >= 0) \
328	{ \
329	PUT_C('+'); \
330	PUT_NUM(cch, fmt, (utype)(num)); \
331	} \
332	else \
333	{ \
334	PUT_C('-'); \
335	PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
336	} \
337	} while (0)
338	#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, "0%02xh", num, int8_t, uint8_t)
339	#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, "0%04xh", num, int16_t, uint16_t)
340	#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, "0%08xh", num, int32_t, uint32_t)
341	#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, "0%016RX64h", num, int64_t, uint64_t)
342
343	#define PUT_SYMBOL_TWO(a_rcSym, a_szStart, a_chEnd) \
344	do { \
345	if (RT_SUCCESS(a_rcSym)) \
346	{ \
347	PUT_SZ(a_szStart); \
348	PUT_PSZ(szSymbol); \
349	if (off != 0) \
350	{ \
351	if ((int8_t)off == off) \
352	PUT_NUM_S8(off); \
353	else if ((int16_t)off == off) \
354	PUT_NUM_S16(off); \
355	else if ((int32_t)off == off) \
356	PUT_NUM_S32(off); \
357	else \
358	PUT_NUM_S64(off); \
359	} \
360	PUT_C(a_chEnd); \
361	} \
362	} while (0)
363
364	#define PUT_SYMBOL(a_uSeg, a_uAddr, a_szStart, a_chEnd) \
365	do { \
366	if (pfnGetSymbol) \
367	{ \
368	int rcSym = pfnGetSymbol(pDis, a_uSeg, a_uAddr, szSymbol, sizeof(szSymbol), &off, pvUser); \
369	PUT_SYMBOL_TWO(rcSym, a_szStart, a_chEnd); \
370	} \
371	} while (0)
372
373
374	/*
375	* The address?
376	*/
377	if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
378	{
379	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
380	if (pDis->uInstrAddr >= _4G)
381	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
382	#endif
383	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
384	PUT_C(' ');
385	}
386
387	/*
388	* The opcode bytes?
389	*/
390	if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
391	{
392	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
393	cchOutput += cchTmp;
394	if (cchDst > 1)
395	{
396	if (cchTmp <= cchDst)
397	{
398	cchDst -= cchTmp;
399	pszDst += cchTmp;
400	}
401	else
402	{
403	pszDst += cchDst - 1;
404	cchDst = 1;
405	}
406	}
407
408	/* Some padding to align the instruction. */
409	size_t cchPadding = (7 * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
410	+ !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
411	+ 2;
412	cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
413	PUT_STR(g_szSpaces, cchPadding);
414	}
415
416
417	/*
418	* Filter out invalid opcodes first as they need special
419	* treatment. UD2 is an exception and should be handled normally.
420	*/
421	size_t const offInstruction = cchOutput;
422	if ( pOp->uOpcode == OP_INVALID
423	\|\| ( pOp->uOpcode == OP_ILLUD2
424	&& (pDis->fPrefix & DISPREFIX_LOCK)))
425	PUT_SZ("Illegal opcode");
426	else
427	{
428	/*
429	* Prefixes
430	*/
431	if (pDis->fPrefix & DISPREFIX_LOCK)
432	PUT_SZ("lock ");
433	if(pDis->fPrefix & DISPREFIX_REP)
434	PUT_SZ("rep ");
435	else if(pDis->fPrefix & DISPREFIX_REPNE)
436	PUT_SZ("repne ");
437
438	/*
439	* Adjust the format string to the correct mnemonic
440	* or to avoid things the assembler cannot handle correctly.
441	*/
442	char szTmpFmt[48];
443	const char *pszFmt = pOp->pszOpcode;
444	switch (pOp->uOpcode)
445	{
446	case OP_JECXZ:
447	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "jcxz %Jb" : pDis->uOpMode == DISCPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb";
448	break;
449	case OP_PUSHF:
450	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "pushfw" : pDis->uOpMode == DISCPUMODE_32BIT ? "pushfd" : "pushfq";
451	break;
452	case OP_POPF:
453	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "popfw" : pDis->uOpMode == DISCPUMODE_32BIT ? "popfd" : "popfq";
454	break;
455	case OP_PUSHA:
456	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "pushaw" : "pushad";
457	break;
458	case OP_POPA:
459	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "popaw" : "popad";
460	break;
461	case OP_INSB:
462	pszFmt = "insb";
463	break;
464	case OP_INSWD:
465	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "insw" : pDis->uOpMode == DISCPUMODE_32BIT ? "insd" : "insq";
466	break;
467	case OP_OUTSB:
468	pszFmt = "outsb";
469	break;
470	case OP_OUTSWD:
471	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "outsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "outsd" : "outsq";
472	break;
473	case OP_MOVSB:
474	pszFmt = "movsb";
475	break;
476	case OP_MOVSWD:
477	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "movsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "movsd" : "movsq";
478	break;
479	case OP_CMPSB:
480	pszFmt = "cmpsb";
481	break;
482	case OP_CMPWD:
483	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cmpsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "cmpsd" : "cmpsq";
484	break;
485	case OP_SCASB:
486	pszFmt = "scasb";
487	break;
488	case OP_SCASWD:
489	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "scasw" : pDis->uOpMode == DISCPUMODE_32BIT ? "scasd" : "scasq";
490	break;
491	case OP_LODSB:
492	pszFmt = "lodsb";
493	break;
494	case OP_LODSWD:
495	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "lodsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "lodsd" : "lodsq";
496	break;
497	case OP_STOSB:
498	pszFmt = "stosb";
499	break;
500	case OP_STOSWD:
501	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "stosw" : pDis->uOpMode == DISCPUMODE_32BIT ? "stosd" : "stosq";
502	break;
503	case OP_CBW:
504	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cbw" : pDis->uOpMode == DISCPUMODE_32BIT ? "cwde" : "cdqe";
505	break;
506	case OP_CWD:
507	pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cwd" : pDis->uOpMode == DISCPUMODE_32BIT ? "cdq" : "cqo";
508	break;
509	case OP_SHL:
510	Assert(pszFmt[3] == '/');
511	pszFmt += 4;
512	break;
513	case OP_XLAT:
514	pszFmt = "xlatb";
515	break;
516	case OP_INT3:
517	pszFmt = "int3";
518	break;
519
520	/*
521	* Don't know how to tell yasm to generate complicated nop stuff, so 'db' it.
522	*/
523	case OP_NOP:
524	if (pDis->bOpCode == 0x90)
525	/* fine, fine */;
526	else if (pszFmt[sizeof("nop %Ev") - 1] == '/' && pszFmt[sizeof("nop %Ev")] == 'p')
527	pszFmt = "prefetch %Eb";
528	else if (pDis->bOpCode == 0x1f)
529	{
530	Assert(pDis->cbInstr >= 3);
531	PUT_SZ("db 00fh, 01fh,");
532	PUT_NUM_8(MAKE_MODRM(pDis->ModRM.Bits.Mod, pDis->ModRM.Bits.Reg, pDis->ModRM.Bits.Rm));
533	for (unsigned i = 3; i < pDis->cbInstr; i++)
534	{
535	PUT_C(',');
536	PUT_NUM_8(0x90); ///@todo fixme.
537	}
538	pszFmt = "";
539	}
540	break;
541
542	default:
543	/* ST(X) -> stX (floating point) */
544	if (*pszFmt == 'f' && strchr(pszFmt, '('))
545	{
546	char *pszFmtDst = szTmpFmt;
547	char ch;
548	do
549	{
550	ch = *pszFmt++;
551	if (ch == 'S' && pszFmt[0] == 'T' && pszFmt[1] == '(')
552	{
553	*pszFmtDst++ = 's';
554	*pszFmtDst++ = 't';
555	pszFmt += 2;
556	ch = *pszFmt;
557	Assert(pszFmt[1] == ')');
558	pszFmt += 2;
559	*pszFmtDst++ = ch;
560	}
561	else
562	*pszFmtDst++ = ch;
563	} while (ch != '\0');
564	pszFmt = szTmpFmt;
565	}
566	break;
567
568	/*
569	* Horrible hacks.
570	*/
571	case OP_FLD:
572	if (pDis->bOpCode == 0xdb) /* m80fp workaround. */
573	(int )&pDis->Param1.fParam &= ~0x1f; /* make it pure OP_PARM_M */
574	break;
575	case OP_LAR: /* hack w -> v, probably not correct. */
576	(int )&pDis->Param2.fParam &= ~0x1f;
577	(int )&pDis->Param2.fParam \|= OP_PARM_v;
578	break;
579	}
580
581	/*
582	* Formatting context and associated macros.
583	*/
584	PCDISOPPARAM pParam = &pDis->Param1;
585	int iParam = 1;
586
587	#define PUT_FAR() \
588	do { \
589	if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_p \
590	&& pOp->uOpcode != OP_LDS /* table bugs? */ \
591	&& pOp->uOpcode != OP_LES \
592	&& pOp->uOpcode != OP_LFS \
593	&& pOp->uOpcode != OP_LGS \
594	&& pOp->uOpcode != OP_LSS ) \
595	PUT_SZ("far "); \
596	} while (0)
597	/** @todo mov ah,ch ends up with a byte 'override'... - check if this wasn't fixed. */
598	/** @todo drop the work/dword/qword override when the src/dst is a register (except for movsx/movzx). */
599	#define PUT_SIZE_OVERRIDE() \
600	do { \
601	switch (OP_PARM_VSUBTYPE(pParam->fParam)) \
602	{ \
603	case OP_PARM_v: \
604	switch (pDis->uOpMode) \
605	{ \
606	case DISCPUMODE_16BIT: PUT_SZ("word "); break; \
607	case DISCPUMODE_32BIT: PUT_SZ("dword "); break; \
608	case DISCPUMODE_64BIT: PUT_SZ("qword "); break; \
609	default: break; \
610	} \
611	break; \
612	case OP_PARM_b: PUT_SZ("byte "); break; \
613	case OP_PARM_w: PUT_SZ("word "); break; \
614	case OP_PARM_d: PUT_SZ("dword "); break; \
615	case OP_PARM_q: PUT_SZ("qword "); break; \
616	case OP_PARM_dq: \
617	if (OP_PARM_VTYPE(pParam->fParam) != OP_PARM_W) /* these are 128 bit, pray they are all unambiguous.. */ \
618	PUT_SZ("qword "); \
619	break; \
620	case OP_PARM_p: break; /* see PUT_FAR */ \
621	case OP_PARM_s: if (pParam->fUse & DISUSE_REG_FP) PUT_SZ("tword "); break; /* ?? */ \
622	case OP_PARM_z: break; \
623	case OP_PARM_NONE: \
624	if ( OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M \
625	&& ((pParam->fUse & DISUSE_REG_FP) \|\| pOp->uOpcode == OP_FLD)) \
626	PUT_SZ("tword "); \
627	break; \
628	default: break; /no pointer type specified/necessary/ \
629	} \
630	} while (0)
631	static const char s_szSegPrefix[6][4] = { "es:", "cs:", "ss:", "ds:", "fs:", "gs:" };
632	#define PUT_SEGMENT_OVERRIDE() \
633	do { \
634	if (pDis->fPrefix & DISPREFIX_SEG) \
635	PUT_STR(s_szSegPrefix[pDis->idxSegPrefix], 3); \
636	} while (0)
637
638
639	/*
640	* Segment prefixing for instructions that doesn't do memory access.
641	*/
642	if ( (pDis->fPrefix & DISPREFIX_SEG)
643	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
644	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
645	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
646	{
647	PUT_STR(s_szSegPrefix[pDis->idxSegPrefix], 2);
648	PUT_C(' ');
649	}
650
651
652	/*
653	* The formatting loop.
654	*/
655	RTINTPTR off;
656	char szSymbol[128];
657	char ch;
658	while ((ch = *pszFmt++) != '\0')
659	{
660	if (ch == '%')
661	{
662	ch = *pszFmt++;
663	switch (ch)
664	{
665	/*
666	* ModRM - Register only.
667	*/
668	case 'C': /* Control register (ParseModRM / UseModRM). */
669	case 'D': /* Debug register (ParseModRM / UseModRM). */
670	case 'G': /* ModRM selects general register (ParseModRM / UseModRM). */
671	case 'S': /* ModRM byte selects a segment register (ParseModRM / UseModRM). */
672	case 'T': /* ModRM byte selects a test register (ParseModRM / UseModRM). */
673	case 'V': /* ModRM byte selects an XMM/SSE register (ParseModRM / UseModRM). */
674	case 'P': /* ModRM byte selects MMX register (ParseModRM / UseModRM). */
675	{
676	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
677	Assert(!(pParam->fUse & (DISUSE_INDEX \| DISUSE_SCALE) /* No SIB here... */));
678	Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)));
679
680	size_t cchReg;
681	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
682	PUT_STR(pszReg, cchReg);
683	break;
684	}
685
686	/*
687	* ModRM - Register or memory.
688	*/
689	case 'E': /* ModRM specifies parameter (ParseModRM / UseModRM / UseSIB). */
690	case 'Q': /* ModRM byte selects MMX register or memory address (ParseModRM / UseModRM). */
691	case 'R': /* ModRM byte may only refer to a general register (ParseModRM / UseModRM). */
692	case 'W': /* ModRM byte selects an XMM/SSE register or a memory address (ParseModRM / UseModRM). */
693	case 'M': /* ModRM may only refer to memory (ParseModRM / UseModRM). */
694	{
695	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
696
697	PUT_FAR();
698	uint32_t const fUse = pParam->fUse;
699	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
700	{
701	/* Work around mov seg,[mem16] and mov [mem16],seg as these always make a 16-bit mem
702	while the register variants deals with 16, 32 & 64 in the normal fashion. */
703	if ( pParam->fParam != OP_PARM_Ev
704	\|\| pOp->uOpcode != OP_MOV
705	\|\| ( pOp->fParam1 != OP_PARM_Sw
706	&& pOp->fParam2 != OP_PARM_Sw))
707	PUT_SIZE_OVERRIDE();
708	PUT_C('[');
709	}
710	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
711	&& (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)))
712	{
713	if ( (fUse & DISUSE_DISPLACEMENT8)
714	&& !pParam->uDisp.i8)
715	PUT_SZ("byte ");
716	else if ( (fUse & DISUSE_DISPLACEMENT16)
717	&& (int8_t)pParam->uDisp.i16 == (int16_t)pParam->uDisp.i16)
718	PUT_SZ("word ");
719	else if ( (fUse & DISUSE_DISPLACEMENT32)
720	&& (int16_t)pParam->uDisp.i32 == (int32_t)pParam->uDisp.i32) //??
721	PUT_SZ("dword ");
722	else if ( (fUse & DISUSE_DISPLACEMENT64)
723	&& (pDis->SIB.Bits.Base != 5 \|\| pDis->ModRM.Bits.Mod != 0)
724	&& (int32_t)pParam->uDisp.i64 == (int64_t)pParam->uDisp.i64) //??
725	PUT_SZ("qword ");
726	}
727	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
728	PUT_SEGMENT_OVERRIDE();
729
730	bool fBase = (fUse & DISUSE_BASE) /* When exactly is DISUSE_BASE supposed to be set? disasmModRMReg doesn't set it. */
731	\|\| ( (fUse & ( DISUSE_REG_GEN8
732	\| DISUSE_REG_GEN16
733	\| DISUSE_REG_GEN32
734	\| DISUSE_REG_GEN64
735	\| DISUSE_REG_FP
736	\| DISUSE_REG_MMX
737	\| DISUSE_REG_XMM
738	\| DISUSE_REG_CR
739	\| DISUSE_REG_DBG
740	\| DISUSE_REG_SEG
741	\| DISUSE_REG_TEST ))
742	&& !DISUSE_IS_EFFECTIVE_ADDR(fUse));
743	if (fBase)
744	{
745	size_t cchReg;
746	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
747	PUT_STR(pszReg, cchReg);
748	}
749
750	if (fUse & DISUSE_INDEX)
751	{
752	if (fBase)
753	PUT_C('+');
754
755	size_t cchReg;
756	const char *pszReg = disasmFormatYasmIndexReg(pDis, pParam, &cchReg);
757	PUT_STR(pszReg, cchReg);
758
759	if (fUse & DISUSE_SCALE)
760	{
761	PUT_C('*');
762	PUT_C('0' + pParam->uScale);
763	}
764	}
765	else
766	Assert(!(fUse & DISUSE_SCALE));
767
768	int64_t off2 = 0;
769	if (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32))
770	{
771	if (fUse & DISUSE_DISPLACEMENT8)
772	off2 = pParam->uDisp.i8;
773	else if (fUse & DISUSE_DISPLACEMENT16)
774	off2 = pParam->uDisp.i16;
775	else if (fUse & (DISUSE_DISPLACEMENT32 \| DISUSE_RIPDISPLACEMENT32))
776	off2 = pParam->uDisp.i32;
777	else if (fUse & DISUSE_DISPLACEMENT64)
778	off2 = pParam->uDisp.i64;
779	else
780	{
781	AssertFailed();
782	off2 = 0;
783	}
784
785	if (fBase \|\| (fUse & DISUSE_INDEX))
786	{
787	PUT_C(off2 >= 0 ? '+' : '-');
788	if (off2 < 0)
789	off2 = -off2;
790	}
791	if (fUse & DISUSE_DISPLACEMENT8)
792	PUT_NUM_8( off2);
793	else if (fUse & DISUSE_DISPLACEMENT16)
794	PUT_NUM_16(off2);
795	else if (fUse & DISUSE_DISPLACEMENT32)
796	PUT_NUM_32(off2);
797	else if (fUse & DISUSE_DISPLACEMENT64)
798	PUT_NUM_64(off2);
799	else
800	{
801	PUT_NUM_32(off2);
802	PUT_SZ(" wrt rip"); //??
803	}
804	}
805
806	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
807	{
808	if (pfnGetSymbol && !fBase && !(fUse & DISUSE_INDEX) && off2 != 0)
809	PUT_SYMBOL((pDis->fPrefix & DISPREFIX_SEG)
810	? DIS_FMT_SEL_FROM_REG(pDis->idxSegPrefix)
811	: DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
812	pDis->uAddrMode == DISCPUMODE_64BIT
813	? (uint64_t)off2
814	: pDis->uAddrMode == DISCPUMODE_32BIT
815	? (uint32_t)off2
816	: (uint16_t)off2,
817	" (=", ')');
818	PUT_C(']');
819	}
820	break;
821	}
822
823	case 'F': /* Eflags register (0 - popf/pushf only, avoided in adjustments above). */
824	AssertFailed();
825	break;
826
827	case 'I': /* Immediate data (ParseImmByte, ParseImmByteSX, ParseImmV, ParseImmUshort, ParseImmZ). */
828	Assert(pszFmt == 'b' \|\| pszFmt == 'v' \|\| pszFmt == 'w' \|\| pszFmt == 'z'); pszFmt++;
829	switch (pParam->fUse & ( DISUSE_IMMEDIATE8 \| DISUSE_IMMEDIATE16 \| DISUSE_IMMEDIATE32 \| DISUSE_IMMEDIATE64
830	\| DISUSE_IMMEDIATE16_SX8 \| DISUSE_IMMEDIATE32_SX8 \| DISUSE_IMMEDIATE64_SX8))
831	{
832	case DISUSE_IMMEDIATE8:
833	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
834	&& ( (pOp->fParam1 >= OP_PARM_REG_GEN8_START && pOp->fParam1 <= OP_PARM_REG_GEN8_END)
835	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN8_START && pOp->fParam2 <= OP_PARM_REG_GEN8_END))
836	)
837	PUT_SZ("strict byte ");
838	PUT_NUM_8(pParam->uValue);
839	break;
840
841	case DISUSE_IMMEDIATE16:
842	if ( pDis->uCpuMode != pDis->uOpMode
843	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
844	&& ( (int8_t)pParam->uValue == (int16_t)pParam->uValue
845	\|\| (pOp->fParam1 >= OP_PARM_REG_GEN16_START && pOp->fParam1 <= OP_PARM_REG_GEN16_END)
846	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN16_START && pOp->fParam2 <= OP_PARM_REG_GEN16_END))
847	)
848	)
849	{
850	if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
851	PUT_SZ_STRICT("strict byte ", "byte ");
852	else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
853	\|\| OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
854	PUT_SZ_STRICT("strict word ", "word ");
855	}
856	PUT_NUM_16(pParam->uValue);
857	break;
858
859	case DISUSE_IMMEDIATE16_SX8:
860	if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
861	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
862	PUT_SZ_STRICT("strict byte ", "byte ");
863	else
864	PUT_SZ("word ");
865	PUT_NUM_16(pParam->uValue);
866	break;
867
868	case DISUSE_IMMEDIATE32:
869	if ( pDis->uOpMode != (pDis->uCpuMode == DISCPUMODE_16BIT ? DISCPUMODE_16BIT : DISCPUMODE_32BIT) /* not perfect */
870	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
871	&& ( (int8_t)pParam->uValue == (int32_t)pParam->uValue
872	\|\| (pOp->fParam1 >= OP_PARM_REG_GEN32_START && pOp->fParam1 <= OP_PARM_REG_GEN32_END)
873	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN32_START && pOp->fParam2 <= OP_PARM_REG_GEN32_END))
874	)
875	)
876	{
877	if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
878	PUT_SZ_STRICT("strict byte ", "byte ");
879	else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
880	\|\| OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
881	PUT_SZ_STRICT("strict dword ", "dword ");
882	}
883	PUT_NUM_32(pParam->uValue);
884	if (pDis->uCpuMode == DISCPUMODE_32BIT)
885	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uValue, " (=", ')');
886	break;
887
888	case DISUSE_IMMEDIATE32_SX8:
889	if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
890	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
891	PUT_SZ_STRICT("strict byte ", "byte ");
892	else
893	PUT_SZ("dword ");
894	PUT_NUM_32(pParam->uValue);
895	break;
896
897	case DISUSE_IMMEDIATE64_SX8:
898	if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
899	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
900	PUT_SZ_STRICT("strict byte ", "byte ");
901	else
902	PUT_SZ("qword ");
903	PUT_NUM_64(pParam->uValue);
904	break;
905
906	case DISUSE_IMMEDIATE64:
907	PUT_NUM_64(pParam->uValue);
908	break;
909
910	default:
911	AssertFailed();
912	break;
913	}
914	break;
915
916	case 'J': /* Relative jump offset (ParseImmBRel + ParseImmVRel). */
917	{
918	int32_t offDisplacement;
919	Assert(iParam == 1);
920	bool fPrefix = (fFlags & DIS_FMT_FLAGS_STRICT)
921	&& pOp->uOpcode != OP_CALL
922	&& pOp->uOpcode != OP_LOOP
923	&& pOp->uOpcode != OP_LOOPE
924	&& pOp->uOpcode != OP_LOOPNE
925	&& pOp->uOpcode != OP_JECXZ;
926	if (pOp->uOpcode == OP_CALL)
927	fFlags &= ~DIS_FMT_FLAGS_RELATIVE_BRANCH;
928
929	if (pParam->fUse & DISUSE_IMMEDIATE8_REL)
930	{
931	if (fPrefix)
932	PUT_SZ("short ");
933	offDisplacement = (int8_t)pParam->uValue;
934	Assert(*pszFmt == 'b'); pszFmt++;
935
936	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
937	PUT_NUM_S8(offDisplacement);
938	}
939	else if (pParam->fUse & DISUSE_IMMEDIATE16_REL)
940	{
941	if (fPrefix)
942	PUT_SZ("near ");
943	offDisplacement = (int16_t)pParam->uValue;
944	Assert(*pszFmt == 'v'); pszFmt++;
945
946	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
947	PUT_NUM_S16(offDisplacement);
948	}
949	else
950	{
951	if (fPrefix)
952	PUT_SZ("near ");
953	offDisplacement = (int32_t)pParam->uValue;
954	Assert(pParam->fUse & (DISUSE_IMMEDIATE32_REL \| DISUSE_IMMEDIATE64_REL));
955	Assert(*pszFmt == 'v'); pszFmt++;
956
957	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
958	PUT_NUM_S32(offDisplacement);
959	}
960	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
961	PUT_SZ(" (");
962
963	RTUINTPTR uTrgAddr = pDis->uInstrAddr + pDis->cbInstr + offDisplacement;
964	if (pDis->uCpuMode == DISCPUMODE_16BIT)
965	PUT_NUM_16(uTrgAddr);
966	else if (pDis->uCpuMode == DISCPUMODE_32BIT)
967	PUT_NUM_32(uTrgAddr);
968	else
969	PUT_NUM_64(uTrgAddr);
970
971	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
972	{
973	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " = ", ' ');
974	PUT_C(')');
975	}
976	else
977	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " (", ')');
978	break;
979	}
980
981	case 'A': /* Direct (jump/call) address (ParseImmAddr). */
982	{
983	Assert(*pszFmt == 'p'); pszFmt++;
984	PUT_FAR();
985	PUT_SIZE_OVERRIDE();
986	PUT_SEGMENT_OVERRIDE();
987	int rc = VERR_SYMBOL_NOT_FOUND;
988	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
989	{
990	case DISUSE_IMMEDIATE_ADDR_16_16:
991	PUT_NUM_16(pParam->uValue >> 16);
992	PUT_C(':');
993	PUT_NUM_16(pParam->uValue);
994	if (pfnGetSymbol)
995	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
996	break;
997	case DISUSE_IMMEDIATE_ADDR_16_32:
998	PUT_NUM_16(pParam->uValue >> 32);
999	PUT_C(':');
1000	PUT_NUM_32(pParam->uValue);
1001	if (pfnGetSymbol)
1002	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1003	break;
1004	case DISUSE_DISPLACEMENT16:
1005	PUT_NUM_16(pParam->uValue);
1006	if (pfnGetSymbol)
1007	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1008	break;
1009	case DISUSE_DISPLACEMENT32:
1010	PUT_NUM_32(pParam->uValue);
1011	if (pfnGetSymbol)
1012	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1013	break;
1014	case DISUSE_DISPLACEMENT64:
1015	PUT_NUM_64(pParam->uValue);
1016	if (pfnGetSymbol)
1017	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint64_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1018	break;
1019	default:
1020	AssertFailed();
1021	break;
1022	}
1023
1024	PUT_SYMBOL_TWO(rc, " [", ']');
1025	break;
1026	}
1027
1028	case 'O': /* No ModRM byte (ParseImmAddr). */
1029	{
1030	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1031	PUT_FAR();
1032	PUT_SIZE_OVERRIDE();
1033	PUT_C('[');
1034	PUT_SEGMENT_OVERRIDE();
1035	int rc = VERR_SYMBOL_NOT_FOUND;
1036	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
1037	{
1038	case DISUSE_IMMEDIATE_ADDR_16_16:
1039	PUT_NUM_16(pParam->uValue >> 16);
1040	PUT_C(':');
1041	PUT_NUM_16(pParam->uValue);
1042	if (pfnGetSymbol)
1043	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1044	break;
1045	case DISUSE_IMMEDIATE_ADDR_16_32:
1046	PUT_NUM_16(pParam->uValue >> 32);
1047	PUT_C(':');
1048	PUT_NUM_32(pParam->uValue);
1049	if (pfnGetSymbol)
1050	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1051	break;
1052	case DISUSE_DISPLACEMENT16:
1053	PUT_NUM_16(pParam->uDisp.i16);
1054	if (pfnGetSymbol)
1055	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u16, szSymbol, sizeof(szSymbol), &off, pvUser);
1056	break;
1057	case DISUSE_DISPLACEMENT32:
1058	PUT_NUM_32(pParam->uDisp.i32);
1059	if (pfnGetSymbol)
1060	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u32, szSymbol, sizeof(szSymbol), &off, pvUser);
1061	break;
1062	case DISUSE_DISPLACEMENT64:
1063	PUT_NUM_64(pParam->uDisp.i64);
1064	if (pfnGetSymbol)
1065	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u64, szSymbol, sizeof(szSymbol), &off, pvUser);
1066	break;
1067	default:
1068	AssertFailed();
1069	break;
1070	}
1071	PUT_C(']');
1072
1073	PUT_SYMBOL_TWO(rc, " (", ')');
1074	break;
1075	}
1076
1077	case 'X': /* DS:SI (ParseXb, ParseXv). */
1078	case 'Y': /* ES:DI (ParseYb, ParseYv). */
1079	{
1080	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1081	PUT_FAR();
1082	PUT_SIZE_OVERRIDE();
1083	PUT_C('[');
1084	if (pParam->fUse & DISUSE_POINTER_DS_BASED)
1085	PUT_SZ("ds:");
1086	else
1087	PUT_SZ("es:");
1088
1089	size_t cchReg;
1090	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1091	PUT_STR(pszReg, cchReg);
1092	PUT_C(']');
1093	break;
1094	}
1095
1096	case 'e': /* Register based on operand size (e.g. %eAX) (ParseFixedReg). */
1097	{
1098	Assert(RT_C_IS_ALPHA(pszFmt[0]) && RT_C_IS_ALPHA(pszFmt[1]) && !RT_C_IS_ALPHA(pszFmt[2])); pszFmt += 2;
1099	size_t cchReg;
1100	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1101	PUT_STR(pszReg, cchReg);
1102	break;
1103	}
1104
1105	default:
1106	AssertMsgFailed(("%c%s!\n", ch, pszFmt));
1107	break;
1108	}
1109	AssertMsg(pszFmt == ',' \|\| pszFmt == '\0', ("%c%s\n", ch, pszFmt));
1110	}
1111	else
1112	{
1113	PUT_C(ch);
1114	if (ch == ',')
1115	{
1116	Assert(*pszFmt != ' ');
1117	PUT_C(' ');
1118	switch (++iParam)
1119	{
1120	case 2: pParam = &pDis->Param2; break;
1121	case 3: pParam = &pDis->Param3; break;
1122	default: pParam = NULL; break;
1123	}
1124	}
1125	}
1126	} /* while more to format */
1127	}
1128
1129	/*
1130	* Any additional output to the right of the instruction?
1131	*/
1132	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1133	{
1134	/* some up front padding. */
1135	size_t cchPadding = cchOutput - offInstruction;
1136	cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
1137	PUT_STR(g_szSpaces, cchPadding);
1138
1139	/* comment? */
1140	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1141	PUT_SZ(";");
1142
1143	/*
1144	* The address?
1145	*/
1146	if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
1147	{
1148	PUT_C(' ');
1149	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
1150	if (pDis->uInstrAddr >= _4G)
1151	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
1152	#endif
1153	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
1154	}
1155
1156	/*
1157	* Opcode bytes?
1158	*/
1159	if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
1160	{
1161	PUT_C(' ');
1162	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
1163	cchOutput += cchTmp;
1164	if (cchTmp >= cchDst)
1165	cchTmp = cchDst - (cchDst != 0);
1166	cchDst -= cchTmp;
1167	pszDst += cchTmp;
1168	}
1169	}
1170
1171	/*
1172	* Terminate it - on overflow we'll have reserved one byte for this.
1173	*/
1174	if (cchDst > 0)
1175	*pszDst = '\0';
1176	else
1177	Assert(!cchBuf);
1178
1179	/* clean up macros */
1180	#undef PUT_PSZ
1181	#undef PUT_SZ
1182	#undef PUT_STR
1183	#undef PUT_C
1184	return cchOutput;
1185	}
1186
1187
1188	/**
1189	* Formats the current instruction in Yasm (/ Nasm) style.
1190	*
1191	* This is a simplified version of DISFormatYasmEx() provided for your convenience.
1192	*
1193	*
1194	* @returns The number of output characters. If this is >= cchBuf, then the content
1195	* of pszBuf will be truncated.
1196	* @param pDis Pointer to the disassembler state.
1197	* @param pszBuf The output buffer.
1198	* @param cchBuf The size of the output buffer.
1199	*/
1200	DISDECL(size_t) DISFormatYasm(PCDISSTATE pDis, char *pszBuf, size_t cchBuf)
1201	{
1202	return DISFormatYasmEx(pDis, pszBuf, cchBuf, 0 /* fFlags /, NULL / pfnGetSymbol /, NULL / pvUser */);
1203	}
1204
1205
1206	/**
1207	* Checks if the encoding of the given disassembled instruction is something we
1208	* can never get YASM to produce.
1209	*
1210	* @returns true if it's odd, false if it isn't.
1211	* @param pDis The disassembler output. The byte fetcher callback will
1212	* be used if present as we might need to fetch opcode
1213	* bytes.
1214	*/
1215	DISDECL(bool) DISFormatYasmIsOddEncoding(PDISSTATE pDis)
1216	{
1217	/*
1218	* Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons.
1219	*/
1220	if ( pDis->uAddrMode != DISCPUMODE_16BIT ///@todo correct?
1221	&& pDis->ModRM.Bits.Rm == 4
1222	&& pDis->ModRM.Bits.Mod != 3)
1223	{
1224	/* No scaled index SIB (index=4), except for ESP. */
1225	if ( pDis->SIB.Bits.Index == 4
1226	&& pDis->SIB.Bits.Base != 4)
1227	return true;
1228
1229	/* EBP + displacement */
1230	if ( pDis->ModRM.Bits.Mod != 0
1231	&& pDis->SIB.Bits.Base == 5
1232	&& pDis->SIB.Bits.Scale == 0)
1233	return true;
1234	}
1235
1236	/*
1237	* Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
1238	*/
1239	if ( pDis->pCurInstr->uOpcode == OP_SHL
1240	&& pDis->ModRM.Bits.Reg == 6)
1241	return true;
1242
1243	/*
1244	* Check for multiple prefixes of the same kind.
1245	*/
1246	uint8_t off1stSeg = UINT8_MAX;
1247	uint8_t offOpSize = UINT8_MAX;
1248	uint8_t offAddrSize = UINT8_MAX;
1249	uint32_t fPrefixes = 0;
1250	for (uint32_t offOpcode = 0; offOpcode < RT_ELEMENTS(pDis->abInstr); offOpcode++)
1251	{
1252	uint32_t f;
1253	switch (pDis->abInstr[offOpcode])
1254	{
1255	case 0xf0:
1256	f = DISPREFIX_LOCK;
1257	break;
1258
1259	case 0xf2:
1260	case 0xf3:
1261	f = DISPREFIX_REP; /* yes, both */
1262	break;
1263
1264	case 0x2e:
1265	case 0x3e:
1266	case 0x26:
1267	case 0x36:
1268	case 0x64:
1269	case 0x65:
1270	if (off1stSeg == UINT8_MAX)
1271	off1stSeg = offOpcode;
1272	f = DISPREFIX_SEG;
1273	break;
1274
1275	case 0x66:
1276	if (offOpSize == UINT8_MAX)
1277	offOpSize = offOpcode;
1278	f = DISPREFIX_OPSIZE;
1279	break;
1280
1281	case 0x67:
1282	if (offAddrSize == UINT8_MAX)
1283	offAddrSize = offOpcode;
1284	f = DISPREFIX_ADDRSIZE;
1285	break;
1286
1287	case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
1288	case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
1289	f = pDis->uCpuMode == DISCPUMODE_64BIT ? DISPREFIX_REX : 0;
1290	break;
1291
1292	default:
1293	f = 0;
1294	break;
1295	}
1296	if (!f)
1297	break; /* done */
1298	if (fPrefixes & f)
1299	return true;
1300	fPrefixes \|= f;
1301	}
1302
1303	/* segment overrides are fun */
1304	if (fPrefixes & DISPREFIX_SEG)
1305	{
1306	/* no effective address which it may apply to. */
1307	Assert((pDis->fPrefix & DISPREFIX_SEG) \|\| pDis->uCpuMode == DISCPUMODE_64BIT);
1308	if ( !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
1309	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
1310	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
1311	return true;
1312
1313	/* Yasm puts the segment prefixes before the operand prefix with no
1314	way of overriding it. */
1315	if (offOpSize < off1stSeg)
1316	return true;
1317	}
1318
1319	/* fixed register + addr override doesn't go down all that well. */
1320	if (fPrefixes & DISPREFIX_ADDRSIZE)
1321	{
1322	Assert(pDis->fPrefix & DISPREFIX_ADDRSIZE);
1323	if ( pDis->pCurInstr->fParam3 == OP_PARM_NONE
1324	&& pDis->pCurInstr->fParam2 == OP_PARM_NONE
1325	&& ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1326	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END))
1327	return true;
1328	}
1329
1330	/* Almost all prefixes are bad for jumps. */
1331	if (fPrefixes)
1332	{
1333	switch (pDis->pCurInstr->uOpcode)
1334	{
1335	/* nop w/ prefix(es). */
1336	case OP_NOP:
1337	return true;
1338
1339	case OP_JMP:
1340	if ( pDis->pCurInstr->fParam1 != OP_PARM_Jb
1341	&& pDis->pCurInstr->fParam1 != OP_PARM_Jv)
1342	break;
1343	/* fall thru */
1344	case OP_JO:
1345	case OP_JNO:
1346	case OP_JC:
1347	case OP_JNC:
1348	case OP_JE:
1349	case OP_JNE:
1350	case OP_JBE:
1351	case OP_JNBE:
1352	case OP_JS:
1353	case OP_JNS:
1354	case OP_JP:
1355	case OP_JNP:
1356	case OP_JL:
1357	case OP_JNL:
1358	case OP_JLE:
1359	case OP_JNLE:
1360	/** @todo branch hinting 0x2e/0x3e... */
1361	return true;
1362	}
1363
1364	}
1365
1366	/* All but the segment prefix is bad news for push/pop. */
1367	if (fPrefixes & ~DISPREFIX_SEG)
1368	{
1369	switch (pDis->pCurInstr->uOpcode)
1370	{
1371	case OP_POP:
1372	case OP_PUSH:
1373	if ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_SEG_START
1374	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_SEG_END)
1375	return true;
1376	if ( (fPrefixes & ~DISPREFIX_OPSIZE)
1377	&& pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1378	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END)
1379	return true;
1380	break;
1381
1382	case OP_POPA:
1383	case OP_POPF:
1384	case OP_PUSHA:
1385	case OP_PUSHF:
1386	if (fPrefixes & ~DISPREFIX_OPSIZE)
1387	return true;
1388	break;
1389	}
1390	}
1391
1392	/* Implicit 8-bit register instructions doesn't mix with operand size. */
1393	if ( (fPrefixes & DISPREFIX_OPSIZE)
1394	&& ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1395	&& pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1396	\|\| ( pDis->pCurInstr->fParam2 == OP_PARM_Gb /* r8 */
1397	&& pDis->pCurInstr->fParam1 == OP_PARM_Eb /* r8/mem8 */))
1398	)
1399	{
1400	switch (pDis->pCurInstr->uOpcode)
1401	{
1402	case OP_ADD:
1403	case OP_OR:
1404	case OP_ADC:
1405	case OP_SBB:
1406	case OP_AND:
1407	case OP_SUB:
1408	case OP_XOR:
1409	case OP_CMP:
1410	return true;
1411	default:
1412	break;
1413	}
1414	}
1415
1416	/* Instructions taking no address or operand which thus may be annoyingly
1417	difficult to format for yasm. */
1418	if (fPrefixes)
1419	{
1420	switch (pDis->pCurInstr->uOpcode)
1421	{
1422	case OP_STI:
1423	case OP_STC:
1424	case OP_CLI:
1425	case OP_CLD:
1426	case OP_CLC:
1427	case OP_INT:
1428	case OP_INT3:
1429	case OP_INTO:
1430	case OP_HLT:
1431	/** @todo Many more to can be added here. */
1432	return true;
1433	default:
1434	break;
1435	}
1436	}
1437
1438	/* FPU and other instructions that ignores operand size override. */
1439	if (fPrefixes & DISPREFIX_OPSIZE)
1440	{
1441	switch (pDis->pCurInstr->uOpcode)
1442	{
1443	/* FPU: */
1444	case OP_FIADD:
1445	case OP_FIMUL:
1446	case OP_FISUB:
1447	case OP_FISUBR:
1448	case OP_FIDIV:
1449	case OP_FIDIVR:
1450	/** @todo there are many more. */
1451	return true;
1452
1453	case OP_MOV:
1454	/** @todo could be that we're not disassembling these correctly. */
1455	if (pDis->pCurInstr->fParam1 == OP_PARM_Sw)
1456	return true;
1457	/** @todo what about the other way? */
1458	break;
1459
1460	default:
1461	break;
1462	}
1463	}
1464
1465
1466	/*
1467	* Check for the version of xyz reg,reg instruction that the assembler doesn't use.
1468	*
1469	* For example:
1470	* expected: 1aee sbb ch, dh ; SBB r8, r/m8
1471	* yasm: 18F5 sbb ch, dh ; SBB r/m8, r8
1472	*/
1473	if (pDis->ModRM.Bits.Mod == 3 /* reg,reg */)
1474	{
1475	switch (pDis->pCurInstr->uOpcode)
1476	{
1477	case OP_ADD:
1478	case OP_OR:
1479	case OP_ADC:
1480	case OP_SBB:
1481	case OP_AND:
1482	case OP_SUB:
1483	case OP_XOR:
1484	case OP_CMP:
1485	if ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1486	&& pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1487	\|\| ( pDis->pCurInstr->fParam1 == OP_PARM_Gv /* rX */
1488	&& pDis->pCurInstr->fParam2 == OP_PARM_Ev /* rX/memX */))
1489	return true;
1490
1491	/* 82 (see table A-6). */
1492	if (pDis->bOpCode == 0x82)
1493	return true;
1494	break;
1495
1496	/* ff /0, fe /0, ff /1, fe /0 */
1497	case OP_DEC:
1498	case OP_INC:
1499	return true;
1500
1501	case OP_POP:
1502	case OP_PUSH:
1503	Assert(pDis->bOpCode == 0x8f);
1504	return true;
1505
1506	case OP_MOV:
1507	if ( pDis->bOpCode == 0x8a
1508	\|\| pDis->bOpCode == 0x8b)
1509	return true;
1510	break;
1511
1512	default:
1513	break;
1514	}
1515	}
1516
1517	/* shl eax,1 will be assembled to the form without the immediate byte. */
1518	if ( pDis->pCurInstr->fParam2 == OP_PARM_Ib
1519	&& (uint8_t)pDis->Param2.uValue == 1)
1520	{
1521	switch (pDis->pCurInstr->uOpcode)
1522	{
1523	case OP_SHL:
1524	case OP_SHR:
1525	case OP_SAR:
1526	case OP_RCL:
1527	case OP_RCR:
1528	case OP_ROL:
1529	case OP_ROR:
1530	return true;
1531	}
1532	}
1533
1534	/* And some more - see table A-6. */
1535	if (pDis->bOpCode == 0x82)
1536	{
1537	switch (pDis->pCurInstr->uOpcode)
1538	{
1539	case OP_ADD:
1540	case OP_OR:
1541	case OP_ADC:
1542	case OP_SBB:
1543	case OP_AND:
1544	case OP_SUB:
1545	case OP_XOR:
1546	case OP_CMP:
1547	return true;
1548	break;
1549	}
1550	}
1551
1552
1553	/* check for REX.X = 1 without SIB. */
1554
1555	/* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
1556	says (intel doesn't appear to care). */
1557	switch (pDis->pCurInstr->uOpcode)
1558	{
1559	case OP_SETO:
1560	case OP_SETNO:
1561	case OP_SETC:
1562	case OP_SETNC:
1563	case OP_SETE:
1564	case OP_SETNE:
1565	case OP_SETBE:
1566	case OP_SETNBE:
1567	case OP_SETS:
1568	case OP_SETNS:
1569	case OP_SETP:
1570	case OP_SETNP:
1571	case OP_SETL:
1572	case OP_SETNL:
1573	case OP_SETLE:
1574	case OP_SETNLE:
1575	AssertMsg(pDis->bOpCode >= 0x90 && pDis->bOpCode <= 0x9f, ("%#x\n", pDis->bOpCode));
1576	if (pDis->ModRM.Bits.Reg != 2)
1577	return true;
1578	break;
1579	}
1580
1581	/*
1582	* The MOVZX reg32,mem16 instruction without an operand size prefix
1583	* doesn't quite make sense...
1584	*/
1585	if ( pDis->pCurInstr->uOpcode == OP_MOVZX
1586	&& pDis->bOpCode == 0xB7
1587	&& (pDis->uCpuMode == DISCPUMODE_16BIT) != !!(fPrefixes & DISPREFIX_OPSIZE))
1588	return true;
1589
1590	return false;
1591	}
1592

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source: vbox/trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp@ 46860

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