DisasmFormatYasm.cpp@ 105726

Last change on this file since 105726 was 105724, checked in by vboxsync, 3 months ago
Disassembler,VMM,HostDrivers,Debugger,MakeAlternativeSource: Convert DISSTATE::Param1,...,DISSTATE::Param4 to DISSTATE::aParams[4] for easier indexing, bugref:10394
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1	/* $Id: DisasmFormatYasm.cpp 105724 2024-08-19 13:27:44Z vboxsync $ */
2	/** @file
3	* VBox Disassembler - Yasm(/Nasm) Style Formatter.
4	*/
5
6	/*
7	* Copyright (C) 2008-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#include <VBox/dis.h>
33	#include "DisasmInternal.h"
34	#include <iprt/assert.h>
35	#include <iprt/ctype.h>
36	#include <iprt/err.h>
37	#include <iprt/string.h>
38
39
40	/*********************************************************************************************************************************
41	* Global Variables *
42	*********************************************************************************************************************************/
43	static const char g_szSpaces[] =
44	" ";
45	static const char g_aszYasmRegGen8[20][5] =
46	{
47	"al\0\0", "cl\0\0", "dl\0\0", "bl\0\0", "ah\0\0", "ch\0\0", "dh\0\0", "bh\0\0", "r8b\0", "r9b\0", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", "spl\0", "bpl\0", "sil\0", "dil\0"
48	};
49	static const char g_aszYasmRegGen16[16][5] =
50	{
51	"ax\0\0", "cx\0\0", "dx\0\0", "bx\0\0", "sp\0\0", "bp\0\0", "si\0\0", "di\0\0", "r8w\0", "r9w\0", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
52	};
53	#if 0 /* unused */
54	static const char g_aszYasmRegGen1616[8][6] =
55	{
56	"bx+si", "bx+di", "bp+si", "bp+di", "si\0\0\0", "di\0\0\0", "bp\0\0\0", "bx\0\0\0"
57	};
58	#endif
59	static const char g_aszYasmRegGen32[16][5] =
60	{
61	"eax\0", "ecx\0", "edx\0", "ebx\0", "esp\0", "ebp\0", "esi\0", "edi\0", "r8d\0", "r9d\0", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
62	};
63	static const char g_aszYasmRegGen64[16][4] =
64	{
65	"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8\0", "r9\0", "r10", "r11", "r12", "r13", "r14", "r15"
66	};
67	static const char g_aszYasmRegSeg[6][3] =
68	{
69	"es", "cs", "ss", "ds", "fs", "gs"
70	};
71	static const char g_aszYasmRegFP[8][4] =
72	{
73	"st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"
74	};
75	static const char g_aszYasmRegMMX[8][4] =
76	{
77	"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"
78	};
79	static const char g_aszYasmRegXMM[16][6] =
80	{
81	"xmm0\0", "xmm1\0", "xmm2\0", "xmm3\0", "xmm4\0", "xmm5\0", "xmm6\0", "xmm7\0", "xmm8\0", "xmm9\0", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
82	};
83	static const char g_aszYasmRegYMM[16][6] =
84	{
85	"ymm0\0", "ymm1\0", "ymm2\0", "ymm3\0", "ymm4\0", "ymm5\0", "ymm6\0", "ymm7\0", "ymm8\0", "ymm9\0", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15"
86	};
87	static const char g_aszYasmRegCRx[16][5] =
88	{
89	"cr0\0", "cr1\0", "cr2\0", "cr3\0", "cr4\0", "cr5\0", "cr6\0", "cr7\0", "cr8\0", "cr9\0", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
90	};
91	static const char g_aszYasmRegDRx[16][5] =
92	{
93	"dr0\0", "dr1\0", "dr2\0", "dr3\0", "dr4\0", "dr5\0", "dr6\0", "dr7\0", "dr8\0", "dr9\0", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
94	};
95	static const char g_aszYasmRegTRx[16][5] =
96	{
97	"tr0\0", "tr1\0", "tr2\0", "tr3\0", "tr4\0", "tr5\0", "tr6\0", "tr7\0", "tr8\0", "tr9\0", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"
98	};
99
100
101
102	/**
103	* Gets the base register name for the given parameter.
104	*
105	* @returns Pointer to the register name.
106	* @param pDis The disassembler state.
107	* @param pParam The parameter.
108	* @param pcchReg Where to store the length of the name.
109	*/
110	static const char disasmFormatYasmBaseReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t pcchReg)
111	{
112	RT_NOREF_PV(pDis);
113
114	switch (pParam->fUse & ( DISUSE_REG_GEN8 \| DISUSE_REG_GEN16 \| DISUSE_REG_GEN32 \| DISUSE_REG_GEN64
115	\| DISUSE_REG_FP \| DISUSE_REG_MMX \| DISUSE_REG_XMM \| DISUSE_REG_YMM
116	\| DISUSE_REG_CR \| DISUSE_REG_DBG \| DISUSE_REG_SEG \| DISUSE_REG_TEST))
117
118	{
119	case DISUSE_REG_GEN8:
120	{
121	Assert(pParam->x86.Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen8));
122	const char *psz = g_aszYasmRegGen8[pParam->x86.Base.idxGenReg];
123	*pcchReg = 2 + !!psz[2] + !!psz[3];
124	return psz;
125	}
126
127	case DISUSE_REG_GEN16:
128	{
129	Assert(pParam->x86.Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
130	const char *psz = g_aszYasmRegGen16[pParam->x86.Base.idxGenReg];
131	*pcchReg = 2 + !!psz[2] + !!psz[3];
132	return psz;
133	}
134
135	// VSIB
136	case DISUSE_REG_XMM \| DISUSE_REG_GEN32:
137	case DISUSE_REG_YMM \| DISUSE_REG_GEN32:
138	case DISUSE_REG_GEN32:
139	{
140	Assert(pParam->x86.Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
141	const char *psz = g_aszYasmRegGen32[pParam->x86.Base.idxGenReg];
142	*pcchReg = 2 + !!psz[2] + !!psz[3];
143	return psz;
144	}
145
146	// VSIB
147	case DISUSE_REG_XMM \| DISUSE_REG_GEN64:
148	case DISUSE_REG_YMM \| DISUSE_REG_GEN64:
149	case DISUSE_REG_GEN64:
150	{
151	Assert(pParam->x86.Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
152	const char *psz = g_aszYasmRegGen64[pParam->x86.Base.idxGenReg];
153	*pcchReg = 2 + !!psz[2] + !!psz[3];
154	return psz;
155	}
156
157	case DISUSE_REG_FP:
158	{
159	Assert(pParam->x86.Base.idxFpuReg < RT_ELEMENTS(g_aszYasmRegFP));
160	const char *psz = g_aszYasmRegFP[pParam->x86.Base.idxFpuReg];
161	*pcchReg = 3;
162	return psz;
163	}
164
165	case DISUSE_REG_MMX:
166	{
167	Assert(pParam->x86.Base.idxMmxReg < RT_ELEMENTS(g_aszYasmRegMMX));
168	const char *psz = g_aszYasmRegMMX[pParam->x86.Base.idxMmxReg];
169	*pcchReg = 3;
170	return psz;
171	}
172
173	case DISUSE_REG_XMM:
174	{
175	Assert(pParam->x86.Base.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
176	const char *psz = g_aszYasmRegXMM[pParam->x86.Base.idxXmmReg];
177	*pcchReg = 4 + !!psz[4];
178	return psz;
179	}
180
181	case DISUSE_REG_YMM:
182	{
183	Assert(pParam->x86.Base.idxYmmReg < RT_ELEMENTS(g_aszYasmRegYMM));
184	const char *psz = g_aszYasmRegYMM[pParam->x86.Base.idxYmmReg];
185	*pcchReg = 4 + !!psz[4];
186	return psz;
187	}
188
189	case DISUSE_REG_CR:
190	{
191	Assert(pParam->x86.Base.idxCtrlReg < RT_ELEMENTS(g_aszYasmRegCRx));
192	const char *psz = g_aszYasmRegCRx[pParam->x86.Base.idxCtrlReg];
193	*pcchReg = 3;
194	return psz;
195	}
196
197	case DISUSE_REG_DBG:
198	{
199	Assert(pParam->x86.Base.idxDbgReg < RT_ELEMENTS(g_aszYasmRegDRx));
200	const char *psz = g_aszYasmRegDRx[pParam->x86.Base.idxDbgReg];
201	*pcchReg = 3;
202	return psz;
203	}
204
205	case DISUSE_REG_SEG:
206	{
207	Assert(pParam->x86.Base.idxSegReg < RT_ELEMENTS(g_aszYasmRegCRx));
208	const char *psz = g_aszYasmRegSeg[pParam->x86.Base.idxSegReg];
209	*pcchReg = 2;
210	return psz;
211	}
212
213	case DISUSE_REG_TEST:
214	{
215	Assert(pParam->x86.Base.idxTestReg < RT_ELEMENTS(g_aszYasmRegTRx));
216	const char *psz = g_aszYasmRegTRx[pParam->x86.Base.idxTestReg];
217	*pcchReg = 3;
218	return psz;
219	}
220
221	default:
222	AssertMsgFailed(("%#x\n", pParam->fUse));
223	*pcchReg = 3;
224	return "r??";
225	}
226	}
227
228
229	/**
230	* Gets the index register name for the given parameter.
231	*
232	* @returns The index register name.
233	* @param pDis The disassembler state.
234	* @param pParam The parameter.
235	* @param pcchReg Where to store the length of the name.
236	*/
237	static const char disasmFormatYasmIndexReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t pcchReg)
238	{
239	if (pParam->fUse & DISUSE_REG_XMM)
240	{
241	Assert(pParam->x86.Index.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
242	const char *psz = g_aszYasmRegXMM[pParam->x86.Index.idxXmmReg];
243	*pcchReg = 4 + !!psz[4];
244	return psz;
245	}
246	else if (pParam->fUse & DISUSE_REG_YMM)
247	{
248	Assert(pParam->x86.Index.idxYmmReg < RT_ELEMENTS(g_aszYasmRegYMM));
249	const char *psz = g_aszYasmRegYMM[pParam->x86.Index.idxYmmReg];
250	*pcchReg = 4 + !!psz[4];
251	return psz;
252
253	}
254	else
255	switch (pDis->x86.uAddrMode)
256	{
257	case DISCPUMODE_16BIT:
258	{
259	Assert(pParam->x86.Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
260	const char *psz = g_aszYasmRegGen16[pParam->x86.Index.idxGenReg];
261	*pcchReg = 2 + !!psz[2] + !!psz[3];
262	return psz;
263	}
264
265	case DISCPUMODE_32BIT:
266	{
267	Assert(pParam->x86.Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
268	const char *psz = g_aszYasmRegGen32[pParam->x86.Index.idxGenReg];
269	*pcchReg = 2 + !!psz[2] + !!psz[3];
270	return psz;
271	}
272
273	case DISCPUMODE_64BIT:
274	{
275	Assert(pParam->x86.Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
276	const char *psz = g_aszYasmRegGen64[pParam->x86.Index.idxGenReg];
277	*pcchReg = 2 + !!psz[2] + !!psz[3];
278	return psz;
279	}
280
281	default:
282	AssertMsgFailed(("%#x %#x\n", pParam->fUse, pDis->x86.uAddrMode));
283	*pcchReg = 3;
284	return "r??";
285	}
286	}
287
288
289	/**
290	* Formats the current instruction in Yasm (/ Nasm) style.
291	*
292	*
293	* @returns The number of output characters. If this is >= cchBuf, then the content
294	* of pszBuf will be truncated.
295	* @param pDis Pointer to the disassembler state.
296	* @param pszBuf The output buffer.
297	* @param cchBuf The size of the output buffer.
298	* @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
299	* @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
300	* @param pvUser User argument for pfnGetSymbol.
301	*/
302	DISDECL(size_t) DISFormatYasmEx(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags,
303	PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
304	{
305	/** @todo monitor and mwait aren't formatted correctly in 64-bit mode. */
306	/*
307	* Input validation and massaging.
308	*/
309	AssertPtr(pDis);
310	AssertPtrNull(pszBuf);
311	Assert(pszBuf \|\| !cchBuf);
312	AssertPtrNull(pfnGetSymbol);
313	AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
314	if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
315	fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) \| DIS_FMT_FLAGS_ADDR_RIGHT;
316	if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
317	fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) \| DIS_FMT_FLAGS_BYTES_RIGHT;
318
319	PCDISOPCODE const pOp = pDis->pCurInstr;
320
321	/*
322	* Output macros
323	*/
324	char *pszDst = pszBuf;
325	size_t cchDst = cchBuf;
326	size_t cchOutput = 0;
327	#define PUT_C(ch) \
328	do { \
329	cchOutput++; \
330	if (cchDst > 1) \
331	{ \
332	cchDst--; \
333	*pszDst++ = (ch); \
334	} \
335	} while (0)
336	#define PUT_STR(pszSrc, cchSrc) \
337	do { \
338	cchOutput += (cchSrc); \
339	if (cchDst > (cchSrc)) \
340	{ \
341	memcpy(pszDst, (pszSrc), (cchSrc)); \
342	pszDst += (cchSrc); \
343	cchDst -= (cchSrc); \
344	} \
345	else if (cchDst > 1) \
346	{ \
347	memcpy(pszDst, (pszSrc), cchDst - 1); \
348	pszDst += cchDst - 1; \
349	cchDst = 1; \
350	} \
351	} while (0)
352	#define PUT_SZ(sz) \
353	PUT_STR((sz), sizeof(sz) - 1)
354	#define PUT_SZ_STRICT(szStrict, szRelaxed) \
355	do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
356	#define PUT_PSZ(psz) \
357	do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
358	#define PUT_NUM(cch, fmt, num) \
359	do { \
360	cchOutput += (cch); \
361	if (cchDst > 1) \
362	{ \
363	const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
364	pszDst += cchTmp; \
365	cchDst -= cchTmp; \
366	Assert(cchTmp == (cch) \|\| cchDst == 1); \
367	} \
368	} while (0)
369	#define PUT_NUM_8(num) PUT_NUM(4, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%02xh" : "%#04x", (uint8_t)(num))
370	#define PUT_NUM_16(num) PUT_NUM(6, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%04xh" : "%#06x", (uint16_t)(num))
371	#define PUT_NUM_32(num) PUT_NUM(10, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%08xh" : "%#010x", (uint32_t)(num))
372	#define PUT_NUM_64(num) PUT_NUM(18, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%016RX64h" : "%#018RX64", (uint64_t)(num))
373
374	#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
375	do { \
376	if ((stype)(num) >= 0) \
377	{ \
378	PUT_C('+'); \
379	PUT_NUM(cch, fmt, (utype)(num)); \
380	} \
381	else \
382	{ \
383	PUT_C('-'); \
384	PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
385	} \
386	} while (0)
387	#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%02xh" : "%#04x", num, int8_t, uint8_t)
388	#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%04xh" : "%#06x", num, int16_t, uint16_t)
389	#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%08xh" : "%#010x", num, int32_t, uint32_t)
390	#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%016RX64h" : "%#018RX64", num, int64_t, uint64_t)
391
392	#define PUT_SYMBOL_TWO(a_rcSym, a_szStart, a_chEnd) \
393	do { \
394	if (RT_SUCCESS(a_rcSym)) \
395	{ \
396	PUT_SZ(a_szStart); \
397	PUT_PSZ(szSymbol); \
398	if (off != 0) \
399	{ \
400	if ((int8_t)off == off) \
401	PUT_NUM_S8(off); \
402	else if ((int16_t)off == off) \
403	PUT_NUM_S16(off); \
404	else if ((int32_t)off == off) \
405	PUT_NUM_S32(off); \
406	else \
407	PUT_NUM_S64(off); \
408	} \
409	PUT_C(a_chEnd); \
410	} \
411	} while (0)
412
413	#define PUT_SYMBOL(a_uSeg, a_uAddr, a_szStart, a_chEnd) \
414	do { \
415	if (pfnGetSymbol) \
416	{ \
417	int rcSym = pfnGetSymbol(pDis, a_uSeg, a_uAddr, szSymbol, sizeof(szSymbol), &off, pvUser); \
418	PUT_SYMBOL_TWO(rcSym, a_szStart, a_chEnd); \
419	} \
420	} while (0)
421
422
423	/*
424	* The address?
425	*/
426	if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
427	{
428	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
429	if (pDis->uInstrAddr >= _4G)
430	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
431	#endif
432	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
433	PUT_C(' ');
434	}
435
436	/*
437	* The opcode bytes?
438	*/
439	if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
440	{
441	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
442	cchOutput += cchTmp;
443	if (cchDst > 1)
444	{
445	if (cchTmp <= cchDst)
446	{
447	cchDst -= cchTmp;
448	pszDst += cchTmp;
449	}
450	else
451	{
452	pszDst += cchDst - 1;
453	cchDst = 1;
454	}
455	}
456
457	/* Some padding to align the instruction. */
458	uint32_t cbWidth = (fFlags & DIS_FMT_FLAGS_BYTES_WIDTH_MASK) >> DIS_FMT_FLAGS_BYTES_WIDTH_SHIFT;
459	if (!cbWidth)
460	cbWidth = 7;
461	size_t cchPadding = (cbWidth * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
462	+ !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
463	+ 2;
464	cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
465	PUT_STR(g_szSpaces, cchPadding);
466	}
467
468
469	/*
470	* Filter out invalid opcodes first as they need special
471	* treatment. UD2 is an exception and should be handled normally.
472	*/
473	size_t const offInstruction = cchOutput;
474	if ( pOp->uOpcode == OP_INVALID
475	\|\| ( pOp->uOpcode == OP_ILLUD2
476	&& (pDis->x86.fPrefix & DISPREFIX_LOCK)))
477	PUT_SZ("Illegal opcode");
478	else
479	{
480	/*
481	* Prefixes
482	*/
483	if (pDis->x86.fPrefix & DISPREFIX_LOCK)
484	PUT_SZ("lock ");
485	if (pDis->x86.fPrefix & DISPREFIX_REP)
486	PUT_SZ("rep ");
487	else if(pDis->x86.fPrefix & DISPREFIX_REPNE)
488	PUT_SZ("repne ");
489
490	/*
491	* Adjust the format string to the correct mnemonic
492	* or to avoid things the assembler cannot handle correctly.
493	*/
494	char szTmpFmt[48];
495	const char *pszFmt = pOp->pszOpcode;
496	bool fIgnoresOpSize = false;
497	bool fMayNeedAddrSize = false;
498	switch (pOp->uOpcode)
499	{
500	case OP_JECXZ:
501	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "jcxz %Jb" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb";
502	break;
503	case OP_PUSHF:
504	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "pushfw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "pushfd" : "pushfq";
505	break;
506	case OP_POPF:
507	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "popfw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "popfd" : "popfq";
508	break;
509	case OP_PUSHA:
510	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "pushaw" : "pushad";
511	break;
512	case OP_POPA:
513	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "popaw" : "popad";
514	break;
515	case OP_INSB:
516	pszFmt = "insb";
517	fIgnoresOpSize = fMayNeedAddrSize = true;
518	break;
519	case OP_INSWD:
520	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "insw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "insd" : "insq";
521	fMayNeedAddrSize = true;
522	break;
523	case OP_OUTSB:
524	pszFmt = "outsb";
525	fIgnoresOpSize = fMayNeedAddrSize = true;
526	break;
527	case OP_OUTSWD:
528	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "outsw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "outsd" : "outsq";
529	fMayNeedAddrSize = true;
530	break;
531	case OP_MOVSB:
532	pszFmt = "movsb";
533	fIgnoresOpSize = fMayNeedAddrSize = true;
534	break;
535	case OP_MOVSWD:
536	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "movsw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "movsd" : "movsq";
537	fMayNeedAddrSize = true;
538	break;
539	case OP_CMPSB:
540	pszFmt = "cmpsb";
541	fIgnoresOpSize = fMayNeedAddrSize = true;
542	break;
543	case OP_CMPWD:
544	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "cmpsw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "cmpsd" : "cmpsq";
545	fMayNeedAddrSize = true;
546	break;
547	case OP_SCASB:
548	pszFmt = "scasb";
549	fIgnoresOpSize = fMayNeedAddrSize = true;
550	break;
551	case OP_SCASWD:
552	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "scasw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "scasd" : "scasq";
553	fMayNeedAddrSize = true;
554	break;
555	case OP_LODSB:
556	pszFmt = "lodsb";
557	fIgnoresOpSize = fMayNeedAddrSize = true;
558	break;
559	case OP_LODSWD:
560	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "lodsw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "lodsd" : "lodsq";
561	fMayNeedAddrSize = true;
562	break;
563	case OP_STOSB:
564	pszFmt = "stosb";
565	fIgnoresOpSize = fMayNeedAddrSize = true;
566	break;
567	case OP_STOSWD:
568	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "stosw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "stosd" : "stosq";
569	fMayNeedAddrSize = true;
570	break;
571	case OP_CBW:
572	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "cbw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "cwde" : "cdqe";
573	break;
574	case OP_CWD:
575	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "cwd" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "cdq" : "cqo";
576	break;
577	case OP_SHL:
578	Assert(pszFmt[3] == '/');
579	pszFmt += 4;
580	break;
581	case OP_XLAT:
582	pszFmt = "xlatb";
583	break;
584	case OP_INT3:
585	pszFmt = "int3";
586	break;
587
588	/*
589	* Don't know how to tell yasm to generate complicated nop stuff, so 'db' it.
590	*/
591	case OP_NOP:
592	if (pDis->x86.bOpCode == 0x90)
593	/* fine, fine */;
594	else if (pszFmt[sizeof("nop %Ev") - 1] == '/' && pszFmt[sizeof("nop %Ev")] == 'p')
595	pszFmt = "prefetch %Eb";
596	else if (pDis->x86.bOpCode == 0x1f)
597	{
598	Assert(pDis->cbInstr >= 3);
599	PUT_SZ("db 00fh, 01fh");
600	for (unsigned off = 2; off < pDis->cbInstr; off++)
601	{
602	PUT_C(',');
603	PUT_C(' ');
604	PUT_NUM_8(pDis->Instr.ab[off]);
605	}
606	pszFmt = "";
607	}
608	break;
609
610	default:
611	/* ST(X) -> stX (floating point) */
612	if (*pszFmt == 'f' && strchr(pszFmt, '('))
613	{
614	char *pszFmtDst = szTmpFmt;
615	char ch;
616	do
617	{
618	ch = *pszFmt++;
619	if (ch == 'S' && pszFmt[0] == 'T' && pszFmt[1] == '(')
620	{
621	*pszFmtDst++ = 's';
622	*pszFmtDst++ = 't';
623	pszFmt += 2;
624	ch = *pszFmt;
625	Assert(pszFmt[1] == ')');
626	pszFmt += 2;
627	*pszFmtDst++ = ch;
628	}
629	else
630	*pszFmtDst++ = ch;
631	} while (ch != '\0');
632	pszFmt = szTmpFmt;
633	}
634	if (strchr("#@&", *pszFmt))
635	{
636	const char *pszDelim = strchr(pszFmt, '/');
637	const char *pszSpace = (pszDelim ? strchr(pszDelim, ' ') : NULL);
638	if (pszDelim != NULL)
639	{
640	char *pszFmtDst = szTmpFmt;
641	if (pszSpace == NULL) pszSpace = strchr(pszDelim, 0);
642	if ( (pszFmt == '#' && !(pDis->x86.bVexByte2 & DISPREFIX_VEX_F_W)) /* @todo check this*/
643	\|\| (*pszFmt == '@' && !VEXREG_IS256B(pDis->x86.bVexDestReg))
644	\|\| (*pszFmt == '&' && ( DISUSE_IS_EFFECTIVE_ADDR(pDis->aParams[0].fUse)
645	\|\| DISUSE_IS_EFFECTIVE_ADDR(pDis->aParams[1].fUse)
646	\|\| DISUSE_IS_EFFECTIVE_ADDR(pDis->aParams[2].fUse)
647	\|\| DISUSE_IS_EFFECTIVE_ADDR(pDis->aParams[3].fUse))))
648	{
649	strncpy(pszFmtDst, pszFmt + 1, pszDelim - pszFmt - 1);
650	pszFmtDst += pszDelim - pszFmt - 1;
651	}
652	else
653	{
654	strncpy(pszFmtDst, pszDelim + 1, pszSpace - pszDelim - 1);
655	pszFmtDst += pszSpace - pszDelim - 1;
656	}
657	strcpy (pszFmtDst, pszSpace);
658	pszFmt = szTmpFmt;
659	}
660	}
661	break;
662
663	/*
664	* Horrible hacks.
665	*/
666	case OP_FLD:
667	if (pDis->x86.bOpCode == 0xdb) /* m80fp workaround. */
668	(int )&pDis->aParams[0].x86.fParam &= ~0x1f; /* make it pure OP_PARM_M */
669	break;
670	case OP_LAR: /* hack w -> v, probably not correct. */
671	(int )&pDis->aParams[1].x86.fParam &= ~0x1f;
672	(int )&pDis->aParams[2].x86.fParam \|= OP_PARM_v;
673	break;
674	}
675
676	/*
677	* Add operand size and address prefixes for outsb, movsb, etc.
678	*/
679	if (pDis->x86.fPrefix & (DISPREFIX_OPSIZE \| DISPREFIX_ADDRSIZE))
680	{
681	if (fIgnoresOpSize && (pDis->x86.fPrefix & DISPREFIX_OPSIZE) )
682	{
683	if (pDis->uCpuMode == DISCPUMODE_16BIT)
684	PUT_SZ("o32 ");
685	else
686	PUT_SZ("o16 ");
687	}
688	if (fMayNeedAddrSize && (pDis->x86.fPrefix & DISPREFIX_ADDRSIZE) )
689	{
690	if (pDis->uCpuMode == DISCPUMODE_16BIT)
691	PUT_SZ("a32 ");
692	else
693	PUT_SZ("a16 ");
694	}
695	}
696
697	/*
698	* Formatting context and associated macros.
699	*/
700	PCDISOPPARAM pParam = &pDis->aParams[0];
701	uint32_t iParam = 0;
702
703	#define PUT_FAR() \
704	do { \
705	if ( OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_p \
706	&& pOp->uOpcode != OP_LDS /* table bugs? */ \
707	&& pOp->uOpcode != OP_LES \
708	&& pOp->uOpcode != OP_LFS \
709	&& pOp->uOpcode != OP_LGS \
710	&& pOp->uOpcode != OP_LSS ) \
711	PUT_SZ("far "); \
712	} while (0)
713	/** @todo mov ah,ch ends up with a byte 'override'... - check if this wasn't fixed. */
714	/** @todo drop the work/dword/qword override when the src/dst is a register (except for movsx/movzx). */
715	#define PUT_SIZE_OVERRIDE() \
716	do { \
717	switch (OP_PARM_VSUBTYPE(pParam->x86.fParam)) \
718	{ \
719	case OP_PARM_v: \
720	case OP_PARM_y: \
721	switch (pDis->x86.uOpMode) \
722	{ \
723	case DISCPUMODE_16BIT: if (OP_PARM_VSUBTYPE(pParam->x86.fParam) != OP_PARM_y) PUT_SZ("word "); break; \
724	case DISCPUMODE_32BIT: \
725	if (pDis->pCurInstr->uOpcode != OP_GATHER \|\| (pDis->x86.bVexByte2 & DISPREFIX_VEX_F_W)) \
726	{ PUT_SZ("dword "); break; } \
727	RT_FALL_THRU(); \
728	case DISCPUMODE_64BIT: PUT_SZ("qword "); break; \
729	default: break; \
730	} \
731	break; \
732	case OP_PARM_b: PUT_SZ("byte "); break; \
733	case OP_PARM_w: \
734	if ( OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_W \
735	\|\| OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_M) \
736	{ \
737	if (VEXREG_IS256B(pDis->x86.bVexDestReg)) PUT_SZ("dword "); \
738	else PUT_SZ("word "); \
739	} \
740	else if (pOp->uOpcode == OP_MOVZX \|\| pOp->uOpcode == OP_MOVSX) \
741	PUT_SZ("word "); \
742	break; \
743	case OP_PARM_d: \
744	if ( OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_W \
745	\|\| OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_M) \
746	{ \
747	if (VEXREG_IS256B(pDis->x86.bVexDestReg)) PUT_SZ("qword "); \
748	else PUT_SZ("dword "); \
749	} \
750	break; \
751	case OP_PARM_q: \
752	if ( OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_W \
753	\|\| OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_M) \
754	{ \
755	if (VEXREG_IS256B(pDis->x86.bVexDestReg)) PUT_SZ("oword "); \
756	else PUT_SZ("qword "); \
757	} \
758	break; \
759	case OP_PARM_ps: \
760	case OP_PARM_pd: \
761	case OP_PARM_x: if (VEXREG_IS256B(pDis->x86.bVexDestReg)) { PUT_SZ("yword "); break; } RT_FALL_THRU(); \
762	case OP_PARM_ss: \
763	case OP_PARM_sd: \
764	case OP_PARM_dq: PUT_SZ("oword "); break; \
765	case OP_PARM_qq: PUT_SZ("yword "); break; \
766	case OP_PARM_p: break; /* see PUT_FAR */ \
767	case OP_PARM_s: if (pParam->fUse & DISUSE_REG_FP) PUT_SZ("tword "); break; /* ?? */ \
768	case OP_PARM_z: break; \
769	case OP_PARM_NONE: \
770	if ( OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_M \
771	&& ((pParam->fUse & DISUSE_REG_FP) \|\| pOp->uOpcode == OP_FLD)) \
772	PUT_SZ("tword "); \
773	break; \
774	default: break; /no pointer type specified/necessary/ \
775	} \
776	} while (0)
777	static const char s_szSegPrefix[6][4] = { "es:", "cs:", "ss:", "ds:", "fs:", "gs:" };
778	#define PUT_SEGMENT_OVERRIDE() \
779	do { \
780	if (pDis->x86.fPrefix & DISPREFIX_SEG) \
781	PUT_STR(s_szSegPrefix[pDis->x86.idxSegPrefix], 3); \
782	} while (0)
783
784
785	/*
786	* Segment prefixing for instructions that doesn't do memory access.
787	*/
788	if ( (pDis->x86.fPrefix & DISPREFIX_SEG)
789	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->aParams[0].fUse)
790	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->aParams[1].fUse)
791	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->aParams[2].fUse))
792	{
793	PUT_STR(s_szSegPrefix[pDis->x86.idxSegPrefix], 2);
794	PUT_C(' ');
795	}
796
797
798	/*
799	* The formatting loop.
800	*/
801	RTINTPTR off;
802	char szSymbol[128];
803	char ch;
804	while ((ch = *pszFmt++) != '\0')
805	{
806	if (ch == '%')
807	{
808	ch = *pszFmt++;
809	switch (ch)
810	{
811	/*
812	* ModRM - Register only / VEX.vvvv.
813	*/
814	case 'C': /* Control register (ParseModRM / UseModRM). */
815	case 'D': /* Debug register (ParseModRM / UseModRM). */
816	case 'G': /* ModRM selects general register (ParseModRM / UseModRM). */
817	case 'S': /* ModRM byte selects a segment register (ParseModRM / UseModRM). */
818	case 'T': /* ModRM byte selects a test register (ParseModRM / UseModRM). */
819	case 'V': /* ModRM byte selects an XMM/SSE register (ParseModRM / UseModRM). */
820	case 'P': /* ModRM byte selects MMX register (ParseModRM / UseModRM). */
821	case 'H': /* The VEX.vvvv field of the VEX prefix selects a XMM/YMM register. */
822	case 'B': /* The VEX.vvvv field of the VEX prefix selects a general register (ParseVexDest). */
823	case 'L': /* The upper 4 bits of the 8-bit immediate selects a XMM/YMM register. */
824	{
825	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
826	Assert(!(pParam->fUse & (DISUSE_INDEX \| DISUSE_SCALE) /* No SIB here... */));
827	Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)));
828
829	size_t cchReg;
830	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
831	PUT_STR(pszReg, cchReg);
832	break;
833	}
834
835	/*
836	* ModRM - Register or memory.
837	*/
838	case 'E': /* ModRM specifies parameter (ParseModRM / UseModRM / UseSIB). */
839	case 'Q': /* ModRM byte selects MMX register or memory address (ParseModRM / UseModRM). */
840	case 'R': /* ModRM byte may only refer to a general register (ParseModRM / UseModRM). */
841	case 'W': /* ModRM byte selects an XMM/SSE register or a memory address (ParseModRM / UseModRM). */
842	case 'U': /* ModRM byte may only refer to a XMM/SSE register (ParseModRM / UseModRM). */
843	case 'M': /* ModRM byte may only refer to memory (ParseModRM / UseModRM). */
844	{
845	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
846
847	PUT_FAR();
848	uint32_t const fUse = pParam->fUse;
849	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
850	{
851	/* Work around mov seg,[mem16] and mov [mem16],seg as these always make a 16-bit mem
852	while the register variants deals with 16, 32 & 64 in the normal fashion. */
853	if ( pParam->x86.fParam != OP_PARM_Ev
854	\|\| pOp->uOpcode != OP_MOV
855	\|\| ( pOp->fParam1 != OP_PARM_Sw
856	&& pOp->fParam2 != OP_PARM_Sw))
857	PUT_SIZE_OVERRIDE();
858	PUT_C('[');
859	}
860	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
861	&& (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)))
862	{
863	if ( (fUse & DISUSE_DISPLACEMENT8)
864	&& !pParam->x86.uDisp.i8)
865	PUT_SZ("byte ");
866	else if ( (fUse & DISUSE_DISPLACEMENT16)
867	&& (int8_t)pParam->x86.uDisp.i16 == (int16_t)pParam->x86.uDisp.i16)
868	PUT_SZ("word ");
869	else if ( (fUse & DISUSE_DISPLACEMENT32)
870	&& (int16_t)pParam->x86.uDisp.i32 == (int32_t)pParam->x86.uDisp.i32) //??
871	PUT_SZ("dword ");
872	else if ( (fUse & DISUSE_DISPLACEMENT64)
873	&& (pDis->x86.SIB.Bits.Base != 5 \|\| pDis->x86.ModRM.Bits.Mod != 0)
874	&& (int32_t)pParam->x86.uDisp.i64 == (int64_t)pParam->x86.uDisp.i64) //??
875	PUT_SZ("qword ");
876	}
877	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
878	PUT_SEGMENT_OVERRIDE();
879
880	bool fBase = (fUse & DISUSE_BASE) /* When exactly is DISUSE_BASE supposed to be set? disasmModRMReg doesn't set it. */
881	\|\| ( (fUse & ( DISUSE_REG_GEN8
882	\| DISUSE_REG_GEN16
883	\| DISUSE_REG_GEN32
884	\| DISUSE_REG_GEN64
885	\| DISUSE_REG_FP
886	\| DISUSE_REG_MMX
887	\| DISUSE_REG_XMM
888	\| DISUSE_REG_YMM
889	\| DISUSE_REG_CR
890	\| DISUSE_REG_DBG
891	\| DISUSE_REG_SEG
892	\| DISUSE_REG_TEST ))
893	&& !DISUSE_IS_EFFECTIVE_ADDR(fUse));
894	if (fBase)
895	{
896	size_t cchReg;
897	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
898	PUT_STR(pszReg, cchReg);
899	}
900
901	if (fUse & DISUSE_INDEX)
902	{
903	if (fBase)
904	PUT_C('+');
905
906	size_t cchReg;
907	const char *pszReg = disasmFormatYasmIndexReg(pDis, pParam, &cchReg);
908	PUT_STR(pszReg, cchReg);
909
910	if (fUse & DISUSE_SCALE)
911	{
912	PUT_C('*');
913	PUT_C('0' + pParam->x86.uScale);
914	}
915	}
916	else
917	Assert(!(fUse & DISUSE_SCALE));
918
919	int64_t off2 = 0;
920	if (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32))
921	{
922	if (fUse & DISUSE_DISPLACEMENT8)
923	off2 = pParam->x86.uDisp.i8;
924	else if (fUse & DISUSE_DISPLACEMENT16)
925	off2 = pParam->x86.uDisp.i16;
926	else if (fUse & (DISUSE_DISPLACEMENT32 \| DISUSE_RIPDISPLACEMENT32))
927	off2 = pParam->x86.uDisp.i32;
928	else if (fUse & DISUSE_DISPLACEMENT64)
929	off2 = pParam->x86.uDisp.i64;
930	else
931	{
932	AssertFailed();
933	off2 = 0;
934	}
935
936	int64_t off3 = off2;
937	if (fBase \|\| (fUse & (DISUSE_INDEX \| DISUSE_RIPDISPLACEMENT32)))
938	{
939	PUT_C(off3 >= 0 ? '+' : '-');
940	if (off3 < 0)
941	off3 = -off3;
942	}
943	if (fUse & DISUSE_DISPLACEMENT8)
944	PUT_NUM_8( off3);
945	else if (fUse & DISUSE_DISPLACEMENT16)
946	PUT_NUM_16(off3);
947	else if (fUse & DISUSE_DISPLACEMENT32)
948	PUT_NUM_32(off3);
949	else if (fUse & DISUSE_DISPLACEMENT64)
950	PUT_NUM_64(off3);
951	else
952	{
953	PUT_NUM_32(off3);
954	PUT_SZ(" wrt rip (");
955	off2 += pDis->uInstrAddr + pDis->cbInstr;
956	PUT_NUM_64(off2);
957	if (pfnGetSymbol)
958	PUT_SYMBOL((pDis->x86.fPrefix & DISPREFIX_SEG)
959	? DIS_FMT_SEL_FROM_REG(pDis->x86.idxSegPrefix)
960	: DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
961	pDis->x86.uAddrMode == DISCPUMODE_64BIT
962	? (uint64_t)off2
963	: pDis->x86.uAddrMode == DISCPUMODE_32BIT
964	? (uint32_t)off2
965	: (uint16_t)off2,
966	" = ",
967	')');
968	else
969	PUT_C(')');
970	}
971	}
972
973	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
974	{
975	if (pfnGetSymbol && !fBase && !(fUse & (DISUSE_INDEX \| DISUSE_RIPDISPLACEMENT32)) && off2 != 0)
976	PUT_SYMBOL((pDis->x86.fPrefix & DISPREFIX_SEG)
977	? DIS_FMT_SEL_FROM_REG(pDis->x86.idxSegPrefix)
978	: DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
979	pDis->x86.uAddrMode == DISCPUMODE_64BIT
980	? (uint64_t)off2
981	: pDis->x86.uAddrMode == DISCPUMODE_32BIT
982	? (uint32_t)off2
983	: (uint16_t)off2,
984	" (=",
985	')');
986	PUT_C(']');
987	}
988	break;
989	}
990
991	case 'F': /* Eflags register (0 - popf/pushf only, avoided in adjustments above). */
992	AssertFailed();
993	break;
994
995	case 'I': /* Immediate data (ParseImmByte, ParseImmByteSX, ParseImmV, ParseImmUshort, ParseImmZ). */
996	Assert(pszFmt == 'b' \|\| pszFmt == 'v' \|\| pszFmt == 'w' \|\| pszFmt == 'z'); pszFmt++;
997	switch (pParam->fUse & ( DISUSE_IMMEDIATE8 \| DISUSE_IMMEDIATE16 \| DISUSE_IMMEDIATE32 \| DISUSE_IMMEDIATE64
998	\| DISUSE_IMMEDIATE16_SX8 \| DISUSE_IMMEDIATE32_SX8 \| DISUSE_IMMEDIATE64_SX8))
999	{
1000	case DISUSE_IMMEDIATE8:
1001	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
1002	&& ( (pOp->fParam1 >= OP_PARM_REG_GEN8_START && pOp->fParam1 <= OP_PARM_REG_GEN8_END)
1003	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN8_START && pOp->fParam2 <= OP_PARM_REG_GEN8_END))
1004	)
1005	PUT_SZ("strict byte ");
1006	PUT_NUM_8(pParam->uValue);
1007	break;
1008
1009	case DISUSE_IMMEDIATE16:
1010	if ( pDis->uCpuMode != pDis->x86.uOpMode
1011	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
1012	&& ( (int8_t)pParam->uValue == (int16_t)pParam->uValue
1013	\|\| (pOp->fParam1 >= OP_PARM_REG_GEN16_START && pOp->fParam1 <= OP_PARM_REG_GEN16_END)
1014	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN16_START && pOp->fParam2 <= OP_PARM_REG_GEN16_END))
1015	)
1016	)
1017	{
1018	if (OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_b)
1019	PUT_SZ_STRICT("strict byte ", "byte ");
1020	else if ( OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_v
1021	\|\| OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_z)
1022	PUT_SZ_STRICT("strict word ", "word ");
1023	}
1024	PUT_NUM_16(pParam->uValue);
1025	break;
1026
1027	case DISUSE_IMMEDIATE16_SX8:
1028	if ( !(pDis->x86.fPrefix & DISPREFIX_OPSIZE)
1029	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
1030	PUT_SZ_STRICT("strict byte ", "byte ");
1031	else
1032	PUT_SZ("word ");
1033	PUT_NUM_16(pParam->uValue);
1034	break;
1035
1036	case DISUSE_IMMEDIATE32:
1037	if ( pDis->x86.uOpMode != (pDis->uCpuMode == DISCPUMODE_16BIT ? DISCPUMODE_16BIT : DISCPUMODE_32BIT) /* not perfect */
1038	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
1039	&& ( (int8_t)pParam->uValue == (int32_t)pParam->uValue
1040	\|\| (pOp->fParam1 >= OP_PARM_REG_GEN32_START && pOp->fParam1 <= OP_PARM_REG_GEN32_END)
1041	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN32_START && pOp->fParam2 <= OP_PARM_REG_GEN32_END))
1042	)
1043	)
1044	{
1045	if (OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_b)
1046	PUT_SZ_STRICT("strict byte ", "byte ");
1047	else if ( OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_v
1048	\|\| OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_z)
1049	PUT_SZ_STRICT("strict dword ", "dword ");
1050	}
1051	PUT_NUM_32(pParam->uValue);
1052	if (pDis->uCpuMode == DISCPUMODE_32BIT)
1053	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uValue, " (=", ')');
1054	break;
1055
1056	case DISUSE_IMMEDIATE32_SX8:
1057	if ( !(pDis->x86.fPrefix & DISPREFIX_OPSIZE)
1058	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
1059	PUT_SZ_STRICT("strict byte ", "byte ");
1060	else
1061	PUT_SZ("dword ");
1062	PUT_NUM_32(pParam->uValue);
1063	break;
1064
1065	case DISUSE_IMMEDIATE64_SX8:
1066	if ( !(pDis->x86.fPrefix & DISPREFIX_OPSIZE)
1067	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
1068	PUT_SZ_STRICT("strict byte ", "byte ");
1069	else
1070	PUT_SZ("qword ");
1071	PUT_NUM_64(pParam->uValue);
1072	break;
1073
1074	case DISUSE_IMMEDIATE64:
1075	PUT_NUM_64(pParam->uValue);
1076	break;
1077
1078	default:
1079	AssertFailed();
1080	break;
1081	}
1082	break;
1083
1084	case 'J': /* Relative jump offset (ParseImmBRel + ParseImmVRel). */
1085	{
1086	int32_t offDisplacement;
1087	Assert(iParam == 0);
1088	bool fPrefix = (fFlags & DIS_FMT_FLAGS_STRICT)
1089	&& pOp->uOpcode != OP_CALL
1090	&& pOp->uOpcode != OP_LOOP
1091	&& pOp->uOpcode != OP_LOOPE
1092	&& pOp->uOpcode != OP_LOOPNE
1093	&& pOp->uOpcode != OP_JECXZ;
1094	if (pOp->uOpcode == OP_CALL)
1095	fFlags &= ~DIS_FMT_FLAGS_RELATIVE_BRANCH;
1096
1097	if (pParam->fUse & DISUSE_IMMEDIATE8_REL)
1098	{
1099	if (fPrefix)
1100	PUT_SZ("short ");
1101	offDisplacement = (int8_t)pParam->uValue;
1102	Assert(*pszFmt == 'b'); pszFmt++;
1103
1104	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1105	PUT_NUM_S8(offDisplacement);
1106	}
1107	else if (pParam->fUse & DISUSE_IMMEDIATE16_REL)
1108	{
1109	if (fPrefix)
1110	PUT_SZ("near ");
1111	offDisplacement = (int16_t)pParam->uValue;
1112	Assert(*pszFmt == 'v'); pszFmt++;
1113
1114	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1115	PUT_NUM_S16(offDisplacement);
1116	}
1117	else
1118	{
1119	if (fPrefix)
1120	PUT_SZ("near ");
1121	offDisplacement = (int32_t)pParam->uValue;
1122	Assert(pParam->fUse & (DISUSE_IMMEDIATE32_REL \| DISUSE_IMMEDIATE64_REL));
1123	Assert(*pszFmt == 'v'); pszFmt++;
1124
1125	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1126	PUT_NUM_S32(offDisplacement);
1127	}
1128	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1129	PUT_SZ(" (");
1130
1131	RTUINTPTR uTrgAddr = pDis->uInstrAddr + pDis->cbInstr + offDisplacement;
1132	if (pDis->uCpuMode == DISCPUMODE_16BIT)
1133	PUT_NUM_16(uTrgAddr);
1134	else if (pDis->uCpuMode == DISCPUMODE_32BIT)
1135	PUT_NUM_32(uTrgAddr);
1136	else
1137	PUT_NUM_64(uTrgAddr);
1138
1139	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1140	{
1141	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " = ", ' ');
1142	PUT_C(')');
1143	}
1144	else
1145	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " (", ')');
1146	break;
1147	}
1148
1149	case 'A': /* Direct (jump/call) address (ParseImmAddr). */
1150	{
1151	Assert(*pszFmt == 'p'); pszFmt++;
1152	PUT_FAR();
1153	PUT_SIZE_OVERRIDE();
1154	PUT_SEGMENT_OVERRIDE();
1155	off = 0;
1156	int rc = VERR_SYMBOL_NOT_FOUND;
1157	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
1158	{
1159	case DISUSE_IMMEDIATE_ADDR_16_16:
1160	PUT_NUM_16(pParam->uValue >> 16);
1161	PUT_C(':');
1162	PUT_NUM_16(pParam->uValue);
1163	if (pfnGetSymbol)
1164	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1165	break;
1166	case DISUSE_IMMEDIATE_ADDR_16_32:
1167	PUT_NUM_16(pParam->uValue >> 32);
1168	PUT_C(':');
1169	PUT_NUM_32(pParam->uValue);
1170	if (pfnGetSymbol)
1171	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1172	break;
1173	case DISUSE_DISPLACEMENT16:
1174	PUT_NUM_16(pParam->uValue);
1175	if (pfnGetSymbol)
1176	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1177	break;
1178	case DISUSE_DISPLACEMENT32:
1179	PUT_NUM_32(pParam->uValue);
1180	if (pfnGetSymbol)
1181	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1182	break;
1183	case DISUSE_DISPLACEMENT64:
1184	PUT_NUM_64(pParam->uValue);
1185	if (pfnGetSymbol)
1186	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint64_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1187	break;
1188	default:
1189	AssertFailed();
1190	break;
1191	}
1192
1193	PUT_SYMBOL_TWO(rc, " [", ']');
1194	break;
1195	}
1196
1197	case 'O': /* No ModRM byte (ParseImmAddr). */
1198	{
1199	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1200	PUT_FAR();
1201	PUT_SIZE_OVERRIDE();
1202	PUT_C('[');
1203	PUT_SEGMENT_OVERRIDE();
1204	off = 0;
1205	int rc = VERR_SYMBOL_NOT_FOUND;
1206	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
1207	{
1208	case DISUSE_IMMEDIATE_ADDR_16_16:
1209	PUT_NUM_16(pParam->uValue >> 16);
1210	PUT_C(':');
1211	PUT_NUM_16(pParam->uValue);
1212	if (pfnGetSymbol)
1213	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1214	break;
1215	case DISUSE_IMMEDIATE_ADDR_16_32:
1216	PUT_NUM_16(pParam->uValue >> 32);
1217	PUT_C(':');
1218	PUT_NUM_32(pParam->uValue);
1219	if (pfnGetSymbol)
1220	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1221	break;
1222	case DISUSE_DISPLACEMENT16:
1223	PUT_NUM_16(pParam->x86.uDisp.i16);
1224	if (pfnGetSymbol)
1225	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->x86.uDisp.u16, szSymbol, sizeof(szSymbol), &off, pvUser);
1226	break;
1227	case DISUSE_DISPLACEMENT32:
1228	PUT_NUM_32(pParam->x86.uDisp.i32);
1229	if (pfnGetSymbol)
1230	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->x86.uDisp.u32, szSymbol, sizeof(szSymbol), &off, pvUser);
1231	break;
1232	case DISUSE_DISPLACEMENT64:
1233	PUT_NUM_64(pParam->x86.uDisp.i64);
1234	if (pfnGetSymbol)
1235	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->x86.uDisp.u64, szSymbol, sizeof(szSymbol), &off, pvUser);
1236	break;
1237	default:
1238	AssertFailed();
1239	break;
1240	}
1241	PUT_C(']');
1242
1243	PUT_SYMBOL_TWO(rc, " (", ')');
1244	break;
1245	}
1246
1247	case 'X': /* DS:SI (ParseXb, ParseXv). */
1248	case 'Y': /* ES:DI (ParseYb, ParseYv). */
1249	{
1250	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1251	PUT_FAR();
1252	PUT_SIZE_OVERRIDE();
1253	PUT_C('[');
1254	if (pParam->fUse & DISUSE_POINTER_DS_BASED)
1255	PUT_SZ("ds:");
1256	else
1257	PUT_SZ("es:");
1258
1259	size_t cchReg;
1260	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1261	PUT_STR(pszReg, cchReg);
1262	PUT_C(']');
1263	break;
1264	}
1265
1266	case 'e': /* Register based on operand size (e.g. %eAX, %eAH) (ParseFixedReg). */
1267	{
1268	Assert(RT_C_IS_ALPHA(pszFmt[0]) && RT_C_IS_ALPHA(pszFmt[1]) && !RT_C_IS_ALPHA(pszFmt[2]));
1269	pszFmt += 2;
1270	size_t cchReg;
1271	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1272	PUT_STR(pszReg, cchReg);
1273	break;
1274	}
1275
1276	default:
1277	AssertMsgFailed(("%c%s!\n", ch, pszFmt));
1278	break;
1279	}
1280	AssertMsg(pszFmt == ',' \|\| pszFmt == '\0', ("%c%s\n", ch, pszFmt));
1281	}
1282	else
1283	{
1284	PUT_C(ch);
1285	if (ch == ',')
1286	{
1287	Assert(*pszFmt != ' ');
1288	PUT_C(' ');
1289	iParam++;
1290	if (iParam >= RT_ELEMENTS(pDis->aParams))
1291	{
1292	AssertFailed();
1293	pParam = NULL;
1294	}
1295	else
1296	pParam = &pDis->aParams[iParam];
1297	}
1298	}
1299	} /* while more to format */
1300	}
1301
1302	/*
1303	* Any additional output to the right of the instruction?
1304	*/
1305	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1306	{
1307	/* some up front padding. */
1308	size_t cchPadding = cchOutput - offInstruction;
1309	cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
1310	PUT_STR(g_szSpaces, cchPadding);
1311
1312	/* comment? */
1313	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1314	PUT_SZ(";");
1315
1316	/*
1317	* The address?
1318	*/
1319	if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
1320	{
1321	PUT_C(' ');
1322	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
1323	if (pDis->uInstrAddr >= _4G)
1324	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
1325	#endif
1326	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
1327	}
1328
1329	/*
1330	* Opcode bytes?
1331	*/
1332	if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
1333	{
1334	PUT_C(' ');
1335	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
1336	cchOutput += cchTmp;
1337	if (cchTmp >= cchDst)
1338	cchTmp = cchDst - (cchDst != 0);
1339	cchDst -= cchTmp;
1340	pszDst += cchTmp;
1341	}
1342	}
1343
1344	/*
1345	* Terminate it - on overflow we'll have reserved one byte for this.
1346	*/
1347	if (cchDst > 0)
1348	*pszDst = '\0';
1349	else
1350	Assert(!cchBuf);
1351
1352	/* clean up macros */
1353	#undef PUT_PSZ
1354	#undef PUT_SZ
1355	#undef PUT_STR
1356	#undef PUT_C
1357	return cchOutput;
1358	}
1359
1360
1361	/**
1362	* Formats the current instruction in Yasm (/ Nasm) style.
1363	*
1364	* This is a simplified version of DISFormatYasmEx() provided for your convenience.
1365	*
1366	*
1367	* @returns The number of output characters. If this is >= cchBuf, then the content
1368	* of pszBuf will be truncated.
1369	* @param pDis Pointer to the disassembler state.
1370	* @param pszBuf The output buffer.
1371	* @param cchBuf The size of the output buffer.
1372	*/
1373	DISDECL(size_t) DISFormatYasm(PCDISSTATE pDis, char *pszBuf, size_t cchBuf)
1374	{
1375	return DISFormatYasmEx(pDis, pszBuf, cchBuf, 0 /* fFlags /, NULL / pfnGetSymbol /, NULL / pvUser */);
1376	}
1377
1378
1379	/**
1380	* Checks if the encoding of the given disassembled instruction is something we
1381	* can never get YASM to produce.
1382	*
1383	* @returns true if it's odd, false if it isn't.
1384	* @param pDis The disassembler output. The byte fetcher callback will
1385	* be used if present as we might need to fetch opcode
1386	* bytes.
1387	*/
1388	DISDECL(bool) DISFormatYasmIsOddEncoding(PDISSTATE pDis)
1389	{
1390	/*
1391	* Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons.
1392	*/
1393	if ( pDis->x86.uAddrMode != DISCPUMODE_16BIT /// @todo correct?
1394	&& pDis->x86.ModRM.Bits.Rm == 4
1395	&& pDis->x86.ModRM.Bits.Mod != 3)
1396	{
1397	/* No scaled index SIB (index=4), except for ESP. */
1398	if ( pDis->x86.SIB.Bits.Index == 4
1399	&& pDis->x86.SIB.Bits.Base != 4)
1400	return true;
1401
1402	/* EBP + displacement */
1403	if ( pDis->x86.ModRM.Bits.Mod != 0
1404	&& pDis->x86.SIB.Bits.Base == 5
1405	&& pDis->x86.SIB.Bits.Scale == 0)
1406	return true;
1407	}
1408
1409	/*
1410	* Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
1411	*/
1412	if ( pDis->pCurInstr->uOpcode == OP_SHL
1413	&& pDis->x86.ModRM.Bits.Reg == 6)
1414	return true;
1415
1416	/*
1417	* Check for multiple prefixes of the same kind.
1418	*/
1419	uint8_t off1stSeg = UINT8_MAX;
1420	uint8_t offOpSize = UINT8_MAX;
1421	uint8_t offAddrSize = UINT8_MAX;
1422	uint32_t fPrefixes = 0;
1423	for (uint32_t offOpcode = 0; offOpcode < RT_ELEMENTS(pDis->Instr.ab); offOpcode++)
1424	{
1425	uint32_t f;
1426	switch (pDis->Instr.ab[offOpcode])
1427	{
1428	case 0xf0:
1429	f = DISPREFIX_LOCK;
1430	break;
1431
1432	case 0xf2:
1433	case 0xf3:
1434	f = DISPREFIX_REP; /* yes, both */
1435	break;
1436
1437	case 0x2e:
1438	case 0x3e:
1439	case 0x26:
1440	case 0x36:
1441	case 0x64:
1442	case 0x65:
1443	if (off1stSeg == UINT8_MAX)
1444	off1stSeg = offOpcode;
1445	f = DISPREFIX_SEG;
1446	break;
1447
1448	case 0x66:
1449	if (offOpSize == UINT8_MAX)
1450	offOpSize = offOpcode;
1451	f = DISPREFIX_OPSIZE;
1452	break;
1453
1454	case 0x67:
1455	if (offAddrSize == UINT8_MAX)
1456	offAddrSize = offOpcode;
1457	f = DISPREFIX_ADDRSIZE;
1458	break;
1459
1460	case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
1461	case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
1462	f = pDis->uCpuMode == DISCPUMODE_64BIT ? DISPREFIX_REX : 0;
1463	break;
1464
1465	default:
1466	f = 0;
1467	break;
1468	}
1469	if (!f)
1470	break; /* done */
1471	if (fPrefixes & f)
1472	return true;
1473	fPrefixes \|= f;
1474	}
1475
1476	/* segment overrides are fun */
1477	if (fPrefixes & DISPREFIX_SEG)
1478	{
1479	/* no effective address which it may apply to. */
1480	Assert((pDis->x86.fPrefix & DISPREFIX_SEG) \|\| pDis->uCpuMode == DISCPUMODE_64BIT);
1481	if ( !DISUSE_IS_EFFECTIVE_ADDR(pDis->aParams[0].fUse)
1482	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->aParams[1].fUse)
1483	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->aParams[2].fUse))
1484	return true;
1485
1486	/* Yasm puts the segment prefixes before the operand prefix with no
1487	way of overriding it. */
1488	if (offOpSize < off1stSeg)
1489	return true;
1490	}
1491
1492	/* fixed register + addr override doesn't go down all that well. */
1493	if (fPrefixes & DISPREFIX_ADDRSIZE)
1494	{
1495	Assert(pDis->x86.fPrefix & DISPREFIX_ADDRSIZE);
1496	if ( pDis->pCurInstr->fParam3 == OP_PARM_NONE
1497	&& pDis->pCurInstr->fParam2 == OP_PARM_NONE
1498	&& ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1499	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END))
1500	return true;
1501	}
1502
1503	/* Almost all prefixes are bad for jumps. */
1504	if (fPrefixes)
1505	{
1506	switch (pDis->pCurInstr->uOpcode)
1507	{
1508	/* nop w/ prefix(es). */
1509	case OP_NOP:
1510	return true;
1511
1512	case OP_JMP:
1513	if ( pDis->pCurInstr->fParam1 != OP_PARM_Jb
1514	&& pDis->pCurInstr->fParam1 != OP_PARM_Jv)
1515	break;
1516	RT_FALL_THRU();
1517	case OP_JO:
1518	case OP_JNO:
1519	case OP_JC:
1520	case OP_JNC:
1521	case OP_JE:
1522	case OP_JNE:
1523	case OP_JBE:
1524	case OP_JNBE:
1525	case OP_JS:
1526	case OP_JNS:
1527	case OP_JP:
1528	case OP_JNP:
1529	case OP_JL:
1530	case OP_JNL:
1531	case OP_JLE:
1532	case OP_JNLE:
1533	/** @todo branch hinting 0x2e/0x3e... */
1534	return true;
1535	}
1536
1537	}
1538
1539	/* All but the segment prefix is bad news for push/pop. */
1540	if (fPrefixes & ~DISPREFIX_SEG)
1541	{
1542	switch (pDis->pCurInstr->uOpcode)
1543	{
1544	case OP_POP:
1545	case OP_PUSH:
1546	if ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_SEG_START
1547	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_SEG_END)
1548	return true;
1549	if ( (fPrefixes & ~DISPREFIX_OPSIZE)
1550	&& pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1551	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END)
1552	return true;
1553	break;
1554
1555	case OP_POPA:
1556	case OP_POPF:
1557	case OP_PUSHA:
1558	case OP_PUSHF:
1559	if (fPrefixes & ~DISPREFIX_OPSIZE)
1560	return true;
1561	break;
1562	}
1563	}
1564
1565	/* Implicit 8-bit register instructions doesn't mix with operand size. */
1566	if ( (fPrefixes & DISPREFIX_OPSIZE)
1567	&& ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1568	&& pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1569	\|\| ( pDis->pCurInstr->fParam2 == OP_PARM_Gb /* r8 */
1570	&& pDis->pCurInstr->fParam1 == OP_PARM_Eb /* r8/mem8 */))
1571	)
1572	{
1573	switch (pDis->pCurInstr->uOpcode)
1574	{
1575	case OP_ADD:
1576	case OP_OR:
1577	case OP_ADC:
1578	case OP_SBB:
1579	case OP_AND:
1580	case OP_SUB:
1581	case OP_XOR:
1582	case OP_CMP:
1583	return true;
1584	default:
1585	break;
1586	}
1587	}
1588
1589	/* Instructions taking no address or operand which thus may be annoyingly
1590	difficult to format for yasm. */
1591	if (fPrefixes)
1592	{
1593	switch (pDis->pCurInstr->uOpcode)
1594	{
1595	case OP_STI:
1596	case OP_STC:
1597	case OP_CLI:
1598	case OP_CLD:
1599	case OP_CLC:
1600	case OP_INT:
1601	case OP_INT3:
1602	case OP_INTO:
1603	case OP_HLT:
1604	/** @todo Many more to can be added here. */
1605	return true;
1606	default:
1607	break;
1608	}
1609	}
1610
1611	/* FPU and other instructions that ignores operand size override. */
1612	if (fPrefixes & DISPREFIX_OPSIZE)
1613	{
1614	switch (pDis->pCurInstr->uOpcode)
1615	{
1616	/* FPU: */
1617	case OP_FIADD:
1618	case OP_FIMUL:
1619	case OP_FISUB:
1620	case OP_FISUBR:
1621	case OP_FIDIV:
1622	case OP_FIDIVR:
1623	/** @todo there are many more. */
1624	return true;
1625
1626	case OP_MOV:
1627	/** @todo could be that we're not disassembling these correctly. */
1628	if (pDis->pCurInstr->fParam1 == OP_PARM_Sw)
1629	return true;
1630	/** @todo what about the other way? */
1631	break;
1632
1633	default:
1634	break;
1635	}
1636	}
1637
1638
1639	/*
1640	* Check for the version of xyz reg,reg instruction that the assembler doesn't use.
1641	*
1642	* For example:
1643	* expected: 1aee sbb ch, dh ; SBB r8, r/m8
1644	* yasm: 18F5 sbb ch, dh ; SBB r/m8, r8
1645	*/
1646	if (pDis->x86.ModRM.Bits.Mod == 3 /* reg,reg */)
1647	{
1648	switch (pDis->pCurInstr->uOpcode)
1649	{
1650	case OP_ADD:
1651	case OP_OR:
1652	case OP_ADC:
1653	case OP_SBB:
1654	case OP_AND:
1655	case OP_SUB:
1656	case OP_XOR:
1657	case OP_CMP:
1658	if ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1659	&& pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1660	\|\| ( pDis->pCurInstr->fParam1 == OP_PARM_Gv /* rX */
1661	&& pDis->pCurInstr->fParam2 == OP_PARM_Ev /* rX/memX */))
1662	return true;
1663
1664	/* 82 (see table A-6). */
1665	if (pDis->x86.bOpCode == 0x82)
1666	return true;
1667	break;
1668
1669	/* ff /0, fe /0, ff /1, fe /0 */
1670	case OP_DEC:
1671	case OP_INC:
1672	return true;
1673
1674	case OP_POP:
1675	case OP_PUSH:
1676	Assert(pDis->x86.bOpCode == 0x8f);
1677	return true;
1678
1679	case OP_MOV:
1680	if ( pDis->x86.bOpCode == 0x8a
1681	\|\| pDis->x86.bOpCode == 0x8b)
1682	return true;
1683	break;
1684
1685	default:
1686	break;
1687	}
1688	}
1689
1690	/* shl eax,1 will be assembled to the form without the immediate byte. */
1691	if ( pDis->pCurInstr->fParam2 == OP_PARM_Ib
1692	&& (uint8_t)pDis->aParams[1].uValue == 1)
1693	{
1694	switch (pDis->pCurInstr->uOpcode)
1695	{
1696	case OP_SHL:
1697	case OP_SHR:
1698	case OP_SAR:
1699	case OP_RCL:
1700	case OP_RCR:
1701	case OP_ROL:
1702	case OP_ROR:
1703	return true;
1704	}
1705	}
1706
1707	/* And some more - see table A-6. */
1708	if (pDis->x86.bOpCode == 0x82)
1709	{
1710	switch (pDis->pCurInstr->uOpcode)
1711	{
1712	case OP_ADD:
1713	case OP_OR:
1714	case OP_ADC:
1715	case OP_SBB:
1716	case OP_AND:
1717	case OP_SUB:
1718	case OP_XOR:
1719	case OP_CMP:
1720	return true;
1721	break;
1722	}
1723	}
1724
1725
1726	/* check for REX.X = 1 without SIB. */
1727
1728	/* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
1729	says (intel doesn't appear to care). */
1730	switch (pDis->pCurInstr->uOpcode)
1731	{
1732	case OP_SETO:
1733	case OP_SETNO:
1734	case OP_SETC:
1735	case OP_SETNC:
1736	case OP_SETE:
1737	case OP_SETNE:
1738	case OP_SETBE:
1739	case OP_SETNBE:
1740	case OP_SETS:
1741	case OP_SETNS:
1742	case OP_SETP:
1743	case OP_SETNP:
1744	case OP_SETL:
1745	case OP_SETNL:
1746	case OP_SETLE:
1747	case OP_SETNLE:
1748	AssertMsg(pDis->x86.bOpCode >= 0x90 && pDis->x86.bOpCode <= 0x9f, ("%#x\n", pDis->x86.bOpCode));
1749	if (pDis->x86.ModRM.Bits.Reg != 2)
1750	return true;
1751	break;
1752	}
1753
1754	/*
1755	* The MOVZX reg32,mem16 instruction without an operand size prefix
1756	* doesn't quite make sense...
1757	*/
1758	if ( pDis->pCurInstr->uOpcode == OP_MOVZX
1759	&& pDis->x86.bOpCode == 0xB7
1760	&& (pDis->uCpuMode == DISCPUMODE_16BIT) != !!(fPrefixes & DISPREFIX_OPSIZE))
1761	return true;
1762
1763	/*
1764	* YASM doesn't do ICEBP/INT1/INT01, unlike NASM.
1765	*/
1766	if (pDis->x86.bOpCode == 0xF1)
1767	return true;
1768
1769	return false;
1770	}
1771

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source: vbox/trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp@ 105726

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