DisasmFormatYasm.cpp@ 101546

Last change on this file since 101546 was 101546, checked in by vboxsync, 11 months ago
DIS: Added DIS_FMT_FLAGS_BYTES_WIDTH_MASK/SHIFT/MAKE and DIS_FMT_FLAGS_C_HEX flags. bugref:10371
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File size: 72.0 KB

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1	/* $Id: DisasmFormatYasm.cpp 101546 2023-10-23 00:50:04Z vboxsync $ */
2	/** @file
3	* VBox Disassembler - Yasm(/Nasm) Style Formatter.
4	*/
5
6	/*
7	* Copyright (C) 2008-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#include <VBox/dis.h>
33	#include "DisasmInternal.h"
34	#include <iprt/assert.h>
35	#include <iprt/ctype.h>
36	#include <iprt/err.h>
37	#include <iprt/string.h>
38
39
40	/*********************************************************************************************************************************
41	* Global Variables *
42	*********************************************************************************************************************************/
43	static const char g_szSpaces[] =
44	" ";
45	static const char g_aszYasmRegGen8[20][5] =
46	{
47	"al\0\0", "cl\0\0", "dl\0\0", "bl\0\0", "ah\0\0", "ch\0\0", "dh\0\0", "bh\0\0", "r8b\0", "r9b\0", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", "spl\0", "bpl\0", "sil\0", "dil\0"
48	};
49	static const char g_aszYasmRegGen16[16][5] =
50	{
51	"ax\0\0", "cx\0\0", "dx\0\0", "bx\0\0", "sp\0\0", "bp\0\0", "si\0\0", "di\0\0", "r8w\0", "r9w\0", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
52	};
53	#if 0 /* unused */
54	static const char g_aszYasmRegGen1616[8][6] =
55	{
56	"bx+si", "bx+di", "bp+si", "bp+di", "si\0\0\0", "di\0\0\0", "bp\0\0\0", "bx\0\0\0"
57	};
58	#endif
59	static const char g_aszYasmRegGen32[16][5] =
60	{
61	"eax\0", "ecx\0", "edx\0", "ebx\0", "esp\0", "ebp\0", "esi\0", "edi\0", "r8d\0", "r9d\0", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
62	};
63	static const char g_aszYasmRegGen64[16][4] =
64	{
65	"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8\0", "r9\0", "r10", "r11", "r12", "r13", "r14", "r15"
66	};
67	static const char g_aszYasmRegSeg[6][3] =
68	{
69	"es", "cs", "ss", "ds", "fs", "gs"
70	};
71	static const char g_aszYasmRegFP[8][4] =
72	{
73	"st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"
74	};
75	static const char g_aszYasmRegMMX[8][4] =
76	{
77	"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"
78	};
79	static const char g_aszYasmRegXMM[16][6] =
80	{
81	"xmm0\0", "xmm1\0", "xmm2\0", "xmm3\0", "xmm4\0", "xmm5\0", "xmm6\0", "xmm7\0", "xmm8\0", "xmm9\0", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
82	};
83	static const char g_aszYasmRegYMM[16][6] =
84	{
85	"ymm0\0", "ymm1\0", "ymm2\0", "ymm3\0", "ymm4\0", "ymm5\0", "ymm6\0", "ymm7\0", "ymm8\0", "ymm9\0", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15"
86	};
87	static const char g_aszYasmRegCRx[16][5] =
88	{
89	"cr0\0", "cr1\0", "cr2\0", "cr3\0", "cr4\0", "cr5\0", "cr6\0", "cr7\0", "cr8\0", "cr9\0", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
90	};
91	static const char g_aszYasmRegDRx[16][5] =
92	{
93	"dr0\0", "dr1\0", "dr2\0", "dr3\0", "dr4\0", "dr5\0", "dr6\0", "dr7\0", "dr8\0", "dr9\0", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
94	};
95	static const char g_aszYasmRegTRx[16][5] =
96	{
97	"tr0\0", "tr1\0", "tr2\0", "tr3\0", "tr4\0", "tr5\0", "tr6\0", "tr7\0", "tr8\0", "tr9\0", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"
98	};
99
100
101
102	/**
103	* Gets the base register name for the given parameter.
104	*
105	* @returns Pointer to the register name.
106	* @param pDis The disassembler state.
107	* @param pParam The parameter.
108	* @param pcchReg Where to store the length of the name.
109	*/
110	static const char disasmFormatYasmBaseReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t pcchReg)
111	{
112	RT_NOREF_PV(pDis);
113
114	switch (pParam->fUse & ( DISUSE_REG_GEN8 \| DISUSE_REG_GEN16 \| DISUSE_REG_GEN32 \| DISUSE_REG_GEN64
115	\| DISUSE_REG_FP \| DISUSE_REG_MMX \| DISUSE_REG_XMM \| DISUSE_REG_YMM
116	\| DISUSE_REG_CR \| DISUSE_REG_DBG \| DISUSE_REG_SEG \| DISUSE_REG_TEST))
117
118	{
119	case DISUSE_REG_GEN8:
120	{
121	Assert(pParam->x86.Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen8));
122	const char *psz = g_aszYasmRegGen8[pParam->x86.Base.idxGenReg];
123	*pcchReg = 2 + !!psz[2] + !!psz[3];
124	return psz;
125	}
126
127	case DISUSE_REG_GEN16:
128	{
129	Assert(pParam->x86.Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
130	const char *psz = g_aszYasmRegGen16[pParam->x86.Base.idxGenReg];
131	*pcchReg = 2 + !!psz[2] + !!psz[3];
132	return psz;
133	}
134
135	// VSIB
136	case DISUSE_REG_XMM \| DISUSE_REG_GEN32:
137	case DISUSE_REG_YMM \| DISUSE_REG_GEN32:
138	case DISUSE_REG_GEN32:
139	{
140	Assert(pParam->x86.Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
141	const char *psz = g_aszYasmRegGen32[pParam->x86.Base.idxGenReg];
142	*pcchReg = 2 + !!psz[2] + !!psz[3];
143	return psz;
144	}
145
146	// VSIB
147	case DISUSE_REG_XMM \| DISUSE_REG_GEN64:
148	case DISUSE_REG_YMM \| DISUSE_REG_GEN64:
149	case DISUSE_REG_GEN64:
150	{
151	Assert(pParam->x86.Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
152	const char *psz = g_aszYasmRegGen64[pParam->x86.Base.idxGenReg];
153	*pcchReg = 2 + !!psz[2] + !!psz[3];
154	return psz;
155	}
156
157	case DISUSE_REG_FP:
158	{
159	Assert(pParam->x86.Base.idxFpuReg < RT_ELEMENTS(g_aszYasmRegFP));
160	const char *psz = g_aszYasmRegFP[pParam->x86.Base.idxFpuReg];
161	*pcchReg = 3;
162	return psz;
163	}
164
165	case DISUSE_REG_MMX:
166	{
167	Assert(pParam->x86.Base.idxMmxReg < RT_ELEMENTS(g_aszYasmRegMMX));
168	const char *psz = g_aszYasmRegMMX[pParam->x86.Base.idxMmxReg];
169	*pcchReg = 3;
170	return psz;
171	}
172
173	case DISUSE_REG_XMM:
174	{
175	Assert(pParam->x86.Base.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
176	const char *psz = g_aszYasmRegXMM[pParam->x86.Base.idxXmmReg];
177	*pcchReg = 4 + !!psz[4];
178	return psz;
179	}
180
181	case DISUSE_REG_YMM:
182	{
183	Assert(pParam->x86.Base.idxYmmReg < RT_ELEMENTS(g_aszYasmRegYMM));
184	const char *psz = g_aszYasmRegYMM[pParam->x86.Base.idxYmmReg];
185	*pcchReg = 4 + !!psz[4];
186	return psz;
187	}
188
189	case DISUSE_REG_CR:
190	{
191	Assert(pParam->x86.Base.idxCtrlReg < RT_ELEMENTS(g_aszYasmRegCRx));
192	const char *psz = g_aszYasmRegCRx[pParam->x86.Base.idxCtrlReg];
193	*pcchReg = 3;
194	return psz;
195	}
196
197	case DISUSE_REG_DBG:
198	{
199	Assert(pParam->x86.Base.idxDbgReg < RT_ELEMENTS(g_aszYasmRegDRx));
200	const char *psz = g_aszYasmRegDRx[pParam->x86.Base.idxDbgReg];
201	*pcchReg = 3;
202	return psz;
203	}
204
205	case DISUSE_REG_SEG:
206	{
207	Assert(pParam->x86.Base.idxSegReg < RT_ELEMENTS(g_aszYasmRegCRx));
208	const char *psz = g_aszYasmRegSeg[pParam->x86.Base.idxSegReg];
209	*pcchReg = 2;
210	return psz;
211	}
212
213	case DISUSE_REG_TEST:
214	{
215	Assert(pParam->x86.Base.idxTestReg < RT_ELEMENTS(g_aszYasmRegTRx));
216	const char *psz = g_aszYasmRegTRx[pParam->x86.Base.idxTestReg];
217	*pcchReg = 3;
218	return psz;
219	}
220
221	default:
222	AssertMsgFailed(("%#x\n", pParam->fUse));
223	*pcchReg = 3;
224	return "r??";
225	}
226	}
227
228
229	/**
230	* Gets the index register name for the given parameter.
231	*
232	* @returns The index register name.
233	* @param pDis The disassembler state.
234	* @param pParam The parameter.
235	* @param pcchReg Where to store the length of the name.
236	*/
237	static const char disasmFormatYasmIndexReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t pcchReg)
238	{
239	if (pParam->fUse & DISUSE_REG_XMM)
240	{
241	Assert(pParam->x86.Index.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
242	const char *psz = g_aszYasmRegXMM[pParam->x86.Index.idxXmmReg];
243	*pcchReg = 4 + !!psz[4];
244	return psz;
245	}
246	else if (pParam->fUse & DISUSE_REG_YMM)
247	{
248	Assert(pParam->x86.Index.idxYmmReg < RT_ELEMENTS(g_aszYasmRegYMM));
249	const char *psz = g_aszYasmRegYMM[pParam->x86.Index.idxYmmReg];
250	*pcchReg = 4 + !!psz[4];
251	return psz;
252
253	}
254	else
255	switch (pDis->x86.uAddrMode)
256	{
257	case DISCPUMODE_16BIT:
258	{
259	Assert(pParam->x86.Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
260	const char *psz = g_aszYasmRegGen16[pParam->x86.Index.idxGenReg];
261	*pcchReg = 2 + !!psz[2] + !!psz[3];
262	return psz;
263	}
264
265	case DISCPUMODE_32BIT:
266	{
267	Assert(pParam->x86.Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
268	const char *psz = g_aszYasmRegGen32[pParam->x86.Index.idxGenReg];
269	*pcchReg = 2 + !!psz[2] + !!psz[3];
270	return psz;
271	}
272
273	case DISCPUMODE_64BIT:
274	{
275	Assert(pParam->x86.Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
276	const char *psz = g_aszYasmRegGen64[pParam->x86.Index.idxGenReg];
277	*pcchReg = 2 + !!psz[2] + !!psz[3];
278	return psz;
279	}
280
281	default:
282	AssertMsgFailed(("%#x %#x\n", pParam->fUse, pDis->x86.uAddrMode));
283	*pcchReg = 3;
284	return "r??";
285	}
286	}
287
288
289	/**
290	* Formats the current instruction in Yasm (/ Nasm) style.
291	*
292	*
293	* @returns The number of output characters. If this is >= cchBuf, then the content
294	* of pszBuf will be truncated.
295	* @param pDis Pointer to the disassembler state.
296	* @param pszBuf The output buffer.
297	* @param cchBuf The size of the output buffer.
298	* @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
299	* @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
300	* @param pvUser User argument for pfnGetSymbol.
301	*/
302	DISDECL(size_t) DISFormatYasmEx(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags,
303	PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
304	{
305	/** @todo monitor and mwait aren't formatted correctly in 64-bit mode. */
306	/*
307	* Input validation and massaging.
308	*/
309	AssertPtr(pDis);
310	AssertPtrNull(pszBuf);
311	Assert(pszBuf \|\| !cchBuf);
312	AssertPtrNull(pfnGetSymbol);
313	AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
314	if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
315	fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) \| DIS_FMT_FLAGS_ADDR_RIGHT;
316	if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
317	fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) \| DIS_FMT_FLAGS_BYTES_RIGHT;
318
319	PCDISOPCODE const pOp = pDis->pCurInstr;
320
321	/*
322	* Output macros
323	*/
324	char *pszDst = pszBuf;
325	size_t cchDst = cchBuf;
326	size_t cchOutput = 0;
327	#define PUT_C(ch) \
328	do { \
329	cchOutput++; \
330	if (cchDst > 1) \
331	{ \
332	cchDst--; \
333	*pszDst++ = (ch); \
334	} \
335	} while (0)
336	#define PUT_STR(pszSrc, cchSrc) \
337	do { \
338	cchOutput += (cchSrc); \
339	if (cchDst > (cchSrc)) \
340	{ \
341	memcpy(pszDst, (pszSrc), (cchSrc)); \
342	pszDst += (cchSrc); \
343	cchDst -= (cchSrc); \
344	} \
345	else if (cchDst > 1) \
346	{ \
347	memcpy(pszDst, (pszSrc), cchDst - 1); \
348	pszDst += cchDst - 1; \
349	cchDst = 1; \
350	} \
351	} while (0)
352	#define PUT_SZ(sz) \
353	PUT_STR((sz), sizeof(sz) - 1)
354	#define PUT_SZ_STRICT(szStrict, szRelaxed) \
355	do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
356	#define PUT_PSZ(psz) \
357	do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
358	#define PUT_NUM(cch, fmt, num) \
359	do { \
360	cchOutput += (cch); \
361	if (cchDst > 1) \
362	{ \
363	const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
364	pszDst += cchTmp; \
365	cchDst -= cchTmp; \
366	Assert(cchTmp == (cch) \|\| cchDst == 1); \
367	} \
368	} while (0)
369	#define PUT_NUM_8(num) PUT_NUM(4, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%02xh" : "%#04x", (uint8_t)(num))
370	#define PUT_NUM_16(num) PUT_NUM(6, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%04xh" : "%#06x", (uint16_t)(num))
371	#define PUT_NUM_32(num) PUT_NUM(10, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%08xh" : "%#010x", (uint32_t)(num))
372	#define PUT_NUM_64(num) PUT_NUM(18, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%016RX64h" : "%#018RX64", (uint64_t)(num))
373
374	#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
375	do { \
376	if ((stype)(num) >= 0) \
377	{ \
378	PUT_C('+'); \
379	PUT_NUM(cch, fmt, (utype)(num)); \
380	} \
381	else \
382	{ \
383	PUT_C('-'); \
384	PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
385	} \
386	} while (0)
387	#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%02xh" : "%#04x", num, int8_t, uint8_t)
388	#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%04xh" : "%#06x", num, int16_t, uint16_t)
389	#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%08xh" : "%#010x", num, int32_t, uint32_t)
390	#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%016RX64h" : "%#018RX64", num, int64_t, uint64_t)
391
392	#define PUT_SYMBOL_TWO(a_rcSym, a_szStart, a_chEnd) \
393	do { \
394	if (RT_SUCCESS(a_rcSym)) \
395	{ \
396	PUT_SZ(a_szStart); \
397	PUT_PSZ(szSymbol); \
398	if (off != 0) \
399	{ \
400	if ((int8_t)off == off) \
401	PUT_NUM_S8(off); \
402	else if ((int16_t)off == off) \
403	PUT_NUM_S16(off); \
404	else if ((int32_t)off == off) \
405	PUT_NUM_S32(off); \
406	else \
407	PUT_NUM_S64(off); \
408	} \
409	PUT_C(a_chEnd); \
410	} \
411	} while (0)
412
413	#define PUT_SYMBOL(a_uSeg, a_uAddr, a_szStart, a_chEnd) \
414	do { \
415	if (pfnGetSymbol) \
416	{ \
417	int rcSym = pfnGetSymbol(pDis, a_uSeg, a_uAddr, szSymbol, sizeof(szSymbol), &off, pvUser); \
418	PUT_SYMBOL_TWO(rcSym, a_szStart, a_chEnd); \
419	} \
420	} while (0)
421
422
423	/*
424	* The address?
425	*/
426	if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
427	{
428	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
429	if (pDis->uInstrAddr >= _4G)
430	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
431	#endif
432	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
433	PUT_C(' ');
434	}
435
436	/*
437	* The opcode bytes?
438	*/
439	if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
440	{
441	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
442	cchOutput += cchTmp;
443	if (cchDst > 1)
444	{
445	if (cchTmp <= cchDst)
446	{
447	cchDst -= cchTmp;
448	pszDst += cchTmp;
449	}
450	else
451	{
452	pszDst += cchDst - 1;
453	cchDst = 1;
454	}
455	}
456
457	/* Some padding to align the instruction. */
458	uint32_t cbWidth = (fFlags & DIS_FMT_FLAGS_BYTES_WIDTH_MASK) >> DIS_FMT_FLAGS_BYTES_WIDTH_SHIFT;
459	if (!cbWidth)
460	cbWidth = 7;
461	size_t cchPadding = (cbWidth * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
462	+ !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
463	+ 2;
464	cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
465	PUT_STR(g_szSpaces, cchPadding);
466	}
467
468
469	/*
470	* Filter out invalid opcodes first as they need special
471	* treatment. UD2 is an exception and should be handled normally.
472	*/
473	size_t const offInstruction = cchOutput;
474	if ( pOp->uOpcode == OP_INVALID
475	\|\| ( pOp->uOpcode == OP_ILLUD2
476	&& (pDis->x86.fPrefix & DISPREFIX_LOCK)))
477	PUT_SZ("Illegal opcode");
478	else
479	{
480	/*
481	* Prefixes
482	*/
483	if (pDis->x86.fPrefix & DISPREFIX_LOCK)
484	PUT_SZ("lock ");
485	if (pDis->x86.fPrefix & DISPREFIX_REP)
486	PUT_SZ("rep ");
487	else if(pDis->x86.fPrefix & DISPREFIX_REPNE)
488	PUT_SZ("repne ");
489
490	/*
491	* Adjust the format string to the correct mnemonic
492	* or to avoid things the assembler cannot handle correctly.
493	*/
494	char szTmpFmt[48];
495	const char *pszFmt = pOp->pszOpcode;
496	bool fIgnoresOpSize = false;
497	bool fMayNeedAddrSize = false;
498	switch (pOp->uOpcode)
499	{
500	case OP_JECXZ:
501	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "jcxz %Jb" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb";
502	break;
503	case OP_PUSHF:
504	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "pushfw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "pushfd" : "pushfq";
505	break;
506	case OP_POPF:
507	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "popfw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "popfd" : "popfq";
508	break;
509	case OP_PUSHA:
510	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "pushaw" : "pushad";
511	break;
512	case OP_POPA:
513	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "popaw" : "popad";
514	break;
515	case OP_INSB:
516	pszFmt = "insb";
517	fIgnoresOpSize = fMayNeedAddrSize = true;
518	break;
519	case OP_INSWD:
520	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "insw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "insd" : "insq";
521	fMayNeedAddrSize = true;
522	break;
523	case OP_OUTSB:
524	pszFmt = "outsb";
525	fIgnoresOpSize = fMayNeedAddrSize = true;
526	break;
527	case OP_OUTSWD:
528	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "outsw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "outsd" : "outsq";
529	fMayNeedAddrSize = true;
530	break;
531	case OP_MOVSB:
532	pszFmt = "movsb";
533	fIgnoresOpSize = fMayNeedAddrSize = true;
534	break;
535	case OP_MOVSWD:
536	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "movsw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "movsd" : "movsq";
537	fMayNeedAddrSize = true;
538	break;
539	case OP_CMPSB:
540	pszFmt = "cmpsb";
541	fIgnoresOpSize = fMayNeedAddrSize = true;
542	break;
543	case OP_CMPWD:
544	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "cmpsw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "cmpsd" : "cmpsq";
545	fMayNeedAddrSize = true;
546	break;
547	case OP_SCASB:
548	pszFmt = "scasb";
549	fIgnoresOpSize = fMayNeedAddrSize = true;
550	break;
551	case OP_SCASWD:
552	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "scasw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "scasd" : "scasq";
553	fMayNeedAddrSize = true;
554	break;
555	case OP_LODSB:
556	pszFmt = "lodsb";
557	fIgnoresOpSize = fMayNeedAddrSize = true;
558	break;
559	case OP_LODSWD:
560	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "lodsw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "lodsd" : "lodsq";
561	fMayNeedAddrSize = true;
562	break;
563	case OP_STOSB:
564	pszFmt = "stosb";
565	fIgnoresOpSize = fMayNeedAddrSize = true;
566	break;
567	case OP_STOSWD:
568	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "stosw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "stosd" : "stosq";
569	fMayNeedAddrSize = true;
570	break;
571	case OP_CBW:
572	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "cbw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "cwde" : "cdqe";
573	break;
574	case OP_CWD:
575	pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "cwd" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "cdq" : "cqo";
576	break;
577	case OP_SHL:
578	Assert(pszFmt[3] == '/');
579	pszFmt += 4;
580	break;
581	case OP_XLAT:
582	pszFmt = "xlatb";
583	break;
584	case OP_INT3:
585	pszFmt = "int3";
586	break;
587
588	/*
589	* Don't know how to tell yasm to generate complicated nop stuff, so 'db' it.
590	*/
591	case OP_NOP:
592	if (pDis->x86.bOpCode == 0x90)
593	/* fine, fine */;
594	else if (pszFmt[sizeof("nop %Ev") - 1] == '/' && pszFmt[sizeof("nop %Ev")] == 'p')
595	pszFmt = "prefetch %Eb";
596	else if (pDis->x86.bOpCode == 0x1f)
597	{
598	Assert(pDis->cbInstr >= 3);
599	PUT_SZ("db 00fh, 01fh");
600	for (unsigned off = 2; off < pDis->cbInstr; off++)
601	{
602	PUT_C(',');
603	PUT_C(' ');
604	PUT_NUM_8(pDis->Instr.ab[off]);
605	}
606	pszFmt = "";
607	}
608	break;
609
610	default:
611	/* ST(X) -> stX (floating point) */
612	if (*pszFmt == 'f' && strchr(pszFmt, '('))
613	{
614	char *pszFmtDst = szTmpFmt;
615	char ch;
616	do
617	{
618	ch = *pszFmt++;
619	if (ch == 'S' && pszFmt[0] == 'T' && pszFmt[1] == '(')
620	{
621	*pszFmtDst++ = 's';
622	*pszFmtDst++ = 't';
623	pszFmt += 2;
624	ch = *pszFmt;
625	Assert(pszFmt[1] == ')');
626	pszFmt += 2;
627	*pszFmtDst++ = ch;
628	}
629	else
630	*pszFmtDst++ = ch;
631	} while (ch != '\0');
632	pszFmt = szTmpFmt;
633	}
634	if (strchr("#@&", *pszFmt))
635	{
636	const char *pszDelim = strchr(pszFmt, '/');
637	const char *pszSpace = (pszDelim ? strchr(pszDelim, ' ') : NULL);
638	if (pszDelim != NULL)
639	{
640	char *pszFmtDst = szTmpFmt;
641	if (pszSpace == NULL) pszSpace = strchr(pszDelim, 0);
642	if ( (pszFmt == '#' && !pDis->x86.bVexWFlag) /* @todo check this*/
643	\|\| (*pszFmt == '@' && !VEXREG_IS256B(pDis->x86.bVexDestReg))
644	\|\| (*pszFmt == '&' && ( DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
645	\|\| DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
646	\|\| DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse)
647	\|\| DISUSE_IS_EFFECTIVE_ADDR(pDis->Param4.fUse))))
648	{
649	strncpy(pszFmtDst, pszFmt + 1, pszDelim - pszFmt - 1);
650	pszFmtDst += pszDelim - pszFmt - 1;
651	}
652	else
653	{
654	strncpy(pszFmtDst, pszDelim + 1, pszSpace - pszDelim - 1);
655	pszFmtDst += pszSpace - pszDelim - 1;
656	}
657	strcpy (pszFmtDst, pszSpace);
658	pszFmt = szTmpFmt;
659	}
660	}
661	break;
662
663	/*
664	* Horrible hacks.
665	*/
666	case OP_FLD:
667	if (pDis->x86.bOpCode == 0xdb) /* m80fp workaround. */
668	(int )&pDis->Param1.x86.fParam &= ~0x1f; /* make it pure OP_PARM_M */
669	break;
670	case OP_LAR: /* hack w -> v, probably not correct. */
671	(int )&pDis->Param2.x86.fParam &= ~0x1f;
672	(int )&pDis->Param2.x86.fParam \|= OP_PARM_v;
673	break;
674	}
675
676	/*
677	* Add operand size and address prefixes for outsb, movsb, etc.
678	*/
679	if (pDis->x86.fPrefix & (DISPREFIX_OPSIZE \| DISPREFIX_ADDRSIZE))
680	{
681	if (fIgnoresOpSize && (pDis->x86.fPrefix & DISPREFIX_OPSIZE) )
682	{
683	if (pDis->uCpuMode == DISCPUMODE_16BIT)
684	PUT_SZ("o32 ");
685	else
686	PUT_SZ("o16 ");
687	}
688	if (fMayNeedAddrSize && (pDis->x86.fPrefix & DISPREFIX_ADDRSIZE) )
689	{
690	if (pDis->uCpuMode == DISCPUMODE_16BIT)
691	PUT_SZ("a32 ");
692	else
693	PUT_SZ("a16 ");
694	}
695	}
696
697	/*
698	* Formatting context and associated macros.
699	*/
700	PCDISOPPARAM pParam = &pDis->Param1;
701	int iParam = 1;
702
703	#define PUT_FAR() \
704	do { \
705	if ( OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_p \
706	&& pOp->uOpcode != OP_LDS /* table bugs? */ \
707	&& pOp->uOpcode != OP_LES \
708	&& pOp->uOpcode != OP_LFS \
709	&& pOp->uOpcode != OP_LGS \
710	&& pOp->uOpcode != OP_LSS ) \
711	PUT_SZ("far "); \
712	} while (0)
713	/** @todo mov ah,ch ends up with a byte 'override'... - check if this wasn't fixed. */
714	/** @todo drop the work/dword/qword override when the src/dst is a register (except for movsx/movzx). */
715	#define PUT_SIZE_OVERRIDE() \
716	do { \
717	switch (OP_PARM_VSUBTYPE(pParam->x86.fParam)) \
718	{ \
719	case OP_PARM_v: \
720	case OP_PARM_y: \
721	switch (pDis->x86.uOpMode) \
722	{ \
723	case DISCPUMODE_16BIT: if (OP_PARM_VSUBTYPE(pParam->x86.fParam) != OP_PARM_y) PUT_SZ("word "); break; \
724	case DISCPUMODE_32BIT: \
725	if (pDis->pCurInstr->uOpcode != OP_GATHER \|\| pDis->x86.bVexWFlag) { PUT_SZ("dword "); break; } \
726	RT_FALL_THRU(); \
727	case DISCPUMODE_64BIT: PUT_SZ("qword "); break; \
728	default: break; \
729	} \
730	break; \
731	case OP_PARM_b: PUT_SZ("byte "); break; \
732	case OP_PARM_w: \
733	if ( OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_W \
734	\|\| OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_M) \
735	{ \
736	if (VEXREG_IS256B(pDis->x86.bVexDestReg)) PUT_SZ("dword "); \
737	else PUT_SZ("word "); \
738	} \
739	break; \
740	case OP_PARM_d: \
741	if ( OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_W \
742	\|\| OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_M) \
743	{ \
744	if (VEXREG_IS256B(pDis->x86.bVexDestReg)) PUT_SZ("qword "); \
745	else PUT_SZ("dword "); \
746	} \
747	break; \
748	case OP_PARM_q: \
749	if ( OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_W \
750	\|\| OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_M) \
751	{ \
752	if (VEXREG_IS256B(pDis->x86.bVexDestReg)) PUT_SZ("oword "); \
753	else PUT_SZ("qword "); \
754	} \
755	break; \
756	case OP_PARM_ps: \
757	case OP_PARM_pd: \
758	case OP_PARM_x: if (VEXREG_IS256B(pDis->x86.bVexDestReg)) { PUT_SZ("yword "); break; } RT_FALL_THRU(); \
759	case OP_PARM_ss: \
760	case OP_PARM_sd: \
761	case OP_PARM_dq: PUT_SZ("oword "); break; \
762	case OP_PARM_qq: PUT_SZ("yword "); break; \
763	case OP_PARM_p: break; /* see PUT_FAR */ \
764	case OP_PARM_s: if (pParam->fUse & DISUSE_REG_FP) PUT_SZ("tword "); break; /* ?? */ \
765	case OP_PARM_z: break; \
766	case OP_PARM_NONE: \
767	if ( OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_M \
768	&& ((pParam->fUse & DISUSE_REG_FP) \|\| pOp->uOpcode == OP_FLD)) \
769	PUT_SZ("tword "); \
770	break; \
771	default: break; /no pointer type specified/necessary/ \
772	} \
773	} while (0)
774	static const char s_szSegPrefix[6][4] = { "es:", "cs:", "ss:", "ds:", "fs:", "gs:" };
775	#define PUT_SEGMENT_OVERRIDE() \
776	do { \
777	if (pDis->x86.fPrefix & DISPREFIX_SEG) \
778	PUT_STR(s_szSegPrefix[pDis->x86.idxSegPrefix], 3); \
779	} while (0)
780
781
782	/*
783	* Segment prefixing for instructions that doesn't do memory access.
784	*/
785	if ( (pDis->x86.fPrefix & DISPREFIX_SEG)
786	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
787	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
788	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
789	{
790	PUT_STR(s_szSegPrefix[pDis->x86.idxSegPrefix], 2);
791	PUT_C(' ');
792	}
793
794
795	/*
796	* The formatting loop.
797	*/
798	RTINTPTR off;
799	char szSymbol[128];
800	char ch;
801	while ((ch = *pszFmt++) != '\0')
802	{
803	if (ch == '%')
804	{
805	ch = *pszFmt++;
806	switch (ch)
807	{
808	/*
809	* ModRM - Register only / VEX.vvvv.
810	*/
811	case 'C': /* Control register (ParseModRM / UseModRM). */
812	case 'D': /* Debug register (ParseModRM / UseModRM). */
813	case 'G': /* ModRM selects general register (ParseModRM / UseModRM). */
814	case 'S': /* ModRM byte selects a segment register (ParseModRM / UseModRM). */
815	case 'T': /* ModRM byte selects a test register (ParseModRM / UseModRM). */
816	case 'V': /* ModRM byte selects an XMM/SSE register (ParseModRM / UseModRM). */
817	case 'P': /* ModRM byte selects MMX register (ParseModRM / UseModRM). */
818	case 'H': /* The VEX.vvvv field of the VEX prefix selects a XMM/YMM register. */
819	case 'B': /* The VEX.vvvv field of the VEX prefix selects a general register (ParseVexDest). */
820	case 'L': /* The upper 4 bits of the 8-bit immediate selects a XMM/YMM register. */
821	{
822	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
823	Assert(!(pParam->fUse & (DISUSE_INDEX \| DISUSE_SCALE) /* No SIB here... */));
824	Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)));
825
826	size_t cchReg;
827	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
828	PUT_STR(pszReg, cchReg);
829	break;
830	}
831
832	/*
833	* ModRM - Register or memory.
834	*/
835	case 'E': /* ModRM specifies parameter (ParseModRM / UseModRM / UseSIB). */
836	case 'Q': /* ModRM byte selects MMX register or memory address (ParseModRM / UseModRM). */
837	case 'R': /* ModRM byte may only refer to a general register (ParseModRM / UseModRM). */
838	case 'W': /* ModRM byte selects an XMM/SSE register or a memory address (ParseModRM / UseModRM). */
839	case 'U': /* ModRM byte may only refer to a XMM/SSE register (ParseModRM / UseModRM). */
840	case 'M': /* ModRM byte may only refer to memory (ParseModRM / UseModRM). */
841	{
842	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
843
844	PUT_FAR();
845	uint32_t const fUse = pParam->fUse;
846	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
847	{
848	/* Work around mov seg,[mem16] and mov [mem16],seg as these always make a 16-bit mem
849	while the register variants deals with 16, 32 & 64 in the normal fashion. */
850	if ( pParam->x86.fParam != OP_PARM_Ev
851	\|\| pOp->uOpcode != OP_MOV
852	\|\| ( pOp->fParam1 != OP_PARM_Sw
853	&& pOp->fParam2 != OP_PARM_Sw))
854	PUT_SIZE_OVERRIDE();
855	PUT_C('[');
856	}
857	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
858	&& (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32)))
859	{
860	if ( (fUse & DISUSE_DISPLACEMENT8)
861	&& !pParam->x86.uDisp.i8)
862	PUT_SZ("byte ");
863	else if ( (fUse & DISUSE_DISPLACEMENT16)
864	&& (int8_t)pParam->x86.uDisp.i16 == (int16_t)pParam->x86.uDisp.i16)
865	PUT_SZ("word ");
866	else if ( (fUse & DISUSE_DISPLACEMENT32)
867	&& (int16_t)pParam->x86.uDisp.i32 == (int32_t)pParam->x86.uDisp.i32) //??
868	PUT_SZ("dword ");
869	else if ( (fUse & DISUSE_DISPLACEMENT64)
870	&& (pDis->x86.SIB.Bits.Base != 5 \|\| pDis->x86.ModRM.Bits.Mod != 0)
871	&& (int32_t)pParam->x86.uDisp.i64 == (int64_t)pParam->x86.uDisp.i64) //??
872	PUT_SZ("qword ");
873	}
874	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
875	PUT_SEGMENT_OVERRIDE();
876
877	bool fBase = (fUse & DISUSE_BASE) /* When exactly is DISUSE_BASE supposed to be set? disasmModRMReg doesn't set it. */
878	\|\| ( (fUse & ( DISUSE_REG_GEN8
879	\| DISUSE_REG_GEN16
880	\| DISUSE_REG_GEN32
881	\| DISUSE_REG_GEN64
882	\| DISUSE_REG_FP
883	\| DISUSE_REG_MMX
884	\| DISUSE_REG_XMM
885	\| DISUSE_REG_YMM
886	\| DISUSE_REG_CR
887	\| DISUSE_REG_DBG
888	\| DISUSE_REG_SEG
889	\| DISUSE_REG_TEST ))
890	&& !DISUSE_IS_EFFECTIVE_ADDR(fUse));
891	if (fBase)
892	{
893	size_t cchReg;
894	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
895	PUT_STR(pszReg, cchReg);
896	}
897
898	if (fUse & DISUSE_INDEX)
899	{
900	if (fBase)
901	PUT_C('+');
902
903	size_t cchReg;
904	const char *pszReg = disasmFormatYasmIndexReg(pDis, pParam, &cchReg);
905	PUT_STR(pszReg, cchReg);
906
907	if (fUse & DISUSE_SCALE)
908	{
909	PUT_C('*');
910	PUT_C('0' + pParam->x86.uScale);
911	}
912	}
913	else
914	Assert(!(fUse & DISUSE_SCALE));
915
916	int64_t off2 = 0;
917	if (fUse & (DISUSE_DISPLACEMENT8 \| DISUSE_DISPLACEMENT16 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT64 \| DISUSE_RIPDISPLACEMENT32))
918	{
919	if (fUse & DISUSE_DISPLACEMENT8)
920	off2 = pParam->x86.uDisp.i8;
921	else if (fUse & DISUSE_DISPLACEMENT16)
922	off2 = pParam->x86.uDisp.i16;
923	else if (fUse & (DISUSE_DISPLACEMENT32 \| DISUSE_RIPDISPLACEMENT32))
924	off2 = pParam->x86.uDisp.i32;
925	else if (fUse & DISUSE_DISPLACEMENT64)
926	off2 = pParam->x86.uDisp.i64;
927	else
928	{
929	AssertFailed();
930	off2 = 0;
931	}
932
933	int64_t off3 = off2;
934	if (fBase \|\| (fUse & (DISUSE_INDEX \| DISUSE_RIPDISPLACEMENT32)))
935	{
936	PUT_C(off3 >= 0 ? '+' : '-');
937	if (off3 < 0)
938	off3 = -off3;
939	}
940	if (fUse & DISUSE_DISPLACEMENT8)
941	PUT_NUM_8( off3);
942	else if (fUse & DISUSE_DISPLACEMENT16)
943	PUT_NUM_16(off3);
944	else if (fUse & DISUSE_DISPLACEMENT32)
945	PUT_NUM_32(off3);
946	else if (fUse & DISUSE_DISPLACEMENT64)
947	PUT_NUM_64(off3);
948	else
949	{
950	PUT_NUM_32(off3);
951	PUT_SZ(" wrt rip (");
952	off2 += pDis->uInstrAddr + pDis->cbInstr;
953	PUT_NUM_64(off2);
954	if (pfnGetSymbol)
955	PUT_SYMBOL((pDis->x86.fPrefix & DISPREFIX_SEG)
956	? DIS_FMT_SEL_FROM_REG(pDis->x86.idxSegPrefix)
957	: DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
958	pDis->x86.uAddrMode == DISCPUMODE_64BIT
959	? (uint64_t)off2
960	: pDis->x86.uAddrMode == DISCPUMODE_32BIT
961	? (uint32_t)off2
962	: (uint16_t)off2,
963	" = ",
964	')');
965	else
966	PUT_C(')');
967	}
968	}
969
970	if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
971	{
972	if (pfnGetSymbol && !fBase && !(fUse & (DISUSE_INDEX \| DISUSE_RIPDISPLACEMENT32)) && off2 != 0)
973	PUT_SYMBOL((pDis->x86.fPrefix & DISPREFIX_SEG)
974	? DIS_FMT_SEL_FROM_REG(pDis->x86.idxSegPrefix)
975	: DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
976	pDis->x86.uAddrMode == DISCPUMODE_64BIT
977	? (uint64_t)off2
978	: pDis->x86.uAddrMode == DISCPUMODE_32BIT
979	? (uint32_t)off2
980	: (uint16_t)off2,
981	" (=",
982	')');
983	PUT_C(']');
984	}
985	break;
986	}
987
988	case 'F': /* Eflags register (0 - popf/pushf only, avoided in adjustments above). */
989	AssertFailed();
990	break;
991
992	case 'I': /* Immediate data (ParseImmByte, ParseImmByteSX, ParseImmV, ParseImmUshort, ParseImmZ). */
993	Assert(pszFmt == 'b' \|\| pszFmt == 'v' \|\| pszFmt == 'w' \|\| pszFmt == 'z'); pszFmt++;
994	switch (pParam->fUse & ( DISUSE_IMMEDIATE8 \| DISUSE_IMMEDIATE16 \| DISUSE_IMMEDIATE32 \| DISUSE_IMMEDIATE64
995	\| DISUSE_IMMEDIATE16_SX8 \| DISUSE_IMMEDIATE32_SX8 \| DISUSE_IMMEDIATE64_SX8))
996	{
997	case DISUSE_IMMEDIATE8:
998	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
999	&& ( (pOp->fParam1 >= OP_PARM_REG_GEN8_START && pOp->fParam1 <= OP_PARM_REG_GEN8_END)
1000	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN8_START && pOp->fParam2 <= OP_PARM_REG_GEN8_END))
1001	)
1002	PUT_SZ("strict byte ");
1003	PUT_NUM_8(pParam->uValue);
1004	break;
1005
1006	case DISUSE_IMMEDIATE16:
1007	if ( pDis->uCpuMode != pDis->x86.uOpMode
1008	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
1009	&& ( (int8_t)pParam->uValue == (int16_t)pParam->uValue
1010	\|\| (pOp->fParam1 >= OP_PARM_REG_GEN16_START && pOp->fParam1 <= OP_PARM_REG_GEN16_END)
1011	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN16_START && pOp->fParam2 <= OP_PARM_REG_GEN16_END))
1012	)
1013	)
1014	{
1015	if (OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_b)
1016	PUT_SZ_STRICT("strict byte ", "byte ");
1017	else if ( OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_v
1018	\|\| OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_z)
1019	PUT_SZ_STRICT("strict word ", "word ");
1020	}
1021	PUT_NUM_16(pParam->uValue);
1022	break;
1023
1024	case DISUSE_IMMEDIATE16_SX8:
1025	if ( !(pDis->x86.fPrefix & DISPREFIX_OPSIZE)
1026	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
1027	PUT_SZ_STRICT("strict byte ", "byte ");
1028	else
1029	PUT_SZ("word ");
1030	PUT_NUM_16(pParam->uValue);
1031	break;
1032
1033	case DISUSE_IMMEDIATE32:
1034	if ( pDis->x86.uOpMode != (pDis->uCpuMode == DISCPUMODE_16BIT ? DISCPUMODE_16BIT : DISCPUMODE_32BIT) /* not perfect */
1035	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
1036	&& ( (int8_t)pParam->uValue == (int32_t)pParam->uValue
1037	\|\| (pOp->fParam1 >= OP_PARM_REG_GEN32_START && pOp->fParam1 <= OP_PARM_REG_GEN32_END)
1038	\|\| (pOp->fParam2 >= OP_PARM_REG_GEN32_START && pOp->fParam2 <= OP_PARM_REG_GEN32_END))
1039	)
1040	)
1041	{
1042	if (OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_b)
1043	PUT_SZ_STRICT("strict byte ", "byte ");
1044	else if ( OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_v
1045	\|\| OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_z)
1046	PUT_SZ_STRICT("strict dword ", "dword ");
1047	}
1048	PUT_NUM_32(pParam->uValue);
1049	if (pDis->uCpuMode == DISCPUMODE_32BIT)
1050	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uValue, " (=", ')');
1051	break;
1052
1053	case DISUSE_IMMEDIATE32_SX8:
1054	if ( !(pDis->x86.fPrefix & DISPREFIX_OPSIZE)
1055	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
1056	PUT_SZ_STRICT("strict byte ", "byte ");
1057	else
1058	PUT_SZ("dword ");
1059	PUT_NUM_32(pParam->uValue);
1060	break;
1061
1062	case DISUSE_IMMEDIATE64_SX8:
1063	if ( !(pDis->x86.fPrefix & DISPREFIX_OPSIZE)
1064	\|\| pDis->pCurInstr->uOpcode != OP_PUSH)
1065	PUT_SZ_STRICT("strict byte ", "byte ");
1066	else
1067	PUT_SZ("qword ");
1068	PUT_NUM_64(pParam->uValue);
1069	break;
1070
1071	case DISUSE_IMMEDIATE64:
1072	PUT_NUM_64(pParam->uValue);
1073	break;
1074
1075	default:
1076	AssertFailed();
1077	break;
1078	}
1079	break;
1080
1081	case 'J': /* Relative jump offset (ParseImmBRel + ParseImmVRel). */
1082	{
1083	int32_t offDisplacement;
1084	Assert(iParam == 1);
1085	bool fPrefix = (fFlags & DIS_FMT_FLAGS_STRICT)
1086	&& pOp->uOpcode != OP_CALL
1087	&& pOp->uOpcode != OP_LOOP
1088	&& pOp->uOpcode != OP_LOOPE
1089	&& pOp->uOpcode != OP_LOOPNE
1090	&& pOp->uOpcode != OP_JECXZ;
1091	if (pOp->uOpcode == OP_CALL)
1092	fFlags &= ~DIS_FMT_FLAGS_RELATIVE_BRANCH;
1093
1094	if (pParam->fUse & DISUSE_IMMEDIATE8_REL)
1095	{
1096	if (fPrefix)
1097	PUT_SZ("short ");
1098	offDisplacement = (int8_t)pParam->uValue;
1099	Assert(*pszFmt == 'b'); pszFmt++;
1100
1101	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1102	PUT_NUM_S8(offDisplacement);
1103	}
1104	else if (pParam->fUse & DISUSE_IMMEDIATE16_REL)
1105	{
1106	if (fPrefix)
1107	PUT_SZ("near ");
1108	offDisplacement = (int16_t)pParam->uValue;
1109	Assert(*pszFmt == 'v'); pszFmt++;
1110
1111	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1112	PUT_NUM_S16(offDisplacement);
1113	}
1114	else
1115	{
1116	if (fPrefix)
1117	PUT_SZ("near ");
1118	offDisplacement = (int32_t)pParam->uValue;
1119	Assert(pParam->fUse & (DISUSE_IMMEDIATE32_REL \| DISUSE_IMMEDIATE64_REL));
1120	Assert(*pszFmt == 'v'); pszFmt++;
1121
1122	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1123	PUT_NUM_S32(offDisplacement);
1124	}
1125	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1126	PUT_SZ(" (");
1127
1128	RTUINTPTR uTrgAddr = pDis->uInstrAddr + pDis->cbInstr + offDisplacement;
1129	if (pDis->uCpuMode == DISCPUMODE_16BIT)
1130	PUT_NUM_16(uTrgAddr);
1131	else if (pDis->uCpuMode == DISCPUMODE_32BIT)
1132	PUT_NUM_32(uTrgAddr);
1133	else
1134	PUT_NUM_64(uTrgAddr);
1135
1136	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1137	{
1138	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " = ", ' ');
1139	PUT_C(')');
1140	}
1141	else
1142	PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " (", ')');
1143	break;
1144	}
1145
1146	case 'A': /* Direct (jump/call) address (ParseImmAddr). */
1147	{
1148	Assert(*pszFmt == 'p'); pszFmt++;
1149	PUT_FAR();
1150	PUT_SIZE_OVERRIDE();
1151	PUT_SEGMENT_OVERRIDE();
1152	off = 0;
1153	int rc = VERR_SYMBOL_NOT_FOUND;
1154	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
1155	{
1156	case DISUSE_IMMEDIATE_ADDR_16_16:
1157	PUT_NUM_16(pParam->uValue >> 16);
1158	PUT_C(':');
1159	PUT_NUM_16(pParam->uValue);
1160	if (pfnGetSymbol)
1161	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1162	break;
1163	case DISUSE_IMMEDIATE_ADDR_16_32:
1164	PUT_NUM_16(pParam->uValue >> 32);
1165	PUT_C(':');
1166	PUT_NUM_32(pParam->uValue);
1167	if (pfnGetSymbol)
1168	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1169	break;
1170	case DISUSE_DISPLACEMENT16:
1171	PUT_NUM_16(pParam->uValue);
1172	if (pfnGetSymbol)
1173	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1174	break;
1175	case DISUSE_DISPLACEMENT32:
1176	PUT_NUM_32(pParam->uValue);
1177	if (pfnGetSymbol)
1178	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1179	break;
1180	case DISUSE_DISPLACEMENT64:
1181	PUT_NUM_64(pParam->uValue);
1182	if (pfnGetSymbol)
1183	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint64_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1184	break;
1185	default:
1186	AssertFailed();
1187	break;
1188	}
1189
1190	PUT_SYMBOL_TWO(rc, " [", ']');
1191	break;
1192	}
1193
1194	case 'O': /* No ModRM byte (ParseImmAddr). */
1195	{
1196	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1197	PUT_FAR();
1198	PUT_SIZE_OVERRIDE();
1199	PUT_C('[');
1200	PUT_SEGMENT_OVERRIDE();
1201	off = 0;
1202	int rc = VERR_SYMBOL_NOT_FOUND;
1203	switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 \| DISUSE_IMMEDIATE_ADDR_16_32 \| DISUSE_DISPLACEMENT64 \| DISUSE_DISPLACEMENT32 \| DISUSE_DISPLACEMENT16))
1204	{
1205	case DISUSE_IMMEDIATE_ADDR_16_16:
1206	PUT_NUM_16(pParam->uValue >> 16);
1207	PUT_C(':');
1208	PUT_NUM_16(pParam->uValue);
1209	if (pfnGetSymbol)
1210	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1211	break;
1212	case DISUSE_IMMEDIATE_ADDR_16_32:
1213	PUT_NUM_16(pParam->uValue >> 32);
1214	PUT_C(':');
1215	PUT_NUM_32(pParam->uValue);
1216	if (pfnGetSymbol)
1217	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1218	break;
1219	case DISUSE_DISPLACEMENT16:
1220	PUT_NUM_16(pParam->x86.uDisp.i16);
1221	if (pfnGetSymbol)
1222	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->x86.uDisp.u16, szSymbol, sizeof(szSymbol), &off, pvUser);
1223	break;
1224	case DISUSE_DISPLACEMENT32:
1225	PUT_NUM_32(pParam->x86.uDisp.i32);
1226	if (pfnGetSymbol)
1227	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->x86.uDisp.u32, szSymbol, sizeof(szSymbol), &off, pvUser);
1228	break;
1229	case DISUSE_DISPLACEMENT64:
1230	PUT_NUM_64(pParam->x86.uDisp.i64);
1231	if (pfnGetSymbol)
1232	rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->x86.uDisp.u64, szSymbol, sizeof(szSymbol), &off, pvUser);
1233	break;
1234	default:
1235	AssertFailed();
1236	break;
1237	}
1238	PUT_C(']');
1239
1240	PUT_SYMBOL_TWO(rc, " (", ')');
1241	break;
1242	}
1243
1244	case 'X': /* DS:SI (ParseXb, ParseXv). */
1245	case 'Y': /* ES:DI (ParseYb, ParseYv). */
1246	{
1247	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1248	PUT_FAR();
1249	PUT_SIZE_OVERRIDE();
1250	PUT_C('[');
1251	if (pParam->fUse & DISUSE_POINTER_DS_BASED)
1252	PUT_SZ("ds:");
1253	else
1254	PUT_SZ("es:");
1255
1256	size_t cchReg;
1257	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1258	PUT_STR(pszReg, cchReg);
1259	PUT_C(']');
1260	break;
1261	}
1262
1263	case 'e': /* Register based on operand size (e.g. %eAX, %eAH) (ParseFixedReg). */
1264	{
1265	Assert(RT_C_IS_ALPHA(pszFmt[0]) && RT_C_IS_ALPHA(pszFmt[1]) && !RT_C_IS_ALPHA(pszFmt[2]));
1266	pszFmt += 2;
1267	size_t cchReg;
1268	const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1269	PUT_STR(pszReg, cchReg);
1270	break;
1271	}
1272
1273	default:
1274	AssertMsgFailed(("%c%s!\n", ch, pszFmt));
1275	break;
1276	}
1277	AssertMsg(pszFmt == ',' \|\| pszFmt == '\0', ("%c%s\n", ch, pszFmt));
1278	}
1279	else
1280	{
1281	PUT_C(ch);
1282	if (ch == ',')
1283	{
1284	Assert(*pszFmt != ' ');
1285	PUT_C(' ');
1286	switch (++iParam)
1287	{
1288	case 2: pParam = &pDis->Param2; break;
1289	case 3: pParam = &pDis->Param3; break;
1290	case 4: pParam = &pDis->Param4; break;
1291	default: pParam = NULL; break;
1292	}
1293	}
1294	}
1295	} /* while more to format */
1296	}
1297
1298	/*
1299	* Any additional output to the right of the instruction?
1300	*/
1301	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1302	{
1303	/* some up front padding. */
1304	size_t cchPadding = cchOutput - offInstruction;
1305	cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
1306	PUT_STR(g_szSpaces, cchPadding);
1307
1308	/* comment? */
1309	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1310	PUT_SZ(";");
1311
1312	/*
1313	* The address?
1314	*/
1315	if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
1316	{
1317	PUT_C(' ');
1318	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
1319	if (pDis->uInstrAddr >= _4G)
1320	PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
1321	#endif
1322	PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
1323	}
1324
1325	/*
1326	* Opcode bytes?
1327	*/
1328	if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
1329	{
1330	PUT_C(' ');
1331	size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
1332	cchOutput += cchTmp;
1333	if (cchTmp >= cchDst)
1334	cchTmp = cchDst - (cchDst != 0);
1335	cchDst -= cchTmp;
1336	pszDst += cchTmp;
1337	}
1338	}
1339
1340	/*
1341	* Terminate it - on overflow we'll have reserved one byte for this.
1342	*/
1343	if (cchDst > 0)
1344	*pszDst = '\0';
1345	else
1346	Assert(!cchBuf);
1347
1348	/* clean up macros */
1349	#undef PUT_PSZ
1350	#undef PUT_SZ
1351	#undef PUT_STR
1352	#undef PUT_C
1353	return cchOutput;
1354	}
1355
1356
1357	/**
1358	* Formats the current instruction in Yasm (/ Nasm) style.
1359	*
1360	* This is a simplified version of DISFormatYasmEx() provided for your convenience.
1361	*
1362	*
1363	* @returns The number of output characters. If this is >= cchBuf, then the content
1364	* of pszBuf will be truncated.
1365	* @param pDis Pointer to the disassembler state.
1366	* @param pszBuf The output buffer.
1367	* @param cchBuf The size of the output buffer.
1368	*/
1369	DISDECL(size_t) DISFormatYasm(PCDISSTATE pDis, char *pszBuf, size_t cchBuf)
1370	{
1371	return DISFormatYasmEx(pDis, pszBuf, cchBuf, 0 /* fFlags /, NULL / pfnGetSymbol /, NULL / pvUser */);
1372	}
1373
1374
1375	/**
1376	* Checks if the encoding of the given disassembled instruction is something we
1377	* can never get YASM to produce.
1378	*
1379	* @returns true if it's odd, false if it isn't.
1380	* @param pDis The disassembler output. The byte fetcher callback will
1381	* be used if present as we might need to fetch opcode
1382	* bytes.
1383	*/
1384	DISDECL(bool) DISFormatYasmIsOddEncoding(PDISSTATE pDis)
1385	{
1386	/*
1387	* Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons.
1388	*/
1389	if ( pDis->x86.uAddrMode != DISCPUMODE_16BIT /// @todo correct?
1390	&& pDis->x86.ModRM.Bits.Rm == 4
1391	&& pDis->x86.ModRM.Bits.Mod != 3)
1392	{
1393	/* No scaled index SIB (index=4), except for ESP. */
1394	if ( pDis->x86.SIB.Bits.Index == 4
1395	&& pDis->x86.SIB.Bits.Base != 4)
1396	return true;
1397
1398	/* EBP + displacement */
1399	if ( pDis->x86.ModRM.Bits.Mod != 0
1400	&& pDis->x86.SIB.Bits.Base == 5
1401	&& pDis->x86.SIB.Bits.Scale == 0)
1402	return true;
1403	}
1404
1405	/*
1406	* Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
1407	*/
1408	if ( pDis->pCurInstr->uOpcode == OP_SHL
1409	&& pDis->x86.ModRM.Bits.Reg == 6)
1410	return true;
1411
1412	/*
1413	* Check for multiple prefixes of the same kind.
1414	*/
1415	uint8_t off1stSeg = UINT8_MAX;
1416	uint8_t offOpSize = UINT8_MAX;
1417	uint8_t offAddrSize = UINT8_MAX;
1418	uint32_t fPrefixes = 0;
1419	for (uint32_t offOpcode = 0; offOpcode < RT_ELEMENTS(pDis->Instr.ab); offOpcode++)
1420	{
1421	uint32_t f;
1422	switch (pDis->Instr.ab[offOpcode])
1423	{
1424	case 0xf0:
1425	f = DISPREFIX_LOCK;
1426	break;
1427
1428	case 0xf2:
1429	case 0xf3:
1430	f = DISPREFIX_REP; /* yes, both */
1431	break;
1432
1433	case 0x2e:
1434	case 0x3e:
1435	case 0x26:
1436	case 0x36:
1437	case 0x64:
1438	case 0x65:
1439	if (off1stSeg == UINT8_MAX)
1440	off1stSeg = offOpcode;
1441	f = DISPREFIX_SEG;
1442	break;
1443
1444	case 0x66:
1445	if (offOpSize == UINT8_MAX)
1446	offOpSize = offOpcode;
1447	f = DISPREFIX_OPSIZE;
1448	break;
1449
1450	case 0x67:
1451	if (offAddrSize == UINT8_MAX)
1452	offAddrSize = offOpcode;
1453	f = DISPREFIX_ADDRSIZE;
1454	break;
1455
1456	case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
1457	case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
1458	f = pDis->uCpuMode == DISCPUMODE_64BIT ? DISPREFIX_REX : 0;
1459	break;
1460
1461	default:
1462	f = 0;
1463	break;
1464	}
1465	if (!f)
1466	break; /* done */
1467	if (fPrefixes & f)
1468	return true;
1469	fPrefixes \|= f;
1470	}
1471
1472	/* segment overrides are fun */
1473	if (fPrefixes & DISPREFIX_SEG)
1474	{
1475	/* no effective address which it may apply to. */
1476	Assert((pDis->x86.fPrefix & DISPREFIX_SEG) \|\| pDis->uCpuMode == DISCPUMODE_64BIT);
1477	if ( !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
1478	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
1479	&& !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
1480	return true;
1481
1482	/* Yasm puts the segment prefixes before the operand prefix with no
1483	way of overriding it. */
1484	if (offOpSize < off1stSeg)
1485	return true;
1486	}
1487
1488	/* fixed register + addr override doesn't go down all that well. */
1489	if (fPrefixes & DISPREFIX_ADDRSIZE)
1490	{
1491	Assert(pDis->x86.fPrefix & DISPREFIX_ADDRSIZE);
1492	if ( pDis->pCurInstr->fParam3 == OP_PARM_NONE
1493	&& pDis->pCurInstr->fParam2 == OP_PARM_NONE
1494	&& ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1495	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END))
1496	return true;
1497	}
1498
1499	/* Almost all prefixes are bad for jumps. */
1500	if (fPrefixes)
1501	{
1502	switch (pDis->pCurInstr->uOpcode)
1503	{
1504	/* nop w/ prefix(es). */
1505	case OP_NOP:
1506	return true;
1507
1508	case OP_JMP:
1509	if ( pDis->pCurInstr->fParam1 != OP_PARM_Jb
1510	&& pDis->pCurInstr->fParam1 != OP_PARM_Jv)
1511	break;
1512	RT_FALL_THRU();
1513	case OP_JO:
1514	case OP_JNO:
1515	case OP_JC:
1516	case OP_JNC:
1517	case OP_JE:
1518	case OP_JNE:
1519	case OP_JBE:
1520	case OP_JNBE:
1521	case OP_JS:
1522	case OP_JNS:
1523	case OP_JP:
1524	case OP_JNP:
1525	case OP_JL:
1526	case OP_JNL:
1527	case OP_JLE:
1528	case OP_JNLE:
1529	/** @todo branch hinting 0x2e/0x3e... */
1530	return true;
1531	}
1532
1533	}
1534
1535	/* All but the segment prefix is bad news for push/pop. */
1536	if (fPrefixes & ~DISPREFIX_SEG)
1537	{
1538	switch (pDis->pCurInstr->uOpcode)
1539	{
1540	case OP_POP:
1541	case OP_PUSH:
1542	if ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_SEG_START
1543	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_SEG_END)
1544	return true;
1545	if ( (fPrefixes & ~DISPREFIX_OPSIZE)
1546	&& pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1547	&& pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END)
1548	return true;
1549	break;
1550
1551	case OP_POPA:
1552	case OP_POPF:
1553	case OP_PUSHA:
1554	case OP_PUSHF:
1555	if (fPrefixes & ~DISPREFIX_OPSIZE)
1556	return true;
1557	break;
1558	}
1559	}
1560
1561	/* Implicit 8-bit register instructions doesn't mix with operand size. */
1562	if ( (fPrefixes & DISPREFIX_OPSIZE)
1563	&& ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1564	&& pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1565	\|\| ( pDis->pCurInstr->fParam2 == OP_PARM_Gb /* r8 */
1566	&& pDis->pCurInstr->fParam1 == OP_PARM_Eb /* r8/mem8 */))
1567	)
1568	{
1569	switch (pDis->pCurInstr->uOpcode)
1570	{
1571	case OP_ADD:
1572	case OP_OR:
1573	case OP_ADC:
1574	case OP_SBB:
1575	case OP_AND:
1576	case OP_SUB:
1577	case OP_XOR:
1578	case OP_CMP:
1579	return true;
1580	default:
1581	break;
1582	}
1583	}
1584
1585	/* Instructions taking no address or operand which thus may be annoyingly
1586	difficult to format for yasm. */
1587	if (fPrefixes)
1588	{
1589	switch (pDis->pCurInstr->uOpcode)
1590	{
1591	case OP_STI:
1592	case OP_STC:
1593	case OP_CLI:
1594	case OP_CLD:
1595	case OP_CLC:
1596	case OP_INT:
1597	case OP_INT3:
1598	case OP_INTO:
1599	case OP_HLT:
1600	/** @todo Many more to can be added here. */
1601	return true;
1602	default:
1603	break;
1604	}
1605	}
1606
1607	/* FPU and other instructions that ignores operand size override. */
1608	if (fPrefixes & DISPREFIX_OPSIZE)
1609	{
1610	switch (pDis->pCurInstr->uOpcode)
1611	{
1612	/* FPU: */
1613	case OP_FIADD:
1614	case OP_FIMUL:
1615	case OP_FISUB:
1616	case OP_FISUBR:
1617	case OP_FIDIV:
1618	case OP_FIDIVR:
1619	/** @todo there are many more. */
1620	return true;
1621
1622	case OP_MOV:
1623	/** @todo could be that we're not disassembling these correctly. */
1624	if (pDis->pCurInstr->fParam1 == OP_PARM_Sw)
1625	return true;
1626	/** @todo what about the other way? */
1627	break;
1628
1629	default:
1630	break;
1631	}
1632	}
1633
1634
1635	/*
1636	* Check for the version of xyz reg,reg instruction that the assembler doesn't use.
1637	*
1638	* For example:
1639	* expected: 1aee sbb ch, dh ; SBB r8, r/m8
1640	* yasm: 18F5 sbb ch, dh ; SBB r/m8, r8
1641	*/
1642	if (pDis->x86.ModRM.Bits.Mod == 3 /* reg,reg */)
1643	{
1644	switch (pDis->pCurInstr->uOpcode)
1645	{
1646	case OP_ADD:
1647	case OP_OR:
1648	case OP_ADC:
1649	case OP_SBB:
1650	case OP_AND:
1651	case OP_SUB:
1652	case OP_XOR:
1653	case OP_CMP:
1654	if ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1655	&& pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1656	\|\| ( pDis->pCurInstr->fParam1 == OP_PARM_Gv /* rX */
1657	&& pDis->pCurInstr->fParam2 == OP_PARM_Ev /* rX/memX */))
1658	return true;
1659
1660	/* 82 (see table A-6). */
1661	if (pDis->x86.bOpCode == 0x82)
1662	return true;
1663	break;
1664
1665	/* ff /0, fe /0, ff /1, fe /0 */
1666	case OP_DEC:
1667	case OP_INC:
1668	return true;
1669
1670	case OP_POP:
1671	case OP_PUSH:
1672	Assert(pDis->x86.bOpCode == 0x8f);
1673	return true;
1674
1675	case OP_MOV:
1676	if ( pDis->x86.bOpCode == 0x8a
1677	\|\| pDis->x86.bOpCode == 0x8b)
1678	return true;
1679	break;
1680
1681	default:
1682	break;
1683	}
1684	}
1685
1686	/* shl eax,1 will be assembled to the form without the immediate byte. */
1687	if ( pDis->pCurInstr->fParam2 == OP_PARM_Ib
1688	&& (uint8_t)pDis->Param2.uValue == 1)
1689	{
1690	switch (pDis->pCurInstr->uOpcode)
1691	{
1692	case OP_SHL:
1693	case OP_SHR:
1694	case OP_SAR:
1695	case OP_RCL:
1696	case OP_RCR:
1697	case OP_ROL:
1698	case OP_ROR:
1699	return true;
1700	}
1701	}
1702
1703	/* And some more - see table A-6. */
1704	if (pDis->x86.bOpCode == 0x82)
1705	{
1706	switch (pDis->pCurInstr->uOpcode)
1707	{
1708	case OP_ADD:
1709	case OP_OR:
1710	case OP_ADC:
1711	case OP_SBB:
1712	case OP_AND:
1713	case OP_SUB:
1714	case OP_XOR:
1715	case OP_CMP:
1716	return true;
1717	break;
1718	}
1719	}
1720
1721
1722	/* check for REX.X = 1 without SIB. */
1723
1724	/* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
1725	says (intel doesn't appear to care). */
1726	switch (pDis->pCurInstr->uOpcode)
1727	{
1728	case OP_SETO:
1729	case OP_SETNO:
1730	case OP_SETC:
1731	case OP_SETNC:
1732	case OP_SETE:
1733	case OP_SETNE:
1734	case OP_SETBE:
1735	case OP_SETNBE:
1736	case OP_SETS:
1737	case OP_SETNS:
1738	case OP_SETP:
1739	case OP_SETNP:
1740	case OP_SETL:
1741	case OP_SETNL:
1742	case OP_SETLE:
1743	case OP_SETNLE:
1744	AssertMsg(pDis->x86.bOpCode >= 0x90 && pDis->x86.bOpCode <= 0x9f, ("%#x\n", pDis->x86.bOpCode));
1745	if (pDis->x86.ModRM.Bits.Reg != 2)
1746	return true;
1747	break;
1748	}
1749
1750	/*
1751	* The MOVZX reg32,mem16 instruction without an operand size prefix
1752	* doesn't quite make sense...
1753	*/
1754	if ( pDis->pCurInstr->uOpcode == OP_MOVZX
1755	&& pDis->x86.bOpCode == 0xB7
1756	&& (pDis->uCpuMode == DISCPUMODE_16BIT) != !!(fPrefixes & DISPREFIX_OPSIZE))
1757	return true;
1758
1759	/*
1760	* YASM doesn't do ICEBP/INT1/INT01, unlike NASM.
1761	*/
1762	if (pDis->x86.bOpCode == 0xF1)
1763	return true;
1764
1765	return false;
1766	}
1767

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source: vbox/trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp@ 101546

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