Virtio.cpp@ 73410

Last change on this file since 73410 was 73410, checked in by vboxsync, 6 years ago
Network/Virtio: TX queue notification flag race fix. TX event stat counters. Existing counters updated to use CTX_SUFF.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 35.6 KB

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1	/* $Id: Virtio.cpp 73410 2018-07-31 12:36:41Z vboxsync $ */
2	/** @file
3	* Virtio - Virtio Common Functions (VRing, VQueue, Virtio PCI)
4	*/
5
6	/*
7	* Copyright (C) 2009-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_VIRTIO
23
24	#include <iprt/param.h>
25	#include <iprt/uuid.h>
26	#include <VBox/vmm/pdmdev.h>
27	#include "Virtio.h"
28
29	#define INSTANCE(pState) pState->szInstance
30	#define IFACE_TO_STATE(pIface, ifaceName) ((VPCISTATE )((char)(pIface) - RT_UOFFSETOF(VPCISTATE, ifaceName)))
31
32	#ifdef LOG_ENABLED
33	# define QUEUENAME(s, q) (q->pcszName)
34	#endif
35
36
37
38	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
39
40	//RT_C_DECLS_BEGIN
41	//RT_C_DECLS_END
42
43
44	static void vqueueReset(PVQUEUE pQueue)
45	{
46	pQueue->VRing.addrDescriptors = 0;
47	pQueue->VRing.addrAvail = 0;
48	pQueue->VRing.addrUsed = 0;
49	pQueue->uNextAvailIndex = 0;
50	pQueue->uNextUsedIndex = 0;
51	pQueue->uPageNumber = 0;
52	}
53
54	static void vqueueInit(PVQUEUE pQueue, uint32_t uPageNumber)
55	{
56	pQueue->VRing.addrDescriptors = (uint64_t)uPageNumber << PAGE_SHIFT;
57	pQueue->VRing.addrAvail = pQueue->VRing.addrDescriptors
58	+ sizeof(VRINGDESC) * pQueue->VRing.uSize;
59	pQueue->VRing.addrUsed = RT_ALIGN(
60	pQueue->VRing.addrAvail + RT_UOFFSETOF_DYN(VRINGAVAIL, auRing[pQueue->VRing.uSize]),
61	PAGE_SIZE); /* The used ring must start from the next page. */
62	pQueue->uNextAvailIndex = 0;
63	pQueue->uNextUsedIndex = 0;
64	}
65
66	// void vqueueElemFree(PVQUEUEELEM pElem)
67	// {
68	// }
69
70	void vringReadDesc(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, PVRINGDESC pDesc)
71	{
72	//Log(("%s vringReadDesc: ring=%p idx=%u\n", INSTANCE(pState), pVRing, uIndex));
73	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
74	pVRing->addrDescriptors + sizeof(VRINGDESC) * (uIndex % pVRing->uSize),
75	pDesc, sizeof(VRINGDESC));
76	}
77
78	uint16_t vringReadAvail(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex)
79	{
80	uint16_t tmp;
81
82	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
83	pVRing->addrAvail + RT_UOFFSETOF_DYN(VRINGAVAIL, auRing[uIndex % pVRing->uSize]),
84	&tmp, sizeof(tmp));
85	return tmp;
86	}
87
88	uint16_t vringReadAvailFlags(PVPCISTATE pState, PVRING pVRing)
89	{
90	uint16_t tmp;
91
92	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
93	pVRing->addrAvail + RT_UOFFSETOF(VRINGAVAIL, uFlags),
94	&tmp, sizeof(tmp));
95	return tmp;
96	}
97
98	void vringSetNotification(PVPCISTATE pState, PVRING pVRing, bool fEnabled)
99	{
100	uint16_t tmp;
101
102	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
103	pVRing->addrUsed + RT_UOFFSETOF(VRINGUSED, uFlags),
104	&tmp, sizeof(tmp));
105
106	if (fEnabled)
107	tmp &= ~ VRINGUSED_F_NO_NOTIFY;
108	else
109	tmp \|= VRINGUSED_F_NO_NOTIFY;
110
111	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
112	pVRing->addrUsed + RT_UOFFSETOF(VRINGUSED, uFlags),
113	&tmp, sizeof(tmp));
114	}
115
116	bool vqueueSkip(PVPCISTATE pState, PVQUEUE pQueue)
117	{
118	if (vqueueIsEmpty(pState, pQueue))
119	return false;
120
121	Log2(("%s vqueueSkip: %s avail_idx=%u\n", INSTANCE(pState),
122	QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
123	pQueue->uNextAvailIndex++;
124	return true;
125	}
126
127	bool vqueueGet(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem, bool fRemove)
128	{
129	if (vqueueIsEmpty(pState, pQueue))
130	return false;
131
132	pElem->nIn = pElem->nOut = 0;
133
134	Log2(("%s vqueueGet: %s avail_idx=%u\n", INSTANCE(pState),
135	QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
136
137	VRINGDESC desc;
138	uint16_t idx = vringReadAvail(pState, &pQueue->VRing, pQueue->uNextAvailIndex);
139	if (fRemove)
140	pQueue->uNextAvailIndex++;
141	pElem->uIndex = idx;
142	do
143	{
144	VQUEUESEG *pSeg;
145
146	/*
147	* Malicious guests may try to trick us into writing beyond aSegsIn or
148	* aSegsOut boundaries by linking several descriptors into a loop. We
149	* cannot possibly get a sequence of linked descriptors exceeding the
150	* total number of descriptors in the ring (see @bugref{8620}).
151	*/
152	if (pElem->nIn + pElem->nOut >= VRING_MAX_SIZE)
153	{
154	static volatile uint32_t s_cMessages = 0;
155	static volatile uint32_t s_cThreshold = 1;
156	if (ASMAtomicIncU32(&s_cMessages) == ASMAtomicReadU32(&s_cThreshold))
157	{
158	LogRel(("%s: too many linked descriptors; check if the guest arranges descriptors in a loop.\n",
159	INSTANCE(pState)));
160	if (ASMAtomicReadU32(&s_cMessages) != 1)
161	LogRel(("%s: (the above error has occured %u times so far)\n",
162	INSTANCE(pState), ASMAtomicReadU32(&s_cMessages)));
163	ASMAtomicWriteU32(&s_cThreshold, ASMAtomicReadU32(&s_cThreshold) * 10);
164	}
165	break;
166	}
167	RT_UNTRUSTED_VALIDATED_FENCE();
168
169	vringReadDesc(pState, &pQueue->VRing, idx, &desc);
170	if (desc.u16Flags & VRINGDESC_F_WRITE)
171	{
172	Log2(("%s vqueueGet: %s IN seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
173	QUEUENAME(pState, pQueue), pElem->nIn, idx, desc.u64Addr, desc.uLen));
174	pSeg = &pElem->aSegsIn[pElem->nIn++];
175	}
176	else
177	{
178	Log2(("%s vqueueGet: %s OUT seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
179	QUEUENAME(pState, pQueue), pElem->nOut, idx, desc.u64Addr, desc.uLen));
180	pSeg = &pElem->aSegsOut[pElem->nOut++];
181	}
182
183	pSeg->addr = desc.u64Addr;
184	pSeg->cb = desc.uLen;
185	pSeg->pv = NULL;
186
187	idx = desc.u16Next;
188	} while (desc.u16Flags & VRINGDESC_F_NEXT);
189
190	Log2(("%s vqueueGet: %s head_desc_idx=%u nIn=%u nOut=%u\n", INSTANCE(pState),
191	QUEUENAME(pState, pQueue), pElem->uIndex, pElem->nIn, pElem->nOut));
192	return true;
193	}
194
195	uint16_t vringReadUsedIndex(PVPCISTATE pState, PVRING pVRing)
196	{
197	uint16_t tmp;
198	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
199	pVRing->addrUsed + RT_UOFFSETOF(VRINGUSED, uIndex),
200	&tmp, sizeof(tmp));
201	return tmp;
202	}
203
204	void vringWriteUsedIndex(PVPCISTATE pState, PVRING pVRing, uint16_t u16Value)
205	{
206	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
207	pVRing->addrUsed + RT_UOFFSETOF(VRINGUSED, uIndex),
208	&u16Value, sizeof(u16Value));
209	}
210
211	void vringWriteUsedElem(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, uint32_t uId, uint32_t uLen)
212	{
213	VRINGUSEDELEM elem;
214
215	elem.uId = uId;
216	elem.uLen = uLen;
217	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
218	pVRing->addrUsed + RT_UOFFSETOF_DYN(VRINGUSED, aRing[uIndex % pVRing->uSize]),
219	&elem, sizeof(elem));
220	}
221
222
223	void vqueuePut(PVPCISTATE pState, PVQUEUE pQueue,
224	PVQUEUEELEM pElem, uint32_t uTotalLen, uint32_t uReserved)
225	{
226	Log2(("%s vqueuePut: %s"
227	" desc_idx=%u acb=%u (%u)\n",
228	INSTANCE(pState), QUEUENAME(pState, pQueue),
229	pElem->uIndex, uTotalLen, uReserved));
230
231	Assert(uReserved < uTotalLen);
232
233	uint32_t cbLen = uTotalLen - uReserved;
234	uint32_t cbSkip = uReserved;
235
236	for (unsigned i = 0; i < pElem->nIn && cbLen > 0; ++i)
237	{
238	if (cbSkip >= pElem->aSegsIn[i].cb) /* segment completely skipped? */
239	{
240	cbSkip -= pElem->aSegsIn[i].cb;
241	continue;
242	}
243
244	uint32_t cbSegLen = pElem->aSegsIn[i].cb - cbSkip;
245	if (cbSegLen > cbLen) /* last segment only partially used? */
246	cbSegLen = cbLen;
247
248	/*
249	* XXX: We should assert pv != NULL, but we need to check and
250	* fix all callers first.
251	*/
252	if (pElem->aSegsIn[i].pv != NULL)
253	{
254	Log2(("%s vqueuePut: %s"
255	" used_idx=%u seg=%u addr=%p pv=%p cb=%u acb=%u\n",
256	INSTANCE(pState), QUEUENAME(pState, pQueue),
257	pQueue->uNextUsedIndex, i,
258	(void *)pElem->aSegsIn[i].addr, pElem->aSegsIn[i].pv,
259	pElem->aSegsIn[i].cb, cbSegLen));
260
261	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
262	pElem->aSegsIn[i].addr + cbSkip,
263	pElem->aSegsIn[i].pv,
264	cbSegLen);
265	}
266
267	cbSkip = 0;
268	cbLen -= cbSegLen;
269	}
270
271	Log2(("%s vqueuePut: %s"
272	" used_idx=%u guest_used_idx=%u id=%u len=%u\n",
273	INSTANCE(pState), QUEUENAME(pState, pQueue),
274	pQueue->uNextUsedIndex, vringReadUsedIndex(pState, &pQueue->VRing),
275	pElem->uIndex, uTotalLen));
276
277	vringWriteUsedElem(pState, &pQueue->VRing,
278	pQueue->uNextUsedIndex++,
279	pElem->uIndex, uTotalLen);
280	}
281
282
283	void vqueueNotify(PVPCISTATE pState, PVQUEUE pQueue)
284	{
285	LogFlow(("%s vqueueNotify: %s availFlags=%x guestFeatures=%x vqueue is %sempty\n",
286	INSTANCE(pState), QUEUENAME(pState, pQueue),
287	vringReadAvailFlags(pState, &pQueue->VRing),
288	pState->uGuestFeatures, vqueueIsEmpty(pState, pQueue)?"":"not "));
289	if (!(vringReadAvailFlags(pState, &pQueue->VRing) & VRINGAVAIL_F_NO_INTERRUPT)
290	\|\| ((pState->uGuestFeatures & VPCI_F_NOTIFY_ON_EMPTY) && vqueueIsEmpty(pState, pQueue)))
291	{
292	int rc = vpciRaiseInterrupt(pState, VERR_INTERNAL_ERROR, VPCI_ISR_QUEUE);
293	if (RT_FAILURE(rc))
294	Log(("%s vqueueNotify: Failed to raise an interrupt (%Rrc).\n", INSTANCE(pState), rc));
295	}
296	else
297	{
298	STAM_COUNTER_INC(&pState->StatIntsSkipped);
299	}
300
301	}
302
303	void vqueueSync(PVPCISTATE pState, PVQUEUE pQueue)
304	{
305	Log2(("%s vqueueSync: %s old_used_idx=%u new_used_idx=%u\n", INSTANCE(pState),
306	QUEUENAME(pState, pQueue), vringReadUsedIndex(pState, &pQueue->VRing), pQueue->uNextUsedIndex));
307	vringWriteUsedIndex(pState, &pQueue->VRing, pQueue->uNextUsedIndex);
308	vqueueNotify(pState, pQueue);
309	}
310
311	void vpciReset(PVPCISTATE pState)
312	{
313	pState->uGuestFeatures = 0;
314	pState->uQueueSelector = 0;
315	pState->uStatus = 0;
316	pState->uISR = 0;
317
318	for (unsigned i = 0; i < pState->nQueues; i++)
319	vqueueReset(&pState->Queues[i]);
320	}
321
322
323	/**
324	* Raise interrupt.
325	*
326	* @param pState The device state structure.
327	* @param rcBusy Status code to return when the critical section is busy.
328	* @param u8IntCause Interrupt cause bit mask to set in PCI ISR port.
329	*/
330	int vpciRaiseInterrupt(VPCISTATE *pState, int rcBusy, uint8_t u8IntCause)
331	{
332	RT_NOREF_PV(rcBusy);
333	// int rc = vpciCsEnter(pState, rcBusy);
334	// if (RT_UNLIKELY(rc != VINF_SUCCESS))
335	// return rc;
336
337	STAM_COUNTER_INC(&pState->StatIntsRaised);
338	LogFlow(("%s vpciRaiseInterrupt: u8IntCause=%x\n",
339	INSTANCE(pState), u8IntCause));
340
341	pState->uISR \|= u8IntCause;
342	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 1);
343	// vpciCsLeave(pState);
344	return VINF_SUCCESS;
345	}
346
347	/**
348	* Lower interrupt.
349	*
350	* @param pState The device state structure.
351	*/
352	static void vpciLowerInterrupt(VPCISTATE *pState)
353	{
354	LogFlow(("%s vpciLowerInterrupt\n", INSTANCE(pState)));
355	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
356	}
357
358	DECLINLINE(uint32_t) vpciGetHostFeatures(PVPCISTATE pState,
359	PFNGETHOSTFEATURES pfnGetHostFeatures)
360	{
361	return pfnGetHostFeatures(pState)
362	\| VPCI_F_NOTIFY_ON_EMPTY;
363	}
364
365	/**
366	* Port I/O Handler for IN operations.
367	*
368	* @returns VBox status code.
369	*
370	* @param pDevIns The device instance.
371	* @param pvUser Pointer to the device state structure.
372	* @param Port Port number used for the IN operation.
373	* @param pu32 Where to store the result.
374	* @param cb Number of bytes read.
375	* @param pCallbacks Pointer to the callbacks.
376	* @thread EMT
377	*/
378	int vpciIOPortIn(PPDMDEVINS pDevIns,
379	void *pvUser,
380	RTIOPORT Port,
381	uint32_t *pu32,
382	unsigned cb,
383	PCVPCIIOCALLBACKS pCallbacks)
384	{
385	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
386	int rc = VINF_SUCCESS;
387	STAM_PROFILE_ADV_START(&pState->CTX_SUFF(StatIORead), a);
388	RT_NOREF_PV(pvUser);
389
390	/*
391	* We probably do not need to enter critical section when reading registers
392	* as the most of them are either constant or being changed during
393	* initialization only, the exception being ISR which can be raced by all
394	* threads but I see no big harm in it. It also happens to be the most read
395	* register as it gets read in interrupt handler. By dropping cs protection
396	* here we gain the ability to deliver RX packets to the guest while TX is
397	* holding cs transmitting queued packets.
398	*
399	rc = vpciCsEnter(pState, VINF_IOM_R3_IOPORT_READ);
400	if (RT_UNLIKELY(rc != VINF_SUCCESS))
401	{
402	STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF(StatIORead), a);
403	return rc;
404	}*/
405
406	Port -= pState->IOPortBase;
407	switch (Port)
408	{
409	case VPCI_HOST_FEATURES:
410	/* Tell the guest what features we support. */
411	*pu32 = vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures)
412	\| VPCI_F_BAD_FEATURE;
413	break;
414
415	case VPCI_GUEST_FEATURES:
416	*pu32 = pState->uGuestFeatures;
417	break;
418
419	case VPCI_QUEUE_PFN:
420	*pu32 = pState->Queues[pState->uQueueSelector].uPageNumber;
421	break;
422
423	case VPCI_QUEUE_NUM:
424	Assert(cb == 2);
425	(uint16_t)pu32 = pState->Queues[pState->uQueueSelector].VRing.uSize;
426	break;
427
428	case VPCI_QUEUE_SEL:
429	Assert(cb == 2);
430	(uint16_t)pu32 = pState->uQueueSelector;
431	break;
432
433	case VPCI_STATUS:
434	Assert(cb == 1);
435	(uint8_t)pu32 = pState->uStatus;
436	break;
437
438	case VPCI_ISR:
439	Assert(cb == 1);
440	(uint8_t)pu32 = pState->uISR;
441	pState->uISR = 0; /* read clears all interrupts */
442	vpciLowerInterrupt(pState);
443	break;
444
445	default:
446	if (Port >= VPCI_CONFIG)
447	rc = pCallbacks->pfnGetConfig(pState, Port - VPCI_CONFIG, cb, pu32);
448	else
449	{
450	*pu32 = 0xFFFFFFFF;
451	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortIn: no valid port at offset port=%RTiop cb=%08x\n",
452	INSTANCE(pState), Port, cb);
453	}
454	break;
455	}
456	Log3(("%s vpciIOPortIn: At %RTiop in %0x\n", INSTANCE(pState), Port, cb2, *pu32));
457	STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF(StatIORead), a);
458	//vpciCsLeave(pState);
459	return rc;
460	}
461
462
463	/**
464	* Port I/O Handler for OUT operations.
465	*
466	* @returns VBox status code.
467	*
468	* @param pDevIns The device instance.
469	* @param pvUser User argument.
470	* @param Port Port number used for the IN operation.
471	* @param u32 The value to output.
472	* @param cb The value size in bytes.
473	* @param pCallbacks Pointer to the callbacks.
474	* @thread EMT
475	*/
476	int vpciIOPortOut(PPDMDEVINS pDevIns,
477	void *pvUser,
478	RTIOPORT Port,
479	uint32_t u32,
480	unsigned cb,
481	PCVPCIIOCALLBACKS pCallbacks)
482	{
483	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
484	int rc = VINF_SUCCESS;
485	bool fHasBecomeReady;
486	STAM_PROFILE_ADV_START(&pState->CTX_SUFF(StatIOWrite), a);
487	RT_NOREF_PV(pvUser);
488
489	Port -= pState->IOPortBase;
490	Log3(("%s virtioIOPortOut: At %RTiop out %0x\n", INSTANCE(pState), Port, cb2, u32));
491
492	switch (Port)
493	{
494	case VPCI_GUEST_FEATURES:
495	{
496	const uint32_t uHostFeatures = vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures);
497
498	if (RT_LIKELY((u32 & ~uHostFeatures) == 0))
499	{
500	pState->uGuestFeatures = u32;
501	}
502	else
503	{
504	/*
505	* Guest requests features we don't advertise. Stick
506	* to the minimum if negotiation looks completely
507	* botched, otherwise restrict to advertised features.
508	*/
509	if (u32 & VPCI_F_BAD_FEATURE)
510	{
511	Log(("%s WARNING! Guest failed to negotiate properly (guest=%x)\n",
512	INSTANCE(pState), u32));
513	pState->uGuestFeatures = pCallbacks->pfnGetHostMinimalFeatures(pState);
514	}
515	else
516	{
517	Log(("%s Guest asked for features host does not support! (host=%x guest=%x)\n",
518	INSTANCE(pState), uHostFeatures, u32));
519	pState->uGuestFeatures = u32 & uHostFeatures;
520	}
521	}
522	pCallbacks->pfnSetHostFeatures(pState, pState->uGuestFeatures);
523	break;
524	}
525
526	case VPCI_QUEUE_PFN:
527	/*
528	* The guest is responsible for allocating the pages for queues,
529	* here it provides us with the page number of descriptor table.
530	* Note that we provide the size of the queue to the guest via
531	* VIRTIO_PCI_QUEUE_NUM.
532	*/
533	pState->Queues[pState->uQueueSelector].uPageNumber = u32;
534	if (u32)
535	vqueueInit(&pState->Queues[pState->uQueueSelector], u32);
536	else
537	rc = pCallbacks->pfnReset(pState);
538	break;
539
540	case VPCI_QUEUE_SEL:
541	Assert(cb == 2);
542	u32 &= 0xFFFF;
543	if (u32 < pState->nQueues)
544	pState->uQueueSelector = u32;
545	else
546	Log3(("%s vpciIOPortOut: Invalid queue selector %08x\n", INSTANCE(pState), u32));
547	break;
548
549	case VPCI_QUEUE_NOTIFY:
550	#ifdef IN_RING3
551	Assert(cb == 2);
552	u32 &= 0xFFFF;
553	if (u32 < pState->nQueues)
554	{
555	RT_UNTRUSTED_VALIDATED_FENCE();
556	if (pState->Queues[u32].VRing.addrDescriptors)
557	{
558	// rc = vpciCsEnter(pState, VERR_SEM_BUSY);
559	// if (RT_LIKELY(rc == VINF_SUCCESS))
560	// {
561	pState->Queues[u32].pfnCallback(pState, &pState->Queues[u32]);
562	// vpciCsLeave(pState);
563	// }
564	}
565	else
566	Log(("%s The queue (#%d) being notified has not been initialized.\n",
567	INSTANCE(pState), u32));
568	}
569	else
570	Log(("%s Invalid queue number (%d)\n", INSTANCE(pState), u32));
571	#else
572	rc = VINF_IOM_R3_IOPORT_WRITE;
573	#endif
574	break;
575
576	case VPCI_STATUS:
577	Assert(cb == 1);
578	u32 &= 0xFF;
579	fHasBecomeReady = !(pState->uStatus & VPCI_STATUS_DRV_OK) && (u32 & VPCI_STATUS_DRV_OK);
580	pState->uStatus = u32;
581	/* Writing 0 to the status port triggers device reset. */
582	if (u32 == 0)
583	rc = pCallbacks->pfnReset(pState);
584	else if (fHasBecomeReady)
585	{
586	/* Older hypervisors were lax and did not enforce bus mastering. Older guests
587	* (Linux prior to 2.6.34, NetBSD 6.x) were lazy and did not enable bus mastering.
588	* We automagically enable bus mastering on driver initialization to make existing
589	* drivers work.
590	*/
591	PDMPciDevSetCommand(&pState->pciDevice, PDMPciDevGetCommand(&pState->pciDevice) \| PCI_COMMAND_BUSMASTER);
592
593	pCallbacks->pfnReady(pState);
594	}
595	break;
596
597	default:
598	if (Port >= VPCI_CONFIG)
599	rc = pCallbacks->pfnSetConfig(pState, Port - VPCI_CONFIG, cb, &u32);
600	else
601	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortOut: no valid port at offset Port=%RTiop cb=%08x\n",
602	INSTANCE(pState), Port, cb);
603	break;
604	}
605
606	STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF(StatIOWrite), a);
607	return rc;
608	}
609
610	#ifdef IN_RING3
611
612	/**
613	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
614	*/
615	void vpciQueryInterface(struct PDMIBASE pInterface, const char *pszIID)
616	{
617	VPCISTATE *pThis = IFACE_TO_STATE(pInterface, IBase);
618	Assert(&pThis->IBase == pInterface);
619
620	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
621	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
622	return NULL;
623	}
624
625	/**
626	* Gets the pointer to the status LED of a unit.
627	*
628	* @returns VBox status code.
629	* @param pInterface Pointer to the interface structure.
630	* @param iLUN The unit which status LED we desire.
631	* @param ppLed Where to store the LED pointer.
632	* @thread EMT
633	*/
634	static DECLCALLBACK(int) vpciQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
635	{
636	VPCISTATE *pState = IFACE_TO_STATE(pInterface, ILeds);
637	int rc = VERR_PDM_LUN_NOT_FOUND;
638
639	if (iLUN == 0)
640	{
641	*ppLed = &pState->led;
642	rc = VINF_SUCCESS;
643	}
644	return rc;
645	}
646
647	/**
648	* Turns on/off the write status LED.
649	*
650	* @returns VBox status code.
651	* @param pState Pointer to the device state structure.
652	* @param fOn New LED state.
653	*/
654	void vpciSetWriteLed(PVPCISTATE pState, bool fOn)
655	{
656	LogFlow(("%s vpciSetWriteLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
657	if (fOn)
658	pState->led.Asserted.s.fWriting = pState->led.Actual.s.fWriting = 1;
659	else
660	pState->led.Actual.s.fWriting = fOn;
661	}
662
663	/**
664	* Turns on/off the read status LED.
665	*
666	* @returns VBox status code.
667	* @param pState Pointer to the device state structure.
668	* @param fOn New LED state.
669	*/
670	void vpciSetReadLed(PVPCISTATE pState, bool fOn)
671	{
672	LogFlow(("%s vpciSetReadLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
673	if (fOn)
674	pState->led.Asserted.s.fReading = pState->led.Actual.s.fReading = 1;
675	else
676	pState->led.Actual.s.fReading = fOn;
677	}
678
679
680	#if 0 /* unused */
681	/**
682	* Sets 32-bit register in PCI configuration space.
683	* @param refPciDev The PCI device.
684	* @param uOffset The register offset.
685	* @param u32Value The value to store in the register.
686	* @thread EMT
687	*/
688	DECLINLINE(void) vpciCfgSetU32(PDMPCIDEV& refPciDev, uint32_t uOffset, uint32_t u32Value)
689	{
690	Assert(uOffset+sizeof(u32Value) <= sizeof(refPciDev.config));
691	(uint32_t)&refPciDev.config[uOffset] = u32Value;
692	}
693	#endif /* unused */
694
695
696	#ifdef DEBUG
697	static void vpciDumpState(PVPCISTATE pState, const char *pcszCaller)
698	{
699	Log2(("vpciDumpState: (called from %s)\n"
700	" uGuestFeatures = 0x%08x\n"
701	" uQueueSelector = 0x%04x\n"
702	" uStatus = 0x%02x\n"
703	" uISR = 0x%02x\n",
704	pcszCaller,
705	pState->uGuestFeatures,
706	pState->uQueueSelector,
707	pState->uStatus,
708	pState->uISR));
709
710	for (unsigned i = 0; i < pState->nQueues; i++)
711	Log2((" %s queue:\n"
712	" VRing.uSize = %u\n"
713	" VRing.addrDescriptors = %p\n"
714	" VRing.addrAvail = %p\n"
715	" VRing.addrUsed = %p\n"
716	" uNextAvailIndex = %u\n"
717	" uNextUsedIndex = %u\n"
718	" uPageNumber = %x\n",
719	pState->Queues[i].pcszName,
720	pState->Queues[i].VRing.uSize,
721	pState->Queues[i].VRing.addrDescriptors,
722	pState->Queues[i].VRing.addrAvail,
723	pState->Queues[i].VRing.addrUsed,
724	pState->Queues[i].uNextAvailIndex,
725	pState->Queues[i].uNextUsedIndex,
726	pState->Queues[i].uPageNumber));
727	}
728	#else
729	# define vpciDumpState(x, s) do {} while (0)
730	#endif
731
732	/**
733	* Saves the state of device.
734	*
735	* @returns VBox status code.
736	* @param pDevIns The device instance.
737	* @param pSSM The handle to the saved state.
738	*/
739	int vpciSaveExec(PVPCISTATE pState, PSSMHANDLE pSSM)
740	{
741	int rc;
742
743	vpciDumpState(pState, "vpciSaveExec");
744
745	rc = SSMR3PutU32(pSSM, pState->uGuestFeatures);
746	AssertRCReturn(rc, rc);
747	rc = SSMR3PutU16(pSSM, pState->uQueueSelector);
748	AssertRCReturn(rc, rc);
749	rc = SSMR3PutU8( pSSM, pState->uStatus);
750	AssertRCReturn(rc, rc);
751	rc = SSMR3PutU8( pSSM, pState->uISR);
752	AssertRCReturn(rc, rc);
753
754	/* Save queue states */
755	rc = SSMR3PutU32(pSSM, pState->nQueues);
756	AssertRCReturn(rc, rc);
757	for (unsigned i = 0; i < pState->nQueues; i++)
758	{
759	rc = SSMR3PutU16(pSSM, pState->Queues[i].VRing.uSize);
760	AssertRCReturn(rc, rc);
761	rc = SSMR3PutU32(pSSM, pState->Queues[i].uPageNumber);
762	AssertRCReturn(rc, rc);
763	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextAvailIndex);
764	AssertRCReturn(rc, rc);
765	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextUsedIndex);
766	AssertRCReturn(rc, rc);
767	}
768
769	return VINF_SUCCESS;
770	}
771
772	/**
773	* Loads a saved device state.
774	*
775	* @returns VBox status code.
776	* @param pDevIns The device instance.
777	* @param pSSM The handle to the saved state.
778	* @param uVersion The data unit version number.
779	* @param uPass The data pass.
780	*/
781	int vpciLoadExec(PVPCISTATE pState, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass, uint32_t nQueues)
782	{
783	int rc;
784
785	if (uPass == SSM_PASS_FINAL)
786	{
787	/* Restore state data */
788	rc = SSMR3GetU32(pSSM, &pState->uGuestFeatures);
789	AssertRCReturn(rc, rc);
790	rc = SSMR3GetU16(pSSM, &pState->uQueueSelector);
791	AssertRCReturn(rc, rc);
792	rc = SSMR3GetU8( pSSM, &pState->uStatus);
793	AssertRCReturn(rc, rc);
794	rc = SSMR3GetU8( pSSM, &pState->uISR);
795	AssertRCReturn(rc, rc);
796
797	/* Restore queues */
798	if (uVersion > VIRTIO_SAVEDSTATE_VERSION_3_1_BETA1)
799	{
800	rc = SSMR3GetU32(pSSM, &pState->nQueues);
801	AssertRCReturn(rc, rc);
802	}
803	else
804	pState->nQueues = nQueues;
805	AssertLogRelMsgReturn(pState->nQueues <= VIRTIO_MAX_NQUEUES, ("%#x\n", pState->nQueues), VERR_SSM_LOAD_CONFIG_MISMATCH);
806	AssertLogRelMsgReturn(pState->uQueueSelector < pState->nQueues \|\| (pState->nQueues == 0 && pState->uQueueSelector),
807	("uQueueSelector=%u nQueues=%u\n", pState->uQueueSelector, pState->nQueues),
808	VERR_SSM_LOAD_CONFIG_MISMATCH);
809
810	for (unsigned i = 0; i < pState->nQueues; i++)
811	{
812	rc = SSMR3GetU16(pSSM, &pState->Queues[i].VRing.uSize);
813	AssertRCReturn(rc, rc);
814	rc = SSMR3GetU32(pSSM, &pState->Queues[i].uPageNumber);
815	AssertRCReturn(rc, rc);
816
817	if (pState->Queues[i].uPageNumber)
818	vqueueInit(&pState->Queues[i], pState->Queues[i].uPageNumber);
819
820	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextAvailIndex);
821	AssertRCReturn(rc, rc);
822	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextUsedIndex);
823	AssertRCReturn(rc, rc);
824	}
825	}
826
827	vpciDumpState(pState, "vpciLoadExec");
828
829	return VINF_SUCCESS;
830	}
831
832	/**
833	* Set PCI configuration space registers.
834	*
835	* @param pci Reference to PCI device structure.
836	* @param uDeviceId VirtiO Device Id
837	* @param uClass Class of PCI device (network, etc)
838	* @thread EMT
839	*/
840	static DECLCALLBACK(void) vpciConfigure(PDMPCIDEV& pci,
841	uint16_t uDeviceId,
842	uint16_t uClass)
843	{
844	/* Configure PCI Device, assume 32-bit mode ******************************/
845	PCIDevSetVendorId(&pci, DEVICE_PCI_VENDOR_ID);
846	PCIDevSetDeviceId(&pci, DEVICE_PCI_BASE_ID + uDeviceId);
847	PDMPciDevSetWord(&pci, VBOX_PCI_SUBSYSTEM_VENDOR_ID, DEVICE_PCI_SUBSYSTEM_VENDOR_ID);
848	PDMPciDevSetWord(&pci, VBOX_PCI_SUBSYSTEM_ID, DEVICE_PCI_SUBSYSTEM_BASE_ID + uDeviceId);
849
850	/* ABI version, must be equal 0 as of 2.6.30 kernel. */
851	PDMPciDevSetByte(&pci, VBOX_PCI_REVISION_ID, 0x00);
852	/* Ethernet adapter */
853	PDMPciDevSetByte(&pci, VBOX_PCI_CLASS_PROG, 0x00);
854	PDMPciDevSetWord(&pci, VBOX_PCI_CLASS_DEVICE, uClass);
855	/* Interrupt Pin: INTA# */
856	PDMPciDevSetByte(&pci, VBOX_PCI_INTERRUPT_PIN, 0x01);
857
858	#ifdef VBOX_WITH_MSI_DEVICES
859	PCIDevSetCapabilityList(&pci, 0x80);
860	PCIDevSetStatus( &pci, VBOX_PCI_STATUS_CAP_LIST);
861	#endif
862	}
863
864	#ifdef VBOX_WITH_STATISTICS
865	/* WARNING! This function must never be used in multithreaded context! */
866	static const char vpciCounter(const char pszDevFmt,
867	const char *pszCounter)
868	{
869	static char s_szCounterName[80];
870
871	RTStrPrintf(s_szCounterName, sizeof(s_szCounterName),
872	"/Devices/%s/%s", pszDevFmt, pszCounter);
873
874	return s_szCounterName;
875	}
876	#endif
877
878	/// @todo header
879	int vpciConstruct(PPDMDEVINS pDevIns, VPCISTATE *pState,
880	int iInstance, const char *pcszNameFmt,
881	uint16_t uDeviceId, uint16_t uClass,
882	uint32_t nQueues)
883	{
884	/* Init handles and log related stuff. */
885	RTStrPrintf(pState->szInstance, sizeof(pState->szInstance),
886	pcszNameFmt, iInstance);
887
888	pState->pDevInsR3 = pDevIns;
889	pState->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
890	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
891	pState->led.u32Magic = PDMLED_MAGIC;
892
893	pState->ILeds.pfnQueryStatusLed = vpciQueryStatusLed;
894
895	/* Initialize critical section. */
896	int rc = PDMDevHlpCritSectInit(pDevIns, &pState->cs, RT_SRC_POS, "%s", pState->szInstance);
897	if (RT_FAILURE(rc))
898	return rc;
899
900	/* Set PCI config registers */
901	vpciConfigure(pState->pciDevice, uDeviceId, uClass);
902	/* Register PCI device */
903	rc = PDMDevHlpPCIRegister(pDevIns, &pState->pciDevice);
904	if (RT_FAILURE(rc))
905	return rc;
906
907	#ifdef VBOX_WITH_MSI_DEVICES
908	#if 0
909	{
910	PDMMSIREG aMsiReg;
911
912	RT_ZERO(aMsiReg);
913	aMsiReg.cMsixVectors = 1;
914	aMsiReg.iMsixCapOffset = 0x80;
915	aMsiReg.iMsixNextOffset = 0x0;
916	aMsiReg.iMsixBar = 0;
917	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
918	if (RT_FAILURE (rc))
919	PCIDevSetCapabilityList(&pState->pciDevice, 0x0);
920	}
921	#endif
922	#endif
923
924	/* Status driver */
925	PPDMIBASE pBase;
926	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pState->IBase, &pBase, "Status Port");
927	if (RT_FAILURE(rc))
928	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
929	pState->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
930
931	pState->nQueues = nQueues;
932
933	#if defined(VBOX_WITH_STATISTICS)
934	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in R3", vpciCounter(pcszNameFmt, "IO/ReadR3"), iInstance);
935	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadR0, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in R0", vpciCounter(pcszNameFmt, "IO/ReadR0"), iInstance);
936	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadRC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in RC", vpciCounter(pcszNameFmt, "IO/ReadRC"), iInstance);
937	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in R3", vpciCounter(pcszNameFmt, "IO/WriteR3"), iInstance);
938	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteR0, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in R0", vpciCounter(pcszNameFmt, "IO/WriteR0"), iInstance);
939	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteRC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in RC", vpciCounter(pcszNameFmt, "IO/WriteRC"), iInstance);
940	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", vpciCounter(pcszNameFmt, "Interrupts/Raised"), iInstance);
941	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsSkipped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of skipped interrupts", vpciCounter(pcszNameFmt, "Interrupts/Skipped"), iInstance);
942	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in R3", vpciCounter(pcszNameFmt, "Cs/CsR3"), iInstance);
943	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsR0, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in R0", vpciCounter(pcszNameFmt, "Cs/CsR0"), iInstance);
944	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsRC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in RC", vpciCounter(pcszNameFmt, "Cs/CsRC"), iInstance);
945	#endif /* VBOX_WITH_STATISTICS */
946
947	return rc;
948	}
949
950	/**
951	* Destruct PCI-related part of device.
952	*
953	* We need to free non-VM resources only.
954	*
955	* @returns VBox status code.
956	* @param pState The device state structure.
957	*/
958	int vpciDestruct(VPCISTATE* pState)
959	{
960	Log(("%s Destroying PCI instance\n", INSTANCE(pState)));
961
962	if (PDMCritSectIsInitialized(&pState->cs))
963	PDMR3CritSectDelete(&pState->cs);
964
965	return VINF_SUCCESS;
966	}
967
968	/**
969	* Device relocation callback.
970	*
971	* When this callback is called the device instance data, and if the
972	* device have a GC component, is being relocated, or/and the selectors
973	* have been changed. The device must use the chance to perform the
974	* necessary pointer relocations and data updates.
975	*
976	* Before the GC code is executed the first time, this function will be
977	* called with a 0 delta so GC pointer calculations can be one in one place.
978	*
979	* @param pDevIns Pointer to the device instance.
980	* @param offDelta The relocation delta relative to the old location.
981	*
982	* @remark A relocation CANNOT fail.
983	*/
984	void vpciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
985	{
986	RT_NOREF(offDelta);
987	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE);
988	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
989	// TBD
990	}
991
992	PVQUEUE vpciAddQueue(VPCISTATE* pState, unsigned uSize, PFNVPCIQUEUECALLBACK pfnCallback, const char *pcszName)
993	{
994	PVQUEUE pQueue = NULL;
995	/* Find an empty queue slot */
996	for (unsigned i = 0; i < pState->nQueues; i++)
997	{
998	if (pState->Queues[i].VRing.uSize == 0)
999	{
1000	pQueue = &pState->Queues[i];
1001	break;
1002	}
1003	}
1004
1005	if (!pQueue)
1006	{
1007	Log(("%s Too many queues being added, no empty slots available!\n", INSTANCE(pState)));
1008	}
1009	else
1010	{
1011	pQueue->VRing.uSize = uSize;
1012	pQueue->VRing.addrDescriptors = 0;
1013	pQueue->uPageNumber = 0;
1014	pQueue->pfnCallback = pfnCallback;
1015	pQueue->pcszName = pcszName;
1016	}
1017
1018	return pQueue;
1019	}
1020
1021	#endif /* IN_RING3 */
1022
1023	#endif /* VBOX_DEVICE_STRUCT_TESTCASE */
1024

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source: vbox/trunk/src/VBox/Devices/VirtIO/Virtio.cpp@ 73410

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