Virtio.cpp@ 58466

Last change on this file since 58466 was 58170, checked in by vboxsync, 9 years ago
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1	/* $Id: Virtio.cpp 58170 2015-10-12 09:27:14Z vboxsync $ */
2	/** @file
3	* Virtio - Virtio Common Functions (VRing, VQueue, Virtio PCI)
4	*/
5
6	/*
7	* Copyright (C) 2009-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_VIRTIO
23
24	#include <iprt/param.h>
25	#include <iprt/uuid.h>
26	#include <VBox/vmm/pdmdev.h>
27	#include "Virtio.h"
28
29	#define INSTANCE(pState) pState->szInstance
30	#define IFACE_TO_STATE(pIface, ifaceName) ((VPCISTATE )((char)pIface - RT_OFFSETOF(VPCISTATE, ifaceName)))
31
32	#ifdef LOG_ENABLED
33	# define QUEUENAME(s, q) (q->pcszName)
34	#endif
35
36
37
38	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
39
40	//RT_C_DECLS_BEGIN
41	//RT_C_DECLS_END
42
43
44	static void vqueueReset(PVQUEUE pQueue)
45	{
46	pQueue->VRing.addrDescriptors = 0;
47	pQueue->VRing.addrAvail = 0;
48	pQueue->VRing.addrUsed = 0;
49	pQueue->uNextAvailIndex = 0;
50	pQueue->uNextUsedIndex = 0;
51	pQueue->uPageNumber = 0;
52	}
53
54	static void vqueueInit(PVQUEUE pQueue, uint32_t uPageNumber)
55	{
56	pQueue->VRing.addrDescriptors = (uint64_t)uPageNumber << PAGE_SHIFT;
57	pQueue->VRing.addrAvail = pQueue->VRing.addrDescriptors
58	+ sizeof(VRINGDESC) * pQueue->VRing.uSize;
59	pQueue->VRing.addrUsed = RT_ALIGN(
60	pQueue->VRing.addrAvail + RT_OFFSETOF(VRINGAVAIL, auRing[pQueue->VRing.uSize]),
61	PAGE_SIZE); /* The used ring must start from the next page. */
62	pQueue->uNextAvailIndex = 0;
63	pQueue->uNextUsedIndex = 0;
64	}
65
66	// void vqueueElemFree(PVQUEUEELEM pElem)
67	// {
68	// }
69
70	void vringReadDesc(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, PVRINGDESC pDesc)
71	{
72	//Log(("%s vringReadDesc: ring=%p idx=%u\n", INSTANCE(pState), pVRing, uIndex));
73	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
74	pVRing->addrDescriptors + sizeof(VRINGDESC) * (uIndex % pVRing->uSize),
75	pDesc, sizeof(VRINGDESC));
76	}
77
78	uint16_t vringReadAvail(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex)
79	{
80	uint16_t tmp;
81
82	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
83	pVRing->addrAvail + RT_OFFSETOF(VRINGAVAIL, auRing[uIndex % pVRing->uSize]),
84	&tmp, sizeof(tmp));
85	return tmp;
86	}
87
88	uint16_t vringReadAvailFlags(PVPCISTATE pState, PVRING pVRing)
89	{
90	uint16_t tmp;
91
92	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
93	pVRing->addrAvail + RT_OFFSETOF(VRINGAVAIL, uFlags),
94	&tmp, sizeof(tmp));
95	return tmp;
96	}
97
98	void vringSetNotification(PVPCISTATE pState, PVRING pVRing, bool fEnabled)
99	{
100	uint16_t tmp;
101
102	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
103	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uFlags),
104	&tmp, sizeof(tmp));
105
106	if (fEnabled)
107	tmp &= ~ VRINGUSED_F_NO_NOTIFY;
108	else
109	tmp \|= VRINGUSED_F_NO_NOTIFY;
110
111	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
112	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uFlags),
113	&tmp, sizeof(tmp));
114	}
115
116	bool vqueueSkip(PVPCISTATE pState, PVQUEUE pQueue)
117	{
118	if (vqueueIsEmpty(pState, pQueue))
119	return false;
120
121	Log2(("%s vqueueSkip: %s avail_idx=%u\n", INSTANCE(pState),
122	QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
123	pQueue->uNextAvailIndex++;
124	return true;
125	}
126
127	bool vqueueGet(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem, bool fRemove)
128	{
129	if (vqueueIsEmpty(pState, pQueue))
130	return false;
131
132	pElem->nIn = pElem->nOut = 0;
133
134	Log2(("%s vqueueGet: %s avail_idx=%u\n", INSTANCE(pState),
135	QUEUENAME(pState, pQueue), pQueue->uNextAvailIndex));
136
137	VRINGDESC desc;
138	uint16_t idx = vringReadAvail(pState, &pQueue->VRing, pQueue->uNextAvailIndex);
139	if (fRemove)
140	pQueue->uNextAvailIndex++;
141	pElem->uIndex = idx;
142	do
143	{
144	VQUEUESEG *pSeg;
145
146	vringReadDesc(pState, &pQueue->VRing, idx, &desc);
147	if (desc.u16Flags & VRINGDESC_F_WRITE)
148	{
149	Log2(("%s vqueueGet: %s IN seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
150	QUEUENAME(pState, pQueue), pElem->nIn, idx, desc.u64Addr, desc.uLen));
151	pSeg = &pElem->aSegsIn[pElem->nIn++];
152	}
153	else
154	{
155	Log2(("%s vqueueGet: %s OUT seg=%u desc_idx=%u addr=%p cb=%u\n", INSTANCE(pState),
156	QUEUENAME(pState, pQueue), pElem->nOut, idx, desc.u64Addr, desc.uLen));
157	pSeg = &pElem->aSegsOut[pElem->nOut++];
158	}
159
160	pSeg->addr = desc.u64Addr;
161	pSeg->cb = desc.uLen;
162	pSeg->pv = NULL;
163
164	idx = desc.u16Next;
165	} while (desc.u16Flags & VRINGDESC_F_NEXT);
166
167	Log2(("%s vqueueGet: %s head_desc_idx=%u nIn=%u nOut=%u\n", INSTANCE(pState),
168	QUEUENAME(pState, pQueue), pElem->uIndex, pElem->nIn, pElem->nOut));
169	return true;
170	}
171
172	uint16_t vringReadUsedIndex(PVPCISTATE pState, PVRING pVRing)
173	{
174	uint16_t tmp;
175	PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns),
176	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uIndex),
177	&tmp, sizeof(tmp));
178	return tmp;
179	}
180
181	void vringWriteUsedIndex(PVPCISTATE pState, PVRING pVRing, uint16_t u16Value)
182	{
183	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
184	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, uIndex),
185	&u16Value, sizeof(u16Value));
186	}
187
188	void vringWriteUsedElem(PVPCISTATE pState, PVRING pVRing, uint32_t uIndex, uint32_t uId, uint32_t uLen)
189	{
190	VRINGUSEDELEM elem;
191
192	elem.uId = uId;
193	elem.uLen = uLen;
194	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns),
195	pVRing->addrUsed + RT_OFFSETOF(VRINGUSED, aRing[uIndex % pVRing->uSize]),
196	&elem, sizeof(elem));
197	}
198
199	void vqueuePut(PVPCISTATE pState, PVQUEUE pQueue, PVQUEUEELEM pElem, uint32_t uLen, uint32_t uReserved)
200	{
201	unsigned int i, uOffset, cbReserved = uReserved;
202
203	Log2(("%s vqueuePut: %s desc_idx=%u acb=%u\n", INSTANCE(pState),
204	QUEUENAME(pState, pQueue), pElem->uIndex, uLen));
205	for (i = uOffset = 0; i < pElem->nIn && uOffset < uLen - uReserved; i++)
206	{
207	uint32_t cbSegLen = RT_MIN(uLen - cbReserved - uOffset, pElem->aSegsIn[i].cb - cbReserved);
208	if (pElem->aSegsIn[i].pv)
209	{
210	Log2(("%s vqueuePut: %s used_idx=%u seg=%u addr=%p pv=%p cb=%u acb=%u\n", INSTANCE(pState),
211	QUEUENAME(pState, pQueue), pQueue->uNextUsedIndex, i, pElem->aSegsIn[i].addr, pElem->aSegsIn[i].pv, pElem->aSegsIn[i].cb, cbSegLen));
212	PDMDevHlpPCIPhysWrite(pState->CTX_SUFF(pDevIns), pElem->aSegsIn[i].addr + cbReserved,
213	pElem->aSegsIn[i].pv, cbSegLen);
214	cbReserved = 0;
215	}
216	uOffset += cbSegLen;
217	}
218
219	Assert((uReserved + uOffset) == uLen \|\| pElem->nIn == 0);
220	Log2(("%s vqueuePut: %s used_idx=%u guest_used_idx=%u id=%u len=%u\n", INSTANCE(pState),
221	QUEUENAME(pState, pQueue), pQueue->uNextUsedIndex, vringReadUsedIndex(pState, &pQueue->VRing), pElem->uIndex, uLen));
222	vringWriteUsedElem(pState, &pQueue->VRing, pQueue->uNextUsedIndex++, pElem->uIndex, uLen);
223	}
224
225	void vqueueNotify(PVPCISTATE pState, PVQUEUE pQueue)
226	{
227	LogFlow(("%s vqueueNotify: %s availFlags=%x guestFeatures=%x vqueue is %sempty\n",
228	INSTANCE(pState), QUEUENAME(pState, pQueue),
229	vringReadAvailFlags(pState, &pQueue->VRing),
230	pState->uGuestFeatures, vqueueIsEmpty(pState, pQueue)?"":"not "));
231	if (!(vringReadAvailFlags(pState, &pQueue->VRing) & VRINGAVAIL_F_NO_INTERRUPT)
232	\|\| ((pState->uGuestFeatures & VPCI_F_NOTIFY_ON_EMPTY) && vqueueIsEmpty(pState, pQueue)))
233	{
234	int rc = vpciRaiseInterrupt(pState, VERR_INTERNAL_ERROR, VPCI_ISR_QUEUE);
235	if (RT_FAILURE(rc))
236	Log(("%s vqueueNotify: Failed to raise an interrupt (%Rrc).\n", INSTANCE(pState), rc));
237	}
238	else
239	{
240	STAM_COUNTER_INC(&pState->StatIntsSkipped);
241	}
242
243	}
244
245	void vqueueSync(PVPCISTATE pState, PVQUEUE pQueue)
246	{
247	Log2(("%s vqueueSync: %s old_used_idx=%u new_used_idx=%u\n", INSTANCE(pState),
248	QUEUENAME(pState, pQueue), vringReadUsedIndex(pState, &pQueue->VRing), pQueue->uNextUsedIndex));
249	vringWriteUsedIndex(pState, &pQueue->VRing, pQueue->uNextUsedIndex);
250	vqueueNotify(pState, pQueue);
251	}
252
253	void vpciReset(PVPCISTATE pState)
254	{
255	pState->uGuestFeatures = 0;
256	pState->uQueueSelector = 0;
257	pState->uStatus = 0;
258	pState->uISR = 0;
259
260	for (unsigned i = 0; i < pState->nQueues; i++)
261	vqueueReset(&pState->Queues[i]);
262	}
263
264
265	/**
266	* Raise interrupt.
267	*
268	* @param pState The device state structure.
269	* @param rcBusy Status code to return when the critical section is busy.
270	* @param u8IntCause Interrupt cause bit mask to set in PCI ISR port.
271	*/
272	int vpciRaiseInterrupt(VPCISTATE *pState, int rcBusy, uint8_t u8IntCause)
273	{
274	// int rc = vpciCsEnter(pState, rcBusy);
275	// if (RT_UNLIKELY(rc != VINF_SUCCESS))
276	// return rc;
277
278	STAM_COUNTER_INC(&pState->StatIntsRaised);
279	LogFlow(("%s vpciRaiseInterrupt: u8IntCause=%x\n",
280	INSTANCE(pState), u8IntCause));
281
282	pState->uISR \|= u8IntCause;
283	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 1);
284	// vpciCsLeave(pState);
285	return VINF_SUCCESS;
286	}
287
288	/**
289	* Lower interrupt.
290	*
291	* @param pState The device state structure.
292	*/
293	static void vpciLowerInterrupt(VPCISTATE *pState)
294	{
295	LogFlow(("%s vpciLowerInterrupt\n", INSTANCE(pState)));
296	PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
297	}
298
299	DECLINLINE(uint32_t) vpciGetHostFeatures(PVPCISTATE pState,
300	PFNGETHOSTFEATURES pfnGetHostFeatures)
301	{
302	return pfnGetHostFeatures(pState)
303	\| VPCI_F_NOTIFY_ON_EMPTY;
304	}
305
306	/**
307	* Port I/O Handler for IN operations.
308	*
309	* @returns VBox status code.
310	*
311	* @param pDevIns The device instance.
312	* @param pvUser Pointer to the device state structure.
313	* @param Port Port number used for the IN operation.
314	* @param pu32 Where to store the result.
315	* @param cb Number of bytes read.
316	* @param pCallbacks Pointer to the callbacks.
317	* @thread EMT
318	*/
319	int vpciIOPortIn(PPDMDEVINS pDevIns,
320	void *pvUser,
321	RTIOPORT Port,
322	uint32_t *pu32,
323	unsigned cb,
324	PCVPCIIOCALLBACKS pCallbacks)
325	{
326	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
327	int rc = VINF_SUCCESS;
328	STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIORead), a);
329
330	/*
331	* We probably do not need to enter critical section when reading registers
332	* as the most of them are either constant or being changed during
333	* initialization only, the exception being ISR which can be raced by all
334	* threads but I see no big harm in it. It also happens to be the most read
335	* register as it gets read in interrupt handler. By dropping cs protection
336	* here we gain the ability to deliver RX packets to the guest while TX is
337	* holding cs transmitting queued packets.
338	*
339	rc = vpciCsEnter(pState, VINF_IOM_R3_IOPORT_READ);
340	if (RT_UNLIKELY(rc != VINF_SUCCESS))
341	{
342	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
343	return rc;
344	}*/
345
346	Port -= pState->IOPortBase;
347	switch (Port)
348	{
349	case VPCI_HOST_FEATURES:
350	/* Tell the guest what features we support. */
351	*pu32 = vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures)
352	\| VPCI_F_BAD_FEATURE;
353	break;
354
355	case VPCI_GUEST_FEATURES:
356	*pu32 = pState->uGuestFeatures;
357	break;
358
359	case VPCI_QUEUE_PFN:
360	*pu32 = pState->Queues[pState->uQueueSelector].uPageNumber;
361	break;
362
363	case VPCI_QUEUE_NUM:
364	Assert(cb == 2);
365	(uint16_t)pu32 = pState->Queues[pState->uQueueSelector].VRing.uSize;
366	break;
367
368	case VPCI_QUEUE_SEL:
369	Assert(cb == 2);
370	(uint16_t)pu32 = pState->uQueueSelector;
371	break;
372
373	case VPCI_STATUS:
374	Assert(cb == 1);
375	(uint8_t)pu32 = pState->uStatus;
376	break;
377
378	case VPCI_ISR:
379	Assert(cb == 1);
380	(uint8_t)pu32 = pState->uISR;
381	pState->uISR = 0; /* read clears all interrupts */
382	vpciLowerInterrupt(pState);
383	break;
384
385	default:
386	if (Port >= VPCI_CONFIG)
387	rc = pCallbacks->pfnGetConfig(pState, Port - VPCI_CONFIG, cb, pu32);
388	else
389	{
390	*pu32 = 0xFFFFFFFF;
391	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortIn: no valid port at offset port=%RTiop cb=%08x\n",
392	INSTANCE(pState), Port, cb);
393	}
394	break;
395	}
396	Log3(("%s vpciIOPortIn: At %RTiop in %0x\n", INSTANCE(pState), Port, cb2, *pu32));
397	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
398	//vpciCsLeave(pState);
399	return rc;
400	}
401
402
403	/**
404	* Port I/O Handler for OUT operations.
405	*
406	* @returns VBox status code.
407	*
408	* @param pDevIns The device instance.
409	* @param pvUser User argument.
410	* @param Port Port number used for the IN operation.
411	* @param u32 The value to output.
412	* @param cb The value size in bytes.
413	* @param pCallbacks Pointer to the callbacks.
414	* @thread EMT
415	*/
416	int vpciIOPortOut(PPDMDEVINS pDevIns,
417	void *pvUser,
418	RTIOPORT Port,
419	uint32_t u32,
420	unsigned cb,
421	PCVPCIIOCALLBACKS pCallbacks)
422	{
423	VPCISTATE pState = PDMINS_2_DATA(pDevIns, VPCISTATE );
424	int rc = VINF_SUCCESS;
425	bool fHasBecomeReady;
426	STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIOWrite), a);
427
428	Port -= pState->IOPortBase;
429	Log3(("%s virtioIOPortOut: At %RTiop out %0x\n", INSTANCE(pState), Port, cb2, u32));
430
431	switch (Port)
432	{
433	case VPCI_GUEST_FEATURES:
434	/* Check if the guest negotiates properly, fall back to basics if it does not. */
435	if (VPCI_F_BAD_FEATURE & u32)
436	{
437	Log(("%s WARNING! Guest failed to negotiate properly (guest=%x)\n",
438	INSTANCE(pState), u32));
439	pState->uGuestFeatures = pCallbacks->pfnGetHostMinimalFeatures(pState);
440	}
441	/* The guest may potentially desire features we don't support! */
442	else if (~vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures) & u32)
443	{
444	Log(("%s Guest asked for features host does not support! (host=%x guest=%x)\n",
445	INSTANCE(pState),
446	vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures), u32));
447	pState->uGuestFeatures =
448	vpciGetHostFeatures(pState, pCallbacks->pfnGetHostFeatures);
449	}
450	else
451	pState->uGuestFeatures = u32;
452	pCallbacks->pfnSetHostFeatures(pState, pState->uGuestFeatures);
453	break;
454
455	case VPCI_QUEUE_PFN:
456	/*
457	* The guest is responsible for allocating the pages for queues,
458	* here it provides us with the page number of descriptor table.
459	* Note that we provide the size of the queue to the guest via
460	* VIRTIO_PCI_QUEUE_NUM.
461	*/
462	pState->Queues[pState->uQueueSelector].uPageNumber = u32;
463	if (u32)
464	vqueueInit(&pState->Queues[pState->uQueueSelector], u32);
465	else
466	rc = pCallbacks->pfnReset(pState);
467	break;
468
469	case VPCI_QUEUE_SEL:
470	Assert(cb == 2);
471	u32 &= 0xFFFF;
472	if (u32 < pState->nQueues)
473	pState->uQueueSelector = u32;
474	else
475	Log3(("%s vpciIOPortOut: Invalid queue selector %08x\n", INSTANCE(pState), u32));
476	break;
477
478	case VPCI_QUEUE_NOTIFY:
479	#ifdef IN_RING3
480	Assert(cb == 2);
481	u32 &= 0xFFFF;
482	if (u32 < pState->nQueues)
483	if (pState->Queues[u32].VRing.addrDescriptors)
484	{
485	// rc = vpciCsEnter(pState, VERR_SEM_BUSY);
486	// if (RT_LIKELY(rc == VINF_SUCCESS))
487	// {
488	pState->Queues[u32].pfnCallback(pState, &pState->Queues[u32]);
489	// vpciCsLeave(pState);
490	// }
491	}
492	else
493	Log(("%s The queue (#%d) being notified has not been initialized.\n",
494	INSTANCE(pState), u32));
495	else
496	Log(("%s Invalid queue number (%d)\n", INSTANCE(pState), u32));
497	#else
498	rc = VINF_IOM_R3_IOPORT_WRITE;
499	#endif
500	break;
501
502	case VPCI_STATUS:
503	Assert(cb == 1);
504	u32 &= 0xFF;
505	fHasBecomeReady = !(pState->uStatus & VPCI_STATUS_DRV_OK) && (u32 & VPCI_STATUS_DRV_OK);
506	pState->uStatus = u32;
507	/* Writing 0 to the status port triggers device reset. */
508	if (u32 == 0)
509	rc = pCallbacks->pfnReset(pState);
510	else if (fHasBecomeReady)
511	pCallbacks->pfnReady(pState);
512	break;
513
514	default:
515	if (Port >= VPCI_CONFIG)
516	rc = pCallbacks->pfnSetConfig(pState, Port - VPCI_CONFIG, cb, &u32);
517	else
518	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s vpciIOPortOut: no valid port at offset Port=%RTiop cb=%08x\n",
519	INSTANCE(pState), Port, cb);
520	break;
521	}
522
523	STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIOWrite), a);
524	return rc;
525	}
526
527	#ifdef IN_RING3
528
529	/**
530	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
531	*/
532	void vpciQueryInterface(struct PDMIBASE pInterface, const char *pszIID)
533	{
534	VPCISTATE *pThis = IFACE_TO_STATE(pInterface, IBase);
535	Assert(&pThis->IBase == pInterface);
536
537	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
538	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
539	return NULL;
540	}
541
542	/**
543	* Gets the pointer to the status LED of a unit.
544	*
545	* @returns VBox status code.
546	* @param pInterface Pointer to the interface structure.
547	* @param iLUN The unit which status LED we desire.
548	* @param ppLed Where to store the LED pointer.
549	* @thread EMT
550	*/
551	static DECLCALLBACK(int) vpciQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
552	{
553	VPCISTATE *pState = IFACE_TO_STATE(pInterface, ILeds);
554	int rc = VERR_PDM_LUN_NOT_FOUND;
555
556	if (iLUN == 0)
557	{
558	*ppLed = &pState->led;
559	rc = VINF_SUCCESS;
560	}
561	return rc;
562	}
563
564	/**
565	* Turns on/off the write status LED.
566	*
567	* @returns VBox status code.
568	* @param pState Pointer to the device state structure.
569	* @param fOn New LED state.
570	*/
571	void vpciSetWriteLed(PVPCISTATE pState, bool fOn)
572	{
573	LogFlow(("%s vpciSetWriteLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
574	if (fOn)
575	pState->led.Asserted.s.fWriting = pState->led.Actual.s.fWriting = 1;
576	else
577	pState->led.Actual.s.fWriting = fOn;
578	}
579
580	/**
581	* Turns on/off the read status LED.
582	*
583	* @returns VBox status code.
584	* @param pState Pointer to the device state structure.
585	* @param fOn New LED state.
586	*/
587	void vpciSetReadLed(PVPCISTATE pState, bool fOn)
588	{
589	LogFlow(("%s vpciSetReadLed: %s\n", INSTANCE(pState), fOn?"on":"off"));
590	if (fOn)
591	pState->led.Asserted.s.fReading = pState->led.Actual.s.fReading = 1;
592	else
593	pState->led.Actual.s.fReading = fOn;
594	}
595
596	/**
597	* Sets 8-bit register in PCI configuration space.
598	* @param refPciDev The PCI device.
599	* @param uOffset The register offset.
600	* @param u16Value The value to store in the register.
601	* @thread EMT
602	*/
603	DECLINLINE(void) vpciCfgSetU8(PCIDEVICE& refPciDev, uint32_t uOffset, uint8_t u8Value)
604	{
605	Assert(uOffset < sizeof(refPciDev.config));
606	refPciDev.config[uOffset] = u8Value;
607	}
608
609	/**
610	* Sets 16-bit register in PCI configuration space.
611	* @param refPciDev The PCI device.
612	* @param uOffset The register offset.
613	* @param u16Value The value to store in the register.
614	* @thread EMT
615	*/
616	DECLINLINE(void) vpciCfgSetU16(PCIDEVICE& refPciDev, uint32_t uOffset, uint16_t u16Value)
617	{
618	Assert(uOffset+sizeof(u16Value) <= sizeof(refPciDev.config));
619	(uint16_t)&refPciDev.config[uOffset] = u16Value;
620	}
621
622	/**
623	* Sets 32-bit register in PCI configuration space.
624	* @param refPciDev The PCI device.
625	* @param uOffset The register offset.
626	* @param u32Value The value to store in the register.
627	* @thread EMT
628	*/
629	DECLINLINE(void) vpciCfgSetU32(PCIDEVICE& refPciDev, uint32_t uOffset, uint32_t u32Value)
630	{
631	Assert(uOffset+sizeof(u32Value) <= sizeof(refPciDev.config));
632	(uint32_t)&refPciDev.config[uOffset] = u32Value;
633	}
634
635
636	#ifdef DEBUG
637	static void vpciDumpState(PVPCISTATE pState, const char *pcszCaller)
638	{
639	Log2(("vpciDumpState: (called from %s)\n"
640	" uGuestFeatures = 0x%08x\n"
641	" uQueueSelector = 0x%04x\n"
642	" uStatus = 0x%02x\n"
643	" uISR = 0x%02x\n",
644	pcszCaller,
645	pState->uGuestFeatures,
646	pState->uQueueSelector,
647	pState->uStatus,
648	pState->uISR));
649
650	for (unsigned i = 0; i < pState->nQueues; i++)
651	Log2((" %s queue:\n"
652	" VRing.uSize = %u\n"
653	" VRing.addrDescriptors = %p\n"
654	" VRing.addrAvail = %p\n"
655	" VRing.addrUsed = %p\n"
656	" uNextAvailIndex = %u\n"
657	" uNextUsedIndex = %u\n"
658	" uPageNumber = %x\n",
659	pState->Queues[i].pcszName,
660	pState->Queues[i].VRing.uSize,
661	pState->Queues[i].VRing.addrDescriptors,
662	pState->Queues[i].VRing.addrAvail,
663	pState->Queues[i].VRing.addrUsed,
664	pState->Queues[i].uNextAvailIndex,
665	pState->Queues[i].uNextUsedIndex,
666	pState->Queues[i].uPageNumber));
667	}
668	#else
669	# define vpciDumpState(x, s) do {} while (0)
670	#endif
671
672	/**
673	* Saves the state of device.
674	*
675	* @returns VBox status code.
676	* @param pDevIns The device instance.
677	* @param pSSM The handle to the saved state.
678	*/
679	int vpciSaveExec(PVPCISTATE pState, PSSMHANDLE pSSM)
680	{
681	int rc;
682
683	vpciDumpState(pState, "vpciSaveExec");
684
685	rc = SSMR3PutU32(pSSM, pState->uGuestFeatures);
686	AssertRCReturn(rc, rc);
687	rc = SSMR3PutU16(pSSM, pState->uQueueSelector);
688	AssertRCReturn(rc, rc);
689	rc = SSMR3PutU8( pSSM, pState->uStatus);
690	AssertRCReturn(rc, rc);
691	rc = SSMR3PutU8( pSSM, pState->uISR);
692	AssertRCReturn(rc, rc);
693
694	/* Save queue states */
695	rc = SSMR3PutU32(pSSM, pState->nQueues);
696	AssertRCReturn(rc, rc);
697	for (unsigned i = 0; i < pState->nQueues; i++)
698	{
699	rc = SSMR3PutU16(pSSM, pState->Queues[i].VRing.uSize);
700	AssertRCReturn(rc, rc);
701	rc = SSMR3PutU32(pSSM, pState->Queues[i].uPageNumber);
702	AssertRCReturn(rc, rc);
703	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextAvailIndex);
704	AssertRCReturn(rc, rc);
705	rc = SSMR3PutU16(pSSM, pState->Queues[i].uNextUsedIndex);
706	AssertRCReturn(rc, rc);
707	}
708
709	return VINF_SUCCESS;
710	}
711
712	/**
713	* Loads a saved device state.
714	*
715	* @returns VBox status code.
716	* @param pDevIns The device instance.
717	* @param pSSM The handle to the saved state.
718	* @param uVersion The data unit version number.
719	* @param uPass The data pass.
720	*/
721	int vpciLoadExec(PVPCISTATE pState, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass, uint32_t nQueues)
722	{
723	int rc;
724
725	if (uPass == SSM_PASS_FINAL)
726	{
727	/* Restore state data */
728	rc = SSMR3GetU32(pSSM, &pState->uGuestFeatures);
729	AssertRCReturn(rc, rc);
730	rc = SSMR3GetU16(pSSM, &pState->uQueueSelector);
731	AssertRCReturn(rc, rc);
732	rc = SSMR3GetU8( pSSM, &pState->uStatus);
733	AssertRCReturn(rc, rc);
734	rc = SSMR3GetU8( pSSM, &pState->uISR);
735	AssertRCReturn(rc, rc);
736
737	/* Restore queues */
738	if (uVersion > VIRTIO_SAVEDSTATE_VERSION_3_1_BETA1)
739	{
740	rc = SSMR3GetU32(pSSM, &pState->nQueues);
741	AssertRCReturn(rc, rc);
742	}
743	else
744	pState->nQueues = nQueues;
745	for (unsigned i = 0; i < pState->nQueues; i++)
746	{
747	rc = SSMR3GetU16(pSSM, &pState->Queues[i].VRing.uSize);
748	AssertRCReturn(rc, rc);
749	rc = SSMR3GetU32(pSSM, &pState->Queues[i].uPageNumber);
750	AssertRCReturn(rc, rc);
751
752	if (pState->Queues[i].uPageNumber)
753	vqueueInit(&pState->Queues[i], pState->Queues[i].uPageNumber);
754
755	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextAvailIndex);
756	AssertRCReturn(rc, rc);
757	rc = SSMR3GetU16(pSSM, &pState->Queues[i].uNextUsedIndex);
758	AssertRCReturn(rc, rc);
759	}
760	}
761
762	vpciDumpState(pState, "vpciLoadExec");
763
764	return VINF_SUCCESS;
765	}
766
767	/**
768	* Set PCI configuration space registers.
769	*
770	* @param pci Reference to PCI device structure.
771	* @param uDeviceId VirtiO Device Id
772	* @param uClass Class of PCI device (network, etc)
773	* @thread EMT
774	*/
775	static DECLCALLBACK(void) vpciConfigure(PCIDEVICE& pci,
776	uint16_t uDeviceId,
777	uint16_t uClass)
778	{
779	/* Configure PCI Device, assume 32-bit mode ******************************/
780	PCIDevSetVendorId(&pci, DEVICE_PCI_VENDOR_ID);
781	PCIDevSetDeviceId(&pci, DEVICE_PCI_BASE_ID + uDeviceId);
782	vpciCfgSetU16(pci, VBOX_PCI_SUBSYSTEM_VENDOR_ID, DEVICE_PCI_SUBSYSTEM_VENDOR_ID);
783	vpciCfgSetU16(pci, VBOX_PCI_SUBSYSTEM_ID, DEVICE_PCI_SUBSYSTEM_BASE_ID + uDeviceId);
784
785	/* ABI version, must be equal 0 as of 2.6.30 kernel. */
786	vpciCfgSetU8( pci, VBOX_PCI_REVISION_ID, 0x00);
787	/* Ethernet adapter */
788	vpciCfgSetU8( pci, VBOX_PCI_CLASS_PROG, 0x00);
789	vpciCfgSetU16(pci, VBOX_PCI_CLASS_DEVICE, uClass);
790	/* Interrupt Pin: INTA# */
791	vpciCfgSetU8( pci, VBOX_PCI_INTERRUPT_PIN, 0x01);
792
793	#ifdef VBOX_WITH_MSI_DEVICES
794	PCIDevSetCapabilityList (&pci, 0x80);
795	PCIDevSetStatus (&pci, VBOX_PCI_STATUS_CAP_LIST);
796	#endif
797	}
798
799	/* WARNING! This function must never be used in multithreaded context! */
800	static const char vpciCounter(const char pszDevFmt,
801	const char *pszCounter)
802	{
803	static char g_szCounterName[80];
804
805	RTStrPrintf(g_szCounterName, sizeof(g_szCounterName),
806	"/Devices/%s/%s", pszDevFmt, pszCounter);
807
808	return g_szCounterName;
809	}
810
811	// TODO: header
812	int vpciConstruct(PPDMDEVINS pDevIns, VPCISTATE *pState,
813	int iInstance, const char *pcszNameFmt,
814	uint16_t uDeviceId, uint16_t uClass,
815	uint32_t nQueues)
816	{
817	/* Init handles and log related stuff. */
818	RTStrPrintf(pState->szInstance, sizeof(pState->szInstance),
819	pcszNameFmt, iInstance);
820
821	pState->pDevInsR3 = pDevIns;
822	pState->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
823	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
824	pState->led.u32Magic = PDMLED_MAGIC;
825
826	pState->ILeds.pfnQueryStatusLed = vpciQueryStatusLed;
827
828	/* Initialize critical section. */
829	int rc = PDMDevHlpCritSectInit(pDevIns, &pState->cs, RT_SRC_POS, "%s", pState->szInstance);
830	if (RT_FAILURE(rc))
831	return rc;
832
833	/* Set PCI config registers */
834	vpciConfigure(pState->pciDevice, uDeviceId, uClass);
835	/* Register PCI device */
836	rc = PDMDevHlpPCIRegister(pDevIns, &pState->pciDevice);
837	if (RT_FAILURE(rc))
838	return rc;
839
840	#ifdef VBOX_WITH_MSI_DEVICES
841	#if 0
842	{
843	PDMMSIREG aMsiReg;
844
845	RT_ZERO(aMsiReg);
846	aMsiReg.cMsixVectors = 1;
847	aMsiReg.iMsixCapOffset = 0x80;
848	aMsiReg.iMsixNextOffset = 0x0;
849	aMsiReg.iMsixBar = 0;
850	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
851	if (RT_FAILURE (rc))
852	PCIDevSetCapabilityList(&pState->pciDevice, 0x0);
853	}
854	#endif
855	#endif
856
857	/* Status driver */
858	PPDMIBASE pBase;
859	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pState->IBase, &pBase, "Status Port");
860	if (RT_FAILURE(rc))
861	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
862	pState->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
863
864	pState->nQueues = nQueues;
865
866	#if defined(VBOX_WITH_STATISTICS)
867	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in GC", vpciCounter(pcszNameFmt, "IO/ReadGC"), iInstance);
868	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in HC", vpciCounter(pcszNameFmt, "IO/ReadHC"), iInstance);
869	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in GC", vpciCounter(pcszNameFmt, "IO/WriteGC"), iInstance);
870	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in HC", vpciCounter(pcszNameFmt, "IO/WriteHC"), iInstance);
871	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", vpciCounter(pcszNameFmt, "Interrupts/Raised"), iInstance);
872	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsSkipped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of skipped interrupts", vpciCounter(pcszNameFmt, "Interrupts/Skipped"), iInstance);
873	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in GC", vpciCounter(pcszNameFmt, "Cs/CsGC"), iInstance);
874	PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatCsHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling CS wait in HC", vpciCounter(pcszNameFmt, "Cs/CsHC"), iInstance);
875	#endif /* VBOX_WITH_STATISTICS */
876
877	return rc;
878	}
879
880	/**
881	* Destruct PCI-related part of device.
882	*
883	* We need to free non-VM resources only.
884	*
885	* @returns VBox status code.
886	* @param pState The device state structure.
887	*/
888	int vpciDestruct(VPCISTATE* pState)
889	{
890	Log(("%s Destroying PCI instance\n", INSTANCE(pState)));
891
892	if (PDMCritSectIsInitialized(&pState->cs))
893	PDMR3CritSectDelete(&pState->cs);
894
895	return VINF_SUCCESS;
896	}
897
898	/**
899	* Device relocation callback.
900	*
901	* When this callback is called the device instance data, and if the
902	* device have a GC component, is being relocated, or/and the selectors
903	* have been changed. The device must use the chance to perform the
904	* necessary pointer relocations and data updates.
905	*
906	* Before the GC code is executed the first time, this function will be
907	* called with a 0 delta so GC pointer calculations can be one in one place.
908	*
909	* @param pDevIns Pointer to the device instance.
910	* @param offDelta The relocation delta relative to the old location.
911	*
912	* @remark A relocation CANNOT fail.
913	*/
914	void vpciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
915	{
916	VPCISTATE* pState = PDMINS_2_DATA(pDevIns, VPCISTATE*);
917	pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
918	// TBD
919	}
920
921	PVQUEUE vpciAddQueue(VPCISTATE* pState, unsigned uSize, PFNVPCIQUEUECALLBACK pfnCallback, const char *pcszName)
922	{
923	PVQUEUE pQueue = NULL;
924	/* Find an empty queue slot */
925	for (unsigned i = 0; i < pState->nQueues; i++)
926	{
927	if (pState->Queues[i].VRing.uSize == 0)
928	{
929	pQueue = &pState->Queues[i];
930	break;
931	}
932	}
933
934	if (!pQueue)
935	{
936	Log(("%s Too many queues being added, no empty slots available!\n", INSTANCE(pState)));
937	}
938	else
939	{
940	pQueue->VRing.uSize = uSize;
941	pQueue->VRing.addrDescriptors = 0;
942	pQueue->uPageNumber = 0;
943	pQueue->pfnCallback = pfnCallback;
944	pQueue->pcszName = pcszName;
945	}
946
947	return pQueue;
948	}
949
950	#endif /* IN_RING3 */
951
952	#endif /* VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/VirtIO/Virtio.cpp@ 58466

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