VirtualBox

source: vbox/trunk/src/VBox/Devices/USB/DevOHCI.cpp@ 60756

Last change on this file since 60756 was 59875, checked in by vboxsync, 9 years ago

VUSB: Move the thread for periodic frame procession down to the roothub. There we don't need to replicate the code to EHCI later and it has much better overview of the amount of active URBs to schedule when to process new frames
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 208.0 KB
Line 
1/* $Id: DevOHCI.cpp 59875 2016-02-29 15:53:00Z vboxsync $ */
2/** @file
3 * DevOHCI - Open Host Controller Interface for USB.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_dev_ohci OHCI - Open Host Controller Interface Emulation.
19 *
20 * This component implements an OHCI USB controller. It is split roughly in
21 * to two main parts, the first part implements the register level
22 * specification of USB OHCI and the second part maintains the root hub (which
23 * is an integrated component of the device).
24 *
25 * The OHCI registers are used for the usual stuff like enabling and disabling
26 * interrupts. Since the USB time is divided in to 1ms frames and various
27 * interrupts may need to be triggered at frame boundary time, a timer-based
28 * approach was taken. Whenever the bus is enabled ohci->eof_timer will be set.
29 *
30 * The actual USB transfers are stored in main memory (along with endpoint and
31 * transfer descriptors). The ED's for all the control and bulk endpoints are
32 * found by consulting the HcControlHeadED and HcBulkHeadED registers
33 * respectively. Interrupt ED's are different, they are found by looking
34 * in the HCCA (another communication area in main memory).
35 *
36 * At the start of every frame (in function ohci_sof) we traverse all enabled
37 * ED lists and queue up as many transfers as possible. No attention is paid
38 * to control/bulk service ratios or bandwidth requirements since our USB
39 * could conceivably contain a dozen high speed busses so this would
40 * artificially limit the performance.
41 *
42 * Once we have a transfer ready to go (in function ohciServiceTd) we
43 * allocate an URB on the stack, fill in all the relevant fields and submit
44 * it using the VUSBIRhSubmitUrb function. The roothub device and the virtual
45 * USB core code (vusb.c) coordinates everything else from this point onwards.
46 *
47 * When the URB has been successfully handed to the lower level driver, our
48 * prepare callback gets called and we can remove the TD from the ED transfer
49 * list. This stops us queueing it twice while it completes.
50 * bird: no, we don't remove it because that confuses the guest! (=> crashes)
51 *
52 * Completed URBs are reaped at the end of every frame (in function
53 * ohci_frame_boundary). Our completion routine makes use of the ED and TD
54 * fields in the URB to store the physical addresses of the descriptors so
55 * that they may be modified in the roothub callbacks. Our completion
56 * routine (ohciRhXferComplete) carries out a number of tasks:
57 * -# Retires the TD associated with the transfer, setting the
58 * relevant error code etc.
59 * -# Updates done-queue interrupt timer and potentially causes
60 * a writeback of the done-queue.
61 * -# If the transfer was device-to-host, we copy the data in to
62 * the host memory.
63 *
64 * As for error handling OHCI allows for 3 retries before failing a transfer,
65 * an error count is stored in each transfer descriptor. A halt flag is also
66 * stored in the transfer descriptor. That allows for ED's to be disabled
67 * without stopping the bus and de-queuing them.
68 *
69 * When the bus is started and stopped we call VUSBIDevPowerOn/Off() on our
70 * roothub to indicate it's powering up and powering down. Whenever we power
71 * down, the USB core makes sure to synchronously complete all outstanding
72 * requests so that the OHCI is never seen in an inconsistent state by the
73 * guest OS (Transfers are not meant to be unlinked until they've actually
74 * completed, but we can't do that unless we work synchronously, so we just
75 * have to fake it).
76 * bird: we do work synchronously now, anything causes guest crashes.
77 */
78
79
80/*********************************************************************************************************************************
81* Header Files *
82*********************************************************************************************************************************/
83#define LOG_GROUP LOG_GROUP_DEV_OHCI
84#include <VBox/pci.h>
85#include <VBox/vmm/pdm.h>
86#include <VBox/vmm/mm.h>
87#include <VBox/err.h>
88#include <VBox/log.h>
89#include <iprt/assert.h>
90#include <iprt/string.h>
91#include <iprt/asm.h>
92#include <iprt/asm-math.h>
93#include <iprt/semaphore.h>
94#include <iprt/critsect.h>
95#ifdef IN_RING3
96# include <iprt/alloca.h>
97# include <iprt/mem.h>
98# include <iprt/thread.h>
99# include <iprt/uuid.h>
100#endif
101#include <VBox/vusb.h>
102#include "VBoxDD.h"
103
104
105/*********************************************************************************************************************************
106* Structures and Typedefs *
107*********************************************************************************************************************************/
108/** The saved state version. */
109#define OHCI_SAVED_STATE_VERSION 5
110// The saved state with support of 8 ports
111#define OHCI_SAVED_STATE_VERSION_8PORTS 4
112/** The saved state version used in 3.0 and earlier.
113 *
114 * @remarks Because of the SSMR3MemPut/Get laziness we ended up with an
115 * accidental format change between 2.0 and 2.1 that didn't get its own
116 * version number. It is therefore not possible to restore states from
117 * 2.0 and earlier with 2.1 and later. */
118#define OHCI_SAVED_STATE_VERSION_MEM_HELL 3
119
120
121/** Maximum supported number of Downstream Ports on the root hub. 15 ports
122 * is the maximum defined by the OHCI spec.
123 * If you change this you need to add more status register words to the 'opreg'
124 * array.
125 */
126#define OHCI_NDP_MAX 15
127
128/** Default NDP, chosen to be compatible with everything. */
129#define OHCI_NDP_DEFAULT 12
130
131/* Macro to query the number of currently configured ports. */
132#define OHCI_NDP_CFG(pohci) ((pohci)->RootHub.desc_a & OHCI_RHA_NDP)
133
134/** Pointer to OHCI device data. */
135typedef struct OHCI *POHCI;
136/** Read-only pointer to the OHCI device data. */
137typedef struct OHCI const *PCOHCI;
138
139#ifndef VBOX_DEVICE_STRUCT_TESTCASE
140/**
141 * Host controller transfer descriptor data.
142 */
143typedef struct VUSBURBHCITDINT
144{
145 /** Type of TD. */
146 uint32_t TdType;
147 /** The address of the */
148 RTGCPHYS32 TdAddr;
149 /** A copy of the TD. */
150 uint32_t TdCopy[16];
151} VUSBURBHCITDINT;
152
153/**
154 * The host controller data associated with each URB.
155 */
156typedef struct VUSBURBHCIINT
157{
158 /** The endpoint descriptor address. */
159 RTGCPHYS32 EdAddr;
160 /** Number of Tds in the array. */
161 uint32_t cTds;
162 /** When this URB was created.
163 * (Used for isochronous frames and for logging.) */
164 uint32_t u32FrameNo;
165 /** Flag indicating that the TDs have been unlinked. */
166 bool fUnlinked;
167} VUSBURBHCIINT;
168#endif
169
170/**
171 * An OHCI root hub port.
172 */
173typedef struct OHCIHUBPORT
174{
175 /** The port register. */
176 uint32_t fReg;
177#if HC_ARCH_BITS == 64
178 uint32_t Alignment0; /**< Align the pointer correctly. */
179#endif
180 /** The device attached to the port. */
181 R3PTRTYPE(PVUSBIDEVICE) pDev;
182} OHCIHUBPORT;
183#if HC_ARCH_BITS == 64
184AssertCompile(sizeof(OHCIHUBPORT) == 16); /* saved state */
185#endif
186/** Pointer to an OHCI hub port. */
187typedef OHCIHUBPORT *POHCIHUBPORT;
188
189/**
190 * The OHCI root hub.
191 *
192 * @implements PDMIBASE
193 * @implements VUSBIROOTHUBPORT
194 * @implements PDMILEDPORTS
195 */
196typedef struct ohci_roothub
197{
198 /** Pointer to the base interface of the VUSB RootHub. */
199 R3PTRTYPE(PPDMIBASE) pIBase;
200 /** Pointer to the connector interface of the VUSB RootHub. */
201 R3PTRTYPE(PVUSBIROOTHUBCONNECTOR) pIRhConn;
202 /** Pointer to the device interface of the VUSB RootHub. */
203 R3PTRTYPE(PVUSBIDEVICE) pIDev;
204 /** The base interface exposed to the roothub driver. */
205 PDMIBASE IBase;
206 /** The roothub port interface exposed to the roothub driver. */
207 VUSBIROOTHUBPORT IRhPort;
208
209 /** The LED. */
210 PDMLED Led;
211 /** The LED ports. */
212 PDMILEDPORTS ILeds;
213 /** Partner of ILeds. */
214 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
215
216 uint32_t status;
217 uint32_t desc_a;
218 uint32_t desc_b;
219#if HC_ARCH_BITS == 64
220 uint32_t Alignment0; /**< Align aPorts on a 8 byte boundary. */
221#endif
222 OHCIHUBPORT aPorts[OHCI_NDP_MAX];
223 R3PTRTYPE(POHCI) pOhci;
224} OHCIROOTHUB;
225/** Pointer to the OHCI root hub. */
226typedef OHCIROOTHUB *POHCIROOTHUB;
227
228
229/**
230 * Data used for reattaching devices on a state load.
231 */
232typedef struct ohci_load {
233 /** Timer used once after state load to inform the guest about new devices.
234 * We do this to be sure the guest get any disconnect / reconnect on the
235 * same port. */
236 PTMTIMERR3 pTimer;
237 /** Number of detached devices. */
238 unsigned cDevs;
239 /** Array of devices which were detached. */
240 PVUSBIDEVICE apDevs[OHCI_NDP_MAX];
241} OHCILOAD;
242/** Pointer to an OHCILOAD structure. */
243typedef OHCILOAD *POHCILOAD;
244
245
246/**
247 * OHCI device data.
248 */
249typedef struct OHCI
250{
251 /** The PCI device. */
252 PCIDEVICE PciDev;
253
254 /** Pointer to the device instance - R3 ptr. */
255 PPDMDEVINSR3 pDevInsR3;
256 /** The End-Of-Frame timer - R3 Ptr. */
257 PTMTIMERR3 pEndOfFrameTimerR3;
258
259 /** Pointer to the device instance - R0 ptr */
260 PPDMDEVINSR0 pDevInsR0;
261 /** The End-Of-Frame timer - R0 Ptr. */
262 PTMTIMERR0 pEndOfFrameTimerR0;
263
264 /** Pointer to the device instance - RC ptr. */
265 PPDMDEVINSRC pDevInsRC;
266 /** The End-Of-Frame timer - RC Ptr. */
267 PTMTIMERRC pEndOfFrameTimerRC;
268
269 /** Start of current frame. */
270 uint64_t SofTime;
271 /* done queue interrupt counter */
272 uint32_t dqic : 3;
273 /** frame number overflow. */
274 uint32_t fno : 1;
275 /** Address of the MMIO region assigned by PCI. */
276 RTGCPHYS32 MMIOBase;
277
278 /* Root hub device */
279 OHCIROOTHUB RootHub;
280
281 /* OHCI registers */
282
283 /** @name Control partition
284 * @{ */
285 /** HcControl. */
286 uint32_t ctl;
287 /** HcCommandStatus. */
288 uint32_t status;
289 /** HcInterruptStatus. */
290 uint32_t intr_status;
291 /** HcInterruptEnabled. */
292 uint32_t intr;
293 /** @} */
294
295 /** @name Memory pointer partition
296 * @{ */
297 /** HcHCCA. */
298 uint32_t hcca;
299 /** HcPeriodCurrentEd. */
300 uint32_t per_cur;
301 /** HcControlCurrentED. */
302 uint32_t ctrl_cur;
303 /** HcControlHeadED. */
304 uint32_t ctrl_head;
305 /** HcBlockCurrendED. */
306 uint32_t bulk_cur;
307 /** HcBlockHeadED. */
308 uint32_t bulk_head;
309 /** HcDoneHead. */
310 uint32_t done;
311 /** @} */
312
313 /** @name Frame counter partition
314 * @{ */
315 /** HcFmInterval.FSMPS - FSLargestDataPacket */
316 uint32_t fsmps : 15;
317 /** HcFmInterval.FIT - FrameItervalToggle */
318 uint32_t fit : 1;
319 /** HcFmInterval.FI - FrameInterval */
320 uint32_t fi : 14;
321 /** HcFmRemaining.FRT - toggle bit. */
322 uint32_t frt : 1;
323 /** HcFmNumber.
324 * @remark The register size is 16-bit, but for debugging and performance
325 * reasons we maintain a 32-bit counter. */
326 uint32_t HcFmNumber;
327 /** HcPeriodicStart */
328 uint32_t pstart;
329 /** @} */
330
331 /** The number of virtual time ticks per frame. */
332 uint64_t cTicksPerFrame;
333 /** The number of virtual time ticks per USB bus tick. */
334 uint64_t cTicksPerUsbTick;
335
336 /** Number of in-flight TDs. */
337 unsigned cInFlight;
338 unsigned Alignment0; /**< Align aInFlight on a 8 byte boundary. */
339 /** Array of in-flight TDs. */
340 struct ohci_td_in_flight
341 {
342 /** Address of the transport descriptor. */
343 uint32_t GCPhysTD;
344 /** Flag indicating an inactive (not-linked) URB. */
345 bool fInactive;
346 /** Pointer to the URB. */
347 R3PTRTYPE(PVUSBURB) pUrb;
348 } aInFlight[257];
349
350#if HC_ARCH_BITS == 32
351 uint32_t Alignment1;
352#endif
353
354 /** Number of in-done-queue TDs. */
355 unsigned cInDoneQueue;
356 /** Array of in-done-queue TDs. */
357 struct ohci_td_in_done_queue
358 {
359 /** Address of the transport descriptor. */
360 uint32_t GCPhysTD;
361 } aInDoneQueue[64];
362 /** When the tail of the done queue was added.
363 * Used to calculate the age of the done queue. */
364 uint32_t u32FmDoneQueueTail;
365#if R3_ARCH_BITS == 32
366 /** Align pLoad, the stats and the struct size correctly. */
367 uint32_t Alignment2;
368#endif
369 /** Pointer to state load data. */
370 R3PTRTYPE(POHCILOAD) pLoad;
371
372 /** Detected canceled isochronous URBs. */
373 STAMCOUNTER StatCanceledIsocUrbs;
374 /** Detected canceled general URBs. */
375 STAMCOUNTER StatCanceledGenUrbs;
376 /** Dropped URBs (endpoint halted, or URB canceled). */
377 STAMCOUNTER StatDroppedUrbs;
378 /** Profiling ohciFrameBoundaryTimer. */
379 STAMPROFILE StatTimer;
380
381 /** This member and all the following are not part of saved state. */
382 uint64_t SavedStateEnd;
383
384 /** VM timer frequency used for frame timer calculations. */
385 uint64_t u64TimerHz;
386 /** Idle detection flag; must be cleared at start of frame */
387 bool fIdle;
388 /** A flag indicating that the bulk list may have in-flight URBs. */
389 bool fBulkNeedsCleaning;
390
391 /** Whether RC/R0 is enabled. */
392 bool fRZEnabled;
393
394 uint32_t Alignment3; /**< Align size on a 8 byte boundary. */
395
396 /** Critical section synchronising interrupt handling. */
397 PDMCRITSECT CsIrq;
398 /** Critical section to synchronize the framer and URB completion handler. */
399 RTCRITSECT CritSect;
400
401} OHCI;
402
403/* Standard OHCI bus speed */
404#define OHCI_DEFAULT_TIMER_FREQ 1000
405
406/* Host Controller Communications Area */
407#define OHCI_HCCA_NUM_INTR 32
408#define OHCI_HCCA_OFS (OHCI_HCCA_NUM_INTR * sizeof(uint32_t))
409struct ohci_hcca
410{
411 uint16_t frame;
412 uint16_t pad;
413 uint32_t done;
414};
415AssertCompileSize(ohci_hcca, 8);
416
417/** @name OHCI Endpoint Descriptor
418 * @{ */
419
420#define ED_PTR_MASK (~(uint32_t)0xf)
421#define ED_HWINFO_MPS 0x07ff0000
422#define ED_HWINFO_ISO RT_BIT(15)
423#define ED_HWINFO_SKIP RT_BIT(14)
424#define ED_HWINFO_LOWSPEED RT_BIT(13)
425#define ED_HWINFO_IN RT_BIT(12)
426#define ED_HWINFO_OUT RT_BIT(11)
427#define ED_HWINFO_DIR (RT_BIT(11) | RT_BIT(12))
428#define ED_HWINFO_ENDPOINT 0x780 /* 4 bits */
429#define ED_HWINFO_ENDPOINT_SHIFT 7
430#define ED_HWINFO_FUNCTION 0x7f /* 7 bits */
431#define ED_HEAD_CARRY RT_BIT(1)
432#define ED_HEAD_HALTED RT_BIT(0)
433
434/**
435 * OHCI Endpoint Descriptor.
436 */
437typedef struct OHCIED
438{
439 /** Flags and stuff. */
440 uint32_t hwinfo;
441 /** TailP - TD Queue Tail pointer. Bits 0-3 ignored / preserved. */
442 uint32_t TailP;
443 /** HeadP - TD Queue head pointer. Bit 0 - Halted, Bit 1 - toggleCarry. Bit 2&3 - 0. */
444 uint32_t HeadP;
445 /** NextED - Next Endpoint Descriptor. Bits 0-3 ignored / preserved. */
446 uint32_t NextED;
447} OHCIED, *POHCIED;
448typedef const OHCIED *PCOHCIED;
449AssertCompileSize(OHCIED, 16);
450
451/** @} */
452
453
454/** @name Completion Codes
455 * @{ */
456#define OHCI_CC_NO_ERROR (UINT32_C(0x00) << 28)
457#define OHCI_CC_CRC (UINT32_C(0x01) << 28)
458#define OHCI_CC_STALL (UINT32_C(0x04) << 28)
459#define OHCI_CC_DEVICE_NOT_RESPONDING (UINT32_C(0x05) << 28)
460#define OHCI_CC_DNR OHCI_CC_DEVICE_NOT_RESPONDING
461#define OHCI_CC_PID_CHECK_FAILURE (UINT32_C(0x06) << 28)
462#define OHCI_CC_UNEXPECTED_PID (UINT32_C(0x07) << 28)
463#define OHCI_CC_DATA_OVERRUN (UINT32_C(0x08) << 28)
464#define OHCI_CC_DATA_UNDERRUN (UINT32_C(0x09) << 28)
465/* 0x0a..0x0b - reserved */
466#define OHCI_CC_BUFFER_OVERRUN (UINT32_C(0x0c) << 28)
467#define OHCI_CC_BUFFER_UNDERRUN (UINT32_C(0x0d) << 28)
468#define OHCI_CC_NOT_ACCESSED_0 (UINT32_C(0x0e) << 28)
469#define OHCI_CC_NOT_ACCESSED_1 (UINT32_C(0x0f) << 28)
470/** @} */
471
472
473/** @name OHCI General transfer descriptor
474 * @{ */
475
476/** Error count (EC) shift. */
477#define TD_ERRORS_SHIFT 26
478/** Error count max. (One greater than what the EC field can hold.) */
479#define TD_ERRORS_MAX 4
480
481/** CC - Condition code mask. */
482#define TD_HWINFO_CC (UINT32_C(0xf0000000))
483#define TD_HWINFO_CC_SHIFT 28
484/** EC - Error count. */
485#define TD_HWINFO_ERRORS (RT_BIT(26) | RT_BIT(27))
486/** T - Data toggle. */
487#define TD_HWINFO_TOGGLE (RT_BIT(24) | RT_BIT(25))
488#define TD_HWINFO_TOGGLE_HI (RT_BIT(25))
489#define TD_HWINFO_TOGGLE_LO (RT_BIT(24))
490/** DI - Delay interrupt. */
491#define TD_HWINFO_DI (RT_BIT(21) | RT_BIT(22) | RT_BIT(23))
492#define TD_HWINFO_IN (RT_BIT(20))
493#define TD_HWINFO_OUT (RT_BIT(19))
494/** DP - Direction / PID. */
495#define TD_HWINFO_DIR (RT_BIT(19) | RT_BIT(20))
496/** R - Buffer rounding. */
497#define TD_HWINFO_ROUNDING (RT_BIT(18))
498/** Bits that are reserved / unknown. */
499#define TD_HWINFO_UNKNOWN_MASK (UINT32_C(0x0003ffff))
500
501/** SETUP - to endpoint. */
502#define OHCI_TD_DIR_SETUP 0x0
503/** OUT - to endpoint. */
504#define OHCI_TD_DIR_OUT 0x1
505/** IN - from endpoint. */
506#define OHCI_TD_DIR_IN 0x2
507/** Reserved. */
508#define OHCI_TD_DIR_RESERVED 0x3
509
510/**
511 * OHCI general transfer descriptor
512 */
513typedef struct OHCITD
514{
515 uint32_t hwinfo;
516 /** CBP - Current Buffer Pointer. (32-bit physical address) */
517 uint32_t cbp;
518 /** NextTD - Link to the next transfer descriptor. (32-bit physical address, dword aligned) */
519 uint32_t NextTD;
520 /** BE - Buffer End (inclusive). (32-bit physical address) */
521 uint32_t be;
522} OHCITD, *POHCITD;
523typedef const OHCITD *PCOHCITD;
524AssertCompileSize(OHCIED, 16);
525/** @} */
526
527
528/** @name OHCI isochronous transfer descriptor.
529 * @{ */
530/** SF - Start frame number. */
531#define ITD_HWINFO_SF 0xffff
532/** DI - Delay interrupt. (TD_HWINFO_DI) */
533#define ITD_HWINFO_DI (RT_BIT(21) | RT_BIT(22) | RT_BIT(23))
534#define ITD_HWINFO_DI_SHIFT 21
535/** FC - Frame count. */
536#define ITD_HWINFO_FC (RT_BIT(24) | RT_BIT(25) | RT_BIT(26))
537#define ITD_HWINFO_FC_SHIFT 24
538/** CC - Condition code mask. (=TD_HWINFO_CC) */
539#define ITD_HWINFO_CC UINT32_C(0xf0000000)
540#define ITD_HWINFO_CC_SHIFT 28
541/** The buffer page 0 mask (lower 12 bits are ignored). */
542#define ITD_BP0_MASK UINT32_C(0xfffff000)
543
544#define ITD_NUM_PSW 8
545/** OFFSET - offset of the package into the buffer page.
546 * (Only valid when CC set to Not Accessed.)
547 *
548 * Note that the top bit of the OFFSET field is overlapping with the
549 * first bit in the CC field. This is ok because both 0xf and 0xe are
550 * defined as "Not Accessed".
551 */
552#define ITD_PSW_OFFSET 0x1fff
553/** SIZE field mask for IN bound transfers.
554 * (Only valid when CC isn't Not Accessed.)*/
555#define ITD_PSW_SIZE 0x07ff
556/** CC field mask.
557 * USed to indicate the format of SIZE (Not Accessed -> OFFSET). */
558#define ITD_PSW_CC 0xf000
559#define ITD_PSW_CC_SHIFT 12
560
561/**
562 * OHCI isochronous transfer descriptor.
563 */
564typedef struct OHCIITD
565{
566 uint32_t HwInfo;
567 /** BP0 - Buffer Page 0. The lower 12 bits are ignored. */
568 uint32_t BP0;
569 /** NextTD - Link to the next transfer descriptor. (32-bit physical address, dword aligned) */
570 uint32_t NextTD;
571 /** BE - Buffer End (inclusive). (32-bit physical address) */
572 uint32_t BE;
573 /** (OffsetN/)PSWN - package status word array (0..7).
574 * The format varies depending on whether the package has been completed or not. */
575 uint16_t aPSW[ITD_NUM_PSW];
576} OHCIITD, *POHCIITD;
577typedef const OHCIITD *PCOHCIITD;
578AssertCompileSize(OHCIITD, 32);
579/** @} */
580
581/**
582 * OHCI register operator.
583 */
584typedef struct ohci_opreg
585{
586 const char *pszName;
587 int (*pfnRead )(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value);
588 int (*pfnWrite)(POHCI pThis, uint32_t iReg, uint32_t u32Value);
589} OHCIOPREG;
590
591
592/* OHCI Local stuff */
593#define OHCI_CTL_CBSR ((1<<0)|(1<<1))
594#define OHCI_CTL_PLE (1<<2)
595#define OHCI_CTL_IE (1<<3)
596#define OHCI_CTL_CLE (1<<4)
597#define OHCI_CTL_BLE (1<<5)
598#define OHCI_CTL_HCFS ((1<<6)|(1<<7))
599#define OHCI_USB_RESET 0x00
600#define OHCI_USB_RESUME 0x40
601#define OHCI_USB_OPERATIONAL 0x80
602#define OHCI_USB_SUSPEND 0xc0
603#define OHCI_CTL_IR (1<<8)
604#define OHCI_CTL_RWC (1<<9)
605#define OHCI_CTL_RWE (1<<10)
606
607#define OHCI_STATUS_HCR (1<<0)
608#define OHCI_STATUS_CLF (1<<1)
609#define OHCI_STATUS_BLF (1<<2)
610#define OHCI_STATUS_OCR (1<<3)
611#define OHCI_STATUS_SOC ((1<<6)|(1<<7))
612
613/** @name Interrupt Status and Enabled/Disabled Flags
614 * @{ */
615/** SO - Scheduling overrun. */
616#define OHCI_INTR_SCHEDULEING_OVERRUN RT_BIT(0)
617/** WDH - HcDoneHead writeback. */
618#define OHCI_INTR_WRITE_DONE_HEAD RT_BIT(1)
619/** SF - Start of frame. */
620#define OHCI_INTR_START_OF_FRAME RT_BIT(2)
621/** RD - Resume detect. */
622#define OHCI_INTR_RESUME_DETECT RT_BIT(3)
623/** UE - Unrecoverable error. */
624#define OHCI_INTR_UNRECOVERABLE_ERROR RT_BIT(4)
625/** FNO - Frame number overflow. */
626#define OHCI_INTR_FRAMENUMBER_OVERFLOW RT_BIT(5)
627/** RHSC- Root hub status change. */
628#define OHCI_INTR_ROOT_HUB_STATUS_CHANGE RT_BIT(6)
629/** OC - Ownership change. */
630#define OHCI_INTR_OWNERSHIP_CHANGE RT_BIT(30)
631/** MIE - Master interrupt enable. */
632#define OHCI_INTR_MASTER_INTERRUPT_ENABLED RT_BIT(31)
633/** @} */
634
635#define OHCI_HCCA_SIZE 0x100
636#define OHCI_HCCA_MASK UINT32_C(0xffffff00)
637
638#define OHCI_FMI_FI UINT32_C(0x00003fff)
639#define OHCI_FMI_FSMPS UINT32_C(0x7fff0000)
640#define OHCI_FMI_FSMPS_SHIFT 16
641#define OHCI_FMI_FIT UINT32_C(0x80000000)
642#define OHCI_FMI_FIT_SHIFT 31
643
644#define OHCI_FR_RT RT_BIT_32(31)
645
646#define OHCI_LS_THRESH 0x628
647
648#define OHCI_RHA_NDP (0xff)
649#define OHCI_RHA_PSM RT_BIT_32(8)
650#define OHCI_RHA_NPS RT_BIT_32(9)
651#define OHCI_RHA_DT RT_BIT_32(10)
652#define OHCI_RHA_OCPM RT_BIT_32(11)
653#define OHCI_RHA_NOCP RT_BIT_32(12)
654#define OHCI_RHA_POTPGP UINT32_C(0xff000000)
655
656#define OHCI_RHS_LPS RT_BIT_32(0)
657#define OHCI_RHS_OCI RT_BIT_32(1)
658#define OHCI_RHS_DRWE RT_BIT_32(15)
659#define OHCI_RHS_LPSC RT_BIT_32(16)
660#define OHCI_RHS_OCIC RT_BIT_32(17)
661#define OHCI_RHS_CRWE RT_BIT_32(31)
662
663/** @name HcRhPortStatus[n] - RH Port Status register (read).
664 * @{ */
665/** CCS - CurrentConnectionStatus - 0 = no device, 1 = device. */
666#define OHCI_PORT_CCS RT_BIT(0)
667/** PES - PortEnableStatus. */
668#define OHCI_PORT_PES RT_BIT(1)
669/** PSS - PortSuspendStatus */
670#define OHCI_PORT_PSS RT_BIT(2)
671/** POCI- PortOverCurrentIndicator. */
672#define OHCI_PORT_POCI RT_BIT(3)
673/** PRS - PortResetStatus */
674#define OHCI_PORT_PRS RT_BIT(4)
675/** PPS - PortPowerStatus */
676#define OHCI_PORT_PPS RT_BIT(8)
677/** LSDA - LowSpeedDeviceAttached */
678#define OHCI_PORT_LSDA RT_BIT(9)
679/** CSC - ConnectStatusChange */
680#define OHCI_PORT_CSC RT_BIT(16)
681/** PESC - PortEnableStatusChange */
682#define OHCI_PORT_PESC RT_BIT(17)
683/** PSSC - PortSuspendStatusChange */
684#define OHCI_PORT_PSSC RT_BIT(18)
685/** OCIC - OverCurrentIndicatorChange */
686#define OHCI_PORT_OCIC RT_BIT(19)
687/** PRSC - PortResetStatusChange */
688#define OHCI_PORT_PRSC RT_BIT(20)
689/** @} */
690
691
692/** @name HcRhPortStatus[n] - Root Hub Port Status Registers - read.
693 * @{ */
694/** CCS - CurrentConnectStatus - 0 = no device, 1 = device. */
695#define OHCI_PORT_R_CURRENT_CONNECT_STATUS RT_BIT(0)
696/** PES - PortEnableStatus. */
697#define OHCI_PORT_R_ENABLE_STATUS RT_BIT(1)
698/** PSS - PortSuspendStatus */
699#define OHCI_PORT_R_SUSPEND_STATUS RT_BIT(2)
700/** POCI- PortOverCurrentIndicator. */
701#define OHCI_PORT_R_OVER_CURRENT_INDICATOR RT_BIT(3)
702/** PRS - PortResetStatus */
703#define OHCI_PORT_R_RESET_STATUS RT_BIT(4)
704/** PPS - PortPowerStatus */
705#define OHCI_PORT_R_POWER_STATUS RT_BIT(8)
706/** LSDA - LowSpeedDeviceAttached */
707#define OHCI_PORT_R_LOW_SPEED_DEVICE_ATTACHED RT_BIT(9)
708/** CSC - ConnectStatusChange */
709#define OHCI_PORT_R_CONNECT_STATUS_CHANGE RT_BIT(16)
710/** PESC - PortEnableStatusChange */
711#define OHCI_PORT_R_ENABLE_STATUS_CHANGE RT_BIT(17)
712/** PSSC - PortSuspendStatusChange */
713#define OHCI_PORT_R_SUSPEND_STATUS_CHANGE RT_BIT(18)
714/** OCIC - OverCurrentIndicatorChange */
715#define OHCI_PORT_R_OVER_CURRENT_INDICATOR_CHANGE RT_BIT(19)
716/** PRSC - PortResetStatusChange */
717#define OHCI_PORT_R_RESET_STATUS_CHANGE RT_BIT(20)
718/** @} */
719
720/** @name HcRhPortStatus[n] - Root Hub Port Status Registers - write.
721 * @{ */
722/** CCS - ClearPortEnable. */
723#define OHCI_PORT_W_CLEAR_ENABLE RT_BIT(0)
724/** PES - SetPortEnable. */
725#define OHCI_PORT_W_SET_ENABLE RT_BIT(1)
726/** PSS - SetPortSuspend */
727#define OHCI_PORT_W_SET_SUSPEND RT_BIT(2)
728/** POCI- ClearSuspendStatus. */
729#define OHCI_PORT_W_CLEAR_SUSPEND_STATUS RT_BIT(3)
730/** PRS - SetPortReset */
731#define OHCI_PORT_W_SET_RESET RT_BIT(4)
732/** PPS - SetPortPower */
733#define OHCI_PORT_W_SET_POWER RT_BIT(8)
734/** LSDA - ClearPortPower */
735#define OHCI_PORT_W_CLEAR_POWER RT_BIT(9)
736/** CSC - ClearConnectStatusChange */
737#define OHCI_PORT_W_CLEAR_CSC RT_BIT(16)
738/** PESC - PortEnableStatusChange */
739#define OHCI_PORT_W_CLEAR_PESC RT_BIT(17)
740/** PSSC - PortSuspendStatusChange */
741#define OHCI_PORT_W_CLEAR_PSSC RT_BIT(18)
742/** OCIC - OverCurrentIndicatorChange */
743#define OHCI_PORT_W_CLEAR_OCIC RT_BIT(19)
744/** PRSC - PortResetStatusChange */
745#define OHCI_PORT_W_CLEAR_PRSC RT_BIT(20)
746/** The mask of bit which are used to clear themselves. */
747#define OHCI_PORT_W_CLEAR_CHANGE_MASK ( OHCI_PORT_W_CLEAR_CSC | OHCI_PORT_W_CLEAR_PESC | OHCI_PORT_W_CLEAR_PSSC \
748 | OHCI_PORT_W_CLEAR_OCIC | OHCI_PORT_W_CLEAR_PRSC)
749/** @} */
750
751
752#ifndef VBOX_DEVICE_STRUCT_TESTCASE
753
754
755/*********************************************************************************************************************************
756* Global Variables *
757*********************************************************************************************************************************/
758#if defined(LOG_ENABLED) && defined(IN_RING3)
759static bool g_fLogBulkEPs = false;
760static bool g_fLogControlEPs = false;
761static bool g_fLogInterruptEPs = false;
762#endif
763#ifdef IN_RING3
764/**
765 * SSM descriptor table for the OHCI structure.
766 */
767static SSMFIELD const g_aOhciFields[] =
768{
769 SSMFIELD_ENTRY( OHCI, SofTime),
770 SSMFIELD_ENTRY_CUSTOM( dpic+fno, RT_OFFSETOF(OHCI, SofTime) + RT_SIZEOFMEMB(OHCI, SofTime), 4),
771 SSMFIELD_ENTRY( OHCI, RootHub.status),
772 SSMFIELD_ENTRY( OHCI, RootHub.desc_a),
773 SSMFIELD_ENTRY( OHCI, RootHub.desc_b),
774 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[0].fReg),
775 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[1].fReg),
776 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[2].fReg),
777 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[3].fReg),
778 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[4].fReg),
779 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[5].fReg),
780 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[6].fReg),
781 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[7].fReg),
782 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[8].fReg),
783 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[9].fReg),
784 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[10].fReg),
785 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[11].fReg),
786 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[12].fReg),
787 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[13].fReg),
788 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[14].fReg),
789 SSMFIELD_ENTRY( OHCI, ctl),
790 SSMFIELD_ENTRY( OHCI, status),
791 SSMFIELD_ENTRY( OHCI, intr_status),
792 SSMFIELD_ENTRY( OHCI, intr),
793 SSMFIELD_ENTRY( OHCI, hcca),
794 SSMFIELD_ENTRY( OHCI, per_cur),
795 SSMFIELD_ENTRY( OHCI, ctrl_cur),
796 SSMFIELD_ENTRY( OHCI, ctrl_head),
797 SSMFIELD_ENTRY( OHCI, bulk_cur),
798 SSMFIELD_ENTRY( OHCI, bulk_head),
799 SSMFIELD_ENTRY( OHCI, done),
800 SSMFIELD_ENTRY_CUSTOM( fsmps+fit+fi+frt, RT_OFFSETOF(OHCI, done) + RT_SIZEOFMEMB(OHCI, done), 4),
801 SSMFIELD_ENTRY( OHCI, HcFmNumber),
802 SSMFIELD_ENTRY( OHCI, pstart),
803 SSMFIELD_ENTRY_TERM()
804};
805#endif
806
807
808/*********************************************************************************************************************************
809* Internal Functions *
810*********************************************************************************************************************************/
811RT_C_DECLS_BEGIN
812#ifdef IN_RING3
813/* Update host controller state to reflect a device attach */
814static void rhport_power(POHCIROOTHUB pRh, unsigned iPort, bool fPowerUp);
815static void ohciBusResume(POHCI ohci, bool fHardware);
816static void ohciBusStop(POHCI pThis);
817
818static DECLCALLBACK(void) ohciRhXferCompletion(PVUSBIROOTHUBPORT pInterface, PVUSBURB pUrb);
819static DECLCALLBACK(bool) ohciRhXferError(PVUSBIROOTHUBPORT pInterface, PVUSBURB pUrb);
820
821static int ohci_in_flight_find(POHCI pThis, uint32_t GCPhysTD);
822# if defined(VBOX_STRICT) || defined(LOG_ENABLED)
823static int ohci_in_done_queue_find(POHCI pThis, uint32_t GCPhysTD);
824# endif
825static DECLCALLBACK(void) ohciR3LoadReattachDevices(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser);
826#endif /* IN_RING3 */
827RT_C_DECLS_END
828
829
830/**
831 * Update PCI IRQ levels
832 */
833static void ohciUpdateInterruptLocked(POHCI ohci, const char *msg)
834{
835 int level = 0;
836
837 if ( (ohci->intr & OHCI_INTR_MASTER_INTERRUPT_ENABLED)
838 && (ohci->intr_status & ohci->intr)
839 && !(ohci->ctl & OHCI_CTL_IR))
840 level = 1;
841
842 PDMDevHlpPCISetIrq(ohci->CTX_SUFF(pDevIns), 0, level);
843 if (level)
844 {
845 uint32_t val = ohci->intr_status & ohci->intr;
846 Log2(("ohci: Fired off interrupt %#010x - SO=%d WDH=%d SF=%d RD=%d UE=%d FNO=%d RHSC=%d OC=%d - %s\n",
847 val, val & 1, (val >> 1) & 1, (val >> 2) & 1, (val >> 3) & 1, (val >> 4) & 1, (val >> 5) & 1,
848 (val >> 6) & 1, (val >> 30) & 1, msg)); NOREF(val); NOREF(msg);
849 }
850}
851
852/**
853 * Set an interrupt, use the wrapper ohciSetInterrupt.
854 */
855DECLINLINE(int) ohciSetInterruptInt(POHCI ohci, int rcBusy, uint32_t intr, const char *msg)
856{
857 int rc = PDMCritSectEnter(&ohci->CsIrq, rcBusy);
858 if (rc != VINF_SUCCESS)
859 return rc;
860
861 if ( (ohci->intr_status & intr) != intr )
862 {
863 ohci->intr_status |= intr;
864 ohciUpdateInterruptLocked(ohci, msg);
865 }
866
867 PDMCritSectLeave(&ohci->CsIrq);
868 return rc;
869}
870
871/**
872 * Set an interrupt wrapper macro for logging purposes.
873 */
874#define ohciSetInterrupt(ohci, a_rcBusy, intr) ohciSetInterruptInt(ohci, a_rcBusy, intr, #intr)
875#define ohciR3SetInterrupt(ohci, intr) ohciSetInterruptInt(ohci, VERR_IGNORED, intr, #intr)
876
877#ifdef IN_RING3
878
879/* Carry out a hardware remote wakeup */
880static void ohci_remote_wakeup(POHCI pThis)
881{
882 if ((pThis->ctl & OHCI_CTL_HCFS) != OHCI_USB_SUSPEND)
883 return;
884 if (!(pThis->RootHub.status & OHCI_RHS_DRWE))
885 return;
886 ohciBusResume(pThis, true /* hardware */);
887}
888
889
890/**
891 * Query interface method for the roothub LUN.
892 */
893static DECLCALLBACK(void *) ohciRhQueryInterface(PPDMIBASE pInterface, const char *pszIID)
894{
895 POHCI pThis = RT_FROM_MEMBER(pInterface, OHCI, RootHub.IBase);
896 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->RootHub.IBase);
897 PDMIBASE_RETURN_INTERFACE(pszIID, VUSBIROOTHUBPORT, &pThis->RootHub.IRhPort);
898 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->RootHub.ILeds);
899 return NULL;
900}
901
902/**
903 * Gets the pointer to the status LED of a unit.
904 *
905 * @returns VBox status code.
906 * @param pInterface Pointer to the interface structure containing the called function pointer.
907 * @param iLUN The unit which status LED we desire.
908 * @param ppLed Where to store the LED pointer.
909 */
910static DECLCALLBACK(int) ohciRhQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
911{
912 POHCI pThis = (POHCI)((uintptr_t)pInterface - RT_OFFSETOF(OHCI, RootHub.ILeds));
913 if (iLUN == 0)
914 {
915 *ppLed = &pThis->RootHub.Led;
916 return VINF_SUCCESS;
917 }
918 return VERR_PDM_LUN_NOT_FOUND;
919}
920
921
922/** Converts a OHCI.roothub.IRhPort pointer to a POHCI. */
923#define VUSBIROOTHUBPORT_2_OHCI(pInterface) ((POHCI)( (uintptr_t)(pInterface) - RT_OFFSETOF(OHCI, RootHub.IRhPort) ))
924
925
926/**
927 * Get the number of available ports in the hub.
928 *
929 * @returns The number of ports available.
930 * @param pInterface Pointer to this structure.
931 * @param pAvailable Bitmap indicating the available ports. Set bit == available port.
932 */
933static DECLCALLBACK(unsigned) ohciRhGetAvailablePorts(PVUSBIROOTHUBPORT pInterface, PVUSBPORTBITMAP pAvailable)
934{
935 POHCI pThis = VUSBIROOTHUBPORT_2_OHCI(pInterface);
936 unsigned iPort;
937 unsigned cPorts = 0;
938
939 memset(pAvailable, 0, sizeof(*pAvailable));
940
941 PDMCritSectEnter(pThis->pDevInsR3->pCritSectRoR3, VERR_IGNORED);
942 for (iPort = 0; iPort < OHCI_NDP_CFG(pThis); iPort++)
943 {
944 if (!pThis->RootHub.aPorts[iPort].pDev)
945 {
946 cPorts++;
947 ASMBitSet(pAvailable, iPort + 1);
948 }
949 }
950 PDMCritSectLeave(pThis->pDevInsR3->pCritSectRoR3);
951
952 return cPorts;
953}
954
955
956/**
957 * Gets the supported USB versions.
958 *
959 * @returns The mask of supported USB versions.
960 * @param pInterface Pointer to this structure.
961 */
962static DECLCALLBACK(uint32_t) ohciRhGetUSBVersions(PVUSBIROOTHUBPORT pInterface)
963{
964 return VUSB_STDVER_11;
965}
966
967
968/**
969 * A device is being attached to a port in the roothub.
970 *
971 * @param pInterface Pointer to this structure.
972 * @param pDev Pointer to the device being attached.
973 * @param uPort The port number assigned to the device.
974 */
975static DECLCALLBACK(int) ohciRhAttach(PVUSBIROOTHUBPORT pInterface, PVUSBIDEVICE pDev, unsigned uPort)
976{
977 POHCI pThis = VUSBIROOTHUBPORT_2_OHCI(pInterface);
978 LogFlow(("ohciRhAttach: pDev=%p uPort=%u\n", pDev, uPort));
979 PDMCritSectEnter(pThis->pDevInsR3->pCritSectRoR3, VERR_IGNORED);
980
981 /*
982 * Validate and adjust input.
983 */
984 Assert(uPort >= 1 && uPort <= OHCI_NDP_CFG(pThis));
985 uPort--;
986 Assert(!pThis->RootHub.aPorts[uPort].pDev);
987 /* Only LS/FS devices can end up here. */
988 Assert(pDev->pfnGetSpeed(pDev) == VUSB_SPEED_LOW || pDev->pfnGetSpeed(pDev) == VUSB_SPEED_FULL);
989
990 /*
991 * Attach it.
992 */
993 pThis->RootHub.aPorts[uPort].fReg = OHCI_PORT_R_CURRENT_CONNECT_STATUS | OHCI_PORT_R_CONNECT_STATUS_CHANGE;
994 pThis->RootHub.aPorts[uPort].pDev = pDev;
995 rhport_power(&pThis->RootHub, uPort, 1 /* power on */);
996
997 ohci_remote_wakeup(pThis);
998 ohciR3SetInterrupt(pThis, OHCI_INTR_ROOT_HUB_STATUS_CHANGE);
999
1000 PDMCritSectLeave(pThis->pDevInsR3->pCritSectRoR3);
1001 return VINF_SUCCESS;
1002}
1003
1004
1005/**
1006 * A device is being detached from a port in the roothub.
1007 *
1008 * @param pInterface Pointer to this structure.
1009 * @param pDev Pointer to the device being detached.
1010 * @param uPort The port number assigned to the device.
1011 */
1012static DECLCALLBACK(void) ohciRhDetach(PVUSBIROOTHUBPORT pInterface, PVUSBIDEVICE pDev, unsigned uPort)
1013{
1014 POHCI pThis = VUSBIROOTHUBPORT_2_OHCI(pInterface);
1015 LogFlow(("ohciRhDetach: pDev=%p uPort=%u\n", pDev, uPort));
1016 PDMCritSectEnter(pThis->pDevInsR3->pCritSectRoR3, VERR_IGNORED);
1017
1018 /*
1019 * Validate and adjust input.
1020 */
1021 Assert(uPort >= 1 && uPort <= OHCI_NDP_CFG(pThis));
1022 uPort--;
1023 Assert(pThis->RootHub.aPorts[uPort].pDev == pDev);
1024
1025 /*
1026 * Detach it.
1027 */
1028 pThis->RootHub.aPorts[uPort].pDev = NULL;
1029 if (pThis->RootHub.aPorts[uPort].fReg & OHCI_PORT_PES)
1030 pThis->RootHub.aPorts[uPort].fReg = OHCI_PORT_R_CONNECT_STATUS_CHANGE | OHCI_PORT_PESC;
1031 else
1032 pThis->RootHub.aPorts[uPort].fReg = OHCI_PORT_R_CONNECT_STATUS_CHANGE;
1033
1034 ohci_remote_wakeup(pThis);
1035 ohciR3SetInterrupt(pThis, OHCI_INTR_ROOT_HUB_STATUS_CHANGE);
1036
1037 PDMCritSectLeave(pThis->pDevInsR3->pCritSectRoR3);
1038}
1039
1040
1041#ifdef IN_RING3
1042/**
1043 * One of the roothub devices has completed its reset operation.
1044 *
1045 * Currently, we don't think anything is required to be done here
1046 * so it's just a stub for forcing async resetting of the devices
1047 * during a root hub reset.
1048 *
1049 * @param pDev The root hub device.
1050 * @param rc The result of the operation.
1051 * @param pvUser Pointer to the controller.
1052 */
1053static DECLCALLBACK(void) ohciRhResetDoneOneDev(PVUSBIDEVICE pDev, int rc, void *pvUser)
1054{
1055 LogRel(("OHCI: root hub reset completed with %Rrc\n", rc));
1056 NOREF(pDev); NOREF(rc); NOREF(pvUser);
1057}
1058#endif
1059
1060
1061/**
1062 * Reset the root hub.
1063 *
1064 * @returns VBox status code.
1065 * @param pInterface Pointer to this structure.
1066 * @param fResetOnLinux This is used to indicate whether we're at VM reset time and
1067 * can do real resets or if we're at any other time where that
1068 * isn't such a good idea.
1069 * @remark Do NOT call VUSBIDevReset on the root hub in an async fashion!
1070 * @thread EMT
1071 */
1072static DECLCALLBACK(int) ohciRhReset(PVUSBIROOTHUBPORT pInterface, bool fResetOnLinux)
1073{
1074 POHCI pThis = VUSBIROOTHUBPORT_2_OHCI(pInterface);
1075 PDMCritSectEnter(pThis->pDevInsR3->pCritSectRoR3, VERR_IGNORED);
1076
1077 pThis->RootHub.status = 0;
1078 pThis->RootHub.desc_a = OHCI_RHA_NPS | OHCI_NDP_CFG(pThis); /* Preserve NDP value. */
1079 pThis->RootHub.desc_b = 0x0; /* Impl. specific */
1080
1081 /*
1082 * We're pending to _reattach_ the device without resetting them.
1083 * Except, during VM reset where we use the opportunity to do a proper
1084 * reset before the guest comes along and expect things.
1085 *
1086 * However, it's very very likely that we're not doing the right thing
1087 * here if coming from the guest (USB Reset state). The docs talks about
1088 * root hub resetting, however what exact behaviour in terms of root hub
1089 * status and changed bits, and HC interrupts aren't stated clearly. IF we
1090 * get trouble and see the guest doing "USB Resets" we will have to look
1091 * into this. For the time being we stick with simple.
1092 */
1093 for (unsigned iPort = 0; iPort < OHCI_NDP_CFG(pThis); iPort++)
1094 {
1095 if (pThis->RootHub.aPorts[iPort].pDev)
1096 {
1097 pThis->RootHub.aPorts[iPort].fReg = OHCI_PORT_R_CURRENT_CONNECT_STATUS | OHCI_PORT_R_CONNECT_STATUS_CHANGE;
1098 if (fResetOnLinux)
1099 {
1100 PVM pVM = PDMDevHlpGetVM(pThis->CTX_SUFF(pDevIns));
1101 VUSBIDevReset(pThis->RootHub.aPorts[iPort].pDev, fResetOnLinux, ohciRhResetDoneOneDev, pThis, pVM);
1102 }
1103 }
1104 else
1105 pThis->RootHub.aPorts[iPort].fReg = 0;
1106 }
1107
1108 PDMCritSectLeave(pThis->pDevInsR3->pCritSectRoR3);
1109 return VINF_SUCCESS;
1110}
1111
1112
1113/**
1114 * Does a software or hardware reset of the controller.
1115 *
1116 * This is called in response to setting HcCommandStatus.HCR, hardware reset,
1117 * and device construction.
1118 *
1119 * @param pThis The ohci instance data.
1120 * @param fNewMode The new mode of operation. This is UsbSuspend if it's a
1121 * software reset, and UsbReset if it's a hardware reset / cold boot.
1122 * @param fResetOnLinux Set if we can do a real reset of the devices attached to the root hub.
1123 * This is really a just a hack for the non-working linux device reset.
1124 * Linux has this feature called 'logical disconnect' if device reset fails
1125 * which prevents us from doing resets when the guest asks for it - the guest
1126 * will get confused when the device seems to be reconnected everytime it tries
1127 * to reset it. But if we're at hardware reset time, we can allow a device to
1128 * be 'reconnected' without upsetting the guest.
1129 *
1130 * @remark This hasn't got anything to do with software setting the mode to UsbReset.
1131 */
1132static void ohciDoReset(POHCI pThis, uint32_t fNewMode, bool fResetOnLinux)
1133{
1134 Log(("ohci: %s reset%s\n", fNewMode == OHCI_USB_RESET ? "hardware" : "software",
1135 fResetOnLinux ? " (reset on linux)" : ""));
1136
1137 /* Stop the bus in any case, disabling walking the lists. */
1138 ohciBusStop(pThis);
1139
1140 /*
1141 * Cancel all outstanding URBs.
1142 *
1143 * We can't, and won't, deal with URBs until we're moved out of the
1144 * suspend/reset state. Also, a real HC isn't going to send anything
1145 * any more when a reset has been signaled.
1146 */
1147 pThis->RootHub.pIRhConn->pfnCancelAllUrbs(pThis->RootHub.pIRhConn);
1148
1149 /*
1150 * Reset the hardware registers.
1151 */
1152 if (fNewMode == OHCI_USB_RESET)
1153 pThis->ctl |= OHCI_CTL_RWC; /* We're the firmware, set RemoteWakeupConnected. */
1154 else
1155 pThis->ctl &= OHCI_CTL_IR | OHCI_CTL_RWC; /* IR and RWC are preserved on software reset. */
1156
1157 /* Clear the HCFS bits first to make setting the new state work. */
1158 pThis->ctl &= ~OHCI_CTL_HCFS;
1159 pThis->ctl |= fNewMode;
1160 pThis->status = 0;
1161 pThis->intr_status = 0;
1162 pThis->intr = OHCI_INTR_MASTER_INTERRUPT_ENABLED; /* (We follow the text and the not reset value column,) */
1163
1164 pThis->hcca = 0;
1165 pThis->per_cur = 0;
1166 pThis->ctrl_head = pThis->ctrl_cur = 0;
1167 pThis->bulk_head = pThis->bulk_cur = 0;
1168 pThis->done = 0;
1169
1170 pThis->fsmps = 0x2778; /* To-Be-Defined, use the value linux sets...*/
1171 pThis->fit = 0;
1172 pThis->fi = 11999; /* (12MHz ticks, one frame is 1ms) */
1173 pThis->frt = 0;
1174 pThis->HcFmNumber = 0;
1175 pThis->pstart = 0;
1176
1177 pThis->dqic = 0x7;
1178 pThis->fno = 0;
1179
1180 /*
1181 * If this is a hardware reset, we will initialize the root hub too.
1182 * Software resets doesn't do this according to the specs.
1183 * (It's not possible to have device connected at the time of the
1184 * device construction, so nothing to worry about there.)
1185 */
1186 if (fNewMode == OHCI_USB_RESET)
1187 VUSBIDevReset(pThis->RootHub.pIDev, fResetOnLinux, NULL, NULL, NULL);
1188}
1189#endif /* IN_RING3 */
1190
1191/**
1192 * Reads physical memory.
1193 */
1194DECLINLINE(void) ohciPhysRead(POHCI pThis, uint32_t Addr, void *pvBuf, size_t cbBuf)
1195{
1196 if (cbBuf)
1197 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), Addr, pvBuf, cbBuf);
1198}
1199
1200/**
1201 * Writes physical memory.
1202 */
1203DECLINLINE(void) ohciPhysWrite(POHCI pThis, uint32_t Addr, const void *pvBuf, size_t cbBuf)
1204{
1205 if (cbBuf)
1206 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), Addr, pvBuf, cbBuf);
1207}
1208
1209/**
1210 * Read an array of dwords from physical memory and correct endianness.
1211 */
1212DECLINLINE(void) ohciGetDWords(POHCI pThis, uint32_t Addr, uint32_t *pau32s, int c32s)
1213{
1214 ohciPhysRead(pThis, Addr, pau32s, c32s * sizeof(uint32_t));
1215#if BYTE_ORDER != LITTLE_ENDIAN
1216 for(int i = 0; i < c32s; i++)
1217 pau32s[i] = RT_H2LE_U32(pau32s[i]);
1218#endif
1219}
1220
1221/**
1222 * Write an array of dwords from physical memory and correct endianness.
1223 */
1224DECLINLINE(void) ohciPutDWords(POHCI pThis, uint32_t Addr, const uint32_t *pau32s, int cu32s)
1225{
1226#if BYTE_ORDER == LITTLE_ENDIAN
1227 ohciPhysWrite(pThis, Addr, pau32s, cu32s << 2);
1228#else
1229 for (int i = 0; i < c32s; i++, pau32s++, Addr += sizeof(*pau32s))
1230 {
1231 uint32_t u32Tmp = RT_H2LE_U32(*pau32s);
1232 ohciPhysWrite(pThis, Addr, (uint8_t *)&u32Tmp, sizeof(u32Tmp));
1233 }
1234#endif
1235}
1236
1237
1238#ifdef IN_RING3
1239
1240/**
1241 * Reads an OHCIED.
1242 */
1243DECLINLINE(void) ohciReadEd(POHCI pThis, uint32_t EdAddr, POHCIED pEd)
1244{
1245 ohciGetDWords(pThis, EdAddr, (uint32_t *)pEd, sizeof(*pEd) >> 2);
1246}
1247
1248/**
1249 * Reads an OHCITD.
1250 */
1251DECLINLINE(void) ohciReadTd(POHCI pThis, uint32_t TdAddr, POHCITD pTd)
1252{
1253 ohciGetDWords(pThis, TdAddr, (uint32_t *)pTd, sizeof(*pTd) >> 2);
1254#ifdef LOG_ENABLED
1255 if (LogIs3Enabled())
1256 {
1257 uint32_t hichg;
1258 hichg = pTd->hwinfo;
1259 Log3(("ohciReadTd(,%#010x,): R=%d DP=%d DI=%d T=%d EC=%d CC=%#x CBP=%#010x NextTD=%#010x BE=%#010x UNK=%#x\n",
1260 TdAddr,
1261 (pTd->hwinfo >> 18) & 1,
1262 (pTd->hwinfo >> 19) & 3,
1263 (pTd->hwinfo >> 21) & 7,
1264 (pTd->hwinfo >> 24) & 3,
1265 (pTd->hwinfo >> 26) & 3,
1266 (pTd->hwinfo >> 28) &15,
1267 pTd->cbp,
1268 pTd->NextTD,
1269 pTd->be,
1270 pTd->hwinfo & TD_HWINFO_UNKNOWN_MASK));
1271#if 0
1272 if (LogIs3Enabled())
1273 {
1274 /*
1275 * usbohci.sys (32-bit XP) allocates 0x80 bytes per TD:
1276 * 0x00-0x0f is the OHCI TD.
1277 * 0x10-0x1f for isochronous TDs
1278 * 0x20 is the physical address of this TD.
1279 * 0x24 is initialized with 0x64745948, probably a magic.
1280 * 0x28 is some kind of flags. the first bit begin the allocated / not allocated indicator.
1281 * 0x30 is a pointer to something. endpoint? interface? device?
1282 * 0x38 is initialized to 0xdeadface. but is changed into a pointer or something.
1283 * 0x40 looks like a pointer.
1284 * The rest is unknown and initialized with zeros.
1285 */
1286 uint8_t abXpTd[0x80];
1287 ohciPhysRead(pThis, TdAddr, abXpTd, sizeof(abXpTd));
1288 Log3(("WinXpTd: alloc=%d PhysSelf=%RX32 s2=%RX32 magic=%RX32 s4=%RX32 s5=%RX32\n"
1289 "%.*Rhxd\n",
1290 abXpTd[28] & RT_BIT(0),
1291 *((uint32_t *)&abXpTd[0x20]), *((uint32_t *)&abXpTd[0x30]),
1292 *((uint32_t *)&abXpTd[0x24]), *((uint32_t *)&abXpTd[0x38]),
1293 *((uint32_t *)&abXpTd[0x40]),
1294 sizeof(abXpTd), &abXpTd[0]));
1295 }
1296#endif
1297 }
1298#endif
1299}
1300
1301/**
1302 * Reads an OHCIITD.
1303 */
1304DECLINLINE(void) ohciReadITd(POHCI pThis, uint32_t ITdAddr, POHCIITD pITd)
1305{
1306 ohciGetDWords(pThis, ITdAddr, (uint32_t *)pITd, sizeof(*pITd) / sizeof(uint32_t));
1307#ifdef LOG_ENABLED
1308 if (LogIs3Enabled())
1309 {
1310 Log3(("ohciReadITd(,%#010x,): SF=%#06x (%#RX32) DI=%#x FC=%d CC=%#x BP0=%#010x NextTD=%#010x BE=%#010x\n",
1311 ITdAddr,
1312 pITd->HwInfo & 0xffff, pThis->HcFmNumber,
1313 (pITd->HwInfo >> 21) & 7,
1314 (pITd->HwInfo >> 24) & 7,
1315 (pITd->HwInfo >> 28) &15,
1316 pITd->BP0,
1317 pITd->NextTD,
1318 pITd->BE));
1319 Log3(("psw0=%x:%03x psw1=%x:%03x psw2=%x:%03x psw3=%x:%03x psw4=%x:%03x psw5=%x:%03x psw6=%x:%03x psw7=%x:%03x\n",
1320 pITd->aPSW[0] >> 12, pITd->aPSW[0] & 0xfff,
1321 pITd->aPSW[1] >> 12, pITd->aPSW[1] & 0xfff,
1322 pITd->aPSW[2] >> 12, pITd->aPSW[2] & 0xfff,
1323 pITd->aPSW[3] >> 12, pITd->aPSW[3] & 0xfff,
1324 pITd->aPSW[4] >> 12, pITd->aPSW[4] & 0xfff,
1325 pITd->aPSW[5] >> 12, pITd->aPSW[5] & 0xfff,
1326 pITd->aPSW[6] >> 12, pITd->aPSW[6] & 0xfff,
1327 pITd->aPSW[7] >> 12, pITd->aPSW[7] & 0xfff));
1328 }
1329#endif
1330}
1331
1332
1333/**
1334 * Writes an OHCIED.
1335 */
1336DECLINLINE(void) ohciWriteEd(POHCI pThis, uint32_t EdAddr, PCOHCIED pEd)
1337{
1338#ifdef LOG_ENABLED
1339 if (LogIs3Enabled())
1340 {
1341 OHCIED EdOld;
1342 uint32_t hichg;
1343
1344 ohciGetDWords(pThis, EdAddr, (uint32_t *)&EdOld, sizeof(EdOld) >> 2);
1345 hichg = EdOld.hwinfo ^ pEd->hwinfo;
1346 Log3(("ohciWriteEd(,%#010x,): %sFA=%#x %sEN=%#x %sD=%#x %sS=%d %sK=%d %sF=%d %sMPS=%#x %sTailP=%#010x %sHeadP=%#010x %sH=%d %sC=%d %sNextED=%#010x\n",
1347 EdAddr,
1348 (hichg >> 0) & 0x7f ? "*" : "", (pEd->hwinfo >> 0) & 0x7f,
1349 (hichg >> 7) & 0xf ? "*" : "", (pEd->hwinfo >> 7) & 0xf,
1350 (hichg >> 11) & 3 ? "*" : "", (pEd->hwinfo >> 11) & 3,
1351 (hichg >> 13) & 1 ? "*" : "", (pEd->hwinfo >> 13) & 1,
1352 (hichg >> 14) & 1 ? "*" : "", (pEd->hwinfo >> 14) & 1,
1353 (hichg >> 15) & 1 ? "*" : "", (pEd->hwinfo >> 15) & 1,
1354 (hichg >> 24) &0x3ff ? "*" : "", (pEd->hwinfo >> 16) &0x3ff,
1355 EdOld.TailP != pEd->TailP ? "*" : "", pEd->TailP,
1356 (EdOld.HeadP & ~3) != (pEd->HeadP & ~3) ? "*" : "", pEd->HeadP & ~3,
1357 (EdOld.HeadP ^ pEd->HeadP) & 1 ? "*" : "", pEd->HeadP & 1,
1358 (EdOld.HeadP ^ pEd->HeadP) & 2 ? "*" : "", (pEd->HeadP >> 1) & 1,
1359 EdOld.NextED != pEd->NextED ? "*" : "", pEd->NextED));
1360 }
1361#endif
1362
1363 ohciPutDWords(pThis, EdAddr, (uint32_t *)pEd, sizeof(*pEd) >> 2);
1364}
1365
1366
1367/**
1368 * Writes an OHCITD.
1369 */
1370DECLINLINE(void) ohciWriteTd(POHCI pThis, uint32_t TdAddr, PCOHCITD pTd, const char *pszLogMsg)
1371{
1372#ifdef LOG_ENABLED
1373 if (LogIs3Enabled())
1374 {
1375 OHCITD TdOld;
1376 ohciGetDWords(pThis, TdAddr, (uint32_t *)&TdOld, sizeof(TdOld) >> 2);
1377 uint32_t hichg = TdOld.hwinfo ^ pTd->hwinfo;
1378 Log3(("ohciWriteTd(,%#010x,): %sR=%d %sDP=%d %sDI=%#x %sT=%d %sEC=%d %sCC=%#x %sCBP=%#010x %sNextTD=%#010x %sBE=%#010x (%s)\n",
1379 TdAddr,
1380 (hichg >> 18) & 1 ? "*" : "", (pTd->hwinfo >> 18) & 1,
1381 (hichg >> 19) & 3 ? "*" : "", (pTd->hwinfo >> 19) & 3,
1382 (hichg >> 21) & 7 ? "*" : "", (pTd->hwinfo >> 21) & 7,
1383 (hichg >> 24) & 3 ? "*" : "", (pTd->hwinfo >> 24) & 3,
1384 (hichg >> 26) & 3 ? "*" : "", (pTd->hwinfo >> 26) & 3,
1385 (hichg >> 28) &15 ? "*" : "", (pTd->hwinfo >> 28) &15,
1386 TdOld.cbp != pTd->cbp ? "*" : "", pTd->cbp,
1387 TdOld.NextTD != pTd->NextTD ? "*" : "", pTd->NextTD,
1388 TdOld.be != pTd->be ? "*" : "", pTd->be,
1389 pszLogMsg));
1390 }
1391#endif
1392 ohciPutDWords(pThis, TdAddr, (uint32_t *)pTd, sizeof(*pTd) >> 2);
1393}
1394
1395/**
1396 * Writes an OHCIITD.
1397 */
1398DECLINLINE(void) ohciWriteITd(POHCI pThis, uint32_t ITdAddr, PCOHCIITD pITd, const char *pszLogMsg)
1399{
1400#ifdef LOG_ENABLED
1401 if (LogIs3Enabled())
1402 {
1403 OHCIITD ITdOld;
1404 ohciGetDWords(pThis, ITdAddr, (uint32_t *)&ITdOld, sizeof(ITdOld) / sizeof(uint32_t));
1405 uint32_t HIChg = ITdOld.HwInfo ^ pITd->HwInfo;
1406 Log3(("ohciWriteITd(,%#010x,): %sSF=%#x (now=%#RX32) %sDI=%#x %sFC=%d %sCC=%#x %sBP0=%#010x %sNextTD=%#010x %sBE=%#010x (%s)\n",
1407 ITdAddr,
1408 (HIChg & 0xffff) & 1 ? "*" : "", pITd->HwInfo & 0xffff, pThis->HcFmNumber,
1409 (HIChg >> 21) & 7 ? "*" : "", (pITd->HwInfo >> 21) & 7,
1410 (HIChg >> 24) & 7 ? "*" : "", (pITd->HwInfo >> 24) & 7,
1411 (HIChg >> 28) &15 ? "*" : "", (pITd->HwInfo >> 28) &15,
1412 ITdOld.BP0 != pITd->BP0 ? "*" : "", pITd->BP0,
1413 ITdOld.NextTD != pITd->NextTD ? "*" : "", pITd->NextTD,
1414 ITdOld.BE != pITd->BE ? "*" : "", pITd->BE,
1415 pszLogMsg));
1416 Log3(("psw0=%s%x:%s%03x psw1=%s%x:%s%03x psw2=%s%x:%s%03x psw3=%s%x:%s%03x psw4=%s%x:%s%03x psw5=%s%x:%s%03x psw6=%s%x:%s%03x psw7=%s%x:%s%03x\n",
1417 (ITdOld.aPSW[0] >> 12) != (pITd->aPSW[0] >> 12) ? "*" : "", pITd->aPSW[0] >> 12, (ITdOld.aPSW[0] & 0xfff) != (pITd->aPSW[0] & 0xfff) ? "*" : "", pITd->aPSW[0] & 0xfff,
1418 (ITdOld.aPSW[1] >> 12) != (pITd->aPSW[1] >> 12) ? "*" : "", pITd->aPSW[1] >> 12, (ITdOld.aPSW[1] & 0xfff) != (pITd->aPSW[1] & 0xfff) ? "*" : "", pITd->aPSW[1] & 0xfff,
1419 (ITdOld.aPSW[2] >> 12) != (pITd->aPSW[2] >> 12) ? "*" : "", pITd->aPSW[2] >> 12, (ITdOld.aPSW[2] & 0xfff) != (pITd->aPSW[2] & 0xfff) ? "*" : "", pITd->aPSW[2] & 0xfff,
1420 (ITdOld.aPSW[3] >> 12) != (pITd->aPSW[3] >> 12) ? "*" : "", pITd->aPSW[3] >> 12, (ITdOld.aPSW[3] & 0xfff) != (pITd->aPSW[3] & 0xfff) ? "*" : "", pITd->aPSW[3] & 0xfff,
1421 (ITdOld.aPSW[4] >> 12) != (pITd->aPSW[4] >> 12) ? "*" : "", pITd->aPSW[4] >> 12, (ITdOld.aPSW[4] & 0xfff) != (pITd->aPSW[4] & 0xfff) ? "*" : "", pITd->aPSW[4] & 0xfff,
1422 (ITdOld.aPSW[5] >> 12) != (pITd->aPSW[5] >> 12) ? "*" : "", pITd->aPSW[5] >> 12, (ITdOld.aPSW[5] & 0xfff) != (pITd->aPSW[5] & 0xfff) ? "*" : "", pITd->aPSW[5] & 0xfff,
1423 (ITdOld.aPSW[6] >> 12) != (pITd->aPSW[6] >> 12) ? "*" : "", pITd->aPSW[6] >> 12, (ITdOld.aPSW[6] & 0xfff) != (pITd->aPSW[6] & 0xfff) ? "*" : "", pITd->aPSW[6] & 0xfff,
1424 (ITdOld.aPSW[7] >> 12) != (pITd->aPSW[7] >> 12) ? "*" : "", pITd->aPSW[7] >> 12, (ITdOld.aPSW[7] & 0xfff) != (pITd->aPSW[7] & 0xfff) ? "*" : "", pITd->aPSW[7] & 0xfff));
1425 }
1426#endif
1427 ohciPutDWords(pThis, ITdAddr, (uint32_t *)pITd, sizeof(*pITd) / sizeof(uint32_t));
1428}
1429
1430
1431#ifdef LOG_ENABLED
1432
1433/**
1434 * Core TD queue dumper. LOG_ENABLED builds only.
1435 */
1436DECLINLINE(void) ohciDumpTdQueueCore(POHCI pThis, uint32_t GCPhysHead, uint32_t GCPhysTail, bool fFull)
1437{
1438 uint32_t GCPhys = GCPhysHead;
1439 int cMax = 100;
1440 for (;;)
1441 {
1442 OHCITD Td;
1443 Log4(("%#010x%s%s", GCPhys,
1444 GCPhys && ohci_in_flight_find(pThis, GCPhys) >= 0 ? "~" : "",
1445 GCPhys && ohci_in_done_queue_find(pThis, GCPhys) >= 0 ? "^" : ""));
1446 if (GCPhys == 0 || GCPhys == GCPhysTail)
1447 break;
1448
1449 /* can't use ohciReadTd() because of Log4. */
1450 ohciGetDWords(pThis, GCPhys, (uint32_t *)&Td, sizeof(Td) >> 2);
1451 if (fFull)
1452 Log4((" [R=%d DP=%d DI=%d T=%d EC=%d CC=%#x CBP=%#010x NextTD=%#010x BE=%#010x] -> ",
1453 (Td.hwinfo >> 18) & 1,
1454 (Td.hwinfo >> 19) & 3,
1455 (Td.hwinfo >> 21) & 7,
1456 (Td.hwinfo >> 24) & 3,
1457 (Td.hwinfo >> 26) & 3,
1458 (Td.hwinfo >> 28) &15,
1459 Td.cbp,
1460 Td.NextTD,
1461 Td.be));
1462 else
1463 Log4((" -> "));
1464 GCPhys = Td.NextTD & ED_PTR_MASK;
1465 Assert(GCPhys != GCPhysHead);
1466 Assert(cMax-- > 0); NOREF(cMax);
1467 }
1468}
1469
1470/**
1471 * Dumps a TD queue. LOG_ENABLED builds only.
1472 */
1473DECLINLINE(void) ohciDumpTdQueue(POHCI pThis, uint32_t GCPhysHead, const char *pszMsg)
1474{
1475 if (pszMsg)
1476 Log4(("%s: ", pszMsg));
1477 ohciDumpTdQueueCore(pThis, GCPhysHead, 0, true);
1478 Log4(("\n"));
1479}
1480
1481/**
1482 * Core ITD queue dumper. LOG_ENABLED builds only.
1483 */
1484DECLINLINE(void) ohciDumpITdQueueCore(POHCI pThis, uint32_t GCPhysHead, uint32_t GCPhysTail, bool fFull)
1485{
1486 uint32_t GCPhys = GCPhysHead;
1487 int cMax = 100;
1488 for (;;)
1489 {
1490 OHCIITD ITd;
1491 Log4(("%#010x%s%s", GCPhys,
1492 GCPhys && ohci_in_flight_find(pThis, GCPhys) >= 0 ? "~" : "",
1493 GCPhys && ohci_in_done_queue_find(pThis, GCPhys) >= 0 ? "^" : ""));
1494 if (GCPhys == 0 || GCPhys == GCPhysTail)
1495 break;
1496
1497 /* can't use ohciReadTd() because of Log4. */
1498 ohciGetDWords(pThis, GCPhys, (uint32_t *)&ITd, sizeof(ITd) / sizeof(uint32_t));
1499 /*if (fFull)
1500 Log4((" [R=%d DP=%d DI=%d T=%d EC=%d CC=%#x CBP=%#010x NextTD=%#010x BE=%#010x] -> ",
1501 (Td.hwinfo >> 18) & 1,
1502 (Td.hwinfo >> 19) & 3,
1503 (Td.hwinfo >> 21) & 7,
1504 (Td.hwinfo >> 24) & 3,
1505 (Td.hwinfo >> 26) & 3,
1506 (Td.hwinfo >> 28) &15,
1507 Td.cbp,
1508 Td.NextTD,
1509 Td.be));
1510 else*/
1511 Log4((" -> "));
1512 GCPhys = ITd.NextTD & ED_PTR_MASK;
1513 Assert(GCPhys != GCPhysHead);
1514 Assert(cMax-- > 0); NOREF(cMax);
1515 }
1516}
1517
1518/**
1519 * Dumps a ED list. LOG_ENABLED builds only.
1520 */
1521DECLINLINE(void) ohciDumpEdList(POHCI pThis, uint32_t GCPhysHead, const char *pszMsg, bool fTDs)
1522{
1523 uint32_t GCPhys = GCPhysHead;
1524 if (pszMsg)
1525 Log4(("%s:", pszMsg));
1526 for (;;)
1527 {
1528 OHCIED Ed;
1529
1530 /* ED */
1531 Log4((" %#010x={", GCPhys));
1532 if (!GCPhys)
1533 {
1534 Log4(("END}\n"));
1535 return;
1536 }
1537
1538 /* TDs */
1539 ohciReadEd(pThis, GCPhys, &Ed);
1540 if (Ed.hwinfo & ED_HWINFO_ISO)
1541 Log4(("[I]"));
1542 if ((Ed.HeadP & ED_HEAD_HALTED) || (Ed.hwinfo & ED_HWINFO_SKIP))
1543 {
1544 if ((Ed.HeadP & ED_HEAD_HALTED) && (Ed.hwinfo & ED_HWINFO_SKIP))
1545 Log4(("SH}"));
1546 else if (Ed.hwinfo & ED_HWINFO_SKIP)
1547 Log4(("S-}"));
1548 else
1549 Log4(("-H}"));
1550 }
1551 else
1552 {
1553 if (Ed.hwinfo & ED_HWINFO_ISO)
1554 ohciDumpITdQueueCore(pThis, Ed.HeadP & ED_PTR_MASK, Ed.TailP & ED_PTR_MASK, false);
1555 else
1556 ohciDumpTdQueueCore(pThis, Ed.HeadP & ED_PTR_MASK, Ed.TailP & ED_PTR_MASK, false);
1557 Log4(("}"));
1558 }
1559
1560 /* next */
1561 GCPhys = Ed.NextED & ED_PTR_MASK;
1562 Assert(GCPhys != GCPhysHead);
1563 }
1564 Log4(("\n"));
1565}
1566
1567#endif /* LOG_ENABLED */
1568
1569
1570DECLINLINE(int) ohci_in_flight_find_free(POHCI pThis, const int iStart)
1571{
1572 unsigned i = iStart;
1573 while (i < RT_ELEMENTS(pThis->aInFlight))
1574 {
1575 if (pThis->aInFlight[i].GCPhysTD == 0)
1576 return i;
1577 i++;
1578 }
1579 i = iStart;
1580 while (i-- > 0)
1581 {
1582 if (pThis->aInFlight[i].GCPhysTD == 0)
1583 return i;
1584 }
1585 return -1;
1586}
1587
1588
1589/**
1590 * Record an in-flight TD.
1591 *
1592 * @param pThis OHCI instance data.
1593 * @param GCPhysTD Physical address of the TD.
1594 * @param pUrb The URB.
1595 */
1596static void ohci_in_flight_add(POHCI pThis, uint32_t GCPhysTD, PVUSBURB pUrb)
1597{
1598 int i = ohci_in_flight_find_free(pThis, (GCPhysTD >> 4) % RT_ELEMENTS(pThis->aInFlight));
1599 if (i >= 0)
1600 {
1601#ifdef LOG_ENABLED
1602 pUrb->pHci->u32FrameNo = pThis->HcFmNumber;
1603#endif
1604 pThis->aInFlight[i].GCPhysTD = GCPhysTD;
1605 pThis->aInFlight[i].pUrb = pUrb;
1606 pThis->cInFlight++;
1607 return;
1608 }
1609 AssertMsgFailed(("Out of space cInFlight=%d!\n", pThis->cInFlight));
1610}
1611
1612
1613/**
1614 * Record in-flight TDs for an URB.
1615 *
1616 * @param pThis OHCI instance data.
1617 * @param pUrb The URB.
1618 */
1619static void ohci_in_flight_add_urb(POHCI pThis, PVUSBURB pUrb)
1620{
1621 for (unsigned iTd = 0; iTd < pUrb->pHci->cTds; iTd++)
1622 ohci_in_flight_add(pThis, pUrb->paTds[iTd].TdAddr, pUrb);
1623}
1624
1625
1626/**
1627 * Finds a in-flight TD.
1628 *
1629 * @returns Index of the record.
1630 * @returns -1 if not found.
1631 * @param pThis OHCI instance data.
1632 * @param GCPhysTD Physical address of the TD.
1633 * @remark This has to be fast.
1634 */
1635static int ohci_in_flight_find(POHCI pThis, uint32_t GCPhysTD)
1636{
1637 unsigned cLeft = pThis->cInFlight;
1638 unsigned i = (GCPhysTD >> 4) % RT_ELEMENTS(pThis->aInFlight);
1639 const int iLast = i;
1640 while (i < RT_ELEMENTS(pThis->aInFlight))
1641 {
1642 if (pThis->aInFlight[i].GCPhysTD == GCPhysTD)
1643 return i;
1644 if (pThis->aInFlight[i].GCPhysTD)
1645 if (cLeft-- <= 1)
1646 return -1;
1647 i++;
1648 }
1649 i = iLast;
1650 while (i-- > 0)
1651 {
1652 if (pThis->aInFlight[i].GCPhysTD == GCPhysTD)
1653 return i;
1654 if (pThis->aInFlight[i].GCPhysTD)
1655 if (cLeft-- <= 1)
1656 return -1;
1657 }
1658 return -1;
1659}
1660
1661
1662/**
1663 * Checks if a TD is in-flight.
1664 *
1665 * @returns true if in flight, false if not.
1666 * @param pThis OHCI instance data.
1667 * @param GCPhysTD Physical address of the TD.
1668 */
1669static bool ohciIsTdInFlight(POHCI pThis, uint32_t GCPhysTD)
1670{
1671 return ohci_in_flight_find(pThis, GCPhysTD) >= 0;
1672}
1673
1674/**
1675 * Returns a URB associated with an in-flight TD, if any.
1676 *
1677 * @returns pointer to URB if TD is in flight.
1678 * @returns NULL if not in flight.
1679 * @param pThis OHCI instance data.
1680 * @param GCPhysTD Physical address of the TD.
1681 */
1682static PVUSBURB ohciTdInFlightUrb(POHCI pThis, uint32_t GCPhysTD)
1683{
1684 int i;
1685
1686 i = ohci_in_flight_find(pThis, GCPhysTD);
1687 if ( i >= 0 )
1688 return pThis->aInFlight[i].pUrb;
1689 return NULL;
1690}
1691
1692/**
1693 * Removes a in-flight TD.
1694 *
1695 * @returns 0 if found. For logged builds this is the number of frames the TD has been in-flight.
1696 * @returns -1 if not found.
1697 * @param pThis OHCI instance data.
1698 * @param GCPhysTD Physical address of the TD.
1699 */
1700static int ohci_in_flight_remove(POHCI pThis, uint32_t GCPhysTD)
1701{
1702 int i = ohci_in_flight_find(pThis, GCPhysTD);
1703 if (i >= 0)
1704 {
1705#ifdef LOG_ENABLED
1706 const int cFramesInFlight = pThis->HcFmNumber - pThis->aInFlight[i].pUrb->pHci->u32FrameNo;
1707#else
1708 const int cFramesInFlight = 0;
1709#endif
1710 Log2(("ohci_in_flight_remove: reaping TD=%#010x %d frames (%#010x-%#010x)\n",
1711 GCPhysTD, cFramesInFlight, pThis->aInFlight[i].pUrb->pHci->u32FrameNo, pThis->HcFmNumber));
1712 pThis->aInFlight[i].GCPhysTD = 0;
1713 pThis->aInFlight[i].pUrb = NULL;
1714 pThis->cInFlight--;
1715 return cFramesInFlight;
1716 }
1717 AssertMsgFailed(("TD %#010x is not in flight\n", GCPhysTD));
1718 return -1;
1719}
1720
1721
1722/**
1723 * Removes all TDs associated with a URB from the in-flight tracking.
1724 *
1725 * @returns 0 if found. For logged builds this is the number of frames the TD has been in-flight.
1726 * @returns -1 if not found.
1727 * @param pThis OHCI instance data.
1728 * @param pUrb The URB.
1729 */
1730static int ohci_in_flight_remove_urb(POHCI pThis, PVUSBURB pUrb)
1731{
1732 int cFramesInFlight = ohci_in_flight_remove(pThis, pUrb->paTds[0].TdAddr);
1733 if (pUrb->pHci->cTds > 1)
1734 {
1735 for (unsigned iTd = 1; iTd < pUrb->pHci->cTds; iTd++)
1736 if (ohci_in_flight_remove(pThis, pUrb->paTds[iTd].TdAddr) < 0)
1737 cFramesInFlight = -1;
1738 }
1739 return cFramesInFlight;
1740}
1741
1742
1743#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
1744
1745/**
1746 * Empties the in-done-queue.
1747 * @param pThis OHCI instance data.
1748 */
1749static void ohci_in_done_queue_zap(POHCI pThis)
1750{
1751 pThis->cInDoneQueue = 0;
1752}
1753
1754/**
1755 * Finds a TD in the in-done-queue.
1756 * @returns >= 0 on success.
1757 * @returns -1 if not found.
1758 * @param pThis OHCI instance data.
1759 * @param GCPhysTD Physical address of the TD.
1760 */
1761static int ohci_in_done_queue_find(POHCI pThis, uint32_t GCPhysTD)
1762{
1763 unsigned i = pThis->cInDoneQueue;
1764 while (i-- > 0)
1765 if (pThis->aInDoneQueue[i].GCPhysTD == GCPhysTD)
1766 return i;
1767 return -1;
1768}
1769
1770/**
1771 * Checks that the specified TD is not in the done queue.
1772 * @param pThis OHCI instance data.
1773 * @param GCPhysTD Physical address of the TD.
1774 */
1775static bool ohci_in_done_queue_check(POHCI pThis, uint32_t GCPhysTD)
1776{
1777 int i = ohci_in_done_queue_find(pThis, GCPhysTD);
1778#if 0
1779 /* This condition has been observed with the USB tablet emulation or with
1780 * a real USB mouse and an SMP XP guest. I am also not sure if this is
1781 * really a problem for us. The assertion checks that the guest doesn't
1782 * re-submit a TD which is still in the done queue. It seems to me that
1783 * this should only be a problem if we either keep track of TDs in the done
1784 * queue somewhere else as well (in which case we should also free those
1785 * references in time, and I can't see any code doing that) or if we
1786 * manipulate TDs in the done queue in some way that might fail if they are
1787 * re-submitted (can't see anything like that either).
1788 */
1789 AssertMsg(i < 0, ("TD %#010x (i=%d)\n", GCPhysTD, i));
1790#endif
1791 return i < 0;
1792}
1793
1794
1795# ifdef VBOX_STRICT
1796/**
1797 * Adds a TD to the in-done-queue tracking, checking that it's not there already.
1798 * @param pThis OHCI instance data.
1799 * @param GCPhysTD Physical address of the TD.
1800 */
1801static void ohci_in_done_queue_add(POHCI pThis, uint32_t GCPhysTD)
1802{
1803 Assert(pThis->cInDoneQueue + 1 <= RT_ELEMENTS(pThis->aInDoneQueue));
1804 if (ohci_in_done_queue_check(pThis, GCPhysTD))
1805 pThis->aInDoneQueue[pThis->cInDoneQueue++].GCPhysTD = GCPhysTD;
1806}
1807# endif /* VBOX_STRICT */
1808#endif /* defined(VBOX_STRICT) || defined(LOG_ENABLED) */
1809
1810
1811/**
1812 * OHCI Transport Buffer - represents a OHCI Transport Descriptor (TD).
1813 * A TD may be split over max 2 pages.
1814 */
1815typedef struct OHCIBUF
1816{
1817 /** Pages involved. */
1818 struct OHCIBUFVEC
1819 {
1820 /** The 32-bit physical address of this part. */
1821 uint32_t Addr;
1822 /** The length. */
1823 uint32_t cb;
1824 } aVecs[2];
1825 /** Number of valid entries in aVecs. */
1826 uint32_t cVecs;
1827 /** The total length. */
1828 uint32_t cbTotal;
1829} OHCIBUF, *POHCIBUF;
1830
1831
1832/**
1833 * Sets up a OHCI transport buffer.
1834 *
1835 * @param pBuf Ohci buffer.
1836 * @param cbp Current buffer pointer. 32-bit physical address.
1837 * @param be Last byte in buffer (BufferEnd). 32-bit physical address.
1838 */
1839static void ohciBufInit(POHCIBUF pBuf, uint32_t cbp, uint32_t be)
1840{
1841 if (!cbp || !be)
1842 {
1843 pBuf->cVecs = 0;
1844 pBuf->cbTotal = 0;
1845 Log2(("ohci: cbp=%#010x be=%#010x cbTotal=0 EMPTY\n", cbp, be));
1846 }
1847 else if ((cbp & ~0xfff) == (be & ~0xfff))
1848 {
1849 pBuf->aVecs[0].Addr = cbp;
1850 pBuf->aVecs[0].cb = (be - cbp) + 1;
1851 pBuf->cVecs = 1;
1852 pBuf->cbTotal = pBuf->aVecs[0].cb;
1853 Log2(("ohci: cbp=%#010x be=%#010x cbTotal=%u\n", cbp, be, pBuf->cbTotal));
1854 }
1855 else
1856 {
1857 pBuf->aVecs[0].Addr = cbp;
1858 pBuf->aVecs[0].cb = 0x1000 - (cbp & 0xfff);
1859 pBuf->aVecs[1].Addr = be & ~0xfff;
1860 pBuf->aVecs[1].cb = (be & 0xfff) + 1;
1861 pBuf->cVecs = 2;
1862 pBuf->cbTotal = pBuf->aVecs[0].cb + pBuf->aVecs[1].cb;
1863 Log2(("ohci: cbp=%#010x be=%#010x cbTotal=%u PAGE FLIP\n", cbp, be, pBuf->cbTotal));
1864 }
1865}
1866
1867/**
1868 * Updates a OHCI transport buffer.
1869 *
1870 * This is called upon completion to adjust the sector lengths if
1871 * the total length has changed. (received less then we had space for
1872 * or a partial transfer.)
1873 *
1874 * @param pBuf The buffer to update. cbTotal contains the new total on input.
1875 * While the aVecs[*].cb members is updated upon return.
1876 */
1877static void ohciBufUpdate(POHCIBUF pBuf)
1878{
1879 for (uint32_t i = 0, cbCur = 0; i < pBuf->cVecs; i++)
1880 {
1881 if (cbCur + pBuf->aVecs[i].cb > pBuf->cbTotal)
1882 {
1883 pBuf->aVecs[i].cb = pBuf->cbTotal - cbCur;
1884 pBuf->cVecs = i + 1;
1885 return;
1886 }
1887 cbCur += pBuf->aVecs[i].cb;
1888 }
1889}
1890
1891
1892/** A worker for ohciUnlinkTds(). */
1893static bool ohciUnlinkIsochronousTdInList(POHCI pThis, uint32_t TdAddr, POHCIITD pITd, POHCIED pEd)
1894{
1895 const uint32_t LastTdAddr = pEd->TailP & ED_PTR_MASK;
1896 Log(("ohciUnlinkIsocTdInList: Unlinking non-head ITD! TdAddr=%#010RX32 HeadTdAddr=%#010RX32 LastEdAddr=%#010RX32\n",
1897 TdAddr, pEd->HeadP & ED_PTR_MASK, LastTdAddr));
1898 AssertMsgReturn(LastTdAddr != TdAddr, ("TdAddr=%#010RX32\n", TdAddr), false);
1899
1900 uint32_t cMax = 256;
1901 uint32_t CurTdAddr = pEd->HeadP & ED_PTR_MASK;
1902 while ( CurTdAddr != LastTdAddr
1903 && cMax-- > 0)
1904 {
1905 OHCIITD ITd;
1906 ohciReadITd(pThis, CurTdAddr, &ITd);
1907 if ((ITd.NextTD & ED_PTR_MASK) == TdAddr)
1908 {
1909 ITd.NextTD = (pITd->NextTD & ED_PTR_MASK) | (ITd.NextTD & ~ED_PTR_MASK);
1910 ohciWriteITd(pThis, CurTdAddr, &ITd, "ohciUnlinkIsocTdInList");
1911 pITd->NextTD &= ~ED_PTR_MASK;
1912 return true;
1913 }
1914
1915 /* next */
1916 CurTdAddr = ITd.NextTD & ED_PTR_MASK;
1917 }
1918
1919 Log(("ohciUnlinkIsocTdInList: TdAddr=%#010RX32 wasn't found in the list!!! (cMax=%d)\n", TdAddr, cMax));
1920 return false;
1921}
1922
1923
1924/** A worker for ohciUnlinkTds(). */
1925static bool ohciUnlinkGeneralTdInList(POHCI pThis, uint32_t TdAddr, POHCITD pTd, POHCIED pEd)
1926{
1927 const uint32_t LastTdAddr = pEd->TailP & ED_PTR_MASK;
1928 Log(("ohciUnlinkGeneralTdInList: Unlinking non-head TD! TdAddr=%#010RX32 HeadTdAddr=%#010RX32 LastEdAddr=%#010RX32\n",
1929 TdAddr, pEd->HeadP & ED_PTR_MASK, LastTdAddr));
1930 AssertMsgReturn(LastTdAddr != TdAddr, ("TdAddr=%#010RX32\n", TdAddr), false);
1931
1932 uint32_t cMax = 256;
1933 uint32_t CurTdAddr = pEd->HeadP & ED_PTR_MASK;
1934 while ( CurTdAddr != LastTdAddr
1935 && cMax-- > 0)
1936 {
1937 OHCITD Td;
1938 ohciReadTd(pThis, CurTdAddr, &Td);
1939 if ((Td.NextTD & ED_PTR_MASK) == TdAddr)
1940 {
1941 Td.NextTD = (pTd->NextTD & ED_PTR_MASK) | (Td.NextTD & ~ED_PTR_MASK);
1942 ohciWriteTd(pThis, CurTdAddr, &Td, "ohciUnlinkGeneralTdInList");
1943 pTd->NextTD &= ~ED_PTR_MASK;
1944 return true;
1945 }
1946
1947 /* next */
1948 CurTdAddr = Td.NextTD & ED_PTR_MASK;
1949 }
1950
1951 Log(("ohciUnlinkGeneralTdInList: TdAddr=%#010RX32 wasn't found in the list!!! (cMax=%d)\n", TdAddr, cMax));
1952 return false;
1953}
1954
1955
1956/**
1957 * Unlinks the TDs that makes up the URB from the ED.
1958 *
1959 * @returns success indicator. true if successfully unlinked.
1960 * @returns false if the TD was not found in the list.
1961 */
1962static bool ohciUnlinkTds(POHCI pThis, PVUSBURB pUrb, POHCIED pEd)
1963{
1964 /*
1965 * Don't unlink more than once.
1966 */
1967 if (pUrb->pHci->fUnlinked)
1968 return true;
1969 pUrb->pHci->fUnlinked = true;
1970
1971 if (pUrb->enmType == VUSBXFERTYPE_ISOC)
1972 {
1973 for (unsigned iTd = 0; iTd < pUrb->pHci->cTds; iTd++)
1974 {
1975 POHCIITD pITd = (POHCIITD)&pUrb->paTds[iTd].TdCopy[0];
1976 const uint32_t ITdAddr = pUrb->paTds[iTd].TdAddr;
1977
1978 /*
1979 * Unlink the TD from the ED list.
1980 * The normal case is that it's at the head of the list.
1981 */
1982 Assert((ITdAddr & ED_PTR_MASK) == ITdAddr);
1983 if ((pEd->HeadP & ED_PTR_MASK) == ITdAddr)
1984 {
1985 pEd->HeadP = (pITd->NextTD & ED_PTR_MASK) | (pEd->HeadP & ~ED_PTR_MASK);
1986 pITd->NextTD &= ~ED_PTR_MASK;
1987 }
1988 else
1989 {
1990 /*
1991 * It's probably somewhere in the list, not a unlikely situation with
1992 * the current isochronous code.
1993 */
1994 if (!ohciUnlinkIsochronousTdInList(pThis, ITdAddr, pITd, pEd))
1995 return false;
1996 }
1997 }
1998 }
1999 else
2000 {
2001 for (unsigned iTd = 0; iTd < pUrb->pHci->cTds; iTd++)
2002 {
2003 POHCITD pTd = (POHCITD)&pUrb->paTds[iTd].TdCopy[0];
2004 const uint32_t TdAddr = pUrb->paTds[iTd].TdAddr;
2005
2006 /** @todo r=bird: Messing with the toggle flag in prepare is probably not correct
2007 * when we encounter a STALL error, 4.3.1.3.7.2: "If an endpoint returns a STALL
2008 * PID, the Host Controller retires the General TD with the ConditionCode set
2009 * to STALL and halts the endpoint. The CurrentBufferPointer, ErrorCount, and
2010 * dataToggle fields retain the values that they had at the start of the
2011 * transaction." */
2012
2013 /* update toggle and set data toggle carry */
2014 pTd->hwinfo &= ~TD_HWINFO_TOGGLE;
2015 if ( pTd->hwinfo & TD_HWINFO_TOGGLE_HI )
2016 {
2017 if ( !!(pTd->hwinfo & TD_HWINFO_TOGGLE_LO) ) /** @todo r=bird: is it just me or doesn't this make sense at all? */
2018 pTd->hwinfo |= TD_HWINFO_TOGGLE_LO;
2019 else
2020 pTd->hwinfo &= ~TD_HWINFO_TOGGLE_LO;
2021 }
2022 else
2023 {
2024 if ( !!(pEd->HeadP & ED_HEAD_CARRY) ) /** @todo r=bird: is it just me or doesn't this make sense at all? */
2025 pEd->HeadP |= ED_HEAD_CARRY;
2026 else
2027 pEd->HeadP &= ~ED_HEAD_CARRY;
2028 }
2029
2030 /*
2031 * Unlink the TD from the ED list.
2032 * The normal case is that it's at the head of the list.
2033 */
2034 Assert((TdAddr & ED_PTR_MASK) == TdAddr);
2035 if ((pEd->HeadP & ED_PTR_MASK) == TdAddr)
2036 {
2037 pEd->HeadP = (pTd->NextTD & ED_PTR_MASK) | (pEd->HeadP & ~ED_PTR_MASK);
2038 pTd->NextTD &= ~ED_PTR_MASK;
2039 }
2040 else
2041 {
2042 /*
2043 * The TD is probably somewhere in the list.
2044 *
2045 * This shouldn't ever happen unless there was a failure! Even on failure,
2046 * we can screw up the HCD state by picking out a TD from within the list
2047 * like this! If this turns out to be a problem, we have to find a better
2048 * solution. For now we'll hope the HCD handles it...
2049 */
2050 if (!ohciUnlinkGeneralTdInList(pThis, TdAddr, pTd, pEd))
2051 return false;
2052 }
2053
2054 /*
2055 * Only unlink the first TD on error.
2056 * See comment in ohciRhXferCompleteGeneralURB().
2057 */
2058 if (pUrb->enmStatus != VUSBSTATUS_OK)
2059 break;
2060 }
2061 }
2062
2063 return true;
2064}
2065
2066
2067/**
2068 * Checks that the transport descriptors associated with the URB
2069 * hasn't been changed in any way indicating that they may have been canceled.
2070 *
2071 * This rountine also updates the TD copies contained within the URB.
2072 *
2073 * @returns true if the URB has been canceled, otherwise false.
2074 * @param pThis The OHCI instance.
2075 * @param pUrb The URB in question.
2076 * @param pEd The ED pointer (optional).
2077 */
2078static bool ohciHasUrbBeenCanceled(POHCI pThis, PVUSBURB pUrb, PCOHCIED pEd)
2079{
2080 if (!pUrb)
2081 return true;
2082
2083 /*
2084 * Make sure we've got an endpoint descriptor so we can
2085 * check for tail TDs.
2086 */
2087 OHCIED Ed;
2088 if (!pEd)
2089 {
2090 ohciReadEd(pThis, pUrb->pHci->EdAddr, &Ed);
2091 pEd = &Ed;
2092 }
2093
2094 if (pUrb->enmType == VUSBXFERTYPE_ISOC)
2095 {
2096 for (unsigned iTd = 0; iTd < pUrb->pHci->cTds; iTd++)
2097 {
2098 union
2099 {
2100 OHCIITD ITd;
2101 uint32_t au32[8];
2102 } u;
2103 if ( (pUrb->paTds[iTd].TdAddr & ED_PTR_MASK)
2104 == (pEd->TailP & ED_PTR_MASK))
2105 {
2106 Log(("%s: ohciHasUrbBeenCanceled: iTd=%d cTds=%d TdAddr=%#010RX32 canceled (tail)! [iso]\n",
2107 pUrb->pszDesc, iTd, pUrb->pHci->cTds, pUrb->paTds[iTd].TdAddr));
2108 STAM_COUNTER_INC(&pThis->StatCanceledIsocUrbs);
2109 return true;
2110 }
2111 ohciReadITd(pThis, pUrb->paTds[iTd].TdAddr, &u.ITd);
2112 if ( u.au32[0] != pUrb->paTds[iTd].TdCopy[0] /* hwinfo */
2113 || u.au32[1] != pUrb->paTds[iTd].TdCopy[1] /* bp0 */
2114 || u.au32[3] != pUrb->paTds[iTd].TdCopy[3] /* be */
2115 || ( u.au32[2] != pUrb->paTds[iTd].TdCopy[2] /* NextTD */
2116 && iTd + 1 < pUrb->pHci->cTds /* ignore the last one */)
2117 || u.au32[4] != pUrb->paTds[iTd].TdCopy[4] /* psw0&1 */
2118 || u.au32[5] != pUrb->paTds[iTd].TdCopy[5] /* psw2&3 */
2119 || u.au32[6] != pUrb->paTds[iTd].TdCopy[6] /* psw4&5 */
2120 || u.au32[7] != pUrb->paTds[iTd].TdCopy[7] /* psw6&7 */
2121 )
2122 {
2123 Log(("%s: ohciHasUrbBeenCanceled: iTd=%d cTds=%d TdAddr=%#010RX32 canceled! [iso]\n",
2124 pUrb->pszDesc, iTd, pUrb->pHci->cTds, pUrb->paTds[iTd].TdAddr));
2125 Log2((" %.*Rhxs (cur)\n"
2126 "!= %.*Rhxs (copy)\n",
2127 sizeof(u.ITd), &u.ITd, sizeof(u.ITd), &pUrb->paTds[iTd].TdCopy[0]));
2128 STAM_COUNTER_INC(&pThis->StatCanceledIsocUrbs);
2129 return true;
2130 }
2131 pUrb->paTds[iTd].TdCopy[2] = u.au32[2];
2132 }
2133 }
2134 else
2135 {
2136 for (unsigned iTd = 0; iTd < pUrb->pHci->cTds; iTd++)
2137 {
2138 union
2139 {
2140 OHCITD Td;
2141 uint32_t au32[4];
2142 } u;
2143 if ( (pUrb->paTds[iTd].TdAddr & ED_PTR_MASK)
2144 == (pEd->TailP & ED_PTR_MASK))
2145 {
2146 Log(("%s: ohciHasUrbBeenCanceled: iTd=%d cTds=%d TdAddr=%#010RX32 canceled (tail)!\n",
2147 pUrb->pszDesc, iTd, pUrb->pHci->cTds, pUrb->paTds[iTd].TdAddr));
2148 STAM_COUNTER_INC(&pThis->StatCanceledGenUrbs);
2149 return true;
2150 }
2151 ohciReadTd(pThis, pUrb->paTds[iTd].TdAddr, &u.Td);
2152 if ( u.au32[0] != pUrb->paTds[iTd].TdCopy[0] /* hwinfo */
2153 || u.au32[1] != pUrb->paTds[iTd].TdCopy[1] /* cbp */
2154 || u.au32[3] != pUrb->paTds[iTd].TdCopy[3] /* be */
2155 || ( u.au32[2] != pUrb->paTds[iTd].TdCopy[2] /* NextTD */
2156 && iTd + 1 < pUrb->pHci->cTds /* ignore the last one */)
2157 )
2158 {
2159 Log(("%s: ohciHasUrbBeenCanceled: iTd=%d cTds=%d TdAddr=%#010RX32 canceled!\n",
2160 pUrb->pszDesc, iTd, pUrb->pHci->cTds, pUrb->paTds[iTd].TdAddr));
2161 Log2((" %.*Rhxs (cur)\n"
2162 "!= %.*Rhxs (copy)\n",
2163 sizeof(u.Td), &u.Td, sizeof(u.Td), &pUrb->paTds[iTd].TdCopy[0]));
2164 STAM_COUNTER_INC(&pThis->StatCanceledGenUrbs);
2165 return true;
2166 }
2167 pUrb->paTds[iTd].TdCopy[2] = u.au32[2];
2168 }
2169 }
2170 return false;
2171}
2172
2173
2174/**
2175 * Returns the OHCI_CC_* corresponding to the VUSB status code.
2176 *
2177 * @returns OHCI_CC_* value.
2178 * @param enmStatus The VUSB status code.
2179 */
2180static uint32_t ohciVUsbStatus2OhciStatus(VUSBSTATUS enmStatus)
2181{
2182 switch (enmStatus)
2183 {
2184 case VUSBSTATUS_OK: return OHCI_CC_NO_ERROR;
2185 case VUSBSTATUS_STALL: return OHCI_CC_STALL;
2186 case VUSBSTATUS_CRC: return OHCI_CC_CRC;
2187 case VUSBSTATUS_DATA_UNDERRUN: return OHCI_CC_DATA_UNDERRUN;
2188 case VUSBSTATUS_DATA_OVERRUN: return OHCI_CC_DATA_OVERRUN;
2189 case VUSBSTATUS_DNR: return OHCI_CC_DNR;
2190 case VUSBSTATUS_NOT_ACCESSED: return OHCI_CC_NOT_ACCESSED_1;
2191 default:
2192 Log(("pUrb->enmStatus=%#x!!!\n", enmStatus));
2193 return OHCI_CC_DNR;
2194 }
2195}
2196
2197/**
2198 * Worker for ohciRhXferCompletion that handles the completion of
2199 * a URB made up of isochronous TDs.
2200 *
2201 * In general, all URBs should have status OK.
2202 */
2203static void ohciRhXferCompleteIsochronousURB(POHCI pThis, PVUSBURB pUrb, POHCIED pEd, int cFmAge)
2204{
2205 /*
2206 * Copy the data back (if IN operation) and update the TDs.
2207 */
2208 for (unsigned iTd = 0; iTd < pUrb->pHci->cTds; iTd++)
2209 {
2210 POHCIITD pITd = (POHCIITD)&pUrb->paTds[iTd].TdCopy[0];
2211 const uint32_t ITdAddr = pUrb->paTds[iTd].TdAddr;
2212 const unsigned cFrames = ((pITd->HwInfo & ITD_HWINFO_FC) >> ITD_HWINFO_FC_SHIFT) + 1;
2213 unsigned R = (pUrb->pHci->u32FrameNo & ITD_HWINFO_SF) - (pITd->HwInfo & ITD_HWINFO_SF);
2214 if (R >= 8)
2215 R = 0; /* submitted ahead of time. */
2216
2217 /*
2218 * Only one case of TD level condition code is document, so
2219 * just set NO_ERROR here to reduce number duplicate code.
2220 */
2221 pITd->HwInfo &= ~TD_HWINFO_CC;
2222 AssertCompile(OHCI_CC_NO_ERROR == 0);
2223
2224 if (pUrb->enmStatus == VUSBSTATUS_OK)
2225 {
2226 /*
2227 * Update the frames and copy back the data.
2228 * We assume that we don't get incorrect lengths here.
2229 */
2230 for (unsigned i = 0; i < cFrames; i++)
2231 {
2232 if ( i < R
2233 || pUrb->aIsocPkts[i - R].enmStatus == VUSBSTATUS_NOT_ACCESSED)
2234 {
2235 /* It should already be NotAccessed. */
2236 pITd->aPSW[i] |= 0xe000; /* (Don't touch the 12th bit.) */
2237 continue;
2238 }
2239
2240 /* Update the PSW (save the offset first in case of a IN). */
2241 uint32_t off = pITd->aPSW[i] & ITD_PSW_OFFSET;
2242 pITd->aPSW[i] = ohciVUsbStatus2OhciStatus(pUrb->aIsocPkts[i - R].enmStatus)
2243 >> (TD_HWINFO_CC_SHIFT - ITD_PSW_CC_SHIFT);
2244
2245 if ( pUrb->enmDir == VUSBDIRECTION_IN
2246 && ( pUrb->aIsocPkts[i - R].enmStatus == VUSBSTATUS_OK
2247 || pUrb->aIsocPkts[i - R].enmStatus == VUSBSTATUS_DATA_UNDERRUN
2248 || pUrb->aIsocPkts[i - R].enmStatus == VUSBSTATUS_DATA_OVERRUN))
2249 {
2250 /* Set the size. */
2251 const unsigned cb = pUrb->aIsocPkts[i - R].cb;
2252 pITd->aPSW[i] |= cb & ITD_PSW_SIZE;
2253 /* Copy data. */
2254 if (cb)
2255 {
2256 uint8_t *pb = &pUrb->abData[pUrb->aIsocPkts[i - R].off];
2257 if (off + cb > 0x1000)
2258 {
2259 if (off < 0x1000)
2260 {
2261 /* both */
2262 const unsigned cb0 = 0x1000 - off;
2263 ohciPhysWrite(pThis, (pITd->BP0 & ITD_BP0_MASK) + off, pb, cb0);
2264 ohciPhysWrite(pThis, pITd->BE & ITD_BP0_MASK, pb + cb0, cb - cb0);
2265 }
2266 else /* only in the 2nd page */
2267 ohciPhysWrite(pThis, (pITd->BE & ITD_BP0_MASK) + (off & ITD_BP0_MASK), pb, cb);
2268 }
2269 else /* only in the 1st page */
2270 ohciPhysWrite(pThis, (pITd->BP0 & ITD_BP0_MASK) + off, pb, cb);
2271 Log5(("packet %d: off=%#x cb=%#x pb=%p (%#x)\n"
2272 "%.*Rhxd\n",
2273 i + R, off, cb, pb, pb - &pUrb->abData[0], cb, pb));
2274 //off += cb;
2275 }
2276 }
2277 }
2278
2279 /*
2280 * If the last package ended with a NotAccessed status, set ITD CC
2281 * to DataOverrun to indicate scheduling overrun.
2282 */
2283 if (pUrb->aIsocPkts[pUrb->cIsocPkts - 1].enmStatus == VUSBSTATUS_NOT_ACCESSED)
2284 pITd->HwInfo |= OHCI_CC_DATA_OVERRUN;
2285 }
2286 else
2287 {
2288 Log(("DevOHCI: Taking untested code path at line %d...\n", __LINE__));
2289 /*
2290 * Most status codes only applies to the individual packets.
2291 *
2292 * If we get a URB level error code of this kind, we'll distribute
2293 * it to all the packages unless some other status is available for
2294 * a package. This is a bit fuzzy, and we will get rid of this code
2295 * before long!
2296 */
2297 //if (pUrb->enmStatus != VUSBSTATUS_DATA_OVERRUN)
2298 {
2299 const unsigned uCC = ohciVUsbStatus2OhciStatus(pUrb->enmStatus)
2300 >> (TD_HWINFO_CC_SHIFT - ITD_PSW_CC_SHIFT);
2301 for (unsigned i = 0; i < cFrames; i++)
2302 pITd->aPSW[i] = uCC;
2303 }
2304 //else
2305 // pITd->HwInfo |= ohciVUsbStatus2OhciStatus(pUrb->enmStatus);
2306 }
2307
2308 /*
2309 * Update the done queue interrupt timer.
2310 */
2311 uint32_t DoneInt = (pITd->HwInfo & ITD_HWINFO_DI) >> ITD_HWINFO_DI_SHIFT;
2312 if ((pITd->HwInfo & TD_HWINFO_CC) != OHCI_CC_NO_ERROR)
2313 DoneInt = 0; /* It's cleared on error. */
2314 if ( DoneInt != 0x7
2315 && DoneInt < pThis->dqic)
2316 pThis->dqic = DoneInt;
2317
2318 /*
2319 * Move on to the done list and write back the modified TD.
2320 */
2321#ifdef LOG_ENABLED
2322 if (!pThis->done)
2323 pThis->u32FmDoneQueueTail = pThis->HcFmNumber;
2324# ifdef VBOX_STRICT
2325 ohci_in_done_queue_add(pThis, ITdAddr);
2326# endif
2327#endif
2328 pITd->NextTD = pThis->done;
2329 pThis->done = ITdAddr;
2330
2331 Log(("%s: ohciRhXferCompleteIsochronousURB: ITdAddr=%#010x EdAddr=%#010x SF=%#x (%#x) CC=%#x FC=%d "
2332 "psw0=%x:%x psw1=%x:%x psw2=%x:%x psw3=%x:%x psw4=%x:%x psw5=%x:%x psw6=%x:%x psw7=%x:%x R=%d\n",
2333 pUrb->pszDesc, ITdAddr,
2334 pUrb->pHci->EdAddr,
2335 pITd->HwInfo & ITD_HWINFO_SF, pThis->HcFmNumber,
2336 (pITd->HwInfo & ITD_HWINFO_CC) >> ITD_HWINFO_CC_SHIFT,
2337 (pITd->HwInfo & ITD_HWINFO_FC) >> ITD_HWINFO_FC_SHIFT,
2338 pITd->aPSW[0] >> ITD_PSW_CC_SHIFT, pITd->aPSW[0] & ITD_PSW_SIZE,
2339 pITd->aPSW[1] >> ITD_PSW_CC_SHIFT, pITd->aPSW[1] & ITD_PSW_SIZE,
2340 pITd->aPSW[2] >> ITD_PSW_CC_SHIFT, pITd->aPSW[2] & ITD_PSW_SIZE,
2341 pITd->aPSW[3] >> ITD_PSW_CC_SHIFT, pITd->aPSW[3] & ITD_PSW_SIZE,
2342 pITd->aPSW[4] >> ITD_PSW_CC_SHIFT, pITd->aPSW[4] & ITD_PSW_SIZE,
2343 pITd->aPSW[5] >> ITD_PSW_CC_SHIFT, pITd->aPSW[5] & ITD_PSW_SIZE,
2344 pITd->aPSW[6] >> ITD_PSW_CC_SHIFT, pITd->aPSW[6] & ITD_PSW_SIZE,
2345 pITd->aPSW[7] >> ITD_PSW_CC_SHIFT, pITd->aPSW[7] & ITD_PSW_SIZE,
2346 R));
2347 ohciWriteITd(pThis, ITdAddr, pITd, "retired");
2348 }
2349}
2350
2351
2352/**
2353 * Worker for ohciRhXferCompletion that handles the completion of
2354 * a URB made up of general TDs.
2355 */
2356static void ohciRhXferCompleteGeneralURB(POHCI pThis, PVUSBURB pUrb, POHCIED pEd, int cFmAge)
2357{
2358 /*
2359 * Copy the data back (if IN operation) and update the TDs.
2360 */
2361 unsigned cbLeft = pUrb->cbData;
2362 uint8_t *pb = &pUrb->abData[0];
2363 for (unsigned iTd = 0; iTd < pUrb->pHci->cTds; iTd++)
2364 {
2365 POHCITD pTd = (POHCITD)&pUrb->paTds[iTd].TdCopy[0];
2366 const uint32_t TdAddr = pUrb->paTds[iTd].TdAddr;
2367
2368 /*
2369 * Setup a ohci transfer buffer and calc the new cbp value.
2370 */
2371 OHCIBUF Buf;
2372 ohciBufInit(&Buf, pTd->cbp, pTd->be);
2373 uint32_t NewCbp;
2374 if (cbLeft >= Buf.cbTotal)
2375 NewCbp = 0;
2376 else
2377 {
2378 /* (len may have changed for short transfers) */
2379 Buf.cbTotal = cbLeft;
2380 ohciBufUpdate(&Buf);
2381 Assert(Buf.cVecs >= 1);
2382 NewCbp = Buf.aVecs[Buf.cVecs-1].Addr + Buf.aVecs[Buf.cVecs-1].cb;
2383 }
2384
2385 /*
2386 * Write back IN buffers.
2387 */
2388 if ( pUrb->enmDir == VUSBDIRECTION_IN
2389 && ( pUrb->enmStatus == VUSBSTATUS_OK
2390 || pUrb->enmStatus == VUSBSTATUS_DATA_OVERRUN
2391 || pUrb->enmStatus == VUSBSTATUS_DATA_UNDERRUN)
2392 && Buf.cbTotal > 0)
2393 {
2394 Assert(Buf.cVecs > 0);
2395 ohciPhysWrite(pThis, Buf.aVecs[0].Addr, pb, Buf.aVecs[0].cb);
2396 if (Buf.cVecs > 1)
2397 ohciPhysWrite(pThis, Buf.aVecs[1].Addr, pb + Buf.aVecs[0].cb, Buf.aVecs[1].cb);
2398 }
2399
2400 /* advance the data buffer. */
2401 cbLeft -= Buf.cbTotal;
2402 pb += Buf.cbTotal;
2403
2404 /*
2405 * Set writeback field.
2406 */
2407 /* zero out writeback fields for retirement */
2408 pTd->hwinfo &= ~TD_HWINFO_CC;
2409 /* always update the CurrentBufferPointer; essential for underrun/overrun errors */
2410 pTd->cbp = NewCbp;
2411
2412 if (pUrb->enmStatus == VUSBSTATUS_OK)
2413 {
2414 pTd->hwinfo &= ~TD_HWINFO_ERRORS;
2415
2416 /* update done queue interrupt timer */
2417 uint32_t DoneInt = (pTd->hwinfo & TD_HWINFO_DI) >> 21;
2418 if ( DoneInt != 0x7
2419 && DoneInt < pThis->dqic)
2420 pThis->dqic = DoneInt;
2421 Log(("%s: ohciRhXferCompleteGeneralURB: ED=%#010x TD=%#010x Age=%d enmStatus=%d cbTotal=%#x NewCbp=%#010RX32 dqic=%d\n",
2422 pUrb->pszDesc, pUrb->pHci->EdAddr, TdAddr, cFmAge, pUrb->enmStatus, Buf.cbTotal, NewCbp, pThis->dqic));
2423 }
2424 else
2425 {
2426 Log(("%s: ohciRhXferCompleteGeneralURB: HALTED ED=%#010x TD=%#010x (age %d) pUrb->enmStatus=%d\n",
2427 pUrb->pszDesc, pUrb->pHci->EdAddr, TdAddr, cFmAge, pUrb->enmStatus));
2428 pEd->HeadP |= ED_HEAD_HALTED;
2429 pThis->dqic = 0; /* "If the Transfer Descriptor is being retired with an error,
2430 * then the Done Queue Interrupt Counter is cleared as if the
2431 * InterruptDelay field were zero."
2432 */
2433 switch (pUrb->enmStatus)
2434 {
2435 case VUSBSTATUS_STALL:
2436 pTd->hwinfo |= OHCI_CC_STALL;
2437 break;
2438 case VUSBSTATUS_CRC:
2439 pTd->hwinfo |= OHCI_CC_CRC;
2440 break;
2441 case VUSBSTATUS_DATA_UNDERRUN:
2442 pTd->hwinfo |= OHCI_CC_DATA_UNDERRUN;
2443 break;
2444 case VUSBSTATUS_DATA_OVERRUN:
2445 pTd->hwinfo |= OHCI_CC_DATA_OVERRUN;
2446 break;
2447 default: /* what the hell */
2448 Log(("pUrb->enmStatus=%#x!!!\n", pUrb->enmStatus));
2449 case VUSBSTATUS_DNR:
2450 pTd->hwinfo |= OHCI_CC_DNR;
2451 break;
2452 }
2453 }
2454
2455 /*
2456 * Move on to the done list and write back the modified TD.
2457 */
2458#ifdef LOG_ENABLED
2459 if (!pThis->done)
2460 pThis->u32FmDoneQueueTail = pThis->HcFmNumber;
2461# ifdef VBOX_STRICT
2462 ohci_in_done_queue_add(pThis, TdAddr);
2463# endif
2464#endif
2465 pTd->NextTD = pThis->done;
2466 pThis->done = TdAddr;
2467
2468 ohciWriteTd(pThis, TdAddr, pTd, "retired");
2469
2470 /*
2471 * If we've halted the endpoint, we stop here.
2472 * ohciUnlinkTds() will make sure we've only unliked the first TD.
2473 *
2474 * The reason for this is that while we can have more than one TD in a URB, real
2475 * OHCI hardware will only deal with one TD at the time and it's therefore incorrect
2476 * to retire TDs after the endpoint has been halted. Win2k will crash or enter infinite
2477 * kernel loop if we don't behave correctly. (See @bugref{1646}.)
2478 */
2479 if (pEd->HeadP & ED_HEAD_HALTED)
2480 break;
2481 }
2482}
2483
2484
2485/**
2486 * Transfer completion callback routine.
2487 *
2488 * VUSB will call this when a transfer have been completed
2489 * in a one or another way.
2490 *
2491 * @param pInterface Pointer to OHCI::ROOTHUB::IRhPort.
2492 * @param pUrb Pointer to the URB in question.
2493 */
2494static DECLCALLBACK(void) ohciRhXferCompletion(PVUSBIROOTHUBPORT pInterface, PVUSBURB pUrb)
2495{
2496 POHCI pThis = VUSBIROOTHUBPORT_2_OHCI(pInterface);
2497 LogFlow(("%s: ohciRhXferCompletion: EdAddr=%#010RX32 cTds=%d TdAddr0=%#010RX32\n",
2498 pUrb->pszDesc, pUrb->pHci->EdAddr, pUrb->pHci->cTds, pUrb->paTds[0].TdAddr));
2499
2500 RTCritSectEnter(&pThis->CritSect);
2501 pThis->fIdle = false; /* Mark as active */
2502
2503 /* get the current end point descriptor. */
2504 OHCIED Ed;
2505 ohciReadEd(pThis, pUrb->pHci->EdAddr, &Ed);
2506
2507 /*
2508 * Check that the URB hasn't been canceled and then try unlink the TDs.
2509 *
2510 * We drop the URB if the ED is marked halted/skip ASSUMING that this
2511 * means the HCD has canceled the URB.
2512 *
2513 * If we succeed here (i.e. not dropping the URB), the TdCopy members will
2514 * be updated but not yet written. We will delay the writing till we're done
2515 * with the data copying, buffer pointer advancing and error handling.
2516 */
2517 int cFmAge = ohci_in_flight_remove_urb(pThis, pUrb);
2518 if (pUrb->enmStatus == VUSBSTATUS_UNDO)
2519 {
2520 /* Leave the TD alone - the HCD doesn't want us talking to the device. */
2521 Log(("%s: ohciRhXferCompletion: CANCELED {ED=%#010x cTds=%d TD0=%#010x age %d}\n",
2522 pUrb->pszDesc, pUrb->pHci->EdAddr, pUrb->pHci->cTds, pUrb->paTds[0].TdAddr, cFmAge));
2523 STAM_COUNTER_INC(&pThis->StatDroppedUrbs);
2524 RTCritSectLeave(&pThis->CritSect);
2525 return;
2526 }
2527 bool fHasBeenCanceled = false;
2528 if ( (Ed.HeadP & ED_HEAD_HALTED)
2529 || (Ed.hwinfo & ED_HWINFO_SKIP)
2530 || cFmAge < 0
2531 || (fHasBeenCanceled = ohciHasUrbBeenCanceled(pThis, pUrb, &Ed))
2532 || !ohciUnlinkTds(pThis, pUrb, &Ed)
2533 )
2534 {
2535 Log(("%s: ohciRhXferCompletion: DROPPED {ED=%#010x cTds=%d TD0=%#010x age %d} because:%s%s%s%s%s!!!\n",
2536 pUrb->pszDesc, pUrb->pHci->EdAddr, pUrb->pHci->cTds, pUrb->paTds[0].TdAddr, cFmAge,
2537 (Ed.HeadP & ED_HEAD_HALTED) ? " ep halted" : "",
2538 (Ed.hwinfo & ED_HWINFO_SKIP) ? " ep skip" : "",
2539 (Ed.HeadP & ED_PTR_MASK) != pUrb->paTds[0].TdAddr ? " ep head-changed" : "",
2540 cFmAge < 0 ? " td not-in-flight" : "",
2541 fHasBeenCanceled ? " td canceled" : ""));
2542 NOREF(fHasBeenCanceled);
2543 STAM_COUNTER_INC(&pThis->StatDroppedUrbs);
2544 RTCritSectLeave(&pThis->CritSect);
2545 return;
2546 }
2547
2548 /*
2549 * Complete the TD updating and write the back.
2550 * When appropriate also copy data back to the guest memory.
2551 */
2552 if (pUrb->enmType == VUSBXFERTYPE_ISOC)
2553 ohciRhXferCompleteIsochronousURB(pThis, pUrb, &Ed, cFmAge);
2554 else
2555 ohciRhXferCompleteGeneralURB(pThis, pUrb, &Ed, cFmAge);
2556
2557 /* finally write back the endpoint descriptor. */
2558 ohciWriteEd(pThis, pUrb->pHci->EdAddr, &Ed);
2559
2560 RTCritSectLeave(&pThis->CritSect);
2561}
2562
2563
2564/**
2565 * Handle transfer errors.
2566 *
2567 * VUSB calls this when a transfer attempt failed. This function will respond
2568 * indicating whether to retry or complete the URB with failure.
2569 *
2570 * @returns true if the URB should be retired.
2571 * @returns false if the URB should be retried.
2572 * @param pInterface Pointer to OHCI::ROOTHUB::IRhPort.
2573 * @param pUrb Pointer to the URB in question.
2574 */
2575static DECLCALLBACK(bool) ohciRhXferError(PVUSBIROOTHUBPORT pInterface, PVUSBURB pUrb)
2576{
2577 POHCI pThis = VUSBIROOTHUBPORT_2_OHCI(pInterface);
2578
2579 /*
2580 * Isochronous URBs can't be retried.
2581 */
2582 if (pUrb->enmType == VUSBXFERTYPE_ISOC)
2583 return true;
2584
2585 /*
2586 * Don't retry on stall.
2587 */
2588 if (pUrb->enmStatus == VUSBSTATUS_STALL)
2589 {
2590 Log2(("%s: ohciRhXferError: STALL, giving up.\n", pUrb->pszDesc));
2591 return true;
2592 }
2593
2594 RTCritSectEnter(&pThis->CritSect);
2595
2596 bool fRetire = false;
2597 /*
2598 * Check if the TDs still are valid.
2599 * This will make sure the TdCopy is up to date.
2600 */
2601 const uint32_t TdAddr = pUrb->paTds[0].TdAddr;
2602/** @todo IMPORTANT! we must check if the ED is still valid at this point!!! */
2603 if (ohciHasUrbBeenCanceled(pThis, pUrb, NULL))
2604 {
2605 Log(("%s: ohciRhXferError: TdAddr0=%#x canceled!\n", pUrb->pszDesc, TdAddr));
2606 fRetire = true;
2607 }
2608 else
2609 {
2610 /*
2611 * Get and update the error counter.
2612 */
2613 POHCITD pTd = (POHCITD)&pUrb->paTds[0].TdCopy[0];
2614 unsigned cErrs = (pTd->hwinfo & TD_HWINFO_ERRORS) >> TD_ERRORS_SHIFT;
2615 pTd->hwinfo &= ~TD_HWINFO_ERRORS;
2616 cErrs++;
2617 pTd->hwinfo |= (cErrs % TD_ERRORS_MAX) << TD_ERRORS_SHIFT;
2618 ohciWriteTd(pThis, TdAddr, pTd, "ohciRhXferError");
2619
2620 if (cErrs >= TD_ERRORS_MAX - 1)
2621 {
2622 Log2(("%s: ohciRhXferError: too many errors, giving up!\n", pUrb->pszDesc));
2623 fRetire = true;
2624 }
2625 else
2626 Log2(("%s: ohciRhXferError: cErrs=%d: retrying...\n", pUrb->pszDesc, cErrs));
2627 }
2628
2629 RTCritSectLeave(&pThis->CritSect);
2630 return fRetire;
2631}
2632
2633
2634/**
2635 * Service a general transport descriptor.
2636 */
2637static bool ohciServiceTd(POHCI pThis, VUSBXFERTYPE enmType, PCOHCIED pEd, uint32_t EdAddr, uint32_t TdAddr, uint32_t *pNextTdAddr, const char *pszListName)
2638{
2639 /*
2640 * Read the TD and setup the buffer data.
2641 */
2642 OHCITD Td;
2643 ohciReadTd(pThis, TdAddr, &Td);
2644 OHCIBUF Buf;
2645 ohciBufInit(&Buf, Td.cbp, Td.be);
2646
2647 *pNextTdAddr = Td.NextTD & ED_PTR_MASK;
2648
2649 /*
2650 * Determine the direction.
2651 */
2652 VUSBDIRECTION enmDir;
2653 switch (pEd->hwinfo & ED_HWINFO_DIR)
2654 {
2655 case ED_HWINFO_OUT: enmDir = VUSBDIRECTION_OUT; break;
2656 case ED_HWINFO_IN: enmDir = VUSBDIRECTION_IN; break;
2657 default:
2658 switch (Td.hwinfo & TD_HWINFO_DIR)
2659 {
2660 case TD_HWINFO_OUT: enmDir = VUSBDIRECTION_OUT; break;
2661 case TD_HWINFO_IN: enmDir = VUSBDIRECTION_IN; break;
2662 case 0: enmDir = VUSBDIRECTION_SETUP; break;
2663 default:
2664 Log(("ohciServiceTd: Invalid direction!!!! Td.hwinfo=%#x Ed.hwdinfo=%#x\n", Td.hwinfo, pEd->hwinfo));
2665 /* TODO: Do the correct thing here */
2666 return false;
2667 }
2668 break;
2669 }
2670
2671 pThis->fIdle = false; /* Mark as active */
2672
2673 /*
2674 * Allocate and initialize a new URB.
2675 */
2676 PVUSBURB pUrb = VUSBIRhNewUrb(pThis->RootHub.pIRhConn, pEd->hwinfo & ED_HWINFO_FUNCTION, NULL,
2677 enmType, enmDir, Buf.cbTotal, 1, NULL);
2678 if (!pUrb)
2679 return false; /* retry later... */
2680
2681 pUrb->EndPt = (pEd->hwinfo & ED_HWINFO_ENDPOINT) >> ED_HWINFO_ENDPOINT_SHIFT;
2682 pUrb->fShortNotOk = !(Td.hwinfo & TD_HWINFO_ROUNDING);
2683 pUrb->enmStatus = VUSBSTATUS_OK;
2684 pUrb->pHci->EdAddr = EdAddr;
2685 pUrb->pHci->fUnlinked = false;
2686 pUrb->pHci->cTds = 1;
2687 pUrb->paTds[0].TdAddr = TdAddr;
2688 pUrb->pHci->u32FrameNo = pThis->HcFmNumber;
2689 AssertCompile(sizeof(pUrb->paTds[0].TdCopy) >= sizeof(Td));
2690 memcpy(pUrb->paTds[0].TdCopy, &Td, sizeof(Td));
2691
2692 /* copy data if out bound transfer. */
2693 pUrb->cbData = Buf.cbTotal;
2694 if ( Buf.cbTotal
2695 && Buf.cVecs > 0
2696 && enmDir != VUSBDIRECTION_IN)
2697 {
2698 ohciPhysRead(pThis, Buf.aVecs[0].Addr, pUrb->abData, Buf.aVecs[0].cb);
2699 if (Buf.cVecs > 1)
2700 ohciPhysRead(pThis, Buf.aVecs[1].Addr, &pUrb->abData[Buf.aVecs[0].cb], Buf.aVecs[1].cb);
2701 }
2702
2703 /*
2704 * Submit the URB.
2705 */
2706 ohci_in_flight_add(pThis, TdAddr, pUrb);
2707 Log(("%s: ohciServiceTd: submitting TdAddr=%#010x EdAddr=%#010x cbData=%#x\n",
2708 pUrb->pszDesc, TdAddr, EdAddr, pUrb->cbData));
2709
2710 RTCritSectLeave(&pThis->CritSect);
2711 int rc = VUSBIRhSubmitUrb(pThis->RootHub.pIRhConn, pUrb, &pThis->RootHub.Led);
2712 RTCritSectEnter(&pThis->CritSect);
2713 if (RT_SUCCESS(rc))
2714 return true;
2715
2716 /* Failure cleanup. Can happen if we're still resetting the device or out of resources. */
2717 Log(("ohciServiceTd: failed submitting TdAddr=%#010x EdAddr=%#010x pUrb=%p!!\n",
2718 TdAddr, EdAddr, pUrb));
2719 ohci_in_flight_remove(pThis, TdAddr);
2720 return false;
2721}
2722
2723
2724/**
2725 * Service a the head TD of an endpoint.
2726 */
2727static bool ohciServiceHeadTd(POHCI pThis, VUSBXFERTYPE enmType, PCOHCIED pEd, uint32_t EdAddr, const char *pszListName)
2728{
2729 /*
2730 * Read the TD, after first checking if it's already in-flight.
2731 */
2732 uint32_t TdAddr = pEd->HeadP & ED_PTR_MASK;
2733 if (ohciIsTdInFlight(pThis, TdAddr))
2734 return false;
2735#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2736 ohci_in_done_queue_check(pThis, TdAddr);
2737#endif
2738 return ohciServiceTd(pThis, enmType, pEd, EdAddr, TdAddr, &TdAddr, pszListName);
2739}
2740
2741
2742/**
2743 * Service one or more general transport descriptors (bulk or interrupt).
2744 */
2745static bool ohciServiceTdMultiple(POHCI pThis, VUSBXFERTYPE enmType, PCOHCIED pEd, uint32_t EdAddr,
2746 uint32_t TdAddr, uint32_t *pNextTdAddr, const char *pszListName)
2747{
2748 /*
2749 * Read the TDs involved in this URB.
2750 */
2751 struct OHCITDENTRY
2752 {
2753 /** The TD. */
2754 OHCITD Td;
2755 /** The associated OHCI buffer tracker. */
2756 OHCIBUF Buf;
2757 /** The TD address. */
2758 uint32_t TdAddr;
2759 /** Pointer to the next element in the chain (stack). */
2760 struct OHCITDENTRY *pNext;
2761 } Head;
2762
2763 /* read the head */
2764 ohciReadTd(pThis, TdAddr, &Head.Td);
2765 ohciBufInit(&Head.Buf, Head.Td.cbp, Head.Td.be);
2766 Head.TdAddr = TdAddr;
2767 Head.pNext = NULL;
2768
2769 /* combine with more TDs. */
2770 struct OHCITDENTRY *pTail = &Head;
2771 unsigned cbTotal = pTail->Buf.cbTotal;
2772 unsigned cTds = 1;
2773 while ( (pTail->Buf.cbTotal == 0x1000 || pTail->Buf.cbTotal == 0x2000)
2774 && !(pTail->Td.hwinfo & TD_HWINFO_ROUNDING) /* This isn't right for *BSD, but let's not . */
2775 && (pTail->Td.NextTD & ED_PTR_MASK) != (pEd->TailP & ED_PTR_MASK)
2776 && cTds < 128)
2777 {
2778 struct OHCITDENTRY *pCur = (struct OHCITDENTRY *)alloca(sizeof(*pCur));
2779
2780 pCur->pNext = NULL;
2781 pCur->TdAddr = pTail->Td.NextTD & ED_PTR_MASK;
2782 ohciReadTd(pThis, pCur->TdAddr, &pCur->Td);
2783 ohciBufInit(&pCur->Buf, pCur->Td.cbp, pCur->Td.be);
2784
2785 /* Don't combine if the direction doesn't match up. There can't actually be
2786 * a mismatch for bulk/interrupt EPs unless the guest is buggy.
2787 */
2788 if ( (pCur->Td.hwinfo & (TD_HWINFO_DIR))
2789 != (Head.Td.hwinfo & (TD_HWINFO_DIR)))
2790 break;
2791
2792 pTail->pNext = pCur;
2793 pTail = pCur;
2794 cbTotal += pCur->Buf.cbTotal;
2795 cTds++;
2796 }
2797
2798 /* calc next TD address */
2799 *pNextTdAddr = pTail->Td.NextTD & ED_PTR_MASK;
2800
2801 /*
2802 * Determine the direction.
2803 */
2804 VUSBDIRECTION enmDir;
2805 switch (pEd->hwinfo & ED_HWINFO_DIR)
2806 {
2807 case ED_HWINFO_OUT: enmDir = VUSBDIRECTION_OUT; break;
2808 case ED_HWINFO_IN: enmDir = VUSBDIRECTION_IN; break;
2809 default:
2810 Log(("ohciServiceTdMultiple: WARNING! Ed.hwdinfo=%#x bulk or interrupt EP shouldn't rely on the TD for direction...\n", pEd->hwinfo));
2811 switch (Head.Td.hwinfo & TD_HWINFO_DIR)
2812 {
2813 case TD_HWINFO_OUT: enmDir = VUSBDIRECTION_OUT; break;
2814 case TD_HWINFO_IN: enmDir = VUSBDIRECTION_IN; break;
2815 default:
2816 Log(("ohciServiceTdMultiple: Invalid direction!!!! Head.Td.hwinfo=%#x Ed.hwdinfo=%#x\n", Head.Td.hwinfo, pEd->hwinfo));
2817 /* TODO: Do the correct thing here */
2818 return false;
2819 }
2820 break;
2821 }
2822
2823 pThis->fIdle = false; /* Mark as active */
2824
2825 /*
2826 * Allocate and initialize a new URB.
2827 */
2828 PVUSBURB pUrb = VUSBIRhNewUrb(pThis->RootHub.pIRhConn, pEd->hwinfo & ED_HWINFO_FUNCTION, NULL,
2829 enmType, enmDir, cbTotal, cTds, "ohciServiceTdMultiple");
2830 if (!pUrb)
2831 /* retry later... */
2832 return false;
2833 Assert(pUrb->cbData == cbTotal);
2834
2835 pUrb->enmType = enmType;
2836 pUrb->EndPt = (pEd->hwinfo & ED_HWINFO_ENDPOINT) >> ED_HWINFO_ENDPOINT_SHIFT;
2837 pUrb->enmDir = enmDir;
2838 pUrb->fShortNotOk = !(pTail->Td.hwinfo & TD_HWINFO_ROUNDING);
2839 pUrb->enmStatus = VUSBSTATUS_OK;
2840 pUrb->pHci->cTds = cTds;
2841 pUrb->pHci->EdAddr = EdAddr;
2842 pUrb->pHci->fUnlinked = false;
2843 pUrb->pHci->u32FrameNo = pThis->HcFmNumber;
2844
2845 /* Copy data and TD information. */
2846 unsigned iTd = 0;
2847 uint8_t *pb = &pUrb->abData[0];
2848 for (struct OHCITDENTRY *pCur = &Head; pCur; pCur = pCur->pNext, iTd++)
2849 {
2850 /* data */
2851 if ( cbTotal
2852 && enmDir != VUSBDIRECTION_IN
2853 && pCur->Buf.cVecs > 0)
2854 {
2855 ohciPhysRead(pThis, pCur->Buf.aVecs[0].Addr, pb, pCur->Buf.aVecs[0].cb);
2856 if (pCur->Buf.cVecs > 1)
2857 ohciPhysRead(pThis, pCur->Buf.aVecs[1].Addr, pb + pCur->Buf.aVecs[0].cb, pCur->Buf.aVecs[1].cb);
2858 }
2859 pb += pCur->Buf.cbTotal;
2860
2861 /* TD info */
2862 pUrb->paTds[iTd].TdAddr = pCur->TdAddr;
2863 AssertCompile(sizeof(pUrb->paTds[iTd].TdCopy) >= sizeof(pCur->Td));
2864 memcpy(pUrb->paTds[iTd].TdCopy, &pCur->Td, sizeof(pCur->Td));
2865 }
2866
2867 /*
2868 * Submit the URB.
2869 */
2870 ohci_in_flight_add_urb(pThis, pUrb);
2871 Log(("%s: ohciServiceTdMultiple: submitting cbData=%#x EdAddr=%#010x cTds=%d TdAddr0=%#010x\n",
2872 pUrb->pszDesc, pUrb->cbData, EdAddr, cTds, TdAddr));
2873 RTCritSectLeave(&pThis->CritSect);
2874 int rc = VUSBIRhSubmitUrb(pThis->RootHub.pIRhConn, pUrb, &pThis->RootHub.Led);
2875 RTCritSectEnter(&pThis->CritSect);
2876 if (RT_SUCCESS(rc))
2877 return true;
2878
2879 /* Failure cleanup. Can happen if we're still resetting the device or out of resources. */
2880 Log(("ohciServiceTdMultiple: failed submitting pUrb=%p cbData=%#x EdAddr=%#010x cTds=%d TdAddr0=%#010x - rc=%Rrc\n",
2881 pUrb, cbTotal, EdAddr, cTds, TdAddr, rc));
2882 for (struct OHCITDENTRY *pCur = &Head; pCur; pCur = pCur->pNext, iTd++)
2883 ohci_in_flight_remove(pThis, pCur->TdAddr);
2884 return false;
2885}
2886
2887
2888/**
2889 * Service the head TD of an endpoint.
2890 */
2891static bool ohciServiceHeadTdMultiple(POHCI pThis, VUSBXFERTYPE enmType, PCOHCIED pEd, uint32_t EdAddr, const char *pszListName)
2892{
2893 /*
2894 * First, check that it's not already in-flight.
2895 */
2896 uint32_t TdAddr = pEd->HeadP & ED_PTR_MASK;
2897 if (ohciIsTdInFlight(pThis, TdAddr))
2898 return false;
2899#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2900 ohci_in_done_queue_check(pThis, TdAddr);
2901#endif
2902 return ohciServiceTdMultiple(pThis, enmType, pEd, EdAddr, TdAddr, &TdAddr, pszListName);
2903}
2904
2905
2906/**
2907 * A worker for ohciServiceIsochronousEndpoint which unlinks a ITD
2908 * that belongs to the past.
2909 */
2910static bool ohciServiceIsochronousTdUnlink(POHCI pThis, POHCIITD pITd, uint32_t ITdAddr, uint32_t ITdAddrPrev,
2911 PVUSBURB pUrb, POHCIED pEd, uint32_t EdAddr)
2912{
2913 LogFlow(("%s%sohciServiceIsochronousTdUnlink: Unlinking ITD: ITdAddr=%#010x EdAddr=%#010x ITdAddrPrev=%#010x\n",
2914 pUrb ? pUrb->pszDesc : "", pUrb ? ": " : "", ITdAddr, EdAddr, ITdAddrPrev));
2915
2916 /*
2917 * Do the unlinking.
2918 */
2919 const uint32_t ITdAddrNext = pITd->NextTD & ED_PTR_MASK;
2920 if (ITdAddrPrev)
2921 {
2922 /* Get validate the previous TD */
2923 int iInFlightPrev = ohci_in_flight_find(pThis, ITdAddrPrev);
2924 AssertMsgReturn(iInFlightPrev >= 0, ("ITdAddr=%#RX32\n", ITdAddrPrev), false);
2925 PVUSBURB pUrbPrev = pThis->aInFlight[iInFlightPrev].pUrb;
2926 if (ohciHasUrbBeenCanceled(pThis, pUrbPrev, pEd)) /* ensures the copy is correct. */
2927 return false;
2928
2929 /* Update the copy and write it back. */
2930 POHCIITD pITdPrev = ((POHCIITD)pUrbPrev->paTds[0].TdCopy);
2931 pITdPrev->NextTD = (pITdPrev->NextTD & ~ED_PTR_MASK) | ITdAddrNext;
2932 ohciWriteITd(pThis, ITdAddrPrev, pITdPrev, "ohciServiceIsochronousEndpoint");
2933 }
2934 else
2935 {
2936 /* It's the head node. update the copy from the caller and write it back. */
2937 pEd->HeadP = (pEd->HeadP & ~ED_PTR_MASK) | ITdAddrNext;
2938 ohciWriteEd(pThis, EdAddr, pEd);
2939 }
2940
2941 /*
2942 * If it's in flight, just mark the URB as unlinked (there is only one ITD per URB atm).
2943 * Otherwise, retire it to the done queue with an error and cause a done line interrupt (?).
2944 */
2945 if (pUrb)
2946 {
2947 pUrb->pHci->fUnlinked = true;
2948 if (ohciHasUrbBeenCanceled(pThis, pUrb, pEd)) /* ensures the copy is correct (paranoia). */
2949 return false;
2950
2951 POHCIITD pITdCopy = ((POHCIITD)pUrb->paTds[0].TdCopy);
2952 pITd->NextTD = pITdCopy->NextTD &= ~ED_PTR_MASK;
2953 }
2954 else
2955 {
2956 pITd->HwInfo &= ~ITD_HWINFO_CC;
2957 pITd->HwInfo |= OHCI_CC_DATA_OVERRUN;
2958
2959 pITd->NextTD = pThis->done;
2960 pThis->done = ITdAddr;
2961
2962 pThis->dqic = 0;
2963 }
2964
2965 ohciWriteITd(pThis, ITdAddr, pITd, "ohciServiceIsochronousTdUnlink");
2966 return true;
2967}
2968
2969
2970/**
2971 * A worker for ohciServiceIsochronousEndpoint which submits the specified TD.
2972 *
2973 * @returns true on success.
2974 * @returns false on failure to submit.
2975 * @param R The start packet (frame) relative to the start of frame in HwInfo.
2976 */
2977static bool ohciServiceIsochronousTd(POHCI pThis, POHCIITD pITd, uint32_t ITdAddr, const unsigned R, PCOHCIED pEd, uint32_t EdAddr)
2978{
2979 /*
2980 * Determine the endpoint direction.
2981 */
2982 VUSBDIRECTION enmDir;
2983 switch (pEd->hwinfo & ED_HWINFO_DIR)
2984 {
2985 case ED_HWINFO_OUT: enmDir = VUSBDIRECTION_OUT; break;
2986 case ED_HWINFO_IN: enmDir = VUSBDIRECTION_IN; break;
2987 default:
2988 Log(("ohciServiceIsochronousTd: Invalid direction!!!! Ed.hwdinfo=%#x\n", pEd->hwinfo));
2989 /* Should probably raise an unrecoverable HC error here */
2990 return false;
2991 }
2992
2993 /*
2994 * Extract the packet sizes and calc the total URB size.
2995 */
2996 struct
2997 {
2998 uint16_t cb;
2999 uint16_t off;
3000 } aPkts[ITD_NUM_PSW];
3001
3002 /* first entry (R) */
3003 uint32_t cbTotal = 0;
3004 if (((uint32_t)pITd->aPSW[R] >> ITD_PSW_CC_SHIFT) < (OHCI_CC_NOT_ACCESSED_0 >> TD_HWINFO_CC_SHIFT))
3005 Log(("ITdAddr=%RX32 PSW%d.CC=%#x < 'Not Accessed'!\n", ITdAddr, R, pITd->aPSW[R] >> ITD_PSW_CC_SHIFT)); /* => Unrecoverable Error*/
3006 uint16_t offPrev = aPkts[0].off = (pITd->aPSW[R] & ITD_PSW_OFFSET);
3007
3008 /* R+1..cFrames */
3009 const unsigned cFrames = ((pITd->HwInfo & ITD_HWINFO_FC) >> ITD_HWINFO_FC_SHIFT) + 1;
3010 for (unsigned iR = R + 1; iR < cFrames; iR++)
3011 {
3012 const uint16_t PSW = pITd->aPSW[iR];
3013 const uint16_t off = aPkts[iR - R].off = (PSW & ITD_PSW_OFFSET);
3014 cbTotal += aPkts[iR - R - 1].cb = off - offPrev;
3015 if (off < offPrev)
3016 Log(("ITdAddr=%RX32 PSW%d.offset=%#x < offPrev=%#x!\n", ITdAddr, iR, off, offPrev)); /* => Unrecoverable Error*/
3017 if (((uint32_t)PSW >> ITD_PSW_CC_SHIFT) < (OHCI_CC_NOT_ACCESSED_0 >> TD_HWINFO_CC_SHIFT))
3018 Log(("ITdAddr=%RX32 PSW%d.CC=%#x < 'Not Accessed'!\n", ITdAddr, iR, PSW >> ITD_PSW_CC_SHIFT)); /* => Unrecoverable Error*/
3019 offPrev = off;
3020 }
3021
3022 /* calc offEnd and figure out the size of the last packet. */
3023 const uint32_t offEnd = (pITd->BE & 0xfff)
3024 + (((pITd->BE & ITD_BP0_MASK) != (pITd->BP0 & ITD_BP0_MASK)) << 12)
3025 + 1 /* BE is inclusive */;
3026 if (offEnd < offPrev)
3027 Log(("ITdAddr=%RX32 offEnd=%#x < offPrev=%#x!\n", ITdAddr, offEnd, offPrev)); /* => Unrecoverable Error*/
3028 cbTotal += aPkts[cFrames - 1 - R].cb = offEnd - offPrev;
3029 Assert(cbTotal <= 0x2000);
3030
3031 pThis->fIdle = false; /* Mark as active */
3032
3033 /*
3034 * Allocate and initialize a new URB.
3035 */
3036 PVUSBURB pUrb = VUSBIRhNewUrb(pThis->RootHub.pIRhConn, pEd->hwinfo & ED_HWINFO_FUNCTION, NULL,
3037 VUSBXFERTYPE_ISOC, enmDir, cbTotal, 1, NULL);
3038 if (!pUrb)
3039 /* retry later... */
3040 return false;
3041
3042 pUrb->EndPt = (pEd->hwinfo & ED_HWINFO_ENDPOINT) >> ED_HWINFO_ENDPOINT_SHIFT;
3043 pUrb->fShortNotOk = false;
3044 pUrb->enmStatus = VUSBSTATUS_OK;
3045 pUrb->pHci->EdAddr = EdAddr;
3046 pUrb->pHci->cTds = 1;
3047 pUrb->pHci->fUnlinked = false;
3048 pUrb->pHci->u32FrameNo = pThis->HcFmNumber;
3049 pUrb->paTds[0].TdAddr = ITdAddr;
3050 AssertCompile(sizeof(pUrb->paTds[0].TdCopy) >= sizeof(*pITd));
3051 memcpy(pUrb->paTds[0].TdCopy, pITd, sizeof(*pITd));
3052#if 0 /* color the data */
3053 memset(pUrb->abData, 0xfe, cbTotal);
3054#endif
3055
3056 /* copy the data */
3057 if ( cbTotal
3058 && enmDir != VUSBDIRECTION_IN)
3059 {
3060 const uint32_t off0 = pITd->aPSW[R] & ITD_PSW_OFFSET;
3061 if (off0 < 0x1000)
3062 {
3063 if (offEnd > 0x1000)
3064 {
3065 /* both pages. */
3066 const unsigned cb0 = 0x1000 - off0;
3067 ohciPhysRead(pThis, (pITd->BP0 & ITD_BP0_MASK) + off0, &pUrb->abData[0], cb0);
3068 ohciPhysRead(pThis, pITd->BE & ITD_BP0_MASK, &pUrb->abData[cb0], offEnd & 0xfff);
3069 }
3070 else /* a portion of the 1st page. */
3071 ohciPhysRead(pThis, (pITd->BP0 & ITD_BP0_MASK) + off0, pUrb->abData, offEnd - off0);
3072 }
3073 else /* a portion of the 2nd page. */
3074 ohciPhysRead(pThis, (pITd->BE & UINT32_C(0xfffff000)) + (off0 & 0xfff), pUrb->abData, cbTotal);
3075 }
3076
3077 /* setup the packets */
3078 pUrb->cIsocPkts = cFrames - R;
3079 unsigned off = 0;
3080 for (unsigned i = 0; i < pUrb->cIsocPkts; i++)
3081 {
3082 pUrb->aIsocPkts[i].enmStatus = VUSBSTATUS_NOT_ACCESSED;
3083 pUrb->aIsocPkts[i].off = off;
3084 off += pUrb->aIsocPkts[i].cb = aPkts[i].cb;
3085 }
3086 Assert(off == cbTotal);
3087
3088 /*
3089 * Submit the URB.
3090 */
3091 ohci_in_flight_add_urb(pThis, pUrb);
3092 Log(("%s: ohciServiceIsochronousTd: submitting cbData=%#x cIsocPkts=%d EdAddr=%#010x TdAddr=%#010x SF=%#x (%#x)\n",
3093 pUrb->pszDesc, pUrb->cbData, pUrb->cIsocPkts, EdAddr, ITdAddr, pITd->HwInfo & ITD_HWINFO_SF, pThis->HcFmNumber));
3094 RTCritSectLeave(&pThis->CritSect);
3095 int rc = VUSBIRhSubmitUrb(pThis->RootHub.pIRhConn, pUrb, &pThis->RootHub.Led);
3096 RTCritSectEnter(&pThis->CritSect);
3097 if (RT_SUCCESS(rc))
3098 return true;
3099
3100 /* Failure cleanup. Can happen if we're still resetting the device or out of resources. */
3101 Log(("ohciServiceIsochronousTd: failed submitting pUrb=%p cbData=%#x EdAddr=%#010x cTds=%d ITdAddr0=%#010x - rc=%Rrc\n",
3102 pUrb, cbTotal, EdAddr, 1, ITdAddr, rc));
3103 ohci_in_flight_remove(pThis, ITdAddr);
3104 return false;
3105}
3106
3107
3108/**
3109 * Service an isochronous endpoint.
3110 */
3111static void ohciServiceIsochronousEndpoint(POHCI pThis, POHCIED pEd, uint32_t EdAddr)
3112{
3113 /*
3114 * We currently process this as if the guest follows the interrupt end point chaining
3115 * hierarchy described in the documenation. This means that for an isochronous endpoint
3116 * with a 1 ms interval we expect to find in-flight TDs at the head of the list. We will
3117 * skip over all in-flight TDs which timeframe has been exceed. Those which aren't in
3118 * flight but which are too late will be retired (possibly out of order, but, we don't
3119 * care right now).
3120 *
3121 * When we reach a TD which still has a buffer which is due for take off, we will
3122 * stop iterating TDs. If it's in-flight, there isn't anything to be done. Otherwise
3123 * we will push it onto the runway for immediate take off. In this process we
3124 * might have to complete buffers which didn't make it on time, something which
3125 * complicates the kind of status info we need to keep around for the TD.
3126 *
3127 * Note: We're currently not making any attempt at reassembling ITDs into URBs.
3128 * However, this will become necessary because of EMT scheduling and guest
3129 * like linux using one TD for each frame (simple but inefficient for us).
3130 */
3131 OHCIITD ITd;
3132 uint32_t ITdAddr = pEd->HeadP & ED_PTR_MASK;
3133 uint32_t ITdAddrPrev = 0;
3134 uint32_t u32NextFrame = UINT32_MAX;
3135 const uint16_t u16CurFrame = pThis->HcFmNumber;
3136 for (;;)
3137 {
3138 /* check for end-of-chain. */
3139 if ( ITdAddr == (pEd->TailP & ED_PTR_MASK)
3140 || !ITdAddr)
3141 break;
3142
3143 /*
3144 * If isochronous endpoints are around, don't slow down the timer. Getting the timing right
3145 * is difficult enough as it is.
3146 */
3147 pThis->fIdle = false;
3148
3149 /*
3150 * Read the current ITD and check what we're supposed to do about it.
3151 */
3152 ohciReadITd(pThis, ITdAddr, &ITd);
3153 const uint32_t ITdAddrNext = ITd.NextTD & ED_PTR_MASK;
3154 const int16_t R = u16CurFrame - (uint16_t)(ITd.HwInfo & ITD_HWINFO_SF); /* 4.3.2.3 */
3155 const int16_t cFrames = ((ITd.HwInfo & ITD_HWINFO_FC) >> ITD_HWINFO_FC_SHIFT) + 1;
3156
3157 if (R < cFrames)
3158 {
3159 /*
3160 * It's inside the current or a future launch window.
3161 *
3162 * We will try maximize the TD in flight here to deal with EMT scheduling
3163 * issues and similar stuff which will screw up the time. So, we will only
3164 * stop submitting TD when we reach a gap (in time) or end of the list.
3165 */
3166 if ( R < 0 /* (a future frame) */
3167 && (uint16_t)u32NextFrame != (uint16_t)(ITd.HwInfo & ITD_HWINFO_SF))
3168 break;
3169 if (ohci_in_flight_find(pThis, ITdAddr) < 0)
3170 if (!ohciServiceIsochronousTd(pThis, &ITd, ITdAddr, R < 0 ? 0 : R, pEd, EdAddr))
3171 break;
3172
3173 ITdAddrPrev = ITdAddr;
3174 }
3175 else
3176 {
3177#if 1
3178 /*
3179 * Ok, the launch window for this TD has passed.
3180 * If it's not in flight it should be retired with a DataOverrun status (TD).
3181 *
3182 * Don't remove in-flight TDs before they complete.
3183 * Windows will, upon the completion of another ITD it seems, check for if
3184 * any other TDs has been unlinked. If we unlink them before they really
3185 * complete all the packet status codes will be NotAccessed and Windows
3186 * will fail the URB with status USBD_STATUS_ISOCH_REQUEST_FAILED.
3187 *
3188 * I don't know if unlinking TDs out of order could cause similar problems,
3189 * time will show.
3190 */
3191 int iInFlight = ohci_in_flight_find(pThis, ITdAddr);
3192 if (iInFlight >= 0)
3193 ITdAddrPrev = ITdAddr;
3194 else if (!ohciServiceIsochronousTdUnlink(pThis, &ITd, ITdAddr, ITdAddrPrev,
3195 NULL, pEd, EdAddr))
3196 {
3197 Log(("ohciServiceIsochronousEndpoint: Failed unlinking old ITD.\n"));
3198 break;
3199 }
3200#else /* BAD IDEA: */
3201 /*
3202 * Ok, the launch window for this TD has passed.
3203 * If it's not in flight it should be retired with a DataOverrun status (TD).
3204 *
3205 * If it's in flight we will try unlink it from the list prematurely to
3206 * help the guest to move on and shorten the list we have to walk. We currently
3207 * are successful with the first URB but then it goes too slowly...
3208 */
3209 int iInFlight = ohci_in_flight_find(pThis, ITdAddr);
3210 if (!ohciServiceIsochronousTdUnlink(pThis, &ITd, ITdAddr, ITdAddrPrev,
3211 iInFlight < 0 ? NULL : pThis->aInFlight[iInFlight].pUrb,
3212 pEd, EdAddr))
3213 {
3214 Log(("ohciServiceIsochronousEndpoint: Failed unlinking old ITD.\n"));
3215 break;
3216 }
3217#endif
3218 }
3219
3220 /* advance to the next ITD */
3221 ITdAddr = ITdAddrNext;
3222 u32NextFrame = (ITd.HwInfo & ITD_HWINFO_SF) + cFrames;
3223 }
3224}
3225
3226
3227/**
3228 * Checks if a endpoints has TDs queued and is ready to have them processed.
3229 *
3230 * @returns true if it's ok to process TDs.
3231 * @param pEd The endpoint data.
3232 */
3233DECLINLINE(bool) ohciIsEdReady(PCOHCIED pEd)
3234{
3235 return (pEd->HeadP & ED_PTR_MASK) != (pEd->TailP & ED_PTR_MASK)
3236 && !(pEd->HeadP & ED_HEAD_HALTED)
3237 && !(pEd->hwinfo & ED_HWINFO_SKIP);
3238}
3239
3240
3241/**
3242 * Checks if an endpoint has TDs queued (not necessarily ready to have them processed).
3243 *
3244 * @returns true if endpoint may have TDs queued.
3245 * @param pEd The endpoint data.
3246 */
3247DECLINLINE(bool) ohciIsEdPresent(PCOHCIED pEd)
3248{
3249 return (pEd->HeadP & ED_PTR_MASK) != (pEd->TailP & ED_PTR_MASK)
3250 && !(pEd->HeadP & ED_HEAD_HALTED);
3251}
3252
3253
3254/**
3255 * Services the bulk list.
3256 *
3257 * On the bulk list we must reassemble URBs from multiple TDs using heuristics
3258 * derived from USB tracing done in the guests and guest source code (when available).
3259 */
3260static void ohciServiceBulkList(POHCI pThis)
3261{
3262#ifdef LOG_ENABLED
3263 if (g_fLogBulkEPs)
3264 ohciDumpEdList(pThis, pThis->bulk_head, "Bulk before", true);
3265 if (pThis->bulk_cur)
3266 Log(("ohciServiceBulkList: bulk_cur=%#010x before listprocessing!!! HCD have positioned us!!!\n", pThis->bulk_cur));
3267#endif
3268
3269 /*
3270 * ", HC will start processing the Bulk list and will set BF [BulkListFilled] to 0"
3271 * - We've simplified and are always starting at the head of the list and working
3272 * our way thru to the end each time.
3273 */
3274 pThis->status &= ~OHCI_STATUS_BLF;
3275 pThis->fBulkNeedsCleaning = false;
3276 pThis->bulk_cur = 0;
3277
3278 uint32_t EdAddr = pThis->bulk_head;
3279 while (EdAddr)
3280 {
3281 OHCIED Ed;
3282 ohciReadEd(pThis, EdAddr, &Ed);
3283 Assert(!(Ed.hwinfo & ED_HWINFO_ISO)); /* the guest is screwing us */
3284 if (ohciIsEdReady(&Ed))
3285 {
3286 pThis->status |= OHCI_STATUS_BLF;
3287 pThis->fBulkNeedsCleaning = true;
3288
3289#if 1
3290 /*
3291
3292 * After we figured out that all the TDs submitted for dealing with MSD
3293 * read/write data really makes up on single URB, and that we must
3294 * reassemble these TDs into an URB before submitting it, there is no
3295 * longer any need for servicing anything other than the head *URB*
3296 * on a bulk endpoint.
3297 */
3298 ohciServiceHeadTdMultiple(pThis, VUSBXFERTYPE_BULK, &Ed, EdAddr, "Bulk");
3299#else
3300 /*
3301 * This alternative code was used before we started reassembling URBs from
3302 * multiple TDs. We keep it handy for debugging.
3303 */
3304 uint32_t TdAddr = Ed.HeadP & ED_PTR_MASK;
3305 if (!ohciIsTdInFlight(pThis, TdAddr))
3306 {
3307 do
3308 {
3309 if (!ohciServiceTdMultiple(pThis, VUSBXFERTYPE_BULK, &Ed, EdAddr, TdAddr, &TdAddr, "Bulk"))
3310 {
3311 LogFlow(("ohciServiceBulkList: ohciServiceTdMultiple -> false\n"));
3312 break;
3313 }
3314 if ( (TdAddr & ED_PTR_MASK) == (Ed.TailP & ED_PTR_MASK)
3315 || !TdAddr /* paranoia */)
3316 {
3317 LogFlow(("ohciServiceBulkList: TdAddr=%#010RX32 Ed.TailP=%#010RX32\n", TdAddr, Ed.TailP));
3318 break;
3319 }
3320
3321 ohciReadEd(pThis, EdAddr, &Ed); /* It might have been updated on URB completion. */
3322 } while (ohciIsEdReady(&Ed));
3323 }
3324#endif
3325 }
3326 else
3327 {
3328 if (Ed.hwinfo & ED_HWINFO_SKIP)
3329 {
3330 LogFlow(("ohciServiceBulkList: Ed=%#010RX32 Ed.TailP=%#010RX32 SKIP\n", EdAddr, Ed.TailP));
3331 /* If the ED is in 'skip' state, no transactions on it are allowed and we must
3332 * cancel outstanding URBs, if any.
3333 */
3334 uint32_t TdAddr = Ed.HeadP & ED_PTR_MASK;
3335 PVUSBURB pUrb = ohciTdInFlightUrb(pThis, TdAddr);
3336 if (pUrb)
3337 pThis->RootHub.pIRhConn->pfnCancelUrbsEp(pThis->RootHub.pIRhConn, pUrb);
3338 }
3339 }
3340
3341 /* next end point */
3342 EdAddr = Ed.NextED & ED_PTR_MASK;
3343
3344 }
3345
3346#ifdef LOG_ENABLED
3347 if (g_fLogBulkEPs)
3348 ohciDumpEdList(pThis, pThis->bulk_head, "Bulk after ", true);
3349#endif
3350}
3351
3352/**
3353 * Abort outstanding transfers on the bulk list.
3354 *
3355 * If the guest disabled bulk list processing, we must abort any outstanding transfers
3356 * (that is, cancel in-flight URBs associated with the list). This is required because
3357 * there may be outstanding read URBs that will never get a response from the device
3358 * and would block further communication.
3359 */
3360static void ohciUndoBulkList(POHCI pThis)
3361{
3362#ifdef LOG_ENABLED
3363 if (g_fLogBulkEPs)
3364 ohciDumpEdList(pThis, pThis->bulk_head, "Bulk before", true);
3365 if (pThis->bulk_cur)
3366 Log(("ohciUndoBulkList: bulk_cur=%#010x before list processing!!! HCD has positioned us!!!\n", pThis->bulk_cur));
3367#endif
3368
3369 /* This flag follows OHCI_STATUS_BLF, but BLF doesn't change when list processing is disabled. */
3370 pThis->fBulkNeedsCleaning = false;
3371
3372 uint32_t EdAddr = pThis->bulk_head;
3373 while (EdAddr)
3374 {
3375 OHCIED Ed;
3376 ohciReadEd(pThis, EdAddr, &Ed);
3377 Assert(!(Ed.hwinfo & ED_HWINFO_ISO)); /* the guest is screwing us */
3378 if (ohciIsEdPresent(&Ed))
3379 {
3380 uint32_t TdAddr = Ed.HeadP & ED_PTR_MASK;
3381 if (ohciIsTdInFlight(pThis, TdAddr))
3382 {
3383 LogFlow(("ohciUndoBulkList: Ed=%#010RX32 Ed.TailP=%#010RX32 UNDO\n", EdAddr, Ed.TailP));
3384 PVUSBURB pUrb = ohciTdInFlightUrb(pThis, TdAddr);
3385 if (pUrb)
3386 pThis->RootHub.pIRhConn->pfnCancelUrbsEp(pThis->RootHub.pIRhConn, pUrb);
3387 }
3388 }
3389 /* next endpoint */
3390 EdAddr = Ed.NextED & ED_PTR_MASK;
3391 }
3392}
3393
3394
3395/**
3396 * Services the control list.
3397 *
3398 * The control list has complex URB assembling, but that's taken
3399 * care of at VUSB level (unlike the other transfer types).
3400 */
3401static void ohciServiceCtrlList(POHCI pThis)
3402{
3403#ifdef LOG_ENABLED
3404 if (g_fLogControlEPs)
3405 ohciDumpEdList(pThis, pThis->ctrl_head, "Ctrl before", true);
3406 if (pThis->ctrl_cur)
3407 Log(("ohciServiceCtrlList: ctrl_cur=%010x before list processing!!! HCD have positioned us!!!\n", pThis->ctrl_cur));
3408#endif
3409
3410 /*
3411 * ", HC will start processing the list and will set ControlListFilled to 0"
3412 * - We've simplified and are always starting at the head of the list and working
3413 * our way thru to the end each time.
3414 */
3415 pThis->status &= ~OHCI_STATUS_CLF;
3416 pThis->ctrl_cur = 0;
3417
3418 uint32_t EdAddr = pThis->ctrl_head;
3419 while (EdAddr)
3420 {
3421 OHCIED Ed;
3422 ohciReadEd(pThis, EdAddr, &Ed);
3423 Assert(!(Ed.hwinfo & ED_HWINFO_ISO)); /* the guest is screwing us */
3424 if (ohciIsEdReady(&Ed))
3425 {
3426#if 1
3427 /*
3428 * Control TDs depends on order and stage. Only one can be in-flight
3429 * at any given time. OTOH, some stages are completed immediately,
3430 * so we process the list until we've got a head which is in-flight
3431 * or reach the end of the list.
3432 */
3433 do
3434 {
3435 if ( !ohciServiceHeadTd(pThis, VUSBXFERTYPE_CTRL, &Ed, EdAddr, "Control")
3436 || ohciIsTdInFlight(pThis, Ed.HeadP & ED_PTR_MASK))
3437 {
3438 pThis->status |= OHCI_STATUS_CLF;
3439 break;
3440 }
3441 ohciReadEd(pThis, EdAddr, &Ed); /* It might have been updated on URB completion. */
3442 } while (ohciIsEdReady(&Ed));
3443#else
3444 /* Simplistic, for debugging. */
3445 ohciServiceHeadTd(pThis, VUSBXFERTYPE_CTRL, &Ed, EdAddr, "Control");
3446 pThis->status |= OHCI_STATUS_CLF;
3447#endif
3448 }
3449
3450 /* next end point */
3451 EdAddr = Ed.NextED & ED_PTR_MASK;
3452 }
3453
3454#ifdef LOG_ENABLED
3455 if (g_fLogControlEPs)
3456 ohciDumpEdList(pThis, pThis->ctrl_head, "Ctrl after ", true);
3457#endif
3458}
3459
3460
3461/**
3462 * Services the periodic list.
3463 *
3464 * On the interrupt portion of the periodic list we must reassemble URBs from multiple
3465 * TDs using heuristics derived from USB tracing done in the guests and guest source
3466 * code (when available).
3467 */
3468static void ohciServicePeriodicList(POHCI pThis)
3469{
3470 /*
3471 * Read the list head from the HCCA.
3472 */
3473 const unsigned iList = pThis->HcFmNumber % OHCI_HCCA_NUM_INTR;
3474 uint32_t EdAddr;
3475 ohciGetDWords(pThis, pThis->hcca + iList * sizeof(EdAddr), &EdAddr, 1);
3476
3477#ifdef LOG_ENABLED
3478 const uint32_t EdAddrHead = EdAddr;
3479 if (g_fLogInterruptEPs)
3480 {
3481 char sz[48];
3482 RTStrPrintf(sz, sizeof(sz), "Int%02x before", iList);
3483 ohciDumpEdList(pThis, EdAddrHead, sz, true);
3484 }
3485#endif
3486
3487 /*
3488 * Iterate the endpoint list.
3489 */
3490 while (EdAddr)
3491 {
3492 OHCIED Ed;
3493 ohciReadEd(pThis, EdAddr, &Ed);
3494
3495 if (ohciIsEdReady(&Ed))
3496 {
3497 /*
3498 * "There is no separate head pointer of isochronous transfers. The first
3499 * isochronous Endpoint Descriptor simply links to the last interrupt
3500 * Endpoint Descriptor."
3501 */
3502 if (!(Ed.hwinfo & ED_HWINFO_ISO))
3503 {
3504 /*
3505 * Presently we will only process the head URB on an interrupt endpoint.
3506 */
3507 ohciServiceHeadTdMultiple(pThis, VUSBXFERTYPE_INTR, &Ed, EdAddr, "Periodic");
3508 }
3509 else if (pThis->ctl & OHCI_CTL_IE)
3510 {
3511 /*
3512 * Presently only the head ITD.
3513 */
3514 ohciServiceIsochronousEndpoint(pThis, &Ed, EdAddr);
3515 }
3516 else
3517 break;
3518 }
3519 else
3520 {
3521 if (Ed.hwinfo & ED_HWINFO_SKIP)
3522 {
3523 LogFlow(("ohciServicePeriodicList: Ed=%#010RX32 Ed.TailP=%#010RX32 SKIP\n", EdAddr, Ed.TailP));
3524 /* If the ED is in 'skip' state, no transactions on it are allowed and we must
3525 * cancel outstanding URBs, if any.
3526 */
3527 uint32_t TdAddr = Ed.HeadP & ED_PTR_MASK;
3528 PVUSBURB pUrb = ohciTdInFlightUrb(pThis, TdAddr);
3529 if (pUrb)
3530 pThis->RootHub.pIRhConn->pfnCancelUrbsEp(pThis->RootHub.pIRhConn, pUrb);
3531 }
3532 }
3533 /* next end point */
3534 EdAddr = Ed.NextED & ED_PTR_MASK;
3535 }
3536
3537#ifdef LOG_ENABLED
3538 if (g_fLogInterruptEPs)
3539 {
3540 char sz[48];
3541 RTStrPrintf(sz, sizeof(sz), "Int%02x after ", iList);
3542 ohciDumpEdList(pThis, EdAddrHead, sz, true);
3543 }
3544#endif
3545}
3546
3547
3548/**
3549 * Update the HCCA.
3550 *
3551 * @param pThis The OHCI instance data.
3552 */
3553static void ohciUpdateHCCA(POHCI pThis)
3554{
3555 struct ohci_hcca hcca;
3556 ohciPhysRead(pThis, pThis->hcca + OHCI_HCCA_OFS, &hcca, sizeof(hcca));
3557
3558 hcca.frame = RT_H2LE_U16((uint16_t)pThis->HcFmNumber);
3559 hcca.pad = 0;
3560
3561 bool fWriteDoneHeadInterrupt = false;
3562 if ( pThis->dqic == 0
3563 && (pThis->intr_status & OHCI_INTR_WRITE_DONE_HEAD) == 0)
3564 {
3565 uint32_t done = pThis->done;
3566
3567 if (pThis->intr_status & ~( OHCI_INTR_MASTER_INTERRUPT_ENABLED | OHCI_INTR_OWNERSHIP_CHANGE
3568 | OHCI_INTR_WRITE_DONE_HEAD) )
3569 done |= 0x1;
3570
3571 hcca.done = RT_H2LE_U32(done);
3572 pThis->done = 0;
3573 pThis->dqic = 0x7;
3574
3575 Log(("ohci: Writeback Done (%#010x) on frame %#x (age %#x)\n", hcca.done,
3576 pThis->HcFmNumber, pThis->HcFmNumber - pThis->u32FmDoneQueueTail));
3577#ifdef LOG_ENABLED
3578 ohciDumpTdQueue(pThis, hcca.done & ED_PTR_MASK, "DoneQueue");
3579#endif
3580 Assert(RT_OFFSETOF(struct ohci_hcca, done) == 4);
3581#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3582 ohci_in_done_queue_zap(pThis);
3583#endif
3584 fWriteDoneHeadInterrupt = true;
3585 }
3586
3587 ohciPhysWrite(pThis, pThis->hcca + OHCI_HCCA_OFS, (uint8_t *)&hcca, sizeof(hcca));
3588 if (fWriteDoneHeadInterrupt)
3589 ohciR3SetInterrupt(pThis, OHCI_INTR_WRITE_DONE_HEAD);
3590}
3591
3592
3593/**
3594 * Go over the in-flight URB list and cancel any URBs that are no longer in use.
3595 * This occurs when the host removes EDs or TDs from the lists and we don't notice
3596 * the sKip bit. Such URBs must be promptly canceled, otherwise there is a risk
3597 * they might "steal" data destined for another URB.
3598 */
3599static void ohciCancelOrphanedURBs(POHCI pThis)
3600{
3601 bool fValidHCCA = !( pThis->hcca >= OHCI_HCCA_MASK
3602 || pThis->hcca < ~OHCI_HCCA_MASK);
3603 unsigned i, cLeft;
3604 int j;
3605 uint32_t EdAddr;
3606 PVUSBURB pUrb;
3607
3608 /* If the HCCA is not currently valid, or there are no in-flight URBs,
3609 * there's nothing to do.
3610 */
3611 if (!fValidHCCA || !pThis->cInFlight)
3612 return;
3613
3614 /* Initially mark all in-flight URBs as inactive. */
3615 for (i = 0, cLeft = pThis->cInFlight; cLeft && i < RT_ELEMENTS(pThis->aInFlight); i++)
3616 {
3617 if (pThis->aInFlight[i].pUrb)
3618 {
3619 pThis->aInFlight[i].fInactive = true;
3620 cLeft--;
3621 }
3622 }
3623 Assert(cLeft == 0);
3624
3625 /* Go over all bulk/control/interrupt endpoint lists; any URB found in these lists
3626 * is marked as active again.
3627 */
3628 for (i = 0; i < OHCI_HCCA_NUM_INTR + 2; i++)
3629 {
3630 switch (i)
3631 {
3632 case OHCI_HCCA_NUM_INTR:
3633 EdAddr = pThis->bulk_head;
3634 break;
3635 case OHCI_HCCA_NUM_INTR + 1:
3636 EdAddr = pThis->ctrl_head;
3637 break;
3638 default:
3639 ohciGetDWords(pThis, pThis->hcca + i * sizeof(EdAddr), &EdAddr, 1);
3640 break;
3641 }
3642 while (EdAddr)
3643 {
3644 OHCIED Ed;
3645 OHCITD Td;
3646 ohciReadEd(pThis, EdAddr, &Ed);
3647 uint32_t TdAddr = Ed.HeadP & ED_PTR_MASK;
3648 uint32_t TailP = Ed.TailP & ED_PTR_MASK;
3649 unsigned k = 0;
3650 if ( !(Ed.hwinfo & ED_HWINFO_SKIP)
3651 && (TdAddr != TailP))
3652 {
3653 do
3654 {
3655 ohciReadTd(pThis, TdAddr, &Td);
3656 j = ohci_in_flight_find(pThis, TdAddr);
3657 if (j > -1)
3658 pThis->aInFlight[j].fInactive = false;
3659 TdAddr = Td.NextTD & ED_PTR_MASK;
3660 /* Failsafe for temporarily looped lists. */
3661 if (++k == 128)
3662 break;
3663 } while (TdAddr != (Ed.TailP & ED_PTR_MASK));
3664 }
3665 EdAddr = Ed.NextED & ED_PTR_MASK;
3666 }
3667 }
3668
3669 /* In-flight URBs still marked as inactive are not used anymore and need
3670 * to be canceled.
3671 */
3672 for (i = 0, cLeft = pThis->cInFlight; cLeft && i < RT_ELEMENTS(pThis->aInFlight); i++)
3673 {
3674 if (pThis->aInFlight[i].pUrb)
3675 {
3676 cLeft--;
3677 pUrb = pThis->aInFlight[i].pUrb;
3678 if (pThis->aInFlight[i].fInactive
3679 && pUrb->enmState == VUSBURBSTATE_IN_FLIGHT
3680 && pUrb->enmType != VUSBXFERTYPE_CTRL)
3681 pThis->RootHub.pIRhConn->pfnCancelUrbsEp(pThis->RootHub.pIRhConn, pUrb);
3682 }
3683 }
3684 Assert(cLeft == 0);
3685}
3686
3687/**
3688 * Generate a Start-Of-Frame event, and set a timer for End-Of-Frame.
3689 */
3690static void ohciStartOfFrame(POHCI pThis)
3691{
3692#ifdef LOG_ENABLED
3693 const uint32_t status_old = pThis->status;
3694#endif
3695
3696 /*
3697 * Update HcFmRemaining.FRT and update start of frame time.
3698 */
3699 pThis->frt = pThis->fit;
3700 pThis->SofTime += pThis->cTicksPerFrame;
3701
3702 /*
3703 * Check that the HCCA address isn't bogus. Linux 2.4.x is known to start
3704 * the bus with a hcca of 0 to work around problem with a specific controller.
3705 */
3706 bool fValidHCCA = !( pThis->hcca >= OHCI_HCCA_MASK
3707 || pThis->hcca < ~OHCI_HCCA_MASK);
3708
3709#if 1
3710 /*
3711 * Update the HCCA.
3712 * Should be done after SOF but before HC read first ED in this frame.
3713 */
3714 if (fValidHCCA)
3715 ohciUpdateHCCA(pThis);
3716#endif
3717
3718 /* "After writing to HCCA, HC will set SF in HcInterruptStatus" - guest isn't executing, so ignore the order! */
3719 ohciR3SetInterrupt(pThis, OHCI_INTR_START_OF_FRAME);
3720
3721 if (pThis->fno)
3722 {
3723 ohciR3SetInterrupt(pThis, OHCI_INTR_FRAMENUMBER_OVERFLOW);
3724 pThis->fno = 0;
3725 }
3726
3727 /* If the HCCA address is invalid, we're quitting here to avoid doing something which cannot be reported to the HCD. */
3728 if (!fValidHCCA)
3729 {
3730 Log(("ohciStartOfFrame: skipping hcca part because hcca=%RX32 (our 'valid' range: %RX32-%RX32)\n",
3731 pThis->hcca, ~OHCI_HCCA_MASK, OHCI_HCCA_MASK));
3732 return;
3733 }
3734
3735 /*
3736 * Periodic EPs.
3737 */
3738 if (pThis->ctl & OHCI_CTL_PLE)
3739 ohciServicePeriodicList(pThis);
3740
3741 /*
3742 * Control EPs.
3743 */
3744 if ( (pThis->ctl & OHCI_CTL_CLE)
3745 && (pThis->status & OHCI_STATUS_CLF) )
3746 ohciServiceCtrlList(pThis);
3747
3748 /*
3749 * Bulk EPs.
3750 */
3751 if ( (pThis->ctl & OHCI_CTL_BLE)
3752 && (pThis->status & OHCI_STATUS_BLF))
3753 ohciServiceBulkList(pThis);
3754 else if ((pThis->status & OHCI_STATUS_BLF)
3755 && pThis->fBulkNeedsCleaning)
3756 ohciUndoBulkList(pThis); /* If list disabled but not empty, abort endpoints. */
3757
3758#if 0
3759 /*
3760 * Update the HCCA after processing the lists and everything. A bit experimental.
3761 *
3762 * ASSUME the guest won't be very upset if a TD is completed, retired and handed
3763 * back immediately. The idea is to be able to retire the data and/or status stages
3764 * of a control transfer together with the setup stage, thus saving a frame. This
3765 * behaviour is should be perfectly ok, since the setup (and maybe data) stages
3766 * have already taken at least one frame to complete.
3767 *
3768 * But, when implementing the first synchronous virtual USB devices, we'll have to
3769 * verify that the guest doesn't choke when having a TD returned in the same frame
3770 * as it was submitted.
3771 */
3772 ohciUpdateHCCA(pThis);
3773#endif
3774
3775#ifdef LOG_ENABLED
3776 if (pThis->status ^ status_old)
3777 {
3778 uint32_t val = pThis->status;
3779 uint32_t chg = val ^ status_old; NOREF(chg);
3780 Log2(("ohciStartOfFrame: HcCommandStatus=%#010x: %sHCR=%d %sCLF=%d %sBLF=%d %sOCR=%d %sSOC=%d\n",
3781 val,
3782 chg & RT_BIT(0) ? "*" : "", val & 1,
3783 chg & RT_BIT(1) ? "*" : "", (val >> 1) & 1,
3784 chg & RT_BIT(2) ? "*" : "", (val >> 2) & 1,
3785 chg & RT_BIT(3) ? "*" : "", (val >> 3) & 1,
3786 chg & (3<<16)? "*" : "", (val >> 16) & 3));
3787 }
3788#endif
3789}
3790
3791/**
3792 * Updates the HcFmNumber and FNO registers.
3793 */
3794static void bump_frame_number(POHCI pThis)
3795{
3796 const uint16_t u16OldFmNumber = pThis->HcFmNumber++;
3797 if ((u16OldFmNumber ^ pThis->HcFmNumber) & RT_BIT(15))
3798 pThis->fno = 1;
3799}
3800
3801/**
3802 * Callback for periodic frame processing.
3803 */
3804static DECLCALLBACK(bool) ohciR3StartFrame(PVUSBIROOTHUBPORT pInterface, uint32_t u32FrameNo)
3805{
3806 POHCI pThis = VUSBIROOTHUBPORT_2_OHCI(pInterface);
3807
3808 RTCritSectEnter(&pThis->CritSect);
3809
3810 /* Reset idle detection flag */
3811 pThis->fIdle = true;
3812
3813 /* Frame boundary, so do EOF stuff here. */
3814 bump_frame_number(pThis);
3815 if ( (pThis->dqic != 0x7) && (pThis->dqic != 0))
3816 pThis->dqic--;
3817
3818 /* Clean up any URBs that have been removed. */
3819 ohciCancelOrphanedURBs(pThis);
3820
3821 /* Start the next frame. */
3822 ohciStartOfFrame(pThis);
3823
3824 RTCritSectLeave(&pThis->CritSect);
3825
3826 return pThis->fIdle;
3827}
3828
3829/**
3830 * @copydoc VUSBIROOTHUBPORT::pfnFramerateChanged.
3831 */
3832static DECLCALLBACK(void) ohciR3FrameRateChanged(PVUSBIROOTHUBPORT pInterface, uint32_t u32FrameRate)
3833{
3834 POHCI pThis = VUSBIROOTHUBPORT_2_OHCI(pInterface);
3835
3836 Assert(u32FrameRate <= OHCI_DEFAULT_TIMER_FREQ);
3837
3838 pThis->cTicksPerFrame = pThis->u64TimerHz / u32FrameRate;
3839 if (!pThis->cTicksPerFrame)
3840 pThis->cTicksPerFrame = 1;
3841 pThis->cTicksPerUsbTick = pThis->u64TimerHz >= VUSB_BUS_HZ ? pThis->u64TimerHz / VUSB_BUS_HZ : 1;
3842}
3843
3844/**
3845 * Do frame processing on frame boundary
3846 */
3847static DECLCALLBACK(void) ohciFrameBoundaryTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3848{
3849}
3850
3851/**
3852 * Start sending SOF tokens across the USB bus, lists are processed in
3853 * next frame
3854 */
3855static void ohciBusStart(POHCI pThis)
3856{
3857 VUSBIDevPowerOn(pThis->RootHub.pIDev);
3858 pThis->dqic = 0x7;
3859
3860 Log(("ohci: %s: Bus started\n", pThis->PciDev.name));
3861
3862 pThis->SofTime = PDMDevHlpTMTimeVirtGet(pThis->CTX_SUFF(pDevIns));
3863 int rc = pThis->RootHub.pIRhConn->pfnSetPeriodicFrameProcessing(pThis->RootHub.pIRhConn, OHCI_DEFAULT_TIMER_FREQ);
3864 AssertRC(rc);
3865}
3866
3867/**
3868 * Stop sending SOF tokens on the bus
3869 */
3870static void ohciBusStop(POHCI pThis)
3871{
3872 int rc = pThis->RootHub.pIRhConn->pfnSetPeriodicFrameProcessing(pThis->RootHub.pIRhConn, 0);
3873 AssertRC(rc);
3874 VUSBIDevPowerOff(pThis->RootHub.pIDev);
3875}
3876
3877/**
3878 * Move in to resume state
3879 */
3880static void ohciBusResume(POHCI pThis, bool fHardware)
3881{
3882 pThis->ctl &= ~OHCI_CTL_HCFS;
3883 pThis->ctl |= OHCI_USB_RESUME;
3884
3885 Log(("pThis: ohciBusResume fHardware=%RTbool RWE=%s\n",
3886 fHardware, (pThis->ctl & OHCI_CTL_RWE) ? "on" : "off"));
3887
3888 if (fHardware && (pThis->ctl & OHCI_CTL_RWE))
3889 ohciR3SetInterrupt(pThis, OHCI_INTR_RESUME_DETECT);
3890
3891 ohciBusStart(pThis);
3892}
3893
3894
3895/* Power a port up or down */
3896static void rhport_power(POHCIROOTHUB pRh, unsigned iPort, bool fPowerUp)
3897{
3898 POHCIHUBPORT pPort = &pRh->aPorts[iPort];
3899 bool fOldPPS = !!(pPort->fReg & OHCI_PORT_PPS);
3900 if (fPowerUp)
3901 {
3902 /* power up */
3903 if (pPort->pDev)
3904 pPort->fReg |= OHCI_PORT_R_CURRENT_CONNECT_STATUS;
3905 if (pPort->fReg & OHCI_PORT_R_CURRENT_CONNECT_STATUS)
3906 pPort->fReg |= OHCI_PORT_R_POWER_STATUS;
3907 if (pPort->pDev && !fOldPPS)
3908 VUSBIDevPowerOn(pPort->pDev);
3909 }
3910 else
3911 {
3912 /* power down */
3913 pPort->fReg &= ~( OHCI_PORT_R_POWER_STATUS
3914 | OHCI_PORT_R_CURRENT_CONNECT_STATUS
3915 | OHCI_PORT_R_SUSPEND_STATUS
3916 | OHCI_PORT_R_RESET_STATUS);
3917 if (pPort->pDev && fOldPPS)
3918 VUSBIDevPowerOff(pPort->pDev);
3919 }
3920}
3921
3922#endif /* IN_RING3 */
3923
3924/**
3925 * Read the HcRevision register.
3926 */
3927static int HcRevision_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
3928{
3929 Log2(("HcRevision_r() -> 0x10\n"));
3930 *pu32Value = 0x10; /* OHCI revision 1.0, no emulation. */
3931 return VINF_SUCCESS;
3932}
3933
3934/**
3935 * Write to the HcRevision register.
3936 */
3937static int HcRevision_w(POHCI pThis, uint32_t iReg, uint32_t u32Value)
3938{
3939 Log2(("HcRevision_w(%#010x) - denied\n", u32Value));
3940 AssertMsgFailed(("Invalid operation!!! u32Value=%#010x\n", u32Value));
3941 return VINF_SUCCESS;
3942}
3943
3944/**
3945 * Read the HcControl register.
3946 */
3947static int HcControl_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
3948{
3949 uint32_t ctl = pThis->ctl;
3950 Log2(("HcControl_r -> %#010x - CBSR=%d PLE=%d IE=%d CLE=%d BLE=%d HCFS=%#x IR=%d RWC=%d RWE=%d\n",
3951 ctl, ctl & 3, (ctl >> 2) & 1, (ctl >> 3) & 1, (ctl >> 4) & 1, (ctl >> 5) & 1, (ctl >> 6) & 3, (ctl >> 8) & 1,
3952 (ctl >> 9) & 1, (ctl >> 10) & 1));
3953 *pu32Value = ctl;
3954 return VINF_SUCCESS;
3955}
3956
3957/**
3958 * Write the HcControl register.
3959 */
3960static int HcControl_w(POHCI pThis, uint32_t iReg, uint32_t val)
3961{
3962 /* log it. */
3963 uint32_t chg = pThis->ctl ^ val; NOREF(chg);
3964 Log2(("HcControl_w(%#010x) => %sCBSR=%d %sPLE=%d %sIE=%d %sCLE=%d %sBLE=%d %sHCFS=%#x %sIR=%d %sRWC=%d %sRWE=%d\n",
3965 val,
3966 chg & 3 ? "*" : "", val & 3,
3967 chg & RT_BIT(2) ? "*" : "", (val >> 2) & 1,
3968 chg & RT_BIT(3) ? "*" : "", (val >> 3) & 1,
3969 chg & RT_BIT(4) ? "*" : "", (val >> 4) & 1,
3970 chg & RT_BIT(5) ? "*" : "", (val >> 5) & 1,
3971 chg & (3 << 6)? "*" : "", (val >> 6) & 3,
3972 chg & RT_BIT(8) ? "*" : "", (val >> 8) & 1,
3973 chg & RT_BIT(9) ? "*" : "", (val >> 9) & 1,
3974 chg & RT_BIT(10) ? "*" : "", (val >> 10) & 1));
3975 if (val & ~0x07ff)
3976 Log2(("Unknown bits %#x are set!!!\n", val & ~0x07ff));
3977
3978 /* see what changed and take action on that. */
3979 uint32_t old_state = pThis->ctl & OHCI_CTL_HCFS;
3980 uint32_t new_state = val & OHCI_CTL_HCFS;
3981
3982#ifdef IN_RING3
3983 pThis->ctl = val;
3984 if (new_state != old_state)
3985 {
3986 switch (new_state)
3987 {
3988 case OHCI_USB_OPERATIONAL:
3989 LogRel(("OHCI: USB Operational\n"));
3990 ohciBusStart(pThis);
3991 break;
3992 case OHCI_USB_SUSPEND:
3993 ohciBusStop(pThis);
3994 LogRel(("OHCI: USB Suspended\n"));
3995 break;
3996 case OHCI_USB_RESUME:
3997 LogRel(("OHCI: USB Resume\n"));
3998 ohciBusResume(pThis, false /* not hardware */);
3999 break;
4000 case OHCI_USB_RESET:
4001 {
4002 LogRel(("OHCI: USB Reset\n"));
4003 ohciBusStop(pThis);
4004 /** @todo This should probably do a real reset, but we don't implement
4005 * that correctly in the roothub reset callback yet. check it's
4006 * comments and argument for more details. */
4007 VUSBIDevReset(pThis->RootHub.pIDev, false /* don't do a real reset */, NULL, NULL, NULL);
4008 break;
4009 }
4010 }
4011 }
4012#else /* !IN_RING3 */
4013 if ( new_state != old_state )
4014 {
4015 Log2(("HcControl_w: state changed -> VINF_IOM_R3_MMIO_WRITE\n"));
4016 return VINF_IOM_R3_MMIO_WRITE;
4017 }
4018 pThis->ctl = val;
4019#endif /* !IN_RING3 */
4020
4021 return VINF_SUCCESS;
4022}
4023
4024/**
4025 * Read the HcCommandStatus register.
4026 */
4027static int HcCommandStatus_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
4028{
4029 uint32_t status = pThis->status;
4030 Log2(("HcCommandStatus_r() -> %#010x - HCR=%d CLF=%d BLF=%d OCR=%d SOC=%d\n",
4031 status, status & 1, (status >> 1) & 1, (status >> 2) & 1, (status >> 3) & 1, (status >> 16) & 3));
4032 *pu32Value = status;
4033 return VINF_SUCCESS;
4034}
4035
4036/**
4037 * Write to the HcCommandStatus register.
4038 */
4039static int HcCommandStatus_w(POHCI pThis, uint32_t iReg, uint32_t val)
4040{
4041 /* log */
4042 uint32_t chg = pThis->status ^ val; NOREF(chg);
4043 Log2(("HcCommandStatus_w(%#010x) => %sHCR=%d %sCLF=%d %sBLF=%d %sOCR=%d %sSOC=%d\n",
4044 val,
4045 chg & RT_BIT(0) ? "*" : "", val & 1,
4046 chg & RT_BIT(1) ? "*" : "", (val >> 1) & 1,
4047 chg & RT_BIT(2) ? "*" : "", (val >> 2) & 1,
4048 chg & RT_BIT(3) ? "*" : "", (val >> 3) & 1,
4049 chg & (3<<16)? "!!!":"", (pThis->status >> 16) & 3));
4050 if (val & ~0x0003000f)
4051 Log2(("Unknown bits %#x are set!!!\n", val & ~0x0003000f));
4052
4053 /* SOC is read-only */
4054 val = (val & ~OHCI_STATUS_SOC);
4055
4056#ifdef IN_RING3
4057 /* "bits written as '0' remain unchanged in the register" */
4058 pThis->status |= val;
4059 if (pThis->status & OHCI_STATUS_HCR)
4060 {
4061 LogRel(("OHCI: Software reset\n"));
4062 ohciDoReset(pThis, OHCI_USB_SUSPEND, false /* N/A */);
4063 }
4064#else
4065 if ((pThis->status | val) & OHCI_STATUS_HCR)
4066 {
4067 LogFlow(("HcCommandStatus_w: reset -> VINF_IOM_R3_MMIO_WRITE\n"));
4068 return VINF_IOM_R3_MMIO_WRITE;
4069 }
4070 pThis->status |= val;
4071#endif
4072 return VINF_SUCCESS;
4073}
4074
4075/**
4076 * Read the HcInterruptStatus register.
4077 */
4078static int HcInterruptStatus_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
4079{
4080 uint32_t val = pThis->intr_status;
4081 Log2(("HcInterruptStatus_r() -> %#010x - SO=%d WDH=%d SF=%d RD=%d UE=%d FNO=%d RHSC=%d OC=%d\n",
4082 val, val & 1, (val >> 1) & 1, (val >> 2) & 1, (val >> 3) & 1, (val >> 4) & 1, (val >> 5) & 1,
4083 (val >> 6) & 1, (val >> 30) & 1));
4084 *pu32Value = val;
4085 return VINF_SUCCESS;
4086}
4087
4088/**
4089 * Write to the HcInterruptStatus register.
4090 */
4091static int HcInterruptStatus_w(POHCI pThis, uint32_t iReg, uint32_t val)
4092{
4093 uint32_t res = pThis->intr_status & ~val;
4094 uint32_t chg = pThis->intr_status ^ res; NOREF(chg);
4095
4096 int rc = PDMCritSectEnter(&pThis->CsIrq, VINF_IOM_R3_MMIO_WRITE);
4097 if (rc != VINF_SUCCESS)
4098 return rc;
4099
4100 Log2(("HcInterruptStatus_w(%#010x) => %sSO=%d %sWDH=%d %sSF=%d %sRD=%d %sUE=%d %sFNO=%d %sRHSC=%d %sOC=%d\n",
4101 val,
4102 chg & RT_BIT(0) ? "*" : "", res & 1,
4103 chg & RT_BIT(1) ? "*" : "", (res >> 1) & 1,
4104 chg & RT_BIT(2) ? "*" : "", (res >> 2) & 1,
4105 chg & RT_BIT(3) ? "*" : "", (res >> 3) & 1,
4106 chg & RT_BIT(4) ? "*" : "", (res >> 4) & 1,
4107 chg & RT_BIT(5) ? "*" : "", (res >> 5) & 1,
4108 chg & RT_BIT(6) ? "*" : "", (res >> 6) & 1,
4109 chg & RT_BIT(30)? "*" : "", (res >> 30) & 1));
4110 if ( (val & ~0xc000007f)
4111 && val != 0xffffffff /* ignore clear-all-like requests from xp. */)
4112 Log2(("Unknown bits %#x are set!!!\n", val & ~0xc000007f));
4113
4114 /* "The Host Controller Driver may clear specific bits in this
4115 * register by writing '1' to bit positions to be cleared"
4116 */
4117 pThis->intr_status &= ~val;
4118 ohciUpdateInterruptLocked(pThis, "HcInterruptStatus_w");
4119 PDMCritSectLeave(&pThis->CsIrq);
4120 return VINF_SUCCESS;
4121}
4122
4123/**
4124 * Read the HcInterruptEnable register
4125 */
4126static int HcInterruptEnable_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
4127{
4128 uint32_t val = pThis->intr;
4129 Log2(("HcInterruptEnable_r() -> %#010x - SO=%d WDH=%d SF=%d RD=%d UE=%d FNO=%d RHSC=%d OC=%d MIE=%d\n",
4130 val, val & 1, (val >> 1) & 1, (val >> 2) & 1, (val >> 3) & 1, (val >> 4) & 1, (val >> 5) & 1,
4131 (val >> 6) & 1, (val >> 30) & 1, (val >> 31) & 1));
4132 *pu32Value = val;
4133 return VINF_SUCCESS;
4134}
4135
4136/**
4137 * Writes to the HcInterruptEnable register.
4138 */
4139static int HcInterruptEnable_w(POHCI pThis, uint32_t iReg, uint32_t val)
4140{
4141 uint32_t res = pThis->intr | val;
4142 uint32_t chg = pThis->intr ^ res; NOREF(chg);
4143
4144 int rc = PDMCritSectEnter(&pThis->CsIrq, VINF_IOM_R3_MMIO_WRITE);
4145 if (rc != VINF_SUCCESS)
4146 return rc;
4147
4148 Log2(("HcInterruptEnable_w(%#010x) => %sSO=%d %sWDH=%d %sSF=%d %sRD=%d %sUE=%d %sFNO=%d %sRHSC=%d %sOC=%d %sMIE=%d\n",
4149 val,
4150 chg & RT_BIT(0) ? "*" : "", res & 1,
4151 chg & RT_BIT(1) ? "*" : "", (res >> 1) & 1,
4152 chg & RT_BIT(2) ? "*" : "", (res >> 2) & 1,
4153 chg & RT_BIT(3) ? "*" : "", (res >> 3) & 1,
4154 chg & RT_BIT(4) ? "*" : "", (res >> 4) & 1,
4155 chg & RT_BIT(5) ? "*" : "", (res >> 5) & 1,
4156 chg & RT_BIT(6) ? "*" : "", (res >> 6) & 1,
4157 chg & RT_BIT(30) ? "*" : "", (res >> 30) & 1,
4158 chg & RT_BIT(31) ? "*" : "", (res >> 31) & 1));
4159 if (val & ~0xc000007f)
4160 Log2(("Uknown bits %#x are set!!!\n", val & ~0xc000007f));
4161
4162 pThis->intr |= val;
4163 ohciUpdateInterruptLocked(pThis, "HcInterruptEnable_w");
4164 PDMCritSectLeave(&pThis->CsIrq);
4165 return VINF_SUCCESS;
4166}
4167
4168/**
4169 * Reads the HcInterruptDisable register.
4170 */
4171static int HcInterruptDisable_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
4172{
4173#if 1 /** @todo r=bird: "On read, the current value of the HcInterruptEnable register is returned." */
4174 uint32_t val = pThis->intr;
4175#else /* old code. */
4176 uint32_t val = ~pThis->intr;
4177#endif
4178 Log2(("HcInterruptDisable_r() -> %#010x - SO=%d WDH=%d SF=%d RD=%d UE=%d FNO=%d RHSC=%d OC=%d MIE=%d\n",
4179 val, val & 1, (val >> 1) & 1, (val >> 2) & 1, (val >> 3) & 1, (val >> 4) & 1, (val >> 5) & 1,
4180 (val >> 6) & 1, (val >> 30) & 1, (val >> 31) & 1));
4181
4182 *pu32Value = val;
4183 return VINF_SUCCESS;
4184}
4185
4186/**
4187 * Writes to the HcInterruptDisable register.
4188 */
4189static int HcInterruptDisable_w(POHCI pThis, uint32_t iReg, uint32_t val)
4190{
4191 uint32_t res = pThis->intr & ~val;
4192 uint32_t chg = pThis->intr ^ res; NOREF(chg);
4193
4194 int rc = PDMCritSectEnter(&pThis->CsIrq, VINF_IOM_R3_MMIO_WRITE);
4195 if (rc != VINF_SUCCESS)
4196 return rc;
4197
4198 Log2(("HcInterruptDisable_w(%#010x) => %sSO=%d %sWDH=%d %sSF=%d %sRD=%d %sUE=%d %sFNO=%d %sRHSC=%d %sOC=%d %sMIE=%d\n",
4199 val,
4200 chg & RT_BIT(0) ? "*" : "", res & 1,
4201 chg & RT_BIT(1) ? "*" : "", (res >> 1) & 1,
4202 chg & RT_BIT(2) ? "*" : "", (res >> 2) & 1,
4203 chg & RT_BIT(3) ? "*" : "", (res >> 3) & 1,
4204 chg & RT_BIT(4) ? "*" : "", (res >> 4) & 1,
4205 chg & RT_BIT(5) ? "*" : "", (res >> 5) & 1,
4206 chg & RT_BIT(6) ? "*" : "", (res >> 6) & 1,
4207 chg & RT_BIT(30) ? "*" : "", (res >> 30) & 1,
4208 chg & RT_BIT(31) ? "*" : "", (res >> 31) & 1));
4209 /* Don't bitch about invalid bits here since it makes sense to disable
4210 * interrupts you don't know about. */
4211
4212 pThis->intr &= ~val;
4213 ohciUpdateInterruptLocked(pThis, "HcInterruptDisable_w");
4214 PDMCritSectLeave(&pThis->CsIrq);
4215 return VINF_SUCCESS;
4216}
4217
4218/**
4219 * Read the HcHCCA register (Host Controller Communications Area physical address).
4220 */
4221static int HcHCCA_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
4222{
4223 Log2(("HcHCCA_r() -> %#010x\n", pThis->hcca));
4224 *pu32Value = pThis->hcca;
4225 return VINF_SUCCESS;
4226}
4227
4228/**
4229 * Write to the HcHCCA register (Host Controller Communications Area physical address).
4230 */
4231static int HcHCCA_w(POHCI pThis, uint32_t iReg, uint32_t Value)
4232{
4233 Log2(("HcHCCA_w(%#010x) - old=%#010x new=%#010x\n", Value, pThis->hcca, Value & OHCI_HCCA_MASK));
4234 pThis->hcca = Value & OHCI_HCCA_MASK;
4235 return VINF_SUCCESS;
4236}
4237
4238/**
4239 * Read the HcPeriodCurrentED register.
4240 */
4241static int HcPeriodCurrentED_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
4242{
4243 Log2(("HcPeriodCurrentED_r() -> %#010x\n", pThis->per_cur));
4244 *pu32Value = pThis->per_cur;
4245 return VINF_SUCCESS;
4246}
4247
4248/**
4249 * Write to the HcPeriodCurrentED register.
4250 */
4251static int HcPeriodCurrentED_w(POHCI pThis, uint32_t iReg, uint32_t val)
4252{
4253 Log(("HcPeriodCurrentED_w(%#010x) - old=%#010x new=%#010x (This is a read only register, only the linux guys don't respect that!)\n",
4254 val, pThis->per_cur, val & ~7));
4255 //AssertMsgFailed(("HCD (Host Controller Driver) should not write to HcPeriodCurrentED! val=%#010x (old=%#010x)\n", val, pThis->per_cur));
4256 AssertMsg(!(val & 7), ("Invalid alignment, val=%#010x\n", val));
4257 pThis->per_cur = val & ~7;
4258 return VINF_SUCCESS;
4259}
4260
4261/**
4262 * Read the HcControlHeadED register.
4263 */
4264static int HcControlHeadED_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
4265{
4266 Log2(("HcControlHeadED_r() -> %#010x\n", pThis->ctrl_head));
4267 *pu32Value = pThis->ctrl_head;
4268 return VINF_SUCCESS;
4269}
4270
4271/**
4272 * Write to the HcControlHeadED register.
4273 */
4274static int HcControlHeadED_w(POHCI pThis, uint32_t iReg, uint32_t val)
4275{
4276 Log2(("HcControlHeadED_w(%#010x) - old=%#010x new=%#010x\n", val, pThis->ctrl_head, val & ~7));
4277 AssertMsg(!(val & 7), ("Invalid alignment, val=%#010x\n", val));
4278 pThis->ctrl_head = val & ~7;
4279 return VINF_SUCCESS;
4280}
4281
4282/**
4283 * Read the HcControlCurrentED register.
4284 */
4285static int HcControlCurrentED_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
4286{
4287 Log2(("HcControlCurrentED_r() -> %#010x\n", pThis->ctrl_cur));
4288 *pu32Value = pThis->ctrl_cur;
4289 return VINF_SUCCESS;
4290}
4291
4292/**
4293 * Write to the HcControlCurrentED register.
4294 */
4295static int HcControlCurrentED_w(POHCI pThis, uint32_t iReg, uint32_t val)
4296{
4297 Log2(("HcControlCurrentED_w(%#010x) - old=%#010x new=%#010x\n", val, pThis->ctrl_cur, val & ~7));
4298 AssertMsg(!(pThis->ctl & OHCI_CTL_CLE), ("Illegal write! HcControl.ControlListEnabled is set! val=%#010x\n", val));
4299 AssertMsg(!(val & 7), ("Invalid alignment, val=%#010x\n", val));
4300 pThis->ctrl_cur = val & ~7;
4301 return VINF_SUCCESS;
4302}
4303
4304/**
4305 * Read the HcBulkHeadED register.
4306 */
4307static int HcBulkHeadED_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
4308{
4309 Log2(("HcBulkHeadED_r() -> %#010x\n", pThis->bulk_head));
4310 *pu32Value = pThis->bulk_head;
4311 return VINF_SUCCESS;
4312}
4313
4314/**
4315 * Write to the HcBulkHeadED register.
4316 */
4317static int HcBulkHeadED_w(POHCI pThis, uint32_t iReg, uint32_t val)
4318{
4319 Log2(("HcBulkHeadED_w(%#010x) - old=%#010x new=%#010x\n", val, pThis->bulk_head, val & ~7));
4320 AssertMsg(!(val & 7), ("Invalid alignment, val=%#010x\n", val));
4321 pThis->bulk_head = val & ~7; /** @todo The ATI OHCI controller on my machine enforces 16-byte address alignment. */
4322 return VINF_SUCCESS;
4323}
4324
4325/**
4326 * Read the HcBulkCurrentED register.
4327 */
4328static int HcBulkCurrentED_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
4329{
4330 Log2(("HcBulkCurrentED_r() -> %#010x\n", pThis->bulk_cur));
4331 *pu32Value = pThis->bulk_cur;
4332 return VINF_SUCCESS;
4333}
4334
4335/**
4336 * Write to the HcBulkCurrentED register.
4337 */
4338static int HcBulkCurrentED_w(POHCI pThis, uint32_t iReg, uint32_t val)
4339{
4340 Log2(("HcBulkCurrentED_w(%#010x) - old=%#010x new=%#010x\n", val, pThis->bulk_cur, val & ~7));
4341 AssertMsg(!(pThis->ctl & OHCI_CTL_BLE), ("Illegal write! HcControl.BulkListEnabled is set! val=%#010x\n", val));
4342 AssertMsg(!(val & 7), ("Invalid alignment, val=%#010x\n", val));
4343 pThis->bulk_cur = val & ~7;
4344 return VINF_SUCCESS;
4345}
4346
4347
4348/**
4349 * Read the HcDoneHead register.
4350 */
4351static int HcDoneHead_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
4352{
4353 Log2(("HcDoneHead_r() -> 0x%#08x\n", pThis->done));
4354 *pu32Value = pThis->done;
4355 return VINF_SUCCESS;
4356}
4357
4358/**
4359 * Write to the HcDoneHead register.
4360 */
4361static int HcDoneHead_w(POHCI pThis, uint32_t iReg, uint32_t val)
4362{
4363 Log2(("HcDoneHead_w(0x%#08x) - denied!!!\n", val));
4364 /*AssertMsgFailed(("Illegal operation!!! val=%#010x\n", val)); - OS/2 does this */
4365 return VINF_SUCCESS;
4366}
4367
4368
4369/**
4370 * Read the HcFmInterval (Fm=Frame) register.
4371 */
4372static int HcFmInterval_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
4373{
4374 uint32_t val = (pThis->fit << 31) | (pThis->fsmps << 16) | (pThis->fi);
4375 Log2(("HcFmInterval_r() -> 0x%#08x - FI=%d FSMPS=%d FIT=%d\n",
4376 val, val & 0x3fff, (val >> 16) & 0x7fff, val >> 31));
4377 *pu32Value = val;
4378 return VINF_SUCCESS;
4379}
4380
4381/**
4382 * Write to the HcFmInterval (Fm = Frame) register.
4383 */
4384static int HcFmInterval_w(POHCI pThis, uint32_t iReg, uint32_t val)
4385{
4386 /* log */
4387 uint32_t chg = val ^ ((pThis->fit << 31) | (pThis->fsmps << 16) | pThis->fi); NOREF(chg);
4388 Log2(("HcFmInterval_w(%#010x) => %sFI=%d %sFSMPS=%d %sFIT=%d\n",
4389 val,
4390 chg & 0x00003fff ? "*" : "", val & 0x3fff,
4391 chg & 0x7fff0000 ? "*" : "", (val >> 16) & 0x7fff,
4392 chg >> 31 ? "*" : "", (val >> 31) & 1));
4393 if ( pThis->fi != (val & OHCI_FMI_FI) )
4394 {
4395 Log(("ohci: FrameInterval: %#010x -> %#010x\n", pThis->fi, val & OHCI_FMI_FI));
4396 AssertMsg(pThis->fit != ((val >> OHCI_FMI_FIT_SHIFT) & 1), ("HCD didn't toggle the FIT bit!!!\n"));
4397 }
4398
4399 /* update */
4400 pThis->fi = val & OHCI_FMI_FI;
4401 pThis->fit = (val & OHCI_FMI_FIT) >> OHCI_FMI_FIT_SHIFT;
4402 pThis->fsmps = (val & OHCI_FMI_FSMPS) >> OHCI_FMI_FSMPS_SHIFT;
4403 return VINF_SUCCESS;
4404}
4405
4406/**
4407 * Read the HcFmRemaining (Fm = Frame) register.
4408 */
4409static int HcFmRemaining_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
4410{
4411 uint32_t Value = pThis->frt << 31;
4412 if ((pThis->ctl & OHCI_CTL_HCFS) == OHCI_USB_OPERATIONAL)
4413 {
4414 /*
4415 * Being in USB operational state guarantees SofTime was set already.
4416 */
4417 uint64_t tks = PDMDevHlpTMTimeVirtGet(pThis->CTX_SUFF(pDevIns)) - pThis->SofTime;
4418 if (tks < pThis->cTicksPerFrame) /* avoid muldiv if possible */
4419 {
4420 uint16_t fr;
4421 tks = ASMMultU64ByU32DivByU32(1, tks, pThis->cTicksPerUsbTick);
4422 fr = (uint16_t)(pThis->fi - tks);
4423 Value |= fr;
4424 }
4425 }
4426
4427 Log2(("HcFmRemaining_r() -> %#010x - FR=%d FRT=%d\n", Value, Value & 0x3fff, Value >> 31));
4428 *pu32Value = Value;
4429 return VINF_SUCCESS;
4430}
4431
4432/**
4433 * Write to the HcFmRemaining (Fm = Frame) register.
4434 */
4435static int HcFmRemaining_w(POHCI pThis, uint32_t iReg, uint32_t val)
4436{
4437 Log2(("HcFmRemaining_w(%#010x) - denied\n", val));
4438 AssertMsgFailed(("Invalid operation!!! val=%#010x\n", val));
4439 return VINF_SUCCESS;
4440}
4441
4442/**
4443 * Read the HcFmNumber (Fm = Frame) register.
4444 */
4445static int HcFmNumber_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
4446{
4447 uint32_t val = (uint16_t)pThis->HcFmNumber;
4448 Log2(("HcFmNumber_r() -> %#010x - FN=%#x(%d) (32-bit=%#x(%d))\n", val, val, val, pThis->HcFmNumber, pThis->HcFmNumber));
4449 *pu32Value = val;
4450 return VINF_SUCCESS;
4451}
4452
4453/**
4454 * Write to the HcFmNumber (Fm = Frame) register.
4455 */
4456static int HcFmNumber_w(POHCI pThis, uint32_t iReg, uint32_t val)
4457{
4458 Log2(("HcFmNumber_w(%#010x) - denied\n", val));
4459 AssertMsgFailed(("Invalid operation!!! val=%#010x\n", val));
4460 return VINF_SUCCESS;
4461}
4462
4463/**
4464 * Read the HcPeriodicStart register.
4465 * The register determines when in a frame to switch from control&bulk to periodic lists.
4466 */
4467static int HcPeriodicStart_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
4468{
4469 Log2(("HcPeriodicStart_r() -> %#010x - PS=%d\n", pThis->pstart, pThis->pstart & 0x3fff));
4470 *pu32Value = pThis->pstart;
4471 return VINF_SUCCESS;
4472}
4473
4474/**
4475 * Write to the HcPeriodicStart register.
4476 * The register determines when in a frame to switch from control&bulk to periodic lists.
4477 */
4478static int HcPeriodicStart_w(POHCI pThis, uint32_t iReg, uint32_t val)
4479{
4480 Log2(("HcPeriodicStart_w(%#010x) => PS=%d\n", val, val & 0x3fff));
4481 if (val & ~0x3fff)
4482 Log2(("Unknown bits %#x are set!!!\n", val & ~0x3fff));
4483 pThis->pstart = val; /** @todo r=bird: should we support setting the other bits? */
4484 return VINF_SUCCESS;
4485}
4486
4487/**
4488 * Read the HcLSThreshold register.
4489 */
4490static int HcLSThreshold_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
4491{
4492 Log2(("HcLSThreshold_r() -> %#010x\n", OHCI_LS_THRESH));
4493 *pu32Value = OHCI_LS_THRESH;
4494 return VINF_SUCCESS;
4495}
4496
4497/**
4498 * Write to the HcLSThreshold register.
4499 *
4500 * Docs are inconsistent here:
4501 *
4502 * "Neither the Host Controller nor the Host Controller Driver are allowed to change this value."
4503 *
4504 * "This value is calculated by HCD with the consideration of transmission and setup overhead."
4505 *
4506 * The register is marked "R/W" the HCD column.
4507 *
4508 */
4509static int HcLSThreshold_w(POHCI pThis, uint32_t iReg, uint32_t val)
4510{
4511 Log2(("HcLSThreshold_w(%#010x) => LST=0x%03x(%d)\n", val, val & 0x0fff, val & 0x0fff));
4512 AssertMsg(val == OHCI_LS_THRESH,
4513 ("HCD tried to write bad LS threshold: 0x%x (see function header)\n", val));
4514 /** @todo the HCD can change this. */
4515 return VINF_SUCCESS;
4516}
4517
4518/**
4519 * Read the HcRhDescriptorA register.
4520 */
4521static int HcRhDescriptorA_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
4522{
4523 uint32_t val = pThis->RootHub.desc_a;
4524#if 0 /* annoying */
4525 Log2(("HcRhDescriptorA_r() -> %#010x - NDP=%d PSM=%d NPS=%d DT=%d OCPM=%d NOCP=%d POTGT=%#x\n",
4526 val, val & 0xff, (val >> 8) & 1, (val >> 9) & 1, (val >> 10) & 1, (val >> 11) & 1,
4527 (val >> 12) & 1, (val >> 24) & 0xff));
4528#endif
4529 *pu32Value = val;
4530 return VINF_SUCCESS;
4531}
4532
4533/**
4534 * Write to the HcRhDescriptorA register.
4535 */
4536static int HcRhDescriptorA_w(POHCI pThis, uint32_t iReg, uint32_t val)
4537{
4538 uint32_t chg = val ^ pThis->RootHub.desc_a; NOREF(chg);
4539 Log2(("HcRhDescriptorA_w(%#010x) => %sNDP=%d %sPSM=%d %sNPS=%d %sDT=%d %sOCPM=%d %sNOCP=%d %sPOTGT=%#x - %sPowerSwitching Set%sPower\n",
4540 val,
4541 chg & 0xff ?"!!!": "", val & 0xff,
4542 (chg >> 8) & 1 ? "*" : "", (val >> 8) & 1,
4543 (chg >> 9) & 1 ? "*" : "", (val >> 9) & 1,
4544 (chg >> 10) & 1 ?"!!!": "", 0,
4545 (chg >> 11) & 1 ? "*" : "", (val >> 11) & 1,
4546 (chg >> 12) & 1 ? "*" : "", (val >> 12) & 1,
4547 (chg >> 24)&0xff? "*" : "", (val >> 24) & 0xff,
4548 val & OHCI_RHA_NPS ? "No" : "",
4549 val & OHCI_RHA_PSM ? "Port" : "Global"));
4550 if (val & ~0xff001fff)
4551 Log2(("Unknown bits %#x are set!!!\n", val & ~0xff001fff));
4552
4553
4554 if ((val & (OHCI_RHA_NDP | OHCI_RHA_DT)) != OHCI_NDP_CFG(pThis))
4555 {
4556 Log(("ohci: %s: invalid write to NDP or DT in roothub descriptor A!!! val=0x%.8x\n",
4557 pThis->PciDev.name, val));
4558 val &= ~(OHCI_RHA_NDP | OHCI_RHA_DT);
4559 val |= OHCI_NDP_CFG(pThis);
4560 }
4561
4562 pThis->RootHub.desc_a = val;
4563 return VINF_SUCCESS;
4564}
4565
4566/**
4567 * Read the HcRhDescriptorB register.
4568 */
4569static int HcRhDescriptorB_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
4570{
4571 uint32_t val = pThis->RootHub.desc_b;
4572 Log2(("HcRhDescriptorB_r() -> %#010x - DR=0x%04x PPCM=0x%04x\n",
4573 val, val & 0xffff, val >> 16));
4574 *pu32Value = val;
4575 return VINF_SUCCESS;
4576}
4577
4578/**
4579 * Write to the HcRhDescriptorB register.
4580 */
4581static int HcRhDescriptorB_w(POHCI pThis, uint32_t iReg, uint32_t val)
4582{
4583 uint32_t chg = pThis->RootHub.desc_b ^ val; NOREF(chg);
4584 Log2(("HcRhDescriptorB_w(%#010x) => %sDR=0x%04x %sPPCM=0x%04x\n",
4585 val,
4586 chg & 0xffff ? "!!!" : "", val & 0xffff,
4587 chg >> 16 ? "!!!" : "", val >> 16));
4588
4589 if ( pThis->RootHub.desc_b != val )
4590 Log(("ohci: %s: unsupported write to root descriptor B!!! 0x%.8x -> 0x%.8x\n",
4591 pThis->PciDev.name,
4592 pThis->RootHub.desc_b, val));
4593 pThis->RootHub.desc_b = val;
4594 return VINF_SUCCESS;
4595}
4596
4597/**
4598 * Read the HcRhStatus (Rh = Root Hub) register.
4599 */
4600static int HcRhStatus_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
4601{
4602 uint32_t val = pThis->RootHub.status;
4603 if (val & (OHCI_RHS_LPSC | OHCI_RHS_OCIC))
4604 Log2(("HcRhStatus_r() -> %#010x - LPS=%d OCI=%d DRWE=%d LPSC=%d OCIC=%d CRWE=%d\n",
4605 val, val & 1, (val >> 1) & 1, (val >> 15) & 1, (val >> 16) & 1, (val >> 17) & 1, (val >> 31) & 1));
4606 *pu32Value = val;
4607 return VINF_SUCCESS;
4608}
4609
4610/**
4611 * Write to the HcRhStatus (Rh = Root Hub) register.
4612 */
4613static int HcRhStatus_w(POHCI pThis, uint32_t iReg, uint32_t val)
4614{
4615#ifdef IN_RING3
4616 /* log */
4617 uint32_t old = pThis->RootHub.status;
4618 uint32_t chg;
4619 if (val & ~0x80038003)
4620 Log2(("HcRhStatus_w: Unknown bits %#x are set!!!\n", val & ~0x80038003));
4621 if ( (val & OHCI_RHS_LPSC) && (val & OHCI_RHS_LPS) )
4622 Log2(("HcRhStatus_w: Warning both CGP and SGP are set! (Clear/Set Global Power)\n"));
4623 if ( (val & OHCI_RHS_DRWE) && (val & OHCI_RHS_CRWE) )
4624 Log2(("HcRhStatus_w: Warning both CRWE and SRWE are set! (Clear/Set Remote Wakeup Enable)\n"));
4625
4626
4627 /* write 1 to clear OCIC */
4628 if ( val & OHCI_RHS_OCIC )
4629 pThis->RootHub.status &= ~OHCI_RHS_OCIC;
4630
4631 /* SetGlobalPower */
4632 if ( val & OHCI_RHS_LPSC )
4633 {
4634 unsigned i;
4635 Log2(("ohci: %s: global power up\n", pThis->PciDev.name));
4636 for (i = 0; i < OHCI_NDP_CFG(pThis); i++)
4637 rhport_power(&pThis->RootHub, i, true /* power up */);
4638 }
4639
4640 /* ClearGlobalPower */
4641 if ( val & OHCI_RHS_LPS )
4642 {
4643 unsigned i;
4644 Log2(("ohci: %s: global power down\n", pThis->PciDev.name));
4645 for (i = 0; i < OHCI_NDP_CFG(pThis); i++)
4646 rhport_power(&pThis->RootHub, i, false /* power down */);
4647 }
4648
4649 if ( val & OHCI_RHS_DRWE )
4650 pThis->RootHub.status |= OHCI_RHS_DRWE;
4651
4652 if ( val & OHCI_RHS_CRWE )
4653 pThis->RootHub.status &= ~OHCI_RHS_DRWE;
4654
4655 chg = pThis->RootHub.status ^ old;
4656 Log2(("HcRhStatus_w(%#010x) => %sCGP=%d %sOCI=%d %sSRWE=%d %sSGP=%d %sOCIC=%d %sCRWE=%d\n",
4657 val,
4658 chg & 1 ? "*" : "", val & 1,
4659 (chg >> 1) & 1 ?"!!!": "", (val >> 1) & 1,
4660 (chg >> 15) & 1 ? "*" : "", (val >> 15) & 1,
4661 (chg >> 16) & 1 ? "*" : "", (val >> 16) & 1,
4662 (chg >> 17) & 1 ? "*" : "", (val >> 17) & 1,
4663 (chg >> 31) & 1 ? "*" : "", (val >> 31) & 1));
4664 return VINF_SUCCESS;
4665#else /* !IN_RING3 */
4666 return VINF_IOM_R3_MMIO_WRITE;
4667#endif /* !IN_RING3 */
4668}
4669
4670/**
4671 * Read the HcRhPortStatus register of a port.
4672 */
4673static int HcRhPortStatus_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
4674{
4675 const unsigned i = iReg - 21;
4676 uint32_t val = pThis->RootHub.aPorts[i].fReg | OHCI_PORT_R_POWER_STATUS; /* PortPowerStatus: see todo on power in _w function. */
4677 if (val & OHCI_PORT_R_RESET_STATUS)
4678 {
4679#ifdef IN_RING3
4680 RTThreadYield();
4681#else
4682 Log2(("HcRhPortStatus_r: yield -> VINF_IOM_R3_MMIO_READ\n"));
4683 return VINF_IOM_R3_MMIO_READ;
4684#endif
4685 }
4686 if (val & (OHCI_PORT_R_RESET_STATUS | OHCI_PORT_CSC | OHCI_PORT_PESC | OHCI_PORT_PSSC | OHCI_PORT_OCIC | OHCI_PORT_PRSC))
4687 Log2(("HcRhPortStatus_r(): port %u: -> %#010x - CCS=%d PES=%d PSS=%d POCI=%d RRS=%d PPS=%d LSDA=%d CSC=%d PESC=%d PSSC=%d OCIC=%d PRSC=%d\n",
4688 i, val, val & 1, (val >> 1) & 1, (val >> 2) & 1, (val >> 3) & 1, (val >> 4) & 1, (val >> 8) & 1, (val >> 9) & 1,
4689 (val >> 16) & 1, (val >> 17) & 1, (val >> 18) & 1, (val >> 19) & 1, (val >> 20) & 1));
4690 *pu32Value = val;
4691 return VINF_SUCCESS;
4692}
4693
4694#ifdef IN_RING3
4695/**
4696 * Completion callback for the vusb_dev_reset() operation.
4697 * @thread EMT.
4698 */
4699static DECLCALLBACK(void) uchi_port_reset_done(PVUSBIDEVICE pDev, int rc, void *pvUser)
4700{
4701 POHCI pThis = (POHCI)pvUser;
4702
4703 /*
4704 * Find the port in question
4705 */
4706 POHCIHUBPORT pPort = NULL;
4707 unsigned iPort;
4708 for (iPort = 0; iPort < OHCI_NDP_CFG(pThis); iPort++) /* lazy bird */
4709 if (pThis->RootHub.aPorts[iPort].pDev == pDev)
4710 {
4711 pPort = &pThis->RootHub.aPorts[iPort];
4712 break;
4713 }
4714 if (!pPort)
4715 {
4716 Assert(pPort); /* sometimes happens because of @bugref{1510} */
4717 return;
4718 }
4719
4720 if (RT_SUCCESS(rc))
4721 {
4722 /*
4723 * Successful reset.
4724 */
4725 Log2(("uchi_port_reset_done: Reset completed.\n"));
4726 pPort->fReg &= ~(OHCI_PORT_R_RESET_STATUS | OHCI_PORT_R_SUSPEND_STATUS | OHCI_PORT_R_SUSPEND_STATUS_CHANGE);
4727 pPort->fReg |= OHCI_PORT_R_ENABLE_STATUS | OHCI_PORT_R_RESET_STATUS_CHANGE;
4728 }
4729 else
4730 {
4731 /* desperate measures. */
4732 if ( pPort->pDev
4733 && VUSBIDevGetState(pPort->pDev) == VUSB_DEVICE_STATE_ATTACHED)
4734 {
4735 /*
4736 * Damn, something weird happened during reset. We'll pretend the user did an
4737 * incredible fast reconnect or something. (probably not gonna work)
4738 */
4739 Log2(("uchi_port_reset_done: The reset failed (rc=%Rrc)!!! Pretending reconnect at the speed of light.\n", rc));
4740 pPort->fReg = OHCI_PORT_R_CURRENT_CONNECT_STATUS | OHCI_PORT_R_CONNECT_STATUS_CHANGE;
4741 }
4742 else
4743 {
4744 /*
4745 * The device have / will be disconnected.
4746 */
4747 Log2(("uchi_port_reset_done: Disconnected (rc=%Rrc)!!!\n", rc));
4748 pPort->fReg &= ~(OHCI_PORT_R_RESET_STATUS | OHCI_PORT_R_SUSPEND_STATUS | OHCI_PORT_R_SUSPEND_STATUS_CHANGE | OHCI_PORT_R_RESET_STATUS_CHANGE);
4749 pPort->fReg |= OHCI_PORT_R_CONNECT_STATUS_CHANGE;
4750 }
4751 }
4752
4753 /* Raise roothub status change interrupt. */
4754 ohciR3SetInterrupt(pThis, OHCI_INTR_ROOT_HUB_STATUS_CHANGE);
4755}
4756
4757/**
4758 * Sets a flag in a port status register but only set it if a device is
4759 * connected, if not set ConnectStatusChange flag to force HCD to reevaluate
4760 * connect status.
4761 *
4762 * @returns true if device was connected and the flag was cleared.
4763 */
4764static bool rhport_set_if_connected(POHCIROOTHUB pRh, int iPort, uint32_t fValue)
4765{
4766 /*
4767 * Writing a 0 has no effect
4768 */
4769 if (fValue == 0)
4770 return false;
4771
4772 /*
4773 * If CurrentConnectStatus is cleared we set ConnectStatusChange.
4774 */
4775 if (!(pRh->aPorts[iPort].fReg & OHCI_PORT_R_CURRENT_CONNECT_STATUS))
4776 {
4777 pRh->aPorts[iPort].fReg |= OHCI_PORT_R_CONNECT_STATUS_CHANGE;
4778 ohciR3SetInterrupt(pRh->pOhci, OHCI_INTR_ROOT_HUB_STATUS_CHANGE);
4779 return false;
4780 }
4781
4782 bool fRc = !(pRh->aPorts[iPort].fReg & fValue);
4783
4784 /* set the bit */
4785 pRh->aPorts[iPort].fReg |= fValue;
4786
4787 return fRc;
4788}
4789#endif /* IN_RING3 */
4790
4791/**
4792 * Write to the HcRhPortStatus register of a port.
4793 */
4794static int HcRhPortStatus_w(POHCI pThis, uint32_t iReg, uint32_t val)
4795{
4796#ifdef IN_RING3
4797 const unsigned i = iReg - 21;
4798 POHCIHUBPORT p = &pThis->RootHub.aPorts[i];
4799 uint32_t old_state = p->fReg;
4800
4801#ifdef LOG_ENABLED
4802 /*
4803 * Log it.
4804 */
4805 static const char *apszCmdNames[32] =
4806 {
4807 "ClearPortEnable", "SetPortEnable", "SetPortSuspend", "!!!ClearSuspendStatus",
4808 "SetPortReset", "!!!5", "!!!6", "!!!7",
4809 "SetPortPower", "ClearPortPower", "!!!10", "!!!11",
4810 "!!!12", "!!!13", "!!!14", "!!!15",
4811 "ClearCSC", "ClearPESC", "ClearPSSC", "ClearOCIC",
4812 "ClearPRSC", "!!!21", "!!!22", "!!!23",
4813 "!!!24", "!!!25", "!!!26", "!!!27",
4814 "!!!28", "!!!29", "!!!30", "!!!31"
4815 };
4816 Log2(("HcRhPortStatus_w(%#010x): port %u:", val, i));
4817 for (unsigned j = 0; j < RT_ELEMENTS(apszCmdNames); j++)
4818 if (val & (1 << j))
4819 Log2((" %s", apszCmdNames[j]));
4820 Log2(("\n"));
4821#endif
4822
4823 /* Write to clear any of the change bits: CSC, PESC, PSSC, OCIC and PRSC */
4824 if (val & OHCI_PORT_W_CLEAR_CHANGE_MASK)
4825 p->fReg &= ~(val & OHCI_PORT_W_CLEAR_CHANGE_MASK);
4826
4827 if (val & OHCI_PORT_W_CLEAR_ENABLE)
4828 {
4829 p->fReg &= ~OHCI_PORT_R_ENABLE_STATUS;
4830 Log2(("HcRhPortStatus_w(): port %u: DISABLE\n", i));
4831 }
4832
4833 if (rhport_set_if_connected(&pThis->RootHub, i, val & OHCI_PORT_W_SET_ENABLE))
4834 Log2(("HcRhPortStatus_w(): port %u: ENABLE\n", i));
4835
4836 if (rhport_set_if_connected(&pThis->RootHub, i, val & OHCI_PORT_W_SET_SUSPEND))
4837 Log2(("HcRhPortStatus_w(): port %u: SUSPEND - not implemented correctly!!!\n", i));
4838
4839 if (val & OHCI_PORT_W_SET_RESET)
4840 {
4841 if (rhport_set_if_connected(&pThis->RootHub, i, val & OHCI_PORT_W_SET_RESET))
4842 {
4843 PVM pVM = PDMDevHlpGetVM(pThis->CTX_SUFF(pDevIns));
4844 p->fReg &= ~OHCI_PORT_R_RESET_STATUS_CHANGE;
4845 VUSBIDevReset(p->pDev, false /* don't reset on linux */, uchi_port_reset_done, pThis, pVM);
4846 }
4847 else if (p->fReg & OHCI_PORT_R_RESET_STATUS)
4848 {
4849 /* the guest is getting impatient. */
4850 Log2(("HcRhPortStatus_w(): port %u: Impatient guest!\n", i));
4851 RTThreadYield();
4852 }
4853 }
4854
4855 if (!(pThis->RootHub.desc_a & OHCI_RHA_NPS))
4856 {
4857 /** @todo To implement per-device power-switching
4858 * we need to check PortPowerControlMask to make
4859 * sure it isn't gang powered
4860 */
4861 if (val & OHCI_PORT_W_CLEAR_POWER)
4862 rhport_power(&pThis->RootHub, i, false /* power down */);
4863 if (val & OHCI_PORT_W_SET_POWER)
4864 rhport_power(&pThis->RootHub, i, true /* power up */);
4865 }
4866
4867 /** @todo r=frank: ClearSuspendStatus. Timing? */
4868 if (val & OHCI_PORT_W_CLEAR_SUSPEND_STATUS)
4869 {
4870 rhport_power(&pThis->RootHub, i, true /* power up */);
4871 pThis->RootHub.aPorts[i].fReg &= ~OHCI_PORT_R_SUSPEND_STATUS;
4872 pThis->RootHub.aPorts[i].fReg |= OHCI_PORT_R_SUSPEND_STATUS_CHANGE;
4873 ohciR3SetInterrupt(pThis, OHCI_INTR_ROOT_HUB_STATUS_CHANGE);
4874 }
4875
4876 if (p->fReg != old_state)
4877 {
4878 uint32_t res = p->fReg;
4879 uint32_t chg = res ^ old_state; NOREF(chg);
4880 Log2(("HcRhPortStatus_w(%#010x): port %u: => %sCCS=%d %sPES=%d %sPSS=%d %sPOCI=%d %sRRS=%d %sPPS=%d %sLSDA=%d %sCSC=%d %sPESC=%d %sPSSC=%d %sOCIC=%d %sPRSC=%d\n",
4881 val, i,
4882 chg & 1 ? "*" : "", res & 1,
4883 (chg >> 1) & 1 ? "*" : "", (res >> 1) & 1,
4884 (chg >> 2) & 1 ? "*" : "", (res >> 2) & 1,
4885 (chg >> 3) & 1 ? "*" : "", (res >> 3) & 1,
4886 (chg >> 4) & 1 ? "*" : "", (res >> 4) & 1,
4887 (chg >> 8) & 1 ? "*" : "", (res >> 8) & 1,
4888 (chg >> 9) & 1 ? "*" : "", (res >> 9) & 1,
4889 (chg >> 16) & 1 ? "*" : "", (res >> 16) & 1,
4890 (chg >> 17) & 1 ? "*" : "", (res >> 17) & 1,
4891 (chg >> 18) & 1 ? "*" : "", (res >> 18) & 1,
4892 (chg >> 19) & 1 ? "*" : "", (res >> 19) & 1,
4893 (chg >> 20) & 1 ? "*" : "", (res >> 20) & 1));
4894 }
4895 return VINF_SUCCESS;
4896#else /* !IN_RING3 */
4897 return VINF_IOM_R3_MMIO_WRITE;
4898#endif /* !IN_RING3 */
4899}
4900
4901/**
4902 * Register descriptor table
4903 */
4904static const OHCIOPREG g_aOpRegs[] =
4905{
4906 { "HcRevision", HcRevision_r, HcRevision_w }, /* 0 */
4907 { "HcControl", HcControl_r, HcControl_w }, /* 1 */
4908 { "HcCommandStatus", HcCommandStatus_r, HcCommandStatus_w }, /* 2 */
4909 { "HcInterruptStatus", HcInterruptStatus_r, HcInterruptStatus_w }, /* 3 */
4910 { "HcInterruptEnable", HcInterruptEnable_r, HcInterruptEnable_w }, /* 4 */
4911 { "HcInterruptDisable", HcInterruptDisable_r, HcInterruptDisable_w }, /* 5 */
4912 { "HcHCCA", HcHCCA_r, HcHCCA_w }, /* 6 */
4913 { "HcPeriodCurrentED", HcPeriodCurrentED_r, HcPeriodCurrentED_w }, /* 7 */
4914 { "HcControlHeadED", HcControlHeadED_r, HcControlHeadED_w }, /* 8 */
4915 { "HcControlCurrentED", HcControlCurrentED_r, HcControlCurrentED_w }, /* 9 */
4916 { "HcBulkHeadED", HcBulkHeadED_r, HcBulkHeadED_w }, /* 10 */
4917 { "HcBulkCurrentED", HcBulkCurrentED_r, HcBulkCurrentED_w }, /* 11 */
4918 { "HcDoneHead", HcDoneHead_r, HcDoneHead_w }, /* 12 */
4919 { "HcFmInterval", HcFmInterval_r, HcFmInterval_w }, /* 13 */
4920 { "HcFmRemaining", HcFmRemaining_r, HcFmRemaining_w }, /* 14 */
4921 { "HcFmNumber", HcFmNumber_r, HcFmNumber_w }, /* 15 */
4922 { "HcPeriodicStart", HcPeriodicStart_r, HcPeriodicStart_w }, /* 16 */
4923 { "HcLSThreshold", HcLSThreshold_r, HcLSThreshold_w }, /* 17 */
4924 { "HcRhDescriptorA", HcRhDescriptorA_r, HcRhDescriptorA_w }, /* 18 */
4925 { "HcRhDescriptorB", HcRhDescriptorB_r, HcRhDescriptorB_w }, /* 19 */
4926 { "HcRhStatus", HcRhStatus_r, HcRhStatus_w }, /* 20 */
4927
4928 /* The number of port status register depends on the definition
4929 * of OHCI_NDP_MAX macro
4930 */
4931 { "HcRhPortStatus[0]", HcRhPortStatus_r, HcRhPortStatus_w }, /* 21 */
4932 { "HcRhPortStatus[1]", HcRhPortStatus_r, HcRhPortStatus_w }, /* 22 */
4933 { "HcRhPortStatus[2]", HcRhPortStatus_r, HcRhPortStatus_w }, /* 23 */
4934 { "HcRhPortStatus[3]", HcRhPortStatus_r, HcRhPortStatus_w }, /* 24 */
4935 { "HcRhPortStatus[4]", HcRhPortStatus_r, HcRhPortStatus_w }, /* 25 */
4936 { "HcRhPortStatus[5]", HcRhPortStatus_r, HcRhPortStatus_w }, /* 26 */
4937 { "HcRhPortStatus[6]", HcRhPortStatus_r, HcRhPortStatus_w }, /* 27 */
4938 { "HcRhPortStatus[7]", HcRhPortStatus_r, HcRhPortStatus_w }, /* 28 */
4939 { "HcRhPortStatus[8]", HcRhPortStatus_r, HcRhPortStatus_w }, /* 29 */
4940 { "HcRhPortStatus[9]", HcRhPortStatus_r, HcRhPortStatus_w }, /* 30 */
4941 { "HcRhPortStatus[10]", HcRhPortStatus_r, HcRhPortStatus_w }, /* 31 */
4942 { "HcRhPortStatus[11]", HcRhPortStatus_r, HcRhPortStatus_w }, /* 32 */
4943 { "HcRhPortStatus[12]", HcRhPortStatus_r, HcRhPortStatus_w }, /* 33 */
4944 { "HcRhPortStatus[13]", HcRhPortStatus_r, HcRhPortStatus_w }, /* 34 */
4945 { "HcRhPortStatus[14]", HcRhPortStatus_r, HcRhPortStatus_w }, /* 35 */
4946};
4947
4948/* Quick way to determine how many op regs are valid. Since at least one port must
4949 * be configured (and no more than 15), there will be between 22 and 36 registers.
4950 */
4951#define NUM_OP_REGS(pohci) (21 + OHCI_NDP_CFG(pohci))
4952
4953AssertCompile(RT_ELEMENTS(g_aOpRegs) > 21);
4954AssertCompile(RT_ELEMENTS(g_aOpRegs) <= 36);
4955
4956/**
4957 * @callback_method_impl{FNIOMMMIOREAD}
4958 */
4959PDMBOTHCBDECL(int) ohciMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
4960{
4961 POHCI pThis = PDMINS_2_DATA(pDevIns, POHCI);
4962
4963 /* Paranoia: Assert that IOMMMIO_FLAGS_READ_DWORD works. */
4964 AssertReturn(cb == sizeof(uint32_t), VERR_INTERNAL_ERROR_3);
4965 AssertReturn(!(GCPhysAddr & 0x3), VERR_INTERNAL_ERROR_4);
4966
4967 /*
4968 * Validate the register and call the read operator.
4969 */
4970 int rc;
4971 const uint32_t iReg = (GCPhysAddr - pThis->MMIOBase) >> 2;
4972 if (iReg < NUM_OP_REGS(pThis))
4973 {
4974 const OHCIOPREG *pReg = &g_aOpRegs[iReg];
4975 rc = pReg->pfnRead(pThis, iReg, (uint32_t *)pv);
4976 }
4977 else
4978 {
4979 Log(("ohci: Trying to read register %u/%u!!!\n", iReg, NUM_OP_REGS(pThis)));
4980 rc = VINF_IOM_MMIO_UNUSED_FF;
4981 }
4982 return rc;
4983}
4984
4985
4986/**
4987 * @callback_method_impl{FNIOMMMIOWRITE}
4988 */
4989PDMBOTHCBDECL(int) ohciMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
4990{
4991 POHCI pThis = PDMINS_2_DATA(pDevIns, POHCI);
4992
4993 /* Paranoia: Assert that IOMMMIO_FLAGS_WRITE_DWORD_ZEROED works. */
4994 AssertReturn(cb == sizeof(uint32_t), VERR_INTERNAL_ERROR_3);
4995 AssertReturn(!(GCPhysAddr & 0x3), VERR_INTERNAL_ERROR_4);
4996
4997 /*
4998 * Validate the register and call the read operator.
4999 */
5000 int rc;
5001 const uint32_t iReg = (GCPhysAddr - pThis->MMIOBase) >> 2;
5002 if (iReg < NUM_OP_REGS(pThis))
5003 {
5004 const OHCIOPREG *pReg = &g_aOpRegs[iReg];
5005 rc = pReg->pfnWrite(pThis, iReg, *(uint32_t const *)pv);
5006 }
5007 else
5008 {
5009 Log(("ohci: Trying to write to register %u/%u!!!\n", iReg, NUM_OP_REGS(pThis)));
5010 rc = VINF_SUCCESS;
5011 }
5012 return rc;
5013}
5014
5015#ifdef IN_RING3
5016
5017/**
5018 * @callback_method_impl{FNPCIIOREGIONMAP}
5019 */
5020static DECLCALLBACK(int) ohciR3Map(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
5021{
5022 POHCI pThis = (POHCI)pPciDev;
5023 int rc = PDMDevHlpMMIORegister(pThis->CTX_SUFF(pDevIns), GCPhysAddress, cb, NULL /*pvUser*/,
5024 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED
5025 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
5026 ohciMmioWrite, ohciMmioRead, "USB OHCI");
5027 if (RT_FAILURE(rc))
5028 return rc;
5029
5030 if (pThis->fRZEnabled)
5031 {
5032 rc = PDMDevHlpMMIORegisterRC(pThis->CTX_SUFF(pDevIns), GCPhysAddress, cb,
5033 NIL_RTRCPTR /*pvUser*/, "ohciMmioWrite", "ohciMmioRead");
5034 if (RT_FAILURE(rc))
5035 return rc;
5036
5037 rc = PDMDevHlpMMIORegisterR0(pThis->CTX_SUFF(pDevIns), GCPhysAddress, cb,
5038 NIL_RTR0PTR /*pvUser*/, "ohciMmioWrite", "ohciMmioRead");
5039 if (RT_FAILURE(rc))
5040 return rc;
5041 }
5042
5043 pThis->MMIOBase = GCPhysAddress;
5044 return VINF_SUCCESS;
5045}
5046
5047
5048/**
5049 * Prepares for state saving.
5050 * All URBs needs to be canceled.
5051 *
5052 * @returns VBox status code.
5053 * @param pDevIns The device instance.
5054 * @param pSSM The handle to save the state to.
5055 */
5056static DECLCALLBACK(int) ohciR3SavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5057{
5058 POHCI pThis = PDMINS_2_DATA(pDevIns, POHCI);
5059 POHCIROOTHUB pRh = &pThis->RootHub;
5060 LogFlow(("ohciR3SavePrep: \n"));
5061
5062 /*
5063 * Detach all proxied devices.
5064 */
5065 PDMCritSectEnter(pThis->pDevInsR3->pCritSectRoR3, VERR_IGNORED);
5066 /** @todo this won't work well when continuing after saving! */
5067 for (unsigned i = 0; i < RT_ELEMENTS(pRh->aPorts); i++)
5068 {
5069 PVUSBIDEVICE pDev = pRh->aPorts[i].pDev;
5070 if (pDev)
5071 {
5072 if (!VUSBIDevIsSavedStateSupported(pDev))
5073 {
5074 VUSBIRhDetachDevice(pRh->pIRhConn, pDev);
5075 /*
5076 * Save the device pointers here so we can reattach them afterwards.
5077 * This will work fine even if the save fails since the Done handler is
5078 * called unconditionally if the Prep handler was called.
5079 */
5080 pRh->aPorts[i].pDev = pDev;
5081 }
5082 }
5083 }
5084
5085 /*
5086 * If the bus was started set the timer. This is ugly but avoids changing the
5087 * saved state version for now so we can backport the changes to other branches.
5088 */
5089 /** @todo: Do it properly for 4.4 by changing the saved state. */
5090 if (VUSBIRhGetPeriodicFrameRate(pRh->pIRhConn) != 0)
5091 {
5092 /* Calculate a new timer expiration so this saved state works with older releases. */
5093 uint64_t u64Expire = PDMDevHlpTMTimeVirtGet(pThis->CTX_SUFF(pDevIns)) + pThis->cTicksPerFrame;
5094
5095 LogFlowFunc(("Bus is active, setting timer to %llu\n", u64Expire));
5096 int rc = TMTimerSet(pThis->pEndOfFrameTimerR3, u64Expire);
5097 AssertRC(rc);
5098 }
5099
5100 PDMCritSectLeave(pThis->pDevInsR3->pCritSectRoR3);
5101
5102 /*
5103 * Kill old load data which might be hanging around.
5104 */
5105 if (pThis->pLoad)
5106 {
5107 TMR3TimerDestroy(pThis->pLoad->pTimer);
5108 MMR3HeapFree(pThis->pLoad);
5109 pThis->pLoad = NULL;
5110 }
5111 return VINF_SUCCESS;
5112}
5113
5114
5115/**
5116 * Saves the state of the OHCI device.
5117 *
5118 * @returns VBox status code.
5119 * @param pDevIns The device instance.
5120 * @param pSSM The handle to save the state to.
5121 */
5122static DECLCALLBACK(int) ohciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5123{
5124 POHCI pThis = PDMINS_2_DATA(pDevIns, POHCI);
5125 LogFlow(("ohciR3SaveExec: \n"));
5126
5127 int rc = SSMR3PutStructEx(pSSM, pThis, sizeof(*pThis), 0 /*fFlags*/, &g_aOhciFields[0], NULL);
5128 if (RT_SUCCESS(rc))
5129 rc = TMR3TimerSave(pThis->CTX_SUFF(pEndOfFrameTimer), pSSM);
5130 return rc;
5131}
5132
5133
5134/**
5135 * Done state save operation.
5136 *
5137 * @returns VBox load code.
5138 * @param pDevIns Device instance of the device which registered the data unit.
5139 * @param pSSM SSM operation handle.
5140 */
5141static DECLCALLBACK(int) ohciR3SaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5142{
5143 POHCI pThis = PDMINS_2_DATA(pDevIns, POHCI);
5144 POHCIROOTHUB pRh = &pThis->RootHub;
5145 OHCIROOTHUB Rh;
5146 unsigned i;
5147 LogFlow(("ohciR3SaveDone: \n"));
5148
5149 /*
5150 * NULL the dev pointers.
5151 */
5152 Rh = *pRh;
5153 for (i = 0; i < RT_ELEMENTS(pRh->aPorts); i++)
5154 {
5155 if ( pRh->aPorts[i].pDev
5156 && !VUSBIDevIsSavedStateSupported(pRh->aPorts[i].pDev))
5157 pRh->aPorts[i].pDev = NULL;
5158 }
5159
5160 /*
5161 * Attach the devices.
5162 */
5163 for (i = 0; i < RT_ELEMENTS(pRh->aPorts); i++)
5164 {
5165 PVUSBIDEVICE pDev = Rh.aPorts[i].pDev;
5166 if ( pDev
5167 && !VUSBIDevIsSavedStateSupported(pDev))
5168 VUSBIRhAttachDevice(pRh->pIRhConn, pDev);
5169 }
5170
5171 return VINF_SUCCESS;
5172}
5173
5174
5175/**
5176 * Prepare loading the state of the OHCI device.
5177 * This must detach the devices currently attached and save
5178 * the up for reconnect after the state load have been completed
5179 *
5180 * @returns VBox status code.
5181 * @param pDevIns The device instance.
5182 * @param pSSM The handle to the saved state.
5183 * @param u32Version The data unit version number.
5184 */
5185static DECLCALLBACK(int) ohciR3LoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5186{
5187 int rc = VINF_SUCCESS;
5188 POHCI pThis = PDMINS_2_DATA(pDevIns, POHCI);
5189 LogFlow(("ohciR3LoadPrep:\n"));
5190 if (!pThis->pLoad)
5191 {
5192 POHCIROOTHUB pRh = &pThis->RootHub;
5193 OHCILOAD Load;
5194 unsigned i;
5195
5196 /*
5197 * Detach all devices which are present in this session. Save them in the load
5198 * structure so we can reattach them after restoring the guest.
5199 */
5200 Load.pTimer = NULL;
5201 Load.cDevs = 0;
5202 for (i = 0; i < RT_ELEMENTS(pRh->aPorts); i++)
5203 {
5204 PVUSBIDEVICE pDev = pRh->aPorts[i].pDev;
5205 if ( pDev
5206 && !VUSBIDevIsSavedStateSupported(pDev))
5207 {
5208 Load.apDevs[Load.cDevs++] = pDev;
5209 VUSBIRhDetachDevice(pRh->pIRhConn, pDev);
5210 Assert(!pRh->aPorts[i].pDev);
5211 }
5212 }
5213
5214 /*
5215 * Any devices to reattach, if so duplicate the Load struct.
5216 */
5217 if (Load.cDevs)
5218 {
5219 pThis->pLoad = (POHCILOAD)PDMDevHlpMMHeapAlloc(pDevIns, sizeof(Load));
5220 if (!pThis->pLoad)
5221 return VERR_NO_MEMORY;
5222 *pThis->pLoad = Load;
5223 }
5224 }
5225 /* else: we ASSUME no device can be attached or detach in the period
5226 * between a state load and the pLoad stuff is processed. */
5227 return rc;
5228}
5229
5230
5231/**
5232 * Loads the state of the OHCI device.
5233 *
5234 * @returns VBox status code.
5235 * @param pDevIns The device instance.
5236 * @param pSSM The handle to the saved state.
5237 * @param uVersion The data unit version number.
5238 * @param uPass The data pass.
5239 */
5240static DECLCALLBACK(int) ohciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5241{
5242 POHCI pThis = PDMINS_2_DATA(pDevIns, POHCI);
5243 int rc;
5244 LogFlow(("ohciR3LoadExec:\n"));
5245 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
5246
5247 if (uVersion == OHCI_SAVED_STATE_VERSION)
5248 {
5249 rc = SSMR3GetStructEx(pSSM, pThis, sizeof(*pThis), 0 /*fFlags*/, &g_aOhciFields[0], NULL);
5250 if (RT_FAILURE(rc))
5251 return rc;
5252 }
5253 else if (uVersion == OHCI_SAVED_STATE_VERSION_8PORTS)
5254 {
5255 static SSMFIELD const s_aOhciFields8Ports[] =
5256 {
5257 SSMFIELD_ENTRY( OHCI, SofTime),
5258 SSMFIELD_ENTRY_CUSTOM( dpic+fno, RT_OFFSETOF(OHCI, SofTime) + RT_SIZEOFMEMB(OHCI, SofTime), 4),
5259 SSMFIELD_ENTRY( OHCI, RootHub.status),
5260 SSMFIELD_ENTRY( OHCI, RootHub.desc_a),
5261 SSMFIELD_ENTRY( OHCI, RootHub.desc_b),
5262 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[0].fReg),
5263 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[1].fReg),
5264 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[2].fReg),
5265 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[3].fReg),
5266 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[4].fReg),
5267 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[5].fReg),
5268 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[6].fReg),
5269 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[7].fReg),
5270 SSMFIELD_ENTRY( OHCI, ctl),
5271 SSMFIELD_ENTRY( OHCI, status),
5272 SSMFIELD_ENTRY( OHCI, intr_status),
5273 SSMFIELD_ENTRY( OHCI, intr),
5274 SSMFIELD_ENTRY( OHCI, hcca),
5275 SSMFIELD_ENTRY( OHCI, per_cur),
5276 SSMFIELD_ENTRY( OHCI, ctrl_cur),
5277 SSMFIELD_ENTRY( OHCI, ctrl_head),
5278 SSMFIELD_ENTRY( OHCI, bulk_cur),
5279 SSMFIELD_ENTRY( OHCI, bulk_head),
5280 SSMFIELD_ENTRY( OHCI, done),
5281 SSMFIELD_ENTRY_CUSTOM( fsmps+fit+fi+frt, RT_OFFSETOF(OHCI, done) + RT_SIZEOFMEMB(OHCI, done), 4),
5282 SSMFIELD_ENTRY( OHCI, HcFmNumber),
5283 SSMFIELD_ENTRY( OHCI, pstart),
5284 SSMFIELD_ENTRY_TERM()
5285 };
5286
5287 rc = SSMR3GetStructEx(pSSM, pThis, sizeof(*pThis), 0 /*fFlags*/, &s_aOhciFields8Ports[0], NULL);
5288 if (RT_FAILURE(rc))
5289 return rc;
5290 }
5291 else if (uVersion == OHCI_SAVED_STATE_VERSION_MEM_HELL)
5292 {
5293 static SSMFIELD const s_aOhciFields22[] =
5294 {
5295 SSMFIELD_ENTRY_OLD( PciDev.config, 256), /* DevPCI restores this. */
5296 SSMFIELD_ENTRY_OLD( PciDev.Int, 224),
5297 SSMFIELD_ENTRY_OLD( PciDev.devfn, 4),
5298 SSMFIELD_ENTRY_OLD( PciDev.Alignment0, 4),
5299 SSMFIELD_ENTRY_OLD_HCPTR( PciDev.name),
5300 SSMFIELD_ENTRY_OLD_HCPTR( PciDev.pDevIns),
5301 SSMFIELD_ENTRY_OLD_HCPTR( pDevInsR3),
5302 SSMFIELD_ENTRY_OLD_HCPTR( pEndOfFrameTimerR3),
5303 SSMFIELD_ENTRY_OLD_HCPTR( pDevInsR0),
5304 SSMFIELD_ENTRY_OLD_HCPTR( pEndOfFrameTimerR0),
5305 SSMFIELD_ENTRY_OLD_RCPTR( pDevInsRC),
5306 SSMFIELD_ENTRY_OLD_RCPTR( pEndOfFrameTimerRC),
5307 SSMFIELD_ENTRY( OHCI, SofTime),
5308 SSMFIELD_ENTRY_CUSTOM( dpic+fno, RT_OFFSETOF(OHCI, SofTime) + RT_SIZEOFMEMB(OHCI, SofTime), 4),
5309 SSMFIELD_ENTRY_OLD( MMIOBase, 4), /* DevPCI implicitly restores this. */
5310 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.pIBase),
5311 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.pIRhConn),
5312 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.pIDev),
5313 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.IBase.pfnQueryInterface),
5314 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.IRhPort.pfnGetAvailablePorts),
5315 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.IRhPort.pfnGetUSBVersions),
5316 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.IRhPort.pfnAttach),
5317 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.IRhPort.pfnDetach),
5318 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.IRhPort.pfnReset),
5319 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.IRhPort.pfnXferCompletion),
5320 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.IRhPort.pfnXferError),
5321 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.IRhPort.Alignment),
5322 SSMFIELD_ENTRY_OLD( RootHub.Led, 16), /* No device restored. */
5323 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.ILeds.pfnQueryStatusLed),
5324 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.pLedsConnector),
5325 SSMFIELD_ENTRY( OHCI, RootHub.status),
5326 SSMFIELD_ENTRY( OHCI, RootHub.desc_a),
5327 SSMFIELD_ENTRY( OHCI, RootHub.desc_b),
5328 SSMFIELD_ENTRY_OLD_PAD_HC64( RootHub.Alignment0, 4),
5329 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[0].fReg),
5330 SSMFIELD_ENTRY_OLD_PAD_HC64( RootHub.aPorts[0].Alignment0, 4),
5331 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.aPorts[0].pDev),
5332 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[1].fReg),
5333 SSMFIELD_ENTRY_OLD_PAD_HC64( RootHub.aPorts[1].Alignment0, 4),
5334 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.aPorts[1].pDev),
5335 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[2].fReg),
5336 SSMFIELD_ENTRY_OLD_PAD_HC64( RootHub.aPorts[2].Alignment0, 4),
5337 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.aPorts[2].pDev),
5338 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[3].fReg),
5339 SSMFIELD_ENTRY_OLD_PAD_HC64( RootHub.aPorts[3].Alignment0, 4),
5340 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.aPorts[3].pDev),
5341 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[4].fReg),
5342 SSMFIELD_ENTRY_OLD_PAD_HC64( RootHub.aPorts[4].Alignment0, 4),
5343 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.aPorts[4].pDev),
5344 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[5].fReg),
5345 SSMFIELD_ENTRY_OLD_PAD_HC64( RootHub.aPorts[5].Alignment0, 4),
5346 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.aPorts[5].pDev),
5347 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[6].fReg),
5348 SSMFIELD_ENTRY_OLD_PAD_HC64( RootHub.aPorts[6].Alignment0, 4),
5349 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.aPorts[6].pDev),
5350 SSMFIELD_ENTRY( OHCI, RootHub.aPorts[7].fReg),
5351 SSMFIELD_ENTRY_OLD_PAD_HC64( RootHub.aPorts[7].Alignment0, 4),
5352 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.aPorts[7].pDev),
5353 SSMFIELD_ENTRY_OLD_HCPTR( RootHub.pThis),
5354 SSMFIELD_ENTRY( OHCI, ctl),
5355 SSMFIELD_ENTRY( OHCI, status),
5356 SSMFIELD_ENTRY( OHCI, intr_status),
5357 SSMFIELD_ENTRY( OHCI, intr),
5358 SSMFIELD_ENTRY( OHCI, hcca),
5359 SSMFIELD_ENTRY( OHCI, per_cur),
5360 SSMFIELD_ENTRY( OHCI, ctrl_cur),
5361 SSMFIELD_ENTRY( OHCI, ctrl_head),
5362 SSMFIELD_ENTRY( OHCI, bulk_cur),
5363 SSMFIELD_ENTRY( OHCI, bulk_head),
5364 SSMFIELD_ENTRY( OHCI, done),
5365 SSMFIELD_ENTRY_CUSTOM( fsmps+fit+fi+frt, RT_OFFSETOF(OHCI, done) + RT_SIZEOFMEMB(OHCI, done), 4),
5366 SSMFIELD_ENTRY( OHCI, HcFmNumber),
5367 SSMFIELD_ENTRY( OHCI, pstart),
5368 SSMFIELD_ENTRY_OLD( cTicksPerFrame, 8), /* done by the constructor */
5369 SSMFIELD_ENTRY_OLD( cTicksPerUsbTick, 8), /* ditto */
5370 SSMFIELD_ENTRY_OLD( cInFlight, 4), /* no in-flight stuff when saving. */
5371 SSMFIELD_ENTRY_OLD( Alignment1, 4),
5372 SSMFIELD_ENTRY_OLD( aInFlight, 257 * 8),
5373 SSMFIELD_ENTRY_OLD_PAD_HC64( aInFlight, 257 * 8),
5374 SSMFIELD_ENTRY_OLD( cInDoneQueue, 4), /* strict builds only, so don't bother. */
5375 SSMFIELD_ENTRY_OLD( aInDoneQueue, 4*64),
5376 SSMFIELD_ENTRY_OLD( u32FmDoneQueueTail, 4), /* logging only */
5377 SSMFIELD_ENTRY_OLD_PAD_HC32( Alignment2, 4),
5378 SSMFIELD_ENTRY_OLD_HCPTR( pLoad),
5379 SSMFIELD_ENTRY_OLD( StatCanceledIsocUrbs, 8),
5380 SSMFIELD_ENTRY_OLD( StatCanceledGenUrbs, 8),
5381 SSMFIELD_ENTRY_OLD( StatDroppedUrbs, 8),
5382 SSMFIELD_ENTRY_OLD( StatTimer, 32),
5383 SSMFIELD_ENTRY_TERM()
5384 };
5385
5386 /* deserialize the struct */
5387 rc = SSMR3GetStructEx(pSSM, pThis, sizeof(*pThis), SSMSTRUCT_FLAGS_NO_MARKERS /*fFlags*/, &s_aOhciFields22[0], NULL);
5388 if (RT_FAILURE(rc))
5389 return rc;
5390
5391 /* check delimiter */
5392 uint32_t u32;
5393 rc = SSMR3GetU32(pSSM, &u32);
5394 if (RT_FAILURE(rc))
5395 return rc;
5396 AssertMsgReturn(u32 == ~0U, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5397 }
5398 else
5399 AssertMsgFailedReturn(("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5400
5401 /*
5402 * Finally restore the timer.
5403 */
5404 return TMR3TimerLoad(pThis->pEndOfFrameTimerR3, pSSM);
5405}
5406
5407
5408/**
5409 * Done state load operation.
5410 *
5411 * @returns VBox load code.
5412 * @param pDevIns Device instance of the device which registered the data unit.
5413 * @param pSSM SSM operation handle.
5414 */
5415static DECLCALLBACK(int) ohciR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5416{
5417 POHCI pThis = PDMINS_2_DATA(pDevIns, POHCI);
5418 LogFlow(("ohciR3LoadDone:\n"));
5419
5420 /*
5421 * Start a timer if we've got devices to reattach
5422 */
5423 if (pThis->pLoad)
5424 {
5425 int rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, ohciR3LoadReattachDevices, pThis,
5426 TMTIMER_FLAGS_NO_CRIT_SECT, "OHCI reattach devices on load",
5427 &pThis->pLoad->pTimer);
5428 if (RT_SUCCESS(rc))
5429 rc = TMTimerSetMillies(pThis->pLoad->pTimer, 250);
5430 return rc;
5431 }
5432
5433 return VINF_SUCCESS;
5434}
5435
5436
5437/**
5438 * Reattaches devices after a saved state load.
5439 */
5440static DECLCALLBACK(void) ohciR3LoadReattachDevices(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
5441{
5442 POHCI pThis = (POHCI)pvUser;
5443 POHCILOAD pLoad = pThis->pLoad;
5444 POHCIROOTHUB pRh = &pThis->RootHub;
5445 LogFlow(("ohciR3LoadReattachDevices:\n"));
5446
5447 /*
5448 * Reattach devices.
5449 */
5450 for (unsigned i = 0; i < pLoad->cDevs; i++)
5451 VUSBIRhAttachDevice(pRh->pIRhConn, pLoad->apDevs[i]);
5452
5453 /*
5454 * Cleanup.
5455 */
5456 TMR3TimerDestroy(pTimer);
5457 MMR3HeapFree(pLoad);
5458 pThis->pLoad = NULL;
5459}
5460
5461
5462/**
5463 * Reset notification.
5464 *
5465 * @returns VBox status code.
5466 * @param pDevIns The device instance data.
5467 */
5468static DECLCALLBACK(void) ohciR3Reset(PPDMDEVINS pDevIns)
5469{
5470 POHCI pThis = PDMINS_2_DATA(pDevIns, POHCI);
5471 LogFlow(("ohciR3Reset:\n"));
5472
5473 /*
5474 * There is no distinction between cold boot, warm reboot and software reboots,
5475 * all of these are treated as cold boots. We are also doing the initialization
5476 * job of a BIOS or SMM driver.
5477 *
5478 * Important: Don't confuse UsbReset with hardware reset. Hardware reset is
5479 * just one way of getting into the UsbReset state.
5480 */
5481 ohciDoReset(pThis, OHCI_USB_RESET, true /* reset devices */);
5482}
5483
5484
5485/**
5486 * Resume notification.
5487 *
5488 * @returns VBox status code.
5489 * @param pDevIns The device instance data.
5490 */
5491static DECLCALLBACK(void) ohciR3Resume(PPDMDEVINS pDevIns)
5492{
5493 POHCI pThis = PDMINS_2_DATA(pDevIns, POHCI);
5494 LogFlowFunc(("\n"));
5495
5496 /* Restart the frame thread if the timer is active. */
5497 if (TMTimerIsActive(pThis->pEndOfFrameTimerR3))
5498 {
5499 int rc = TMTimerStop(pThis->pEndOfFrameTimerR3);
5500 AssertRC(rc);
5501
5502 LogFlowFunc(("Bus was active, enable periodic frame processing\n"));
5503 rc = pThis->RootHub.pIRhConn->pfnSetPeriodicFrameProcessing(pThis->RootHub.pIRhConn, OHCI_DEFAULT_TIMER_FREQ);
5504 AssertRC(rc);
5505 }
5506}
5507
5508
5509/**
5510 * Info handler, device version. Dumps OHCI control registers.
5511 *
5512 * @param pDevIns Device instance which registered the info.
5513 * @param pHlp Callback functions for doing output.
5514 * @param pszArgs Argument string. Optional and specific to the handler.
5515 */
5516static DECLCALLBACK(void) ohciR3InfoRegs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5517{
5518 POHCI pThis = PDMINS_2_DATA(pDevIns, POHCI);
5519 uint32_t val, ctl, status;
5520
5521 /* Control register */
5522 ctl = pThis->ctl;
5523 pHlp->pfnPrintf(pHlp, "HcControl: %08x - CBSR=%d PLE=%d IE=%d CLE=%d BLE=%d HCFS=%#x IR=%d RWC=%d RWE=%d\n",
5524 ctl, ctl & 3, (ctl >> 2) & 1, (ctl >> 3) & 1, (ctl >> 4) & 1, (ctl >> 5) & 1, (ctl >> 6) & 3, (ctl >> 8) & 1,
5525 (ctl >> 9) & 1, (ctl >> 10) & 1);
5526
5527 /* Command status register */
5528 status = pThis->status;
5529 pHlp->pfnPrintf(pHlp, "HcCommandStatus: %08x - HCR=%d CLF=%d BLF=%d OCR=%d SOC=%d\n",
5530 status, status & 1, (status >> 1) & 1, (status >> 2) & 1, (status >> 3) & 1, (status >> 16) & 3);
5531
5532 /* Interrupt status register */
5533 val = pThis->intr_status;
5534 pHlp->pfnPrintf(pHlp, "HcInterruptStatus: %08x - SO=%d WDH=%d SF=%d RD=%d UE=%d FNO=%d RHSC=%d OC=%d\n",
5535 val, val & 1, (val >> 1) & 1, (val >> 2) & 1, (val >> 3) & 1, (val >> 4) & 1, (val >> 5) & 1,
5536 (val >> 6) & 1, (val >> 30) & 1);
5537
5538 /* Interrupt enable register */
5539 val = pThis->intr;
5540 pHlp->pfnPrintf(pHlp, "HcInterruptEnable: %08x - SO=%d WDH=%d SF=%d RD=%d UE=%d FNO=%d RHSC=%d OC=%d MIE=%d\n",
5541 val, val & 1, (val >> 1) & 1, (val >> 2) & 1, (val >> 3) & 1, (val >> 4) & 1, (val >> 5) & 1,
5542 (val >> 6) & 1, (val >> 30) & 1, (val >> 31) & 1);
5543
5544 /* HCCA address register */
5545 pHlp->pfnPrintf(pHlp, "HcHCCA: %08x\n", pThis->hcca);
5546
5547 /* Current periodic ED register */
5548 pHlp->pfnPrintf(pHlp, "HcPeriodCurrentED: %08x\n", pThis->per_cur);
5549
5550 /* Control ED registers */
5551 pHlp->pfnPrintf(pHlp, "HcControlHeadED: %08x\n", pThis->ctrl_head);
5552 pHlp->pfnPrintf(pHlp, "HcControlCurrentED: %08x\n", pThis->ctrl_cur);
5553
5554 /* Bulk ED registers */
5555 pHlp->pfnPrintf(pHlp, "HcBulkHeadED: %08x\n", pThis->bulk_head);
5556 pHlp->pfnPrintf(pHlp, "HcBulkCurrentED: %08x\n", pThis->bulk_cur);
5557
5558 /* Done head register */
5559 pHlp->pfnPrintf(pHlp, "HcDoneHead: %08x\n", pThis->done);
5560
5561 pHlp->pfnPrintf(pHlp, "\n");
5562}
5563
5564
5565/**
5566 * Relocate device instance data.
5567 *
5568 * @returns VBox status code.
5569 * @param pDevIns The device instance data.
5570 * @param offDelta The relocation delta.
5571 */
5572static DECLCALLBACK(void) ohciR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
5573{
5574 POHCI pThis = PDMINS_2_DATA(pDevIns, POHCI);
5575 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5576 pThis->pEndOfFrameTimerRC = TMTimerRCPtr(pThis->pEndOfFrameTimerR3);
5577}
5578
5579
5580/**
5581 * Destruct a device instance.
5582 *
5583 * Most VM resources are freed by the VM. This callback is provided so that any non-VM
5584 * resources can be freed correctly.
5585 *
5586 * @returns VBox status code.
5587 * @param pDevIns The device instance data.
5588 */
5589static DECLCALLBACK(int) ohciR3Destruct(PPDMDEVINS pDevIns)
5590{
5591 POHCI pThis = PDMINS_2_DATA(pDevIns, POHCI);
5592 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
5593
5594 if (RTCritSectIsInitialized(&pThis->CritSect))
5595 RTCritSectDelete(&pThis->CritSect);
5596 PDMR3CritSectDelete(&pThis->CsIrq);
5597
5598 /*
5599 * Tear down the per endpoint in-flight tracking...
5600 */
5601
5602 return VINF_SUCCESS;
5603}
5604
5605
5606/**
5607 * @interface_method_impl{PDMDEVREG,pfnConstruct,OHCI constructor}
5608 */
5609static DECLCALLBACK(int) ohciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5610{
5611 POHCI pThis = PDMINS_2_DATA(pDevIns, POHCI);
5612 uint32_t cPorts;
5613 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5614
5615 /*
5616 * Init instance data.
5617 */
5618 pThis->pDevInsR3 = pDevIns;
5619 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5620 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5621
5622 PCIDevSetVendorId (&pThis->PciDev, 0x106b);
5623 PCIDevSetDeviceId (&pThis->PciDev, 0x003f);
5624 PCIDevSetClassProg (&pThis->PciDev, 0x10); /* OHCI */
5625 PCIDevSetClassSub (&pThis->PciDev, 0x03);
5626 PCIDevSetClassBase (&pThis->PciDev, 0x0c);
5627 PCIDevSetInterruptPin (&pThis->PciDev, 0x01);
5628#ifdef VBOX_WITH_MSI_DEVICES
5629 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST);
5630 PCIDevSetCapabilityList(&pThis->PciDev, 0x80);
5631#endif
5632
5633 pThis->RootHub.pOhci = pThis;
5634 pThis->RootHub.IBase.pfnQueryInterface = ohciRhQueryInterface;
5635 pThis->RootHub.IRhPort.pfnGetAvailablePorts = ohciRhGetAvailablePorts;
5636 pThis->RootHub.IRhPort.pfnGetUSBVersions = ohciRhGetUSBVersions;
5637 pThis->RootHub.IRhPort.pfnAttach = ohciRhAttach;
5638 pThis->RootHub.IRhPort.pfnDetach = ohciRhDetach;
5639 pThis->RootHub.IRhPort.pfnReset = ohciRhReset;
5640 pThis->RootHub.IRhPort.pfnXferCompletion = ohciRhXferCompletion;
5641 pThis->RootHub.IRhPort.pfnXferError = ohciRhXferError;
5642 pThis->RootHub.IRhPort.pfnStartFrame = ohciR3StartFrame;
5643 pThis->RootHub.IRhPort.pfnFrameRateChanged = ohciR3FrameRateChanged;
5644
5645 /* USB LED */
5646 pThis->RootHub.Led.u32Magic = PDMLED_MAGIC;
5647 pThis->RootHub.ILeds.pfnQueryStatusLed = ohciRhQueryStatusLed;
5648
5649
5650 /*
5651 * Read configuration.
5652 */
5653 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "RZEnabled", "");
5654 int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pThis->fRZEnabled, true);
5655 AssertLogRelRCReturn(rc, rc);
5656
5657 /* Number of ports option. */
5658 rc = CFGMR3QueryU32Def(pCfg, "Ports", &cPorts, OHCI_NDP_DEFAULT);
5659 if (RT_FAILURE(rc))
5660 return PDMDEV_SET_ERROR(pDevIns, rc,
5661 N_("OHCI configuration error: failed to read Ports as integer"));
5662
5663 if (cPorts == 0 || cPorts > OHCI_NDP_MAX)
5664 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
5665 N_("OHCI configuration error: Ports must be in range [%u,%u]"),
5666 1, OHCI_NDP_MAX);
5667
5668 /* Store the configured NDP; it will be used everywhere else from now on. */
5669 pThis->RootHub.desc_a = cPorts;
5670
5671 /*
5672 * Register PCI device and I/O region.
5673 */
5674 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
5675 if (RT_FAILURE(rc))
5676 return rc;
5677
5678#ifdef VBOX_WITH_MSI_DEVICES
5679 PDMMSIREG MsiReg;
5680 RT_ZERO(MsiReg);
5681 MsiReg.cMsiVectors = 1;
5682 MsiReg.iMsiCapOffset = 0x80;
5683 MsiReg.iMsiNextOffset = 0x00;
5684 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5685 if (RT_FAILURE(rc))
5686 {
5687 PCIDevSetCapabilityList(&pThis->PciDev, 0x0);
5688 /* That's OK, we can work without MSI */
5689 }
5690#endif
5691
5692 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 4096, PCI_ADDRESS_SPACE_MEM, ohciR3Map);
5693 if (RT_FAILURE(rc))
5694 return rc;
5695
5696 /*
5697 * Create the end-of-frame timer.
5698 */
5699 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, ohciFrameBoundaryTimer, pThis,
5700 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "USB Frame Timer",
5701 &pThis->pEndOfFrameTimerR3);
5702 if (RT_FAILURE(rc))
5703 return rc;
5704 pThis->pEndOfFrameTimerR0 = TMTimerR0Ptr(pThis->pEndOfFrameTimerR3);
5705 pThis->pEndOfFrameTimerRC = TMTimerRCPtr(pThis->pEndOfFrameTimerR3);
5706
5707 /*
5708 * Register the saved state data unit.
5709 */
5710 rc = PDMDevHlpSSMRegisterEx(pDevIns, OHCI_SAVED_STATE_VERSION, sizeof(*pThis), NULL,
5711 NULL, NULL, NULL,
5712 ohciR3SavePrep, ohciR3SaveExec, ohciR3SaveDone,
5713 ohciR3LoadPrep, ohciR3LoadExec, ohciR3LoadDone);
5714 if (RT_FAILURE(rc))
5715 return rc;
5716
5717 /*
5718 * Attach to the VBox USB RootHub Driver on LUN #0.
5719 */
5720 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->RootHub.IBase, &pThis->RootHub.pIBase, "RootHub");
5721 if (RT_FAILURE(rc))
5722 {
5723 AssertMsgFailed(("Configuration error: No roothub driver attached to LUN #0!\n"));
5724 return rc;
5725 }
5726 pThis->RootHub.pIRhConn = PDMIBASE_QUERY_INTERFACE(pThis->RootHub.pIBase, VUSBIROOTHUBCONNECTOR);
5727 AssertMsgReturn(pThis->RootHub.pIRhConn,
5728 ("Configuration error: The driver doesn't provide the VUSBIROOTHUBCONNECTOR interface!\n"),
5729 VERR_PDM_MISSING_INTERFACE);
5730 pThis->RootHub.pIDev = PDMIBASE_QUERY_INTERFACE(pThis->RootHub.pIBase, VUSBIDEVICE);
5731 AssertMsgReturn(pThis->RootHub.pIDev,
5732 ("Configuration error: The driver doesn't provide the VUSBIDEVICE interface!\n"),
5733 VERR_PDM_MISSING_INTERFACE);
5734
5735 /*
5736 * Attach status driver (optional).
5737 */
5738 PPDMIBASE pBase;
5739 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->RootHub.IBase, &pBase, "Status Port");
5740 if (RT_SUCCESS(rc))
5741 pThis->RootHub.pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
5742 else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
5743 {
5744 AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
5745 return rc;
5746 }
5747
5748 /* Set URB parameters. */
5749 rc = VUSBIRhSetUrbParams(pThis->RootHub.pIRhConn, sizeof(VUSBURBHCIINT), sizeof(VUSBURBHCITDINT));
5750 if (RT_FAILURE(rc))
5751 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5752 N_("OHCI: Failed to set URB parameters"));
5753
5754 /*
5755 * Calculate the timer intervals.
5756 * This assumes that the VM timer doesn't change frequency during the run.
5757 */
5758 pThis->u64TimerHz = TMTimerGetFreq(pThis->CTX_SUFF(pEndOfFrameTimer));
5759
5760 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CsIrq, RT_SRC_POS, "OHCI#%uIrq", iInstance);
5761 if (RT_FAILURE(rc))
5762 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5763 N_("OHCI: Failed to create critical section"));
5764
5765 rc = RTCritSectInit(&pThis->CritSect);
5766 if (RT_FAILURE(rc))
5767 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5768 N_("OHCI: Failed to create critical section"));
5769
5770 /*
5771 * Do a hardware reset.
5772 */
5773 ohciDoReset(pThis, OHCI_USB_RESET, false /* don't reset devices */);
5774
5775#ifdef VBOX_WITH_STATISTICS
5776 /*
5777 * Register statistics.
5778 */
5779 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCanceledIsocUrbs, STAMTYPE_COUNTER, "/Devices/OHCI/CanceledIsocUrbs", STAMUNIT_OCCURENCES, "Detected canceled isochronous URBs.");
5780 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCanceledGenUrbs, STAMTYPE_COUNTER, "/Devices/OHCI/CanceledGenUrbs", STAMUNIT_OCCURENCES, "Detected canceled general URBs.");
5781 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDroppedUrbs, STAMTYPE_COUNTER, "/Devices/OHCI/DroppedUrbs", STAMUNIT_OCCURENCES, "Dropped URBs (endpoint halted, or URB canceled).");
5782#endif
5783
5784 /*
5785 * Register debugger info callbacks.
5786 */
5787 PDMDevHlpDBGFInfoRegister(pDevIns, "ohci", "OHCI control registers.", ohciR3InfoRegs);
5788
5789#if 0/*def DEBUG_bird*/
5790// g_fLogInterruptEPs = true;
5791 g_fLogControlEPs = true;
5792 g_fLogBulkEPs = true;
5793#endif
5794
5795 return VINF_SUCCESS;
5796}
5797
5798
5799const PDMDEVREG g_DeviceOHCI =
5800{
5801 /* u32version */
5802 PDM_DEVREG_VERSION,
5803 /* szName */
5804 "usb-ohci",
5805 /* szRCMod */
5806 "VBoxDDRC.rc",
5807 /* szR0Mod */
5808 "VBoxDDR0.r0",
5809 /* pszDescription */
5810 "OHCI USB controller.\n",
5811 /* fFlags */
5812 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
5813 /* fClass */
5814 PDM_DEVREG_CLASS_BUS_USB,
5815 /* cMaxInstances */
5816 ~0U,
5817 /* cbInstance */
5818 sizeof(OHCI),
5819 /* pfnConstruct */
5820 ohciR3Construct,
5821 /* pfnDestruct */
5822 ohciR3Destruct,
5823 /* pfnRelocate */
5824 ohciR3Relocate,
5825 /* pfnMemSetup */
5826 NULL,
5827 /* pfnPowerOn */
5828 NULL,
5829 /* pfnReset */
5830 ohciR3Reset,
5831 /* pfnSuspend */
5832 NULL,
5833 /* pfnResume */
5834 ohciR3Resume,
5835 /* pfnAttach */
5836 NULL,
5837 /* pfnDetach */
5838 NULL,
5839 /* pfnQueryInterface */
5840 NULL,
5841 /* pfnInitComplete */
5842 NULL,
5843 /* pfnPowerOff */
5844 NULL,
5845 /* pfnSoftReset */
5846 NULL,
5847 /* u32VersionEnd */
5848 PDM_DEVREG_VERSION
5849};
5850
5851#endif /* IN_RING3 */
5852#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette