VirtualBox

source: vbox/trunk/src/VBox/Devices/Storage/DevLsiLogicSCSI.h@ 30714

Last change on this file since 30714 was 29588, checked in by vboxsync, 15 years ago

LsiLogic: The request queue should have the same size as the reply queue or we risk overwriting completed requests by others causing timeouts in the guest
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 122.8 KB
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1/* $Id: DevLsiLogicSCSI.h 29588 2010-05-17 22:32:29Z vboxsync $ */
2/** @file
3 * VBox storage devices: LsiLogic LSI53c1030 SCSI controller - Defines and structures.
4 */
5
6/*
7 * Copyright (C) 2006-2009 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17#ifndef __DEVLSILOGICSCSI_H__
18#define __DEVLSILOGICSCSI_H__
19
20#include <iprt/stdint.h>
21
22/*
23 * I/O port registered in the ISA compatible range to let the BIOS access
24 * the controller.
25 */
26#define LSILOGIC_ISA_IO_PORT 0x340
27#define LSILOGIC_SAS_ISA_IO_PORT 0x350
28
29#define LSILOGICSCSI_REQUEST_QUEUE_DEPTH_DEFAULT 256
30#define LSILOGICSCSI_REPLY_QUEUE_DEPTH_DEFAULT 256
31
32#define LSILOGICSCSI_MAXIMUM_CHAIN_DEPTH 3
33
34#define LSILOGIC_NR_OF_ALLOWED_BIGGER_LISTS 100
35
36/** Equal for all devices */
37#define LSILOGICSCSI_PCI_VENDOR_ID (0x1000)
38
39/** SPI SCSI controller (LSI53C1030) */
40#define LSILOGICSCSI_PCI_SPI_CTRLNAME "LSI53C1030"
41#define LSILOGICSCSI_PCI_SPI_DEVICE_ID (0x0030)
42#define LSILOGICSCSI_PCI_SPI_REVISION_ID (0x00)
43#define LSILOGICSCSI_PCI_SPI_CLASS_CODE (0x01)
44#define LSILOGICSCSI_PCI_SPI_SUBSYSTEM_VENDOR_ID (0x1000)
45#define LSILOGICSCSI_PCI_SPI_SUBSYSTEM_ID (0x8000)
46#define LSILOGICSCSI_PCI_SPI_PORTS_MAX 1
47#define LSILOGICSCSI_PCI_SPI_BUSES_MAX 1
48#define LSILOGICSCSI_PCI_SPI_DEVICES_PER_BUS_MAX 16
49#define LSILOGICSCSI_PCI_SPI_DEVICES_MAX (LSILOGICSCSI_PCI_SPI_BUSES_MAX*LSILOGICSCSI_PCI_SPI_DEVICES_PER_BUS_MAX)
50
51/** SAS SCSI controller (SAS1068 PCI-X Fusion-MPT SAS) */
52#define LSILOGICSCSI_PCI_SAS_CTRLNAME "SAS1068"
53#define LSILOGICSCSI_PCI_SAS_DEVICE_ID (0x0054)
54#define LSILOGICSCSI_PCI_SAS_REVISION_ID (0x00)
55#define LSILOGICSCSI_PCI_SAS_CLASS_CODE (0x00)
56#define LSILOGICSCSI_PCI_SAS_SUBSYSTEM_VENDOR_ID (0x1000)
57#define LSILOGICSCSI_PCI_SAS_SUBSYSTEM_ID (0x8000)
58#define LSILOGICSCSI_PCI_SAS_PORTS_MAX 256
59#define LSILOGICSCSI_PCI_SAS_PORTS_DEFAULT 8
60#define LSILOGICSCSI_PCI_SAS_DEVICES_PER_PORT_MAX 1
61#define LSILOGICSCSI_PCI_SAS_DEVICES_MAX (LSILOGICSCSI_PCI_SAS_PORTS_MAX * LSILOGICSCSI_PCI_SAS_DEVICES_PER_PORT_MAX)
62
63/**
64 * A SAS address.
65 */
66#pragma pack(1)
67typedef union SASADDRESS
68{
69 /** 64bit view. */
70 uint64_t u64Address;
71 /** 32bit view. */
72 uint32_t u32Address[2];
73 /** 16bit view. */
74 uint16_t u16Address[4];
75 /** Byte view. */
76 uint8_t u8Address[8];
77} SASADDRESS, *PSASADDRESS;
78#pragma pack()
79AssertCompileSize(SASADDRESS, 8);
80
81/**
82 * Possible device types we support.
83 */
84typedef enum LSILOGICCTRLTYPE
85{
86 /** SPI SCSI controller (PCI dev id 0x0030) */
87 LSILOGICCTRLTYPE_SCSI_SPI = 0,
88 /** SAS SCSI controller (PCI dev id 0x0054) */
89 LSILOGICCTRLTYPE_SCSI_SAS = 1,
90 /** 32bit hack */
91 LSILOGICCTRLTYPE_32BIT_HACK = 0x7fffffff
92} LSILOGICCTRLTYPE, *PLSILOGICCTRLTYPE;
93
94/**
95 * A simple SG element for a 64bit adress.
96 */
97#pragma pack(1)
98typedef struct MptSGEntrySimple64
99{
100 /** Length of the buffer this entry describes. */
101 unsigned u24Length: 24;
102 /** Flag whether this element is the end of the list. */
103 unsigned fEndOfList: 1;
104 /** Flag whether the address is 32bit or 64bits wide. */
105 unsigned f64BitAddress: 1;
106 /** Flag whether this buffer contains data to be transfered or is the destination. */
107 unsigned fBufferContainsData: 1;
108 /** Flag whether this is a local address or a system address. */
109 unsigned fLocalAddress: 1;
110 /** Element type. */
111 unsigned u2ElementType: 2;
112 /** Flag whether this is the last element of the buffer. */
113 unsigned fEndOfBuffer: 1;
114 /** Flag whether this is the last element of the current segment. */
115 unsigned fLastElement: 1;
116 /** Lower 32bits of the address of the data buffer. */
117 unsigned u32DataBufferAddressLow: 32;
118 /** Upper 32bits of the address of the data buffer. */
119 unsigned u32DataBufferAddressHigh: 32;
120} MptSGEntrySimple64, *PMptSGEntrySimple64;
121#pragma pack()
122AssertCompileSize(MptSGEntrySimple64, 12);
123
124/**
125 * A simple SG element for a 32bit adress.
126 */
127#pragma pack(1)
128typedef struct MptSGEntrySimple32
129{
130 /** Length of the buffer this entry describes. */
131 unsigned u24Length: 24;
132 /** Flag whether this element is the end of the list. */
133 unsigned fEndOfList: 1;
134 /** Flag whether the address is 32bit or 64bits wide. */
135 unsigned f64BitAddress: 1;
136 /** Flag whether this buffer contains data to be transfered or is the destination. */
137 unsigned fBufferContainsData: 1;
138 /** Flag whether this is a local address or a system address. */
139 unsigned fLocalAddress: 1;
140 /** Element type. */
141 unsigned u2ElementType: 2;
142 /** Flag whether this is the last element of the buffer. */
143 unsigned fEndOfBuffer: 1;
144 /** Flag whether this is the last element of the current segment. */
145 unsigned fLastElement: 1;
146 /** Lower 32bits of the address of the data buffer. */
147 unsigned u32DataBufferAddressLow: 32;
148} MptSGEntrySimple32, *PMptSGEntrySimple32;
149#pragma pack()
150AssertCompileSize(MptSGEntrySimple32, 8);
151
152/**
153 * A chain SG element.
154 */
155#pragma pack(1)
156typedef struct MptSGEntryChain
157{
158 /** Size of the segment. */
159 unsigned u16Length: 16;
160 /** Offset in 32bit words of the next chain element in the segment
161 * identified by this element. */
162 unsigned u8NextChainOffset: 8;
163 /** Reserved. */
164 unsigned fReserved0: 1;
165 /** Flag whether the address is 32bit or 64bits wide. */
166 unsigned f64BitAddress: 1;
167 /** Reserved. */
168 unsigned fReserved1: 1;
169 /** Flag whether this is a local address or a system address. */
170 unsigned fLocalAddress: 1;
171 /** Element type. */
172 unsigned u2ElementType: 2;
173 /** Flag whether this is the last element of the buffer. */
174 unsigned u2Reserved2: 2;
175 /** Lower 32bits of the address of the data buffer. */
176 unsigned u32SegmentAddressLow: 32;
177 /** Upper 32bits of the address of the data buffer. */
178 unsigned u32SegmentAddressHigh: 32;
179} MptSGEntryChain, *PMptSGEntryChain;
180#pragma pack()
181AssertCompileSize(MptSGEntryChain, 12);
182
183typedef union MptSGEntryUnion
184{
185 MptSGEntrySimple64 Simple64;
186 MptSGEntrySimple32 Simple32;
187 MptSGEntryChain Chain;
188} MptSGEntryUnion, *PMptSGEntryUnion;
189
190/**
191 * MPT Fusion message header - Common for all message frames.
192 * This is filled in by the guest.
193 */
194#pragma pack(1)
195typedef struct MptMessageHdr
196{
197 /** Function dependent data. */
198 uint16_t u16FunctionDependent;
199 /** Chain offset. */
200 uint8_t u8ChainOffset;
201 /** The function code. */
202 uint8_t u8Function;
203 /** Function dependent data. */
204 uint8_t au8FunctionDependent[3];
205 /** Message flags. */
206 uint8_t u8MessageFlags;
207 /** Message context - Unique ID from the guest unmodified by the device. */
208 uint32_t u32MessageContext;
209} MptMessageHdr, *PMptMessageHdr;
210#pragma pack()
211AssertCompileSize(MptMessageHdr, 12);
212
213/** Defined function codes found in the message header. */
214#define MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST (0x00)
215#define MPT_MESSAGE_HDR_FUNCTION_SCSI_TASK_MGMT (0x01)
216#define MPT_MESSAGE_HDR_FUNCTION_IOC_INIT (0x02)
217#define MPT_MESSAGE_HDR_FUNCTION_IOC_FACTS (0x03)
218#define MPT_MESSAGE_HDR_FUNCTION_CONFIG (0x04)
219#define MPT_MESSAGE_HDR_FUNCTION_PORT_FACTS (0x05)
220#define MPT_MESSAGE_HDR_FUNCTION_PORT_ENABLE (0x06)
221#define MPT_MESSAGE_HDR_FUNCTION_EVENT_NOTIFICATION (0x07)
222#define MPT_MESSAGE_HDR_FUNCTION_EVENT_ACK (0x08)
223#define MPT_MESSAGE_HDR_FUNCTION_FW_DOWNLOAD (0x09)
224#define MPT_MESSAGE_HDR_FUNCTION_TARGET_CMD_BUFFER_POST (0x0A)
225#define MPT_MESSAGE_HDR_FUNCTION_TARGET_ASSIST (0x0B)
226#define MPT_MESSAGE_HDR_FUNCTION_TARGET_STATUS_SEND (0x0C)
227#define MPT_MESSAGE_HDR_FUNCTION_TARGET_MODE_ABORT (0x0D)
228
229#ifdef DEBUG
230/**
231 * Function names
232 */
233static const char * const g_apszMPTFunctionNames[] =
234{
235 "SCSI I/O Request",
236 "SCSI Task Management",
237 "IOC Init",
238 "IOC Facts",
239 "Config",
240 "Port Facts",
241 "Port Enable",
242 "Event Notification",
243 "Event Ack",
244 "Firmware Download"
245};
246#endif
247
248/**
249 * Default reply message.
250 * Send from the device to the guest upon completion of a request.
251 */
252 #pragma pack(1)
253typedef struct MptDefaultReplyMessage
254{
255 /** Function dependent data. */
256 uint16_t u16FunctionDependent;
257 /** Length of the message in 32bit DWords. */
258 uint8_t u8MessageLength;
259 /** Function which completed. */
260 uint8_t u8Function;
261 /** Function dependent. */
262 uint8_t au8FunctionDependent[3];
263 /** Message flags. */
264 uint8_t u8MessageFlags;
265 /** Message context given in the request. */
266 uint32_t u32MessageContext;
267 /** Function dependent status code. */
268 uint16_t u16FunctionDependentStatus;
269 /** Status of the IOC. */
270 uint16_t u16IOCStatus;
271 /** Additional log info. */
272 uint32_t u32IOCLogInfo;
273} MptDefaultReplyMessage, *PMptDefaultReplyMessage;
274#pragma pack()
275AssertCompileSize(MptDefaultReplyMessage, 20);
276
277/**
278 * IO controller init request.
279 */
280#pragma pack(1)
281typedef struct MptIOCInitRequest
282{
283 /** Which system send this init request. */
284 uint8_t u8WhoInit;
285 /** Reserved */
286 uint8_t u8Reserved;
287 /** Chain offset in the SG list. */
288 uint8_t u8ChainOffset;
289 /** Function to execute. */
290 uint8_t u8Function;
291 /** Flags */
292 uint8_t u8Flags;
293 /** Maximum number of devices the driver can handle. */
294 uint8_t u8MaxDevices;
295 /** Maximum number of buses the driver can handle. */
296 uint8_t u8MaxBuses;
297 /** Message flags. */
298 uint8_t u8MessageFlags;
299 /** Message context ID. */
300 uint32_t u32MessageContext;
301 /** Reply frame size. */
302 uint16_t u16ReplyFrameSize;
303 /** Reserved */
304 uint16_t u16Reserved;
305 /** Upper 32bit part of the 64bit address the message frames are in.
306 * That means all frames must be in the same 4GB segment. */
307 uint32_t u32HostMfaHighAddr;
308 /** Upper 32bit of the sense buffer. */
309 uint32_t u32SenseBufferHighAddr;
310} MptIOCInitRequest, *PMptIOCInitRequest;
311#pragma pack()
312AssertCompileSize(MptIOCInitRequest, 24);
313
314/**
315 * IO controller init reply.
316 */
317#pragma pack(1)
318typedef struct MptIOCInitReply
319{
320 /** Which subsystem send this init request. */
321 uint8_t u8WhoInit;
322 /** Reserved */
323 uint8_t u8Reserved;
324 /** Message length */
325 uint8_t u8MessageLength;
326 /** Function. */
327 uint8_t u8Function;
328 /** Flags */
329 uint8_t u8Flags;
330 /** Maximum number of devices the driver can handle. */
331 uint8_t u8MaxDevices;
332 /** Maximum number of busses the driver can handle. */
333 uint8_t u8MaxBuses;
334 /** Message flags. */
335 uint8_t u8MessageFlags;
336 /** Message context ID */
337 uint32_t u32MessageContext;
338 /** Reserved */
339 uint16_t u16Reserved;
340 /** IO controller status. */
341 uint16_t u16IOCStatus;
342 /** IO controller log information. */
343 uint32_t u32IOCLogInfo;
344} MptIOCInitReply, *PMptIOCInitReply;
345#pragma pack()
346AssertCompileSize(MptIOCInitReply, 20);
347
348/**
349 * IO controller facts request.
350 */
351#pragma pack(1)
352typedef struct MptIOCFactsRequest
353{
354 /** Reserved. */
355 uint16_t u16Reserved;
356 /** Chain offset in SG list. */
357 uint8_t u8ChainOffset;
358 /** Function number. */
359 uint8_t u8Function;
360 /** Reserved */
361 uint8_t u8Reserved[3];
362 /** Message flags. */
363 uint8_t u8MessageFlags;
364 /** Message context ID. */
365 uint32_t u32MessageContext;
366} MptIOCFactsRequest, *PMptIOCFactsRequest;
367#pragma pack()
368AssertCompileSize(MptIOCFactsRequest, 12);
369
370/**
371 * IO controller facts reply.
372 */
373#pragma pack(1)
374typedef struct MptIOCFactsReply
375{
376 /** Message version. */
377 uint16_t u16MessageVersion;
378 /** Message length. */
379 uint8_t u8MessageLength;
380 /** Function number. */
381 uint8_t u8Function;
382 /** Reserved */
383 uint16_t u16Reserved1;
384 /** IO controller number */
385 uint8_t u8IOCNumber;
386 /** Message flags. */
387 uint8_t u8MessageFlags;
388 /** Message context ID. */
389 uint32_t u32MessageContext;
390 /** IO controller exceptions */
391 uint16_t u16IOCExceptions;
392 /** IO controller status. */
393 uint16_t u16IOCStatus;
394 /** IO controller log information. */
395 uint32_t u32IOCLogInfo;
396 /** Maximum chain depth. */
397 uint8_t u8MaxChainDepth;
398 /** The current value of the WhoInit field. */
399 uint8_t u8WhoInit;
400 /** Block size. */
401 uint8_t u8BlockSize;
402 /** Flags. */
403 uint8_t u8Flags;
404 /** Depth of the reply queue. */
405 uint16_t u16ReplyQueueDepth;
406 /** Size of a request frame. */
407 uint16_t u16RequestFrameSize;
408 /** Reserved */
409 uint16_t u16Reserved2;
410 /** Product ID. */
411 uint16_t u16ProductID;
412 /** Current value of the high 32bit MFA address. */
413 uint32_t u32CurrentHostMFAHighAddr;
414 /** Global credits - Number of entries allocated to queues */
415 uint16_t u16GlobalCredits;
416 /** Number of ports on the IO controller */
417 uint8_t u8NumberOfPorts;
418 /** Event state. */
419 uint8_t u8EventState;
420 /** Current value of the high 32bit sense buffer address. */
421 uint32_t u32CurrentSenseBufferHighAddr;
422 /** Current reply frame size. */
423 uint16_t u16CurReplyFrameSize;
424 /** Maximum number of devices. */
425 uint8_t u8MaxDevices;
426 /** Maximum number of buses. */
427 uint8_t u8MaxBuses;
428 /** Size of the firmware image. */
429 uint32_t u32FwImageSize;
430 /** Reserved. */
431 uint32_t u32Reserved;
432 /** Firmware version */
433 uint32_t u32FWVersion;
434} MptIOCFactsReply, *PMptIOCFactsReply;
435#pragma pack()
436AssertCompileSize(MptIOCFactsReply, 60);
437
438/**
439 * Port facts request
440 */
441#pragma pack(1)
442typedef struct MptPortFactsRequest
443{
444 /** Reserved */
445 uint16_t u16Reserved1;
446 /** Message length. */
447 uint8_t u8MessageLength;
448 /** Function number. */
449 uint8_t u8Function;
450 /** Reserved */
451 uint16_t u16Reserved2;
452 /** Port number to get facts for. */
453 uint8_t u8PortNumber;
454 /** Message flags. */
455 uint8_t u8MessageFlags;
456 /** Message context ID. */
457 uint32_t u32MessageContext;
458} MptPortFactsRequest, *PMptPortFactsRequest;
459#pragma pack()
460AssertCompileSize(MptPortFactsRequest, 12);
461
462/**
463 * Port facts reply.
464 */
465#pragma pack(1)
466typedef struct MptPortFactsReply
467{
468 /** Reserved. */
469 uint16_t u16Reserved1;
470 /** Message length. */
471 uint8_t u8MessageLength;
472 /** Function number. */
473 uint8_t u8Function;
474 /** Reserved */
475 uint16_t u16Reserved2;
476 /** Port number the facts are for. */
477 uint8_t u8PortNumber;
478 /** Message flags. */
479 uint8_t u8MessageFlags;
480 /** Message context ID. */
481 uint32_t u32MessageContext;
482 /** Reserved. */
483 uint16_t u16Reserved3;
484 /** IO controller status. */
485 uint16_t u16IOCStatus;
486 /** IO controller log information. */
487 uint32_t u32IOCLogInfo;
488 /** Reserved */
489 uint8_t u8Reserved;
490 /** Port type */
491 uint8_t u8PortType;
492 /** Maximum number of devices on this port. */
493 uint16_t u16MaxDevices;
494 /** SCSI ID of this port on the attached bus. */
495 uint16_t u16PortSCSIID;
496 /** Protocol flags. */
497 uint16_t u16ProtocolFlags;
498 /** Maxmimum number of target command buffers which can be posted to this port at a time. */
499 uint16_t u16MaxPostedCmdBuffers;
500 /** Maximum number of target IDs that remain persistent between power/reset cycles. */
501 uint16_t u16MaxPersistentIDs;
502 /** Maximum number of LAN buckets. */
503 uint16_t u16MaxLANBuckets;
504 /** Reserved. */
505 uint16_t u16Reserved4;
506 /** Reserved. */
507 uint32_t u32Reserved;
508} MptPortFactsReply, *PMptPortFactsReply;
509#pragma pack()
510AssertCompileSize(MptPortFactsReply, 40);
511
512/**
513 * Port Enable request.
514 */
515#pragma pack(1)
516typedef struct MptPortEnableRequest
517{
518 /** Reserved. */
519 uint16_t u16Reserved1;
520 /** Message length. */
521 uint8_t u8MessageLength;
522 /** Function number. */
523 uint8_t u8Function;
524 /** Reserved. */
525 uint16_t u16Reserved2;
526 /** Port number to enable. */
527 uint8_t u8PortNumber;
528 /** Message flags. */
529 uint8_t u8MessageFlags;
530 /** Message context ID. */
531 uint32_t u32MessageContext;
532} MptPortEnableRequest, *PMptPortEnableRequest;
533#pragma pack()
534AssertCompileSize(MptPortEnableRequest, 12);
535
536/**
537 * Port enable reply.
538 */
539#pragma pack(1)
540typedef struct MptPortEnableReply
541{
542 /** Reserved. */
543 uint16_t u16Reserved1;
544 /** Message length. */
545 uint8_t u8MessageLength;
546 /** Function number. */
547 uint8_t u8Function;
548 /** Reserved */
549 uint16_t u16Reserved2;
550 /** Port number which was enabled. */
551 uint8_t u8PortNumber;
552 /** Message flags. */
553 uint8_t u8MessageFlags;
554 /** Message context ID. */
555 uint32_t u32MessageContext;
556 /** Reserved. */
557 uint16_t u16Reserved3;
558 /** IO controller status */
559 uint16_t u16IOCStatus;
560 /** IO controller log information. */
561 uint32_t u32IOCLogInfo;
562} MptPortEnableReply, *PMptPortEnableReply;
563#pragma pack()
564AssertCompileSize(MptPortEnableReply, 20);
565
566/**
567 * Event notification request.
568 */
569#pragma pack(1)
570typedef struct MptEventNotificationRequest
571{
572 /** Switch - Turns event notification on and off. */
573 uint8_t u8Switch;
574 /** Reserved. */
575 uint8_t u8Reserved1;
576 /** Chain offset. */
577 uint8_t u8ChainOffset;
578 /** Function number. */
579 uint8_t u8Function;
580 /** Reserved. */
581 uint8_t u8reserved2[3];
582 /** Message flags. */
583 uint8_t u8MessageFlags;
584 /** Message context ID. */
585 uint32_t u32MessageContext;
586} MptEventNotificationRequest, *PMptEventNotificationRequest;
587#pragma pack()
588AssertCompileSize(MptEventNotificationRequest, 12);
589
590/**
591 * Event notification reply.
592 */
593#pragma pack(1)
594typedef struct MptEventNotificationReply
595{
596 /** Event data length. */
597 uint16_t u16EventDataLength;
598 /** Message length. */
599 uint8_t u8MessageLength;
600 /** Function number. */
601 uint8_t u8Function;
602 /** Reserved. */
603 uint16_t u16Reserved1;
604 /** Ack required. */
605 uint8_t u8AckRequired;
606 /** Message flags. */
607 uint8_t u8MessageFlags;
608 /** Message context ID. */
609 uint32_t u32MessageContext;
610 /** Reserved. */
611 uint16_t u16Reserved2;
612 /** IO controller status. */
613 uint16_t u16IOCStatus;
614 /** IO controller log information. */
615 uint32_t u32IOCLogInfo;
616 /** Notification event. */
617 uint32_t u32Event;
618 /** Event context. */
619 uint32_t u32EventContext;
620 /** Event data. */
621 uint32_t u32EventData;
622} MptEventNotificationReply, *PMptEventNotificationReply;
623#pragma pack()
624AssertCompileSize(MptEventNotificationReply, 32);
625
626#define MPT_EVENT_EVENT_CHANGE (0x0000000a)
627
628/**
629 * SCSI IO Request
630 */
631#pragma pack(1)
632typedef struct MptSCSIIORequest
633{
634 /** Target ID */
635 uint8_t u8TargetID;
636 /** Bus number */
637 uint8_t u8Bus;
638 /** Chain offset */
639 uint8_t u8ChainOffset;
640 /** Function number. */
641 uint8_t u8Function;
642 /** CDB length. */
643 uint8_t u8CDBLength;
644 /** Sense buffer length. */
645 uint8_t u8SenseBufferLength;
646 /** Rserved */
647 uint8_t u8Reserved;
648 /** Message flags. */
649 uint8_t u8MessageFlags;
650 /** Message context ID. */
651 uint32_t u32MessageContext;
652 /** LUN */
653 uint8_t au8LUN[8];
654 /** Control values. */
655 uint32_t u32Control;
656 /** The CDB. */
657 uint8_t au8CDB[16];
658 /** Data length. */
659 uint32_t u32DataLength;
660 /** Sense buffer low 32bit address. */
661 uint32_t u32SenseBufferLowAddress;
662} MptSCSIIORequest, *PMptSCSIIORequest;
663#pragma pack()
664AssertCompileSize(MptSCSIIORequest, 48);
665
666#define MPT_SCSIIO_REQUEST_CONTROL_TXDIR_GET(x) (((x) & 0x3000000) >> 24)
667#define MPT_SCSIIO_REQUEST_CONTROL_TXDIR_NONE (0x0)
668#define MPT_SCSIIO_REQUEST_CONTROL_TXDIR_WRITE (0x1)
669#define MPT_SCSIIO_REQUEST_CONTROL_TXDIR_READ (0x2)
670
671/**
672 * SCSI IO error reply.
673 */
674#pragma pack(1)
675typedef struct MptSCSIIOErrorReply
676{
677 /** Target ID */
678 uint8_t u8TargetID;
679 /** Bus number */
680 uint8_t u8Bus;
681 /** Message length. */
682 uint8_t u8MessageLength;
683 /** Function number. */
684 uint8_t u8Function;
685 /** CDB length */
686 uint8_t u8CDBLength;
687 /** Sense buffer length */
688 uint8_t u8SenseBufferLength;
689 /** Reserved */
690 uint8_t u8Reserved;
691 /** Message flags */
692 uint8_t u8MessageFlags;
693 /** Message context ID */
694 uint32_t u32MessageContext;
695 /** SCSI status. */
696 uint8_t u8SCSIStatus;
697 /** SCSI state */
698 uint8_t u8SCSIState;
699 /** IO controller status */
700 uint16_t u16IOCStatus;
701 /** IO controller log information */
702 uint32_t u32IOCLogInfo;
703 /** Transfer count */
704 uint32_t u32TransferCount;
705 /** Sense count */
706 uint32_t u32SenseCount;
707 /** Response information */
708 uint32_t u32ResponseInfo;
709} MptSCSIIOErrorReply, *PMptSCSIIOErrorReply;
710#pragma pack()
711AssertCompileSize(MptSCSIIOErrorReply, 32);
712
713#define MPT_SCSI_IO_ERROR_SCSI_STATE_AUTOSENSE_VALID (0x01)
714#define MPT_SCSI_IO_ERROR_SCSI_STATE_TERMINATED (0x08)
715
716/**
717 * IOC status codes sepcific to the SCSI I/O error reply.
718 */
719#define MPT_SCSI_IO_ERROR_IOCSTATUS_INVALID_BUS (0x0041)
720#define MPT_SCSI_IO_ERROR_IOCSTATUS_INVALID_TARGETID (0x0042)
721#define MPT_SCSI_IO_ERROR_IOCSTATUS_DEVICE_NOT_THERE (0x0043)
722
723/**
724 * SCSI task management request.
725 */
726#pragma pack(1)
727typedef struct MptSCSITaskManagementRequest
728{
729 /** Target ID */
730 uint8_t u8TargetID;
731 /** Bus number */
732 uint8_t u8Bus;
733 /** Chain offset */
734 uint8_t u8ChainOffset;
735 /** Function number */
736 uint8_t u8Function;
737 /** Reserved */
738 uint8_t u8Reserved1;
739 /** Task type */
740 uint8_t u8TaskType;
741 /** Reserved */
742 uint8_t u8Reserved2;
743 /** Message flags */
744 uint8_t u8MessageFlags;
745 /** Message context ID */
746 uint32_t u32MessageContext;
747 /** LUN */
748 uint8_t au8LUN[8];
749 /** Reserved */
750 uint8_t auReserved[28];
751 /** Task message context ID. */
752 uint32_t u32TaskMessageContext;
753} MptSCSITaskManagementRequest, *PMptSCSITaskManagementRequest;
754#pragma pack()
755AssertCompileSize(MptSCSITaskManagementRequest, 52);
756
757/**
758 * SCSI task management reply.
759 */
760#pragma pack(1)
761typedef struct MptSCSITaskManagementReply
762{
763 /** Target ID */
764 uint8_t u8TargetID;
765 /** Bus number */
766 uint8_t u8Bus;
767 /** Message length */
768 uint8_t u8MessageLength;
769 /** Function number */
770 uint8_t u8Function;
771 /** Reserved */
772 uint8_t u8Reserved1;
773 /** Task type */
774 uint8_t u8TaskType;
775 /** Reserved */
776 uint8_t u8Reserved2;
777 /** Message flags */
778 uint8_t u8MessageFlags;
779 /** Message context ID */
780 uint32_t u32MessageContext;
781 /** Reserved */
782 uint16_t u16Reserved;
783 /** IO controller status */
784 uint16_t u16IOCStatus;
785 /** IO controller log information */
786 uint32_t u32IOCLogInfo;
787 /** Termination count */
788 uint32_t u32TerminationCount;
789} MptSCSITaskManagementReply, *PMptSCSITaskManagementReply;
790#pragma pack()
791AssertCompileSize(MptSCSITaskManagementReply, 24);
792
793/**
794 * Page address for SAS expander page types.
795 */
796#pragma pack(1)
797typedef union MptConfigurationPageAddressSASExpander
798{
799 struct
800 {
801 uint16_t u16Handle;
802 uint16_t u16Reserved;
803 } Form0And2;
804 struct
805 {
806 uint16_t u16Handle;
807 uint8_t u8PhyNum;
808 uint8_t u8Reserved;
809 } Form1;
810} MptConfigurationPageAddressSASExpander, *PMptConfigurationPageAddressSASExpander;
811#pragma pack()
812
813/**
814 * Page address for SAS device page types.
815 */
816#pragma pack(1)
817typedef union MptConfigurationPageAddressSASDevice
818{
819 struct
820 {
821 uint16_t u16Handle;
822 uint16_t u16Reserved;
823 } Form0And2;
824 struct
825 {
826 uint8_t u8TargetID;
827 uint8_t u8Bus;
828 uint8_t u8Reserved;
829 } Form1;
830} MptConfigurationPageAddressSASDevice, *PMptConfigurationPageAddressSASDevice;
831#pragma pack()
832
833/**
834 * Page address for SAS PHY page types.
835 */
836#pragma pack(1)
837typedef union MptConfigurationPageAddressSASPHY
838{
839 struct
840 {
841 uint8_t u8PhyNumber;
842 uint8_t u8Reserved[3];
843 } Form0;
844 struct
845 {
846 uint16_t u16Index;
847 uint16_t u16Reserved;
848 } Form1;
849} MptConfigurationPageAddressSASPHY, *PMptConfigurationPageAddressSASPHY;
850#pragma pack()
851
852/**
853 * Page address for SAS Enclosure page types.
854 */
855#pragma pack(1)
856typedef struct MptConfigurationPageAddressSASEnclosure
857{
858 uint16_t u16Handle;
859 uint16_t u16Reserved;
860} MptConfigurationPageAddressSASEnclosure, *PMptConfigurationPageAddressSASEnclosure;
861#pragma pack()
862
863/**
864 * Union of all possible address types.
865 */
866#pragma pack(1)
867typedef union MptConfigurationPageAddress
868{
869 /** 32bit view. */
870 uint32_t u32PageAddress;
871 struct
872 {
873 /** Port number to get the configuration page for. */
874 uint8_t u8PortNumber;
875 /** Reserved. */
876 uint8_t u8Reserved[3];
877 } MPIPortNumber;
878 struct
879 {
880 /** Target ID to get the configuration page for. */
881 uint8_t u8TargetID;
882 /** Bus number to get the configuration page for. */
883 uint8_t u8Bus;
884 /** Reserved. */
885 uint8_t u8Reserved[2];
886 } BusAndTargetId;
887 MptConfigurationPageAddressSASExpander SASExpander;
888 MptConfigurationPageAddressSASDevice SASDevice;
889 MptConfigurationPageAddressSASPHY SASPHY;
890 MptConfigurationPageAddressSASEnclosure SASEnclosure;
891} MptConfigurationPageAddress, *PMptConfigurationPageAddress;
892#pragma pack()
893AssertCompileSize(MptConfigurationPageAddress, 4);
894
895#define MPT_CONFIGURATION_PAGE_ADDRESS_GET_SAS_FORM(x) (((x).u32PageAddress >> 28) & 0x0f)
896
897/**
898 * Configuration request
899 */
900#pragma pack(1)
901typedef struct MptConfigurationRequest
902{
903 /** Action code. */
904 uint8_t u8Action;
905 /** Reserved. */
906 uint8_t u8Reserved1;
907 /** Chain offset. */
908 uint8_t u8ChainOffset;
909 /** Function number. */
910 uint8_t u8Function;
911 /** Extended page length. */
912 uint16_t u16ExtPageLength;
913 /** Extended page type */
914 uint8_t u8ExtPageType;
915 /** Message flags. */
916 uint8_t u8MessageFlags;
917 /** Message context ID. */
918 uint32_t u32MessageContext;
919 /** Reserved. */
920 uint8_t u8Reserved2[8];
921 /** Version number of the page. */
922 uint8_t u8PageVersion;
923 /** Length of the page in 32bit Dwords. */
924 uint8_t u8PageLength;
925 /** Page number to access. */
926 uint8_t u8PageNumber;
927 /** Type of the page beeing accessed. */
928 uint8_t u8PageType;
929 /** Page type dependent address. */
930 MptConfigurationPageAddress PageAddress;
931 /** Simple SG element describing the buffer. */
932 MptSGEntrySimple64 SimpleSGElement;
933} MptConfigurationRequest, *PMptConfigurationRequest;
934#pragma pack()
935AssertCompileSize(MptConfigurationRequest, 40);
936
937/** Possible action codes. */
938#define MPT_CONFIGURATION_REQUEST_ACTION_HEADER (0x00)
939#define MPT_CONFIGURATION_REQUEST_ACTION_READ_CURRENT (0x01)
940#define MPT_CONFIGURATION_REQUEST_ACTION_WRITE_CURRENT (0x02)
941#define MPT_CONFIGURATION_REQUEST_ACTION_DEFAULT (0x03)
942#define MPT_CONFIGURATION_REQUEST_ACTION_WRITE_NVRAM (0x04)
943#define MPT_CONFIGURATION_REQUEST_ACTION_READ_DEFAULT (0x05)
944#define MPT_CONFIGURATION_REQUEST_ACTION_READ_NVRAM (0x06)
945
946/** Page type codes. */
947#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_IO_UNIT (0x00)
948#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_IOC (0x01)
949#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_BIOS (0x02)
950#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_SCSI_PORT (0x03)
951#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_EXTENDED (0x0F)
952
953/**
954 * Configuration reply.
955 */
956#pragma pack(1)
957typedef struct MptConfigurationReply
958{
959 /** Action code. */
960 uint8_t u8Action;
961 /** Reserved. */
962 uint8_t u8Reserved;
963 /** Message length. */
964 uint8_t u8MessageLength;
965 /** Function number. */
966 uint8_t u8Function;
967 /** Extended page length. */
968 uint16_t u16ExtPageLength;
969 /** Extended page type */
970 uint8_t u8ExtPageType;
971 /** Message flags. */
972 uint8_t u8MessageFlags;
973 /** Message context ID. */
974 uint32_t u32MessageContext;
975 /** Reserved. */
976 uint16_t u16Reserved;
977 /** I/O controller status. */
978 uint16_t u16IOCStatus;
979 /** I/O controller log information. */
980 uint32_t u32IOCLogInfo;
981 /** Version number of the page. */
982 uint8_t u8PageVersion;
983 /** Length of the page in 32bit Dwords. */
984 uint8_t u8PageLength;
985 /** Page number to access. */
986 uint8_t u8PageNumber;
987 /** Type of the page beeing accessed. */
988 uint8_t u8PageType;
989} MptConfigurationReply, *PMptConfigurationReply;
990#pragma pack()
991AssertCompileSize(MptConfigurationReply, 24);
992
993/** Additional I/O controller status codes for the configuration reply. */
994#define MPT_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
995#define MPT_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
996#define MPT_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
997#define MPT_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
998#define MPT_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
999#define MPT_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
1000
1001/**
1002 * Union of all possible request messages.
1003 */
1004typedef union MptRequestUnion
1005{
1006 MptMessageHdr Header;
1007 MptIOCInitRequest IOCInit;
1008 MptIOCFactsRequest IOCFacts;
1009 MptPortFactsRequest PortFacts;
1010 MptPortEnableRequest PortEnable;
1011 MptEventNotificationRequest EventNotification;
1012 MptSCSIIORequest SCSIIO;
1013 MptSCSITaskManagementRequest SCSITaskManagement;
1014 MptConfigurationRequest Configuration;
1015} MptRequestUnion, *PMptRequestUnion;
1016
1017/**
1018 * Union of all possible reply messages.
1019 */
1020typedef union MptReplyUnion
1021{
1022 /** 16bit view. */
1023 uint16_t au16Reply[30];
1024 MptDefaultReplyMessage Header;
1025 MptIOCInitReply IOCInit;
1026 MptIOCFactsReply IOCFacts;
1027 MptPortFactsReply PortFacts;
1028 MptPortEnableReply PortEnable;
1029 MptEventNotificationReply EventNotification;
1030 MptSCSIIOErrorReply SCSIIOError;
1031 MptSCSITaskManagementReply SCSITaskManagement;
1032 MptConfigurationReply Configuration;
1033} MptReplyUnion, *PMptReplyUnion;
1034
1035
1036/**
1037 * Configuration Page attributes.
1038 */
1039#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY (0x00)
1040#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE (0x10)
1041#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT (0x20)
1042#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY (0x30)
1043
1044#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_GET(u8PageType) ((u8PageType) & 0xf0)
1045
1046/**
1047 * Configuration Page types.
1048 */
1049#define MPT_CONFIGURATION_PAGE_TYPE_IO_UNIT (0x00)
1050#define MPT_CONFIGURATION_PAGE_TYPE_IOC (0x01)
1051#define MPT_CONFIGURATION_PAGE_TYPE_BIOS (0x02)
1052#define MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT (0x03)
1053#define MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE (0x04)
1054#define MPT_CONFIGURATION_PAGE_TYPE_MANUFACTURING (0x09)
1055#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED (0x0F)
1056
1057#define MPT_CONFIGURATION_PAGE_TYPE_GET(u8PageType) ((u8PageType) & 0x0f)
1058
1059/**
1060 * Extented page types.
1061 */
1062#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT (0x10)
1063#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASEXPANDER (0x11)
1064#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE (0x12)
1065#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASPHYS (0x13)
1066#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_LOG (0x14)
1067#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_ENCLOSURE (0x15)
1068
1069/**
1070 * Configuration Page header - Common to all pages.
1071 */
1072#pragma pack(1)
1073typedef struct MptConfigurationPageHeader
1074{
1075 /** Version of the page. */
1076 uint8_t u8PageVersion;
1077 /** The length of the page in 32bit D-Words. */
1078 uint8_t u8PageLength;
1079 /** Number of the page. */
1080 uint8_t u8PageNumber;
1081 /** Type of the page. */
1082 uint8_t u8PageType;
1083} MptConfigurationPageHeader, *PMptConfigurationPageHeader;
1084#pragma pack()
1085AssertCompileSize(MptConfigurationPageHeader, 4);
1086
1087/**
1088 * Extended configuration page header - Common to all extended pages.
1089 */
1090#pragma pack(1)
1091typedef struct MptExtendedConfigurationPageHeader
1092{
1093 /** Version of the page. */
1094 uint8_t u8PageVersion;
1095 /** Reserved. */
1096 uint8_t u8Reserved1;
1097 /** Number of the page. */
1098 uint8_t u8PageNumber;
1099 /** Type of the page. */
1100 uint8_t u8PageType;
1101 /** Extended page length. */
1102 uint16_t u16ExtPageLength;
1103 /** Extended page type. */
1104 uint8_t u8ExtPageType;
1105 /** Reserved */
1106 uint8_t u8Reserved2;
1107} MptExtendedConfigurationPageHeader, *PMptExtendedConfigurationPageHeader;
1108#pragma pack()
1109AssertCompileSize(MptExtendedConfigurationPageHeader, 8);
1110
1111/**
1112 * Manufacturing page 0. - Readonly.
1113 */
1114#pragma pack(1)
1115typedef struct MptConfigurationPageManufacturing0
1116{
1117 /** Union. */
1118 union
1119 {
1120 /** Byte view. */
1121 uint8_t abPageData[76];
1122 /** Field view. */
1123 struct
1124 {
1125 /** The omnipresent header. */
1126 MptConfigurationPageHeader Header;
1127 /** Name of the chip. */
1128 uint8_t abChipName[16];
1129 /** Chip revision. */
1130 uint8_t abChipRevision[8];
1131 /** Board name. */
1132 uint8_t abBoardName[16];
1133 /** Board assembly. */
1134 uint8_t abBoardAssembly[16];
1135 /** Board tracer number. */
1136 uint8_t abBoardTracerNumber[16];
1137 } fields;
1138 } u;
1139} MptConfigurationPageManufacturing0, *PMptConfigurationPageManufacturing0;
1140#pragma pack()
1141AssertCompileSize(MptConfigurationPageManufacturing0, 76);
1142
1143/**
1144 * Manufacturing page 1. - Readonly Persistent.
1145 */
1146#pragma pack(1)
1147typedef struct MptConfigurationPageManufacturing1
1148{
1149 /** Union */
1150 union
1151 {
1152 /** Byte view */
1153 uint8_t abPageData[260];
1154 /** Field view */
1155 struct
1156 {
1157 /** The omnipresent header. */
1158 MptConfigurationPageHeader Header;
1159 /** VPD info - don't know what belongs here so all zero. */
1160 uint8_t abVPDInfo[256];
1161 } fields;
1162 } u;
1163} MptConfigurationPageManufacturing1, *PMptConfigurationPageManufacturing1;
1164#pragma pack()
1165AssertCompileSize(MptConfigurationPageManufacturing1, 260);
1166
1167/**
1168 * Manufacturing page 2. - Readonly.
1169 */
1170#pragma pack(1)
1171typedef struct MptConfigurationPageManufacturing2
1172{
1173 /** Union. */
1174 union
1175 {
1176 /** Byte view. */
1177 uint8_t abPageData[8];
1178 /** Field view. */
1179 struct
1180 {
1181 /** The omnipresent header. */
1182 MptConfigurationPageHeader Header;
1183 /** PCI Device ID. */
1184 uint16_t u16PCIDeviceID;
1185 /** PCI Revision ID. */
1186 uint8_t u8PCIRevisionID;
1187 /** Reserved. */
1188 uint8_t u8Reserved;
1189 /** Hardware specific settings... */
1190 } fields;
1191 } u;
1192} MptConfigurationPageManufacturing2, *PMptConfigurationPageManufacturing2;
1193#pragma pack()
1194AssertCompileSize(MptConfigurationPageManufacturing2, 8);
1195
1196/**
1197 * Manufacturing page 3. - Readonly.
1198 */
1199#pragma pack(1)
1200typedef struct MptConfigurationPageManufacturing3
1201{
1202 /** Union. */
1203 union
1204 {
1205 /** Byte view. */
1206 uint8_t abPageData[8];
1207 /** Field view. */
1208 struct
1209 {
1210 /** The omnipresent header. */
1211 MptConfigurationPageHeader Header;
1212 /** PCI Device ID. */
1213 uint16_t u16PCIDeviceID;
1214 /** PCI Revision ID. */
1215 uint8_t u8PCIRevisionID;
1216 /** Reserved. */
1217 uint8_t u8Reserved;
1218 /** Chip specific settings... */
1219 } fields;
1220 } u;
1221} MptConfigurationPageManufacturing3, *PMptConfigurationPageManufacturing3;
1222#pragma pack()
1223AssertCompileSize(MptConfigurationPageManufacturing3, 8);
1224
1225/**
1226 * Manufacturing page 4. - Readonly.
1227 */
1228#pragma pack(1)
1229typedef struct MptConfigurationPageManufacturing4
1230{
1231 /** Union. */
1232 union
1233 {
1234 /** Byte view. */
1235 uint8_t abPageData[84];
1236 /** Field view. */
1237 struct
1238 {
1239 /** The omnipresent header. */
1240 MptConfigurationPageHeader Header;
1241 /** Reserved. */
1242 uint32_t u32Reserved;
1243 /** InfoOffset0. */
1244 uint8_t u8InfoOffset0;
1245 /** Info size. */
1246 uint8_t u8InfoSize0;
1247 /** InfoOffset1. */
1248 uint8_t u8InfoOffset1;
1249 /** Info size. */
1250 uint8_t u8InfoSize1;
1251 /** Size of the inquiry data. */
1252 uint8_t u8InquirySize;
1253 /** Reserved. */
1254 uint8_t abReserved[3];
1255 /** Inquiry data. */
1256 uint8_t abInquiryData[56];
1257 /** IS volume settings. */
1258 uint32_t u32ISVolumeSettings;
1259 /** IME volume settings. */
1260 uint32_t u32IMEVolumeSettings;
1261 /** IM volume settings. */
1262 uint32_t u32IMVolumeSettings;
1263 } fields;
1264 } u;
1265} MptConfigurationPageManufacturing4, *PMptConfigurationPageManufacturing4;
1266#pragma pack()
1267AssertCompileSize(MptConfigurationPageManufacturing4, 84);
1268
1269/**
1270 * Manufacturing page 5 - Readonly.
1271 */
1272#pragma pack(1)
1273typedef struct MptConfigurationPageManufacturing5
1274{
1275 /** Union. */
1276 union
1277 {
1278 /** Byte view. */
1279 uint8_t abPageData[88];
1280 /** Field view. */
1281 struct
1282 {
1283 /** The omnipresent header. */
1284 MptConfigurationPageHeader Header;
1285 /** Base WWID. */
1286 uint64_t u64BaseWWID;
1287 /** Flags */
1288 uint8_t u8Flags;
1289 /** Number of ForceWWID fields in this page. */
1290 uint8_t u8NumForceWWID;
1291 /** Reserved */
1292 uint16_t u16Reserved;
1293 /** Reserved */
1294 uint32_t au32Reserved[2];
1295 /** ForceWWID entries Maximum of 8 because the SAS controller doesn't has more */
1296 uint64_t au64ForceWWID[8];
1297 } fields;
1298 } u;
1299} MptConfigurationPageManufacturing5, *PMptConfigurationPageManufacturing5;
1300#pragma pack()
1301AssertCompileSize(MptConfigurationPageManufacturing5, 24+64);
1302
1303/**
1304 * Manufacturing page 6 - Readonly.
1305 */
1306#pragma pack(1)
1307typedef struct MptConfigurationPageManufacturing6
1308{
1309 /** Union. */
1310 union
1311 {
1312 /** Byte view. */
1313 uint8_t abPageData[4];
1314 /** Field view. */
1315 struct
1316 {
1317 /** The omnipresent header. */
1318 MptConfigurationPageHeader Header;
1319 /** Product specific data - 0 for now */
1320 } fields;
1321 } u;
1322} MptConfigurationPageManufacturing6, *PMptConfigurationPageManufacturing6;
1323#pragma pack()
1324AssertCompileSize(MptConfigurationPageManufacturing6, 4);
1325
1326/**
1327 * Manufacutring page 7 - PHY element.
1328 */
1329#pragma pack(1)
1330typedef struct MptConfigurationPageManufacturing7PHY
1331{
1332 /** Pinout */
1333 uint32_t u32Pinout;
1334 /** Connector name */
1335 uint8_t szConnector[16];
1336 /** Location */
1337 uint8_t u8Location;
1338 /** reserved */
1339 uint8_t u8Reserved;
1340 /** Slot */
1341 uint16_t u16Slot;
1342} MptConfigurationPageManufacturing7PHY, *PMptConfigurationPageManufacturing7PHY;
1343#pragma pack()
1344AssertCompileSize(MptConfigurationPageManufacturing7PHY, 24);
1345
1346/**
1347 * Manufacturing page 7 - Readonly.
1348 */
1349#pragma pack(1)
1350typedef struct MptConfigurationPageManufacturing7
1351{
1352 /** Union. */
1353 union
1354 {
1355 /** Byte view. */
1356 uint8_t abPageData[1];
1357 /** Field view. */
1358 struct
1359 {
1360 /** The omnipresent header. */
1361 MptConfigurationPageHeader Header;
1362 /** Reserved */
1363 uint32_t au32Reserved[2];
1364 /** Flags */
1365 uint32_t u32Flags;
1366 /** Enclosure name */
1367 uint8_t szEnclosureName[16];
1368 /** Nummber of PHYs */
1369 uint8_t u8NumPhys;
1370 /** Reserved */
1371 uint8_t au8Reserved[3];
1372 /** PHY list for the SAS controller - variable depending on the number of ports */
1373 MptConfigurationPageManufacturing7PHY aPHY[1];
1374 } fields;
1375 } u;
1376} MptConfigurationPageManufacturing7, *PMptConfigurationPageManufacturing7;
1377#pragma pack()
1378AssertCompileSize(MptConfigurationPageManufacturing7, 36+sizeof(MptConfigurationPageManufacturing7PHY));
1379
1380#define LSILOGICSCSI_MANUFACTURING7_GET_SIZE(ports) (sizeof(MptConfigurationPageManufacturing7) + ((ports) - 1) * sizeof(MptConfigurationPageManufacturing7PHY))
1381
1382/** Flags for the flags field */
1383#define LSILOGICSCSI_MANUFACTURING7_FLAGS_USE_PROVIDED_INFORMATION RT_BIT(0)
1384
1385/** Flags for the pinout field */
1386#define LSILOGICSCSI_MANUFACTURING7_PINOUT_UNKNOWN RT_BIT(0)
1387#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8482 RT_BIT(1)
1388#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8470_LANE1 RT_BIT(8)
1389#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8470_LANE2 RT_BIT(9)
1390#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8470_LANE3 RT_BIT(10)
1391#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8470_LANE4 RT_BIT(11)
1392#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8484_LANE1 RT_BIT(16)
1393#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8484_LANE2 RT_BIT(17)
1394#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8484_LANE3 RT_BIT(18)
1395#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8484_LANE4 RT_BIT(19)
1396
1397/** Flags for the location field */
1398#define LSILOGICSCSI_MANUFACTURING7_LOCATION_UNKNOWN 0x01
1399#define LSILOGICSCSI_MANUFACTURING7_LOCATION_INTERNAL 0x02
1400#define LSILOGICSCSI_MANUFACTURING7_LOCATION_EXTERNAL 0x04
1401#define LSILOGICSCSI_MANUFACTURING7_LOCATION_SWITCHABLE 0x08
1402#define LSILOGICSCSI_MANUFACTURING7_LOCATION_AUTO 0x10
1403#define LSILOGICSCSI_MANUFACTURING7_LOCATION_NOT_PRESENT 0x20
1404#define LSILOGICSCSI_MANUFACTURING7_LOCATION_NOT_CONNECTED 0x80
1405
1406/**
1407 * Manufacturing page 8 - Readonly.
1408 */
1409#pragma pack(1)
1410typedef struct MptConfigurationPageManufacturing8
1411{
1412 /** Union. */
1413 union
1414 {
1415 /** Byte view. */
1416 uint8_t abPageData[4];
1417 /** Field view. */
1418 struct
1419 {
1420 /** The omnipresent header. */
1421 MptConfigurationPageHeader Header;
1422 /** Product specific information */
1423 } fields;
1424 } u;
1425} MptConfigurationPageManufacturing8, *PMptConfigurationPageManufacturing8;
1426#pragma pack()
1427AssertCompileSize(MptConfigurationPageManufacturing8, 4);
1428
1429/**
1430 * Manufacturing page 9 - Readonly.
1431 */
1432#pragma pack(1)
1433typedef struct MptConfigurationPageManufacturing9
1434{
1435 /** Union. */
1436 union
1437 {
1438 /** Byte view. */
1439 uint8_t abPageData[4];
1440 /** Field view. */
1441 struct
1442 {
1443 /** The omnipresent header. */
1444 MptConfigurationPageHeader Header;
1445 /** Product specific information */
1446 } fields;
1447 } u;
1448} MptConfigurationPageManufacturing9, *PMptConfigurationPageManufacturing9;
1449#pragma pack()
1450AssertCompileSize(MptConfigurationPageManufacturing9, 4);
1451
1452/**
1453 * Manufacturing page 10 - Readonly.
1454 */
1455#pragma pack(1)
1456typedef struct MptConfigurationPageManufacturing10
1457{
1458 /** Union. */
1459 union
1460 {
1461 /** Byte view. */
1462 uint8_t abPageData[4];
1463 /** Field view. */
1464 struct
1465 {
1466 /** The omnipresent header. */
1467 MptConfigurationPageHeader Header;
1468 /** Product specific information */
1469 } fields;
1470 } u;
1471} MptConfigurationPageManufacturing10, *PMptConfigurationPageManufacturing10;
1472#pragma pack()
1473AssertCompileSize(MptConfigurationPageManufacturing10, 4);
1474
1475/**
1476 * IO Unit page 0. - Readonly.
1477 */
1478#pragma pack(1)
1479typedef struct MptConfigurationPageIOUnit0
1480{
1481 /** Union. */
1482 union
1483 {
1484 /** Byte view. */
1485 uint8_t abPageData[12];
1486 /** Field view. */
1487 struct
1488 {
1489 /** The omnipresent header. */
1490 MptConfigurationPageHeader Header;
1491 /** A unique identifier. */
1492 uint64_t u64UniqueIdentifier;
1493 } fields;
1494 } u;
1495} MptConfigurationPageIOUnit0, *PMptConfigurationPageIOUnit0;
1496#pragma pack()
1497AssertCompileSize(MptConfigurationPageIOUnit0, 12);
1498
1499/**
1500 * IO Unit page 1. - Read/Write.
1501 */
1502#pragma pack(1)
1503typedef struct MptConfigurationPageIOUnit1
1504{
1505 /** Union. */
1506 union
1507 {
1508 /** Byte view. */
1509 uint8_t abPageData[8];
1510 /** Field view. */
1511 struct
1512 {
1513 /** The omnipresent header. */
1514 MptConfigurationPageHeader Header;
1515 /** Flag whether this is a single function PCI device. */
1516 unsigned fSingleFunction: 1;
1517 /** Flag whether all possible paths to a device are mapped. */
1518 unsigned fAllPathsMapped: 1;
1519 /** Reserved. */
1520 unsigned u4Reserved: 4;
1521 /** Flag whether all RAID functionality is disabled. */
1522 unsigned fIntegratedRAIDDisabled: 1;
1523 /** Flag whether 32bit PCI accesses are forced. */
1524 unsigned f32BitAccessForced: 1;
1525 /** Reserved. */
1526 unsigned abReserved: 24;
1527 } fields;
1528 } u;
1529} MptConfigurationPageIOUnit1, *PMptConfigurationPageIOUnit1;
1530#pragma pack()
1531AssertCompileSize(MptConfigurationPageIOUnit1, 8);
1532
1533/**
1534 * Adapter Ordering.
1535 */
1536#pragma pack(1)
1537typedef struct MptConfigurationPageIOUnit2AdapterOrdering
1538{
1539 /** PCI bus number. */
1540 unsigned u8PCIBusNumber: 8;
1541 /** PCI device and function number. */
1542 unsigned u8PCIDevFn: 8;
1543 /** Flag whether the adapter is embedded. */
1544 unsigned fAdapterEmbedded: 1;
1545 /** Flag whether the adapter is enabled. */
1546 unsigned fAdapterEnabled: 1;
1547 /** Reserved. */
1548 unsigned u6Reserved: 6;
1549 /** Reserved. */
1550 unsigned u8Reserved: 8;
1551} MptConfigurationPageIOUnit2AdapterOrdering, *PMptConfigurationPageIOUnit2AdapterOrdering;
1552#pragma pack()
1553AssertCompileSize(MptConfigurationPageIOUnit2AdapterOrdering, 4);
1554
1555/**
1556 * IO Unit page 2. - Read/Write.
1557 */
1558#pragma pack(1)
1559typedef struct MptConfigurationPageIOUnit2
1560{
1561 /** Union. */
1562 union
1563 {
1564 /** Byte view. */
1565 uint8_t abPageData[28];
1566 /** Field view. */
1567 struct
1568 {
1569 /** The omnipresent header. */
1570 MptConfigurationPageHeader Header;
1571 /** Reserved. */
1572 unsigned fReserved: 1;
1573 /** Flag whether Pause on error is enabled. */
1574 unsigned fPauseOnError: 1;
1575 /** Flag whether verbose mode is enabled. */
1576 unsigned fVerboseModeEnabled: 1;
1577 /** Set to disable color video. */
1578 unsigned fDisableColorVideo: 1;
1579 /** Flag whether int 40h is hooked. */
1580 unsigned fNotHookInt40h: 1;
1581 /** Reserved. */
1582 unsigned u3Reserved: 3;
1583 /** Reserved. */
1584 unsigned abReserved: 24;
1585 /** BIOS version. */
1586 uint32_t u32BIOSVersion;
1587 /** Adapter ordering. */
1588 MptConfigurationPageIOUnit2AdapterOrdering aAdapterOrder[4];
1589 } fields;
1590 } u;
1591} MptConfigurationPageIOUnit2, *PMptConfigurationPageIOUnit2;
1592#pragma pack()
1593AssertCompileSize(MptConfigurationPageIOUnit2, 28);
1594
1595/*
1596 * IO Unit page 3. - Read/Write.
1597 */
1598#pragma pack(1)
1599typedef struct MptConfigurationPageIOUnit3
1600{
1601 /** Union. */
1602 union
1603 {
1604 /** Byte view. */
1605 uint8_t abPageData[8];
1606 /** Field view. */
1607 struct
1608 {
1609 /** The omnipresent header. */
1610 MptConfigurationPageHeader Header;
1611 /** Number of GPIO values. */
1612 uint8_t u8GPIOCount;
1613 /** Reserved. */
1614 uint8_t abReserved[3];
1615 } fields;
1616 } u;
1617} MptConfigurationPageIOUnit3, *PMptConfigurationPageIOUnit3;
1618#pragma pack()
1619AssertCompileSize(MptConfigurationPageIOUnit3, 8);
1620
1621/*
1622 * IO Unit page 4. - Readonly for everyone except the BIOS.
1623 */
1624#pragma pack(1)
1625typedef struct MptConfigurationPageIOUnit4
1626{
1627 /** Union. */
1628 union
1629 {
1630 /** Byte view. */
1631 uint8_t abPageData[20];
1632 /** Field view. */
1633 struct
1634 {
1635 /** The omnipresent header. */
1636 MptConfigurationPageHeader Header;
1637 /** Reserved */
1638 uint32_t u32Reserved;
1639 /** SG entry describing the Firmware location. */
1640 MptSGEntrySimple64 FWImageSGE;
1641 } fields;
1642 } u;
1643} MptConfigurationPageIOUnit4, *PMptConfigurationPageIOUnit4;
1644#pragma pack()
1645AssertCompileSize(MptConfigurationPageIOUnit4, 20);
1646
1647/**
1648 * IOC page 0. - Readonly
1649 */
1650#pragma pack(1)
1651typedef struct MptConfigurationPageIOC0
1652{
1653 /** Union. */
1654 union
1655 {
1656 /** Byte view. */
1657 uint8_t abPageData[28];
1658 /** Field view. */
1659 struct
1660 {
1661 /** The omnipresent header. */
1662 MptConfigurationPageHeader Header;
1663 /** Total ammount of NV memory in bytes. */
1664 uint32_t u32TotalNVStore;
1665 /** Number of free bytes in the NV store. */
1666 uint32_t u32FreeNVStore;
1667 /** PCI vendor ID. */
1668 uint16_t u16VendorId;
1669 /** PCI device ID. */
1670 uint16_t u16DeviceId;
1671 /** PCI revision ID. */
1672 uint8_t u8RevisionId;
1673 /** Reserved. */
1674 uint8_t abReserved[3];
1675 /** PCI class code. */
1676 uint32_t u32ClassCode;
1677 /** Subsystem vendor Id. */
1678 uint16_t u16SubsystemVendorId;
1679 /** Subsystem Id. */
1680 uint16_t u16SubsystemId;
1681 } fields;
1682 } u;
1683} MptConfigurationPageIOC0, *PMptConfigurationPageIOC0;
1684#pragma pack()
1685AssertCompileSize(MptConfigurationPageIOC0, 28);
1686
1687/**
1688 * IOC page 1. - Read/Write
1689 */
1690#pragma pack(1)
1691typedef struct MptConfigurationPageIOC1
1692{
1693 /** Union. */
1694 union
1695 {
1696 /** Byte view. */
1697 uint8_t abPageData[16];
1698 /** Field view. */
1699 struct
1700 {
1701 /** The omnipresent header. */
1702 MptConfigurationPageHeader Header;
1703 /** Flag whether reply coalescing is enabled. */
1704 unsigned fReplyCoalescingEnabled: 1;
1705 /** Reserved. */
1706 unsigned u31Reserved: 31;
1707 /** Coalescing Timeout in microseconds. */
1708 unsigned u32CoalescingTimeout: 32;
1709 /** Coalescing depth. */
1710 unsigned u8CoalescingDepth: 8;
1711 /** Reserved. */
1712 unsigned u8Reserved0: 8;
1713 unsigned u8Reserved1: 8;
1714 unsigned u8Reserved2: 8;
1715 } fields;
1716 } u;
1717} MptConfigurationPageIOC1, *PMptConfigurationPageIOC1;
1718#pragma pack()
1719AssertCompileSize(MptConfigurationPageIOC1, 16);
1720
1721/**
1722 * IOC page 2. - Readonly
1723 */
1724#pragma pack(1)
1725typedef struct MptConfigurationPageIOC2
1726{
1727 /** Union. */
1728 union
1729 {
1730 /** Byte view. */
1731 uint8_t abPageData[12];
1732 /** Field view. */
1733 struct
1734 {
1735 /** The omnipresent header. */
1736 MptConfigurationPageHeader Header;
1737 /** Flag whether striping is supported. */
1738 unsigned fStripingSupported: 1;
1739 /** Flag whether enhanced mirroring is supported. */
1740 unsigned fEnhancedMirroringSupported: 1;
1741 /** Flag whether mirroring is supported. */
1742 unsigned fMirroringSupported: 1;
1743 /** Reserved. */
1744 unsigned u26Reserved: 26;
1745 /** Flag whether SES is supported. */
1746 unsigned fSESSupported: 1;
1747 /** Flag whether SAF-TE is supported. */
1748 unsigned fSAFTESupported: 1;
1749 /** Flag whether cross channel volumes are supported. */
1750 unsigned fCrossChannelVolumesSupported: 1;
1751 /** Number of active integrated RAID volumes. */
1752 unsigned u8NumActiveVolumes: 8;
1753 /** Maximum number of integrated RAID volumes supported. */
1754 unsigned u8MaxVolumes: 8;
1755 /** Number of active integrated RAID physical disks. */
1756 unsigned u8NumActivePhysDisks: 8;
1757 /** Maximum number of integrated RAID physical disks supported. */
1758 unsigned u8MaxPhysDisks: 8;
1759 /** RAID volumes... - not supported. */
1760 } fields;
1761 } u;
1762} MptConfigurationPageIOC2, *PMptConfigurationPageIOC2;
1763#pragma pack()
1764AssertCompileSize(MptConfigurationPageIOC2, 12);
1765
1766/**
1767 * IOC page 3. - Readonly
1768 */
1769#pragma pack(1)
1770typedef struct MptConfigurationPageIOC3
1771{
1772 /** Union. */
1773 union
1774 {
1775 /** Byte view. */
1776 uint8_t abPageData[8];
1777 /** Field view. */
1778 struct
1779 {
1780 /** The omnipresent header. */
1781 MptConfigurationPageHeader Header;
1782 /** Number of active integrated RAID physical disks. */
1783 uint8_t u8NumPhysDisks;
1784 /** Reserved. */
1785 uint8_t abReserved[3];
1786 } fields;
1787 } u;
1788} MptConfigurationPageIOC3, *PMptConfigurationPageIOC3;
1789#pragma pack()
1790AssertCompileSize(MptConfigurationPageIOC3, 8);
1791
1792/**
1793 * IOC page 4. - Read/Write
1794 */
1795#pragma pack(1)
1796typedef struct MptConfigurationPageIOC4
1797{
1798 /** Union. */
1799 union
1800 {
1801 /** Byte view. */
1802 uint8_t abPageData[8];
1803 /** Field view. */
1804 struct
1805 {
1806 /** The omnipresent header. */
1807 MptConfigurationPageHeader Header;
1808 /** Number of SEP entries in this page. */
1809 uint8_t u8ActiveSEP;
1810 /** Maximum number of SEp entries supported. */
1811 uint8_t u8MaxSEP;
1812 /** Reserved. */
1813 uint16_t u16Reserved;
1814 /** SEP entries... - not supported. */
1815 } fields;
1816 } u;
1817} MptConfigurationPageIOC4, *PMptConfigurationPageIOC4;
1818#pragma pack()
1819AssertCompileSize(MptConfigurationPageIOC4, 8);
1820
1821/**
1822 * IOC page 6. - Read/Write
1823 */
1824#pragma pack(1)
1825typedef struct MptConfigurationPageIOC6
1826{
1827 /** Union. */
1828 union
1829 {
1830 /** Byte view. */
1831 uint8_t abPageData[60];
1832 /** Field view. */
1833 struct
1834 {
1835 /** The omnipresent header. */
1836 MptConfigurationPageHeader Header;
1837 uint32_t u32CapabilitiesFlags;
1838 uint8_t u8MaxDrivesIS;
1839 uint8_t u8MaxDrivesIM;
1840 uint8_t u8MaxDrivesIME;
1841 uint8_t u8Reserved1;
1842 uint8_t u8MinDrivesIS;
1843 uint8_t u8MinDrivesIM;
1844 uint8_t u8MinDrivesIME;
1845 uint8_t u8Reserved2;
1846 uint8_t u8MaxGlobalHotSpares;
1847 uint8_t u8Reserved3;
1848 uint16_t u16Reserved4;
1849 uint32_t u32Reserved5;
1850 uint32_t u32SupportedStripeSizeMapIS;
1851 uint32_t u32SupportedStripeSizeMapIME;
1852 uint32_t u32Reserved6;
1853 uint8_t u8MetadataSize;
1854 uint8_t u8Reserved7;
1855 uint16_t u16Reserved8;
1856 uint16_t u16MaxBadBlockTableEntries;
1857 uint16_t u16Reserved9;
1858 uint16_t u16IRNvsramUsage;
1859 uint16_t u16Reserved10;
1860 uint32_t u32IRNvsramVersion;
1861 uint32_t u32Reserved11;
1862 } fields;
1863 } u;
1864} MptConfigurationPageIOC6, *PMptConfigurationPageIOC6;
1865#pragma pack()
1866AssertCompileSize(MptConfigurationPageIOC6, 60);
1867
1868/**
1869 * BIOS page 1 - Read/write.
1870 */
1871#pragma pack(1)
1872typedef struct MptConfigurationPageBIOS1
1873{
1874 /** Union. */
1875 union
1876 {
1877 /** Byte view. */
1878 uint8_t abPageData[48];
1879 /** Field view. */
1880 struct
1881 {
1882 /** The omnipresent header. */
1883 MptConfigurationPageHeader Header;
1884 /** BIOS options */
1885 uint32_t u32BiosOptions;
1886 /** IOC settings */
1887 uint32_t u32IOCSettings;
1888 /** Reserved */
1889 uint32_t u32Reserved;
1890 /** Device settings */
1891 uint32_t u32DeviceSettings;
1892 /** Number of devices */
1893 uint16_t u16NumberOfDevices;
1894 /** Expander spinup */
1895 uint8_t u8ExpanderSpinup;
1896 /** Reserved */
1897 uint8_t u8Reserved;
1898 /** I/O timeout of block devices without removable media */
1899 uint16_t u16IOTimeoutBlockDevicesNonRM;
1900 /** I/O timeout sequential */
1901 uint16_t u16IOTimeoutSequential;
1902 /** I/O timeout other */
1903 uint16_t u16IOTimeoutOther;
1904 /** I/O timeout of block devices with removable media */
1905 uint16_t u16IOTimeoutBlockDevicesRM;
1906 } fields;
1907 } u;
1908} MptConfigurationPageBIOS1, *PMptConfigurationPageBIOS1;
1909#pragma pack()
1910AssertCompileSize(MptConfigurationPageBIOS1, 48);
1911
1912#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_BIOS_DISABLE RT_BIT(0)
1913#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_SCAN_FROM_HIGH_TO_LOW RT_BIT(1)
1914#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_BIOS_EXTENDED_SAS_SUPPORT RT_BIT(8)
1915#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_BIOS_EXTENDED_FC_SUPPORT RT_BIT(9)
1916#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_BIOS_EXTENDED_SPI_SUPPORT RT_BIT(10)
1917
1918#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ALTERNATE_CHS RT_BIT(3)
1919
1920#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_SET(x) ((x) << 4)
1921#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_DISABLED 0x00
1922#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_BIOS_ONLY 0x01
1923#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_OS_ONLY 0x02
1924#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_BOT 0x03
1925
1926#define LSILOGICSCSI_BIOS1_IOCSETTINGS_REMOVABLE_MEDIA_SET(x) ((x) << 6)
1927#define LSILOGICSCSI_BIOS1_IOCSETTINGS_REMOVABLE_MEDIA_NO_INT13H 0x00
1928#define LSILOGICSCSI_BIOS1_IOCSETTINGS_REMOVABLE_BOOT_MEDIA_INT13H 0x01
1929#define LSILOGICSCSI_BIOS1_IOCSETTINGS_REMOVABLE_MEDIA_INT13H 0x02
1930
1931#define LSILOGICSCSI_BIOS1_IOCSETTINGS_SPINUP_DELAY_SET(x) ((x & 0xF) << 8)
1932#define LSILOGICSCSI_BIOS1_IOCSETTINGS_SPINUP_DELAY_GET(x) ((x >> 8) & 0x0F)
1933#define LSILOGICSCSI_BIOS1_IOCSETTINGS_MAX_TARGET_SPINUP_SET(x) ((x & 0xF) << 12)
1934#define LSILOGICSCSI_BIOS1_IOCSETTINGS_MAX_TARGET_SPINUP_GET(x) ((x >> 12) & 0x0F)
1935
1936#define LSILOGICSCSI_BIOS1_IOCSETTINGS_BOOT_PREFERENCE_SET(x) (((x) & 0x3) << 16)
1937#define LSILOGICSCSI_BIOS1_IOCSETTINGS_BOOT_PREFERENCE_ENCLOSURE 0x0
1938#define LSILOGICSCSI_BIOS1_IOCSETTINGS_BOOT_PREFERENCE_SAS_ADDRESS 0x1
1939
1940#define LSILOGICSCSI_BIOS1_IOCSETTINGS_DIRECT_ATTACH_SPINUP_MODE_ALL RT_BIT(18)
1941#define LSILOGICSCSI_BIOS1_IOCSETTINGS_AUTO_PORT_ENABLE RT_BIT(19)
1942
1943#define LSILOGICSCSI_BIOS1_IOCSETTINGS_PORT_ENABLE_REPLY_DELAY_SET(x) (((x) & 0xF) << 20)
1944#define LSILOGICSCSI_BIOS1_IOCSETTINGS_PORT_ENABLE_REPLY_DELAY_GET(x) ((x >> 20) & 0x0F)
1945
1946#define LSILOGICSCSI_BIOS1_IOCSETTINGS_PORT_ENABLE_SPINUP_DELAY_SET(x) (((x) & 0xF) << 24)
1947#define LSILOGICSCSI_BIOS1_IOCSETTINGS_PORT_ENABLE_SPINUP_DELAY_GET(x) ((x >> 24) & 0x0F)
1948
1949#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_LUN_SCANS RT_BIT(0)
1950#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_LUN_SCANS_FOR_NON_REMOVABLE_DEVICES RT_BIT(1)
1951#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_LUN_SCANS_FOR_REMOVABLE_DEVICES RT_BIT(2)
1952#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_LUN_SCANS2 RT_BIT(3)
1953#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_SMART_POLLING RT_BIT(4)
1954
1955#define LSILOGICSCSI_BIOS1_EXPANDERSPINUP_SPINUP_DELAY_SET(x) ((x) & 0x0F)
1956#define LSILOGICSCSI_BIOS1_EXPANDERSPINUP_SPINUP_DELAY_GET(x) ((x) & 0x0F)
1957#define LSILOGICSCSI_BIOS1_EXPANDERSPINUP_MAX_SPINUP_DELAY_SET(x) (((x) & 0x0F) << 4)
1958#define LSILOGICSCSI_BIOS1_EXPANDERSPINUP_MAX_SPINUP_DELAY_GET(x) ((x >> 4) & 0x0F)
1959
1960/**
1961 * BIOS page 2 - Read/write.
1962 */
1963#pragma pack(1)
1964typedef struct MptConfigurationPageBIOS2
1965{
1966 /** Union. */
1967 union
1968 {
1969 /** Byte view. */
1970 uint8_t abPageData[384];
1971 /** Field view. */
1972 struct
1973 {
1974 /** The omnipresent header. */
1975 MptConfigurationPageHeader Header;
1976 /** Reserved */
1977 uint32_t au32Reserved[6];
1978 /** Format of the boot device field. */
1979 uint8_t u8BootDeviceForm;
1980 /** Previous format of the boot device field. */
1981 uint8_t u8PrevBootDeviceForm;
1982 /** Reserved */
1983 uint16_t u16Reserved;
1984 /** Boot device fields - dependent on the format */
1985 union
1986 {
1987 /** Device for AdapterNumber:Bus:Target:LUN */
1988 struct
1989 {
1990 /** Target ID */
1991 uint8_t u8TargetID;
1992 /** Bus */
1993 uint8_t u8Bus;
1994 /** Adapter Number */
1995 uint8_t u8AdapterNumber;
1996 /** Reserved */
1997 uint8_t u8Reserved;
1998 /** Reserved */
1999 uint32_t au32Reserved[3];
2000 /** LUN */
2001 uint32_t aLUN[5];
2002 /** Reserved */
2003 uint32_t au32Reserved2[56];
2004 } AdapterNumberBusTargetLUN;
2005 /** Device for PCIAddress:Bus:Target:LUN */
2006 struct
2007 {
2008 /** Target ID */
2009 uint8_t u8TargetID;
2010 /** Bus */
2011 uint8_t u8Bus;
2012 /** Adapter Number */
2013 uint16_t u16PCIAddress;
2014 /** Reserved */
2015 uint32_t au32Reserved[3];
2016 /** LUN */
2017 uint32_t aLUN[5];
2018 /** Reserved */
2019 uint32_t au32Reserved2[56];
2020 } PCIAddressBusTargetLUN;
2021 /** Device for PCISlotNo:Bus:Target:LUN */
2022 struct
2023 {
2024 /** Target ID */
2025 uint8_t u8TargetID;
2026 /** Bus */
2027 uint8_t u8Bus;
2028 /** PCI Slot Number */
2029 uint8_t u16PCISlotNo;
2030 /** Reserved */
2031 uint32_t au32Reserved[3];
2032 /** LUN */
2033 uint32_t aLUN[5];
2034 /** Reserved */
2035 uint32_t au32Reserved2[56];
2036 } PCIAddressBusSlotLUN;
2037 /** Device for FC channel world wide name */
2038 struct
2039 {
2040 /** World wide port name low */
2041 uint32_t u32WorldWidePortNameLow;
2042 /** World wide port name high */
2043 uint32_t u32WorldWidePortNameHigh;
2044 /** Reserved */
2045 uint32_t au32Reserved[3];
2046 /** LUN */
2047 uint32_t aLUN[5];
2048 /** Reserved */
2049 uint32_t au32Reserved2[56];
2050 } FCWorldWideName;
2051 /** Device for FC channel world wide name */
2052 struct
2053 {
2054 /** SAS address */
2055 SASADDRESS SASAddress;
2056 /** Reserved */
2057 uint32_t au32Reserved[3];
2058 /** LUN */
2059 uint32_t aLUN[5];
2060 /** Reserved */
2061 uint32_t au32Reserved2[56];
2062 } SASWorldWideName;
2063 /** Device for Enclosure/Slot */
2064 struct
2065 {
2066 /** Enclosure logical ID */
2067 uint64_t u64EnclosureLogicalID;
2068 /** Reserved */
2069 uint32_t au32Reserved[3];
2070 /** LUN */
2071 uint32_t aLUN[5];
2072 /** Reserved */
2073 uint32_t au32Reserved2[56];
2074 } EnclosureSlot;
2075 } BootDevice;
2076 } fields;
2077 } u;
2078} MptConfigurationPageBIOS2, *PMptConfigurationPageBIOS2;
2079#pragma pack()
2080AssertCompileSize(MptConfigurationPageBIOS2, 384);
2081
2082#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_SET(x) ((x) & 0x0F)
2083#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_FIRST 0x0
2084#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_ADAPTER_BUS_TARGET_LUN 0x1
2085#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_PCIADDR_BUS_TARGET_LUN 0x2
2086#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_PCISLOT_BUS_TARGET_LUN 0x3
2087#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_FC_WWN 0x4
2088#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_SAS_WWN 0x5
2089#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_ENCLOSURE_SLOT 0x6
2090
2091/**
2092 * BIOS page 4 - Read/Write (Where is 3? - not defined in the spec)
2093 */
2094#pragma pack(1)
2095typedef struct MptConfigurationPageBIOS4
2096{
2097 /** Union. */
2098 union
2099 {
2100 /** Byte view. */
2101 uint8_t abPageData[12];
2102 /** Field view. */
2103 struct
2104 {
2105 /** The omnipresent header. */
2106 MptConfigurationPageHeader Header;
2107 /** Reassignment Base WWID */
2108 uint64_t u64ReassignmentBaseWWID;
2109 } fields;
2110 } u;
2111} MptConfigurationPageBIOS4, *PMptConfigurationPageBIOS4;
2112#pragma pack()
2113AssertCompileSize(MptConfigurationPageBIOS4, 12);
2114
2115/**
2116 * SCSI-SPI port page 0. - Readonly
2117 */
2118#pragma pack(1)
2119typedef struct MptConfigurationPageSCSISPIPort0
2120{
2121 /** Union. */
2122 union
2123 {
2124 /** Byte view. */
2125 uint8_t abPageData[12];
2126 /** Field view. */
2127 struct
2128 {
2129 /** The omnipresent header. */
2130 MptConfigurationPageHeader Header;
2131 /** Flag whether this port is information unit trnafsers capable. */
2132 unsigned fInformationUnitTransfersCapable: 1;
2133 /** Flag whether the port is DT (Dual Transfer) capable. */
2134 unsigned fDTCapable: 1;
2135 /** Flag whether the port is QAS (Quick Arbitrate and Select) capable. */
2136 unsigned fQASCapable: 1;
2137 /** Reserved. */
2138 unsigned u5Reserved1: 5;
2139 /** Minimum Synchronous transfer period. */
2140 unsigned u8MinimumSynchronousTransferPeriod: 8;
2141 /** Maximum synchronous offset. */
2142 unsigned u8MaximumSynchronousOffset: 8;
2143 /** Reserved. */
2144 unsigned u5Reserved2: 5;
2145 /** Flag whether indicating the width of the bus - 0 narrow and 1 for wide. */
2146 unsigned fWide: 1;
2147 /** Reserved */
2148 unsigned fReserved: 1;
2149 /** Flag whether the port is AIP (Asynchronous Information Protection) capable. */
2150 unsigned fAIPCapable: 1;
2151 /** Signaling Type. */
2152 unsigned u2SignalingType: 2;
2153 /** Reserved. */
2154 unsigned u30Reserved: 30;
2155 } fields;
2156 } u;
2157} MptConfigurationPageSCSISPIPort0, *PMptConfigurationPageSCSISPIPort0;
2158#pragma pack()
2159AssertCompileSize(MptConfigurationPageSCSISPIPort0, 12);
2160
2161/**
2162 * SCSI-SPI port page 1. - Read/Write
2163 */
2164#pragma pack(1)
2165typedef struct MptConfigurationPageSCSISPIPort1
2166{
2167 /** Union. */
2168 union
2169 {
2170 /** Byte view. */
2171 uint8_t abPageData[12];
2172 /** Field view. */
2173 struct
2174 {
2175 /** The omnipresent header. */
2176 MptConfigurationPageHeader Header;
2177 /** The SCSI ID of the port. */
2178 uint8_t u8SCSIID;
2179 /** Reserved. */
2180 uint8_t u8Reserved;
2181 /** Port response IDs Bit mask field. */
2182 uint16_t u16PortResponseIDsBitmask;
2183 /** Value for the on BUS timer. */
2184 uint32_t u32OnBusTimerValue;
2185 } fields;
2186 } u;
2187} MptConfigurationPageSCSISPIPort1, *PMptConfigurationPageSCSISPIPort1;
2188#pragma pack()
2189AssertCompileSize(MptConfigurationPageSCSISPIPort1, 12);
2190
2191/**
2192 * Device settings for one device.
2193 */
2194#pragma pack(1)
2195typedef struct MptDeviceSettings
2196{
2197 /** Timeout for I/O in seconds. */
2198 unsigned u8Timeout: 8;
2199 /** Minimum synchronous factor. */
2200 unsigned u8SyncFactor: 8;
2201 /** Flag whether disconnect is enabled. */
2202 unsigned fDisconnectEnable: 1;
2203 /** Flag whether Scan ID is enabled. */
2204 unsigned fScanIDEnable: 1;
2205 /** Flag whether Scan LUNs is enabled. */
2206 unsigned fScanLUNEnable: 1;
2207 /** Flag whether tagged queuing is enabled. */
2208 unsigned fTaggedQueuingEnabled: 1;
2209 /** Flag whether wide is enabled. */
2210 unsigned fWideDisable: 1;
2211 /** Flag whether this device is bootable. */
2212 unsigned fBootChoice: 1;
2213 /** Reserved. */
2214 unsigned u10Reserved: 10;
2215} MptDeviceSettings, *PMptDeviceSettings;
2216#pragma pack()
2217AssertCompileSize(MptDeviceSettings, 4);
2218
2219/**
2220 * SCSI-SPI port page 2. - Read/Write for the BIOS
2221 */
2222#pragma pack(1)
2223typedef struct MptConfigurationPageSCSISPIPort2
2224{
2225 /** Union. */
2226 union
2227 {
2228 /** Byte view. */
2229 uint8_t abPageData[76];
2230 /** Field view. */
2231 struct
2232 {
2233 /** The omnipresent header. */
2234 MptConfigurationPageHeader Header;
2235 /** Flag indicating the bus scan order. */
2236 unsigned fBusScanOrderHighToLow: 1;
2237 /** Reserved. */
2238 unsigned fReserved: 1;
2239 /** Flag whether SCSI Bus resets are avoided. */
2240 unsigned fAvoidSCSIBusResets: 1;
2241 /** Flag whether alternate CHS is used. */
2242 unsigned fAlternateCHS: 1;
2243 /** Flag whether termination is disabled. */
2244 unsigned fTerminationDisabled: 1;
2245 /** Reserved. */
2246 unsigned u27Reserved: 27;
2247 /** Host SCSI ID. */
2248 unsigned u4HostSCSIID: 4;
2249 /** Initialize HBA. */
2250 unsigned u2InitializeHBA: 2;
2251 /** Removeable media setting. */
2252 unsigned u2RemovableMediaSetting: 2;
2253 /** Spinup delay. */
2254 unsigned u4SpinupDelay: 4;
2255 /** Negotiating settings. */
2256 unsigned u2NegotitatingSettings: 2;
2257 /** Reserved. */
2258 unsigned u18Reserved: 18;
2259 /** Device Settings. */
2260 MptDeviceSettings aDeviceSettings[16];
2261 } fields;
2262 } u;
2263} MptConfigurationPageSCSISPIPort2, *PMptConfigurationPageSCSISPIPort2;
2264#pragma pack()
2265AssertCompileSize(MptConfigurationPageSCSISPIPort2, 76);
2266
2267/**
2268 * SCSI-SPI device page 0. - Readonly
2269 */
2270#pragma pack(1)
2271typedef struct MptConfigurationPageSCSISPIDevice0
2272{
2273 /** Union. */
2274 union
2275 {
2276 /** Byte view. */
2277 uint8_t abPageData[12];
2278 /** Field view. */
2279 struct
2280 {
2281 /** The omnipresent header. */
2282 MptConfigurationPageHeader Header;
2283 /** Negotiated Parameters. */
2284 /** Information Units enabled. */
2285 unsigned fInformationUnitsEnabled: 1;
2286 /** Dual Transfers Enabled. */
2287 unsigned fDTEnabled: 1;
2288 /** QAS enabled. */
2289 unsigned fQASEnabled: 1;
2290 /** Reserved. */
2291 unsigned u5Reserved1: 5;
2292 /** Synchronous Transfer period. */
2293 unsigned u8NegotiatedSynchronousTransferPeriod: 8;
2294 /** Synchronous offset. */
2295 unsigned u8NegotiatedSynchronousOffset: 8;
2296 /** Reserved. */
2297 unsigned u5Reserved2: 5;
2298 /** Width - 0 for narrow and 1 for wide. */
2299 unsigned fWide: 1;
2300 /** Reserved. */
2301 unsigned fReserved: 1;
2302 /** AIP enabled. */
2303 unsigned fAIPEnabled: 1;
2304 /** Flag whether negotiation occurred. */
2305 unsigned fNegotationOccured: 1;
2306 /** Flag whether a SDTR message was rejected. */
2307 unsigned fSDTRRejected: 1;
2308 /** Flag whether a WDTR message was rejected. */
2309 unsigned fWDTRRejected: 1;
2310 /** Flag whether a PPR message was rejected. */
2311 unsigned fPPRRejected: 1;
2312 /** Reserved. */
2313 unsigned u28Reserved: 28;
2314 } fields;
2315 } u;
2316} MptConfigurationPageSCSISPIDevice0, *PMptConfigurationPageSCSISPIDevice0;
2317#pragma pack()
2318AssertCompileSize(MptConfigurationPageSCSISPIDevice0, 12);
2319
2320/**
2321 * SCSI-SPI device page 1. - Read/Write
2322 */
2323#pragma pack(1)
2324typedef struct MptConfigurationPageSCSISPIDevice1
2325{
2326 /** Union. */
2327 union
2328 {
2329 /** Byte view. */
2330 uint8_t abPageData[16];
2331 /** Field view. */
2332 struct
2333 {
2334 /** The omnipresent header. */
2335 MptConfigurationPageHeader Header;
2336 /** Requested Parameters. */
2337 /** Information Units enable. */
2338 bool fInformationUnitsEnable: 1;
2339 /** Dual Transfers Enable. */
2340 bool fDTEnable: 1;
2341 /** QAS enable. */
2342 bool fQASEnable: 1;
2343 /** Reserved. */
2344 unsigned u5Reserved1: 5;
2345 /** Synchronous Transfer period. */
2346 unsigned u8NegotiatedSynchronousTransferPeriod: 8;
2347 /** Synchronous offset. */
2348 unsigned u8NegotiatedSynchronousOffset: 8;
2349 /** Reserved. */
2350 unsigned u5Reserved2: 5;
2351 /** Width - 0 for narrow and 1 for wide. */
2352 bool fWide: 1;
2353 /** Reserved. */
2354 bool fReserved1: 1;
2355 /** AIP enable. */
2356 bool fAIPEnable: 1;
2357 /** Reserved. */
2358 bool fReserved2: 1;
2359 /** WDTR disallowed. */
2360 bool fWDTRDisallowed: 1;
2361 /** SDTR disallowed. */
2362 bool fSDTRDisallowed: 1;
2363 /** Reserved. */
2364 unsigned u29Reserved: 29;
2365 } fields;
2366 } u;
2367} MptConfigurationPageSCSISPIDevice1, *PMptConfigurationPageSCSISPIDevice1;
2368#pragma pack()
2369AssertCompileSize(MptConfigurationPageSCSISPIDevice1, 16);
2370
2371/**
2372 * SCSI-SPI device page 2. - Read/Write
2373 */
2374#pragma pack(1)
2375typedef struct MptConfigurationPageSCSISPIDevice2
2376{
2377 /** Union. */
2378 union
2379 {
2380 /** Byte view. */
2381 uint8_t abPageData[16];
2382 /** Field view. */
2383 struct
2384 {
2385 /** The omnipresent header. */
2386 MptConfigurationPageHeader Header;
2387 /** Reserved. */
2388 unsigned u4Reserved: 4;
2389 /** ISI enable. */
2390 unsigned fISIEnable: 1;
2391 /** Secondary driver enable. */
2392 unsigned fSecondaryDriverEnable: 1;
2393 /** Reserved. */
2394 unsigned fReserved: 1;
2395 /** Slew reate controler. */
2396 unsigned u3SlewRateControler: 3;
2397 /** Primary drive strength controler. */
2398 unsigned u3PrimaryDriveStrengthControl: 3;
2399 /** Secondary drive strength controler. */
2400 unsigned u3SecondaryDriveStrengthControl: 3;
2401 /** Reserved. */
2402 unsigned u12Reserved: 12;
2403 /** XCLKH_ST. */
2404 unsigned fXCLKH_ST: 1;
2405 /** XCLKS_ST. */
2406 unsigned fXCLKS_ST: 1;
2407 /** XCLKH_DT. */
2408 unsigned fXCLKH_DT: 1;
2409 /** XCLKS_DT. */
2410 unsigned fXCLKS_DT: 1;
2411 /** Parity pipe select. */
2412 unsigned u2ParityPipeSelect: 2;
2413 /** Reserved. */
2414 unsigned u30Reserved: 30;
2415 /** Data bit pipeline select. */
2416 unsigned u32DataPipelineSelect: 32;
2417 } fields;
2418 } u;
2419} MptConfigurationPageSCSISPIDevice2, *PMptConfigurationPageSCSISPIDevice2;
2420#pragma pack()
2421AssertCompileSize(MptConfigurationPageSCSISPIDevice2, 16);
2422
2423/**
2424 * SCSI-SPI device page 3 (Revision G). - Readonly
2425 */
2426#pragma pack(1)
2427typedef struct MptConfigurationPageSCSISPIDevice3
2428{
2429 /** Union. */
2430 union
2431 {
2432 /** Byte view. */
2433 uint8_t abPageData[1];
2434 /** Field view. */
2435 struct
2436 {
2437 /** The omnipresent header. */
2438 MptConfigurationPageHeader Header;
2439 /** Number of times the IOC rejected a message because it doesn't support the operation. */
2440 uint16_t u16MsgRejectCount;
2441 /** Number of times the SCSI bus entered an invalid operation state. */
2442 uint16_t u16PhaseErrorCount;
2443 /** Number of parity errors. */
2444 uint16_t u16ParityCount;
2445 /** Reserved. */
2446 uint16_t u16Reserved;
2447 } fields;
2448 } u;
2449} MptConfigurationPageSCSISPIDevice3, *PMptConfigurationPageSCSISPIDevice3;
2450#pragma pack()
2451AssertCompileSize(MptConfigurationPageSCSISPIDevice3, 12);
2452
2453/**
2454 * PHY entry for the SAS I/O unit page 0
2455 */
2456#pragma pack(1)
2457typedef struct MptConfigurationPageSASIOUnit0PHY
2458{
2459 /** Port number */
2460 uint8_t u8Port;
2461 /** Port flags */
2462 uint8_t u8PortFlags;
2463 /** Phy flags */
2464 uint8_t u8PhyFlags;
2465 /** negotiated link rate */
2466 uint8_t u8NegotiatedLinkRate;
2467 /** Controller phy device info */
2468 uint32_t u32ControllerPhyDeviceInfo;
2469 /** Attached device handle */
2470 uint16_t u16AttachedDevHandle;
2471 /** Controller device handle */
2472 uint16_t u16ControllerDevHandle;
2473 /** Discovery status */
2474 uint32_t u32DiscoveryStatus;
2475} MptConfigurationPageSASIOUnit0PHY, *PMptConfigurationPageSASIOUnit0PHY;
2476#pragma pack()
2477AssertCompileSize(MptConfigurationPageSASIOUnit0PHY, 16);
2478
2479/**
2480 * SAS I/O Unit page 0 - Readonly
2481 */
2482#pragma pack(1)
2483typedef struct MptConfigurationPageSASIOUnit0
2484{
2485 /** Union. */
2486 union
2487 {
2488 /** Byte view - variable. */
2489 uint8_t abPageData[1];
2490 /** Field view. */
2491 struct
2492 {
2493 /** The omnipresent header. */
2494 MptExtendedConfigurationPageHeader ExtHeader;
2495 /** Nvdata version default */
2496 uint16_t u16NvdataVersionDefault;
2497 /** Nvdata version persisent */
2498 uint16_t u16NvdataVersionPersistent;
2499 /** Number of physical ports */
2500 uint8_t u8NumPhys;
2501 /** Reserved */
2502 uint8_t au8Reserved[3];
2503 /** Content for each physical port - variable depending on the amount of ports. */
2504 MptConfigurationPageSASIOUnit0PHY aPHY[1];
2505 } fields;
2506 } u;
2507} MptConfigurationPageSASIOUnit0, *PMptConfigurationPageSASIOUnit0;
2508#pragma pack()
2509AssertCompileSize(MptConfigurationPageSASIOUnit0, 8+2+2+1+3+sizeof(MptConfigurationPageSASIOUnit0PHY));
2510
2511#define LSILOGICSCSI_SASIOUNIT0_GET_SIZE(ports) (sizeof(MptConfigurationPageSASIOUnit0) + ((ports) - 1) * sizeof(MptConfigurationPageSASIOUnit0PHY))
2512
2513#define LSILOGICSCSI_SASIOUNIT0_PORT_CONFIGURATION_AUTO RT_BIT(0)
2514#define LSILOGICSCSI_SASIOUNIT0_PORT_TARGET_IOC RT_BIT(2)
2515#define LSILOGICSCSI_SASIOUNIT0_PORT_DISCOVERY_IN_STATUS RT_BIT(3)
2516
2517#define LSILOGICSCSI_SASIOUNIT0_PHY_RX_INVERTED RT_BIT(0)
2518#define LSILOGICSCSI_SASIOUNIT0_PHY_TX_INVERTED RT_BIT(1)
2519#define LSILOGICSCSI_SASIOUNIT0_PHY_DISABLED RT_BIT(2)
2520
2521#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_SET(x) ((x) & 0x0F)
2522#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_GET(x) ((x) & 0x0F)
2523#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_UNKNOWN 0x00
2524#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_DISABLED 0x01
2525#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_FAILED 0x02
2526#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_SATA_OOB 0x03
2527#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_15GB 0x08
2528#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_30GB 0x09
2529
2530#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(x) ((x) & 0x3)
2531#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_NO 0x0
2532#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_END 0x1
2533#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_EDGE_EXPANDER 0x2
2534#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_FANOUT_EXPANDER 0x3
2535
2536#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SATA_HOST RT_BIT(3)
2537#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SMP_INITIATOR RT_BIT(4)
2538#define LSILOGICSCSI_SASIOUNIT0_DEVICE_STP_INITIATOR RT_BIT(5)
2539#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_INITIATOR RT_BIT(6)
2540#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SATA RT_BIT(7)
2541#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SMP_TARGET RT_BIT(8)
2542#define LSILOGICSCSI_SASIOUNIT0_DEVICE_STP_TARGET RT_BIT(9)
2543#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_TARGET RT_BIT(10)
2544#define LSILOGICSCSI_SASIOUNIT0_DEVICE_DIRECT_ATTACHED RT_BIT(11)
2545#define LSILOGICSCSI_SASIOUNIT0_DEVICE_LSI RT_BIT(12)
2546#define LSILOGICSCSI_SASIOUNIT0_DEVICE_ATAPI_DEVICE RT_BIT(13)
2547#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SEP_DEVICE RT_BIT(14)
2548
2549#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_LOOP RT_BIT(0)
2550#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_UNADDRESSABLE RT_BIT(1)
2551#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SAME_SAS_ADDR RT_BIT(2)
2552#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_EXPANDER_ERROR RT_BIT(3)
2553#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SMP_TIMEOUT RT_BIT(4)
2554#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_EXP_ROUTE_OOE RT_BIT(5)
2555#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_EXP_ROUTE_IDX RT_BIT(6)
2556#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SMP_FUNC_FAILED RT_BIT(7)
2557#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SMP_CRC_ERROR RT_BIT(8)
2558#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SUBTRSCTIVE_LNK RT_BIT(9)
2559#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_TBL_LNK RT_BIT(10)
2560#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_UNSUPPORTED_DEV RT_BIT(11)
2561#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_MAX_SATA_TGTS RT_BIT(12)
2562#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_MULT_CTRLS RT_BIT(13)
2563
2564/**
2565 * PHY entry for the SAS I/O unit page 1
2566 */
2567#pragma pack(1)
2568typedef struct MptConfigurationPageSASIOUnit1PHY
2569{
2570 /** Port number */
2571 uint8_t u8Port;
2572 /** Port flags */
2573 uint8_t u8PortFlags;
2574 /** Phy flags */
2575 uint8_t u8PhyFlags;
2576 /** Max link rate */
2577 uint8_t u8MaxMinLinkRate;
2578 /** Controller phy device info */
2579 uint32_t u32ControllerPhyDeviceInfo;
2580 /** Maximum target port connect time */
2581 uint16_t u16MaxTargetPortConnectTime;
2582 /** Reserved */
2583 uint16_t u16Reserved;
2584} MptConfigurationPageSASIOUnit1PHY, *PMptConfigurationPageSASIOUnit1PHY;
2585#pragma pack()
2586AssertCompileSize(MptConfigurationPageSASIOUnit1PHY, 12);
2587
2588/**
2589 * SAS I/O Unit page 1 - Read/Write
2590 */
2591#pragma pack(1)
2592typedef struct MptConfigurationPageSASIOUnit1
2593{
2594 /** Union. */
2595 union
2596 {
2597 /** Byte view - variable. */
2598 uint8_t abPageData[1];
2599 /** Field view. */
2600 struct
2601 {
2602 /** The omnipresent header. */
2603 MptExtendedConfigurationPageHeader ExtHeader;
2604 /** Control flags */
2605 uint16_t u16ControlFlags;
2606 /** maximum number of SATA targets */
2607 uint16_t u16MaxNumSATATargets;
2608 /** additional control flags */
2609 uint16_t u16AdditionalControlFlags;
2610 /** Reserved */
2611 uint16_t u16Reserved;
2612 /** Number of PHYs */
2613 uint8_t u8NumPhys;
2614 /** maximum SATA queue depth */
2615 uint8_t u8SATAMaxQDepth;
2616 /** Delay for reporting missing devices. */
2617 uint8_t u8ReportDeviceMissingDelay;
2618 /** I/O device missing delay */
2619 uint8_t u8IODeviceMissingDelay;
2620 /** Content for each physical port - variable depending on the number of ports */
2621 MptConfigurationPageSASIOUnit1PHY aPHY[1];
2622 } fields;
2623 } u;
2624} MptConfigurationPageSASIOUnit1, *PMptConfigurationPageSASIOUnit1;
2625#pragma pack()
2626AssertCompileSize(MptConfigurationPageSASIOUnit1, 8+12+sizeof(MptConfigurationPageSASIOUnit1PHY));
2627
2628#define LSILOGICSCSI_SASIOUNIT1_GET_SIZE(ports) (sizeof(MptConfigurationPageSASIOUnit1) + ((ports) - 1) * sizeof(MptConfigurationPageSASIOUnit1PHY))
2629
2630#define LSILOGICSCSI_SASIOUNIT1_CONTROL_CLEAR_SATA_AFFILIATION RT_BIT(0)
2631#define LSILOGICSCSI_SASIOUNIT1_CONTROL_FIRST_LEVEL_DISCOVERY_ONLY RT_BIT(1)
2632#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SUBTRACTIVE_LNK_ILLEGAL RT_BIT(2)
2633#define LSILOGICSCSI_SASIOUNIT1_CONTROL_IOC_ENABLE_HIGH_PHY RT_BIT(3)
2634#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED RT_BIT(4)
2635#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED RT_BIT(5)
2636#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED RT_BIT(6)
2637#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_LBA48_REQUIRED RT_BIT(7)
2638#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_INIT_POSTPONED RT_BIT(8)
2639
2640#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_SET(x) (((x) & 0x3) << 9)
2641#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_GET(x) (((x) >> 9) & 0x3)
2642#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_SAS_AND_SATA 0x00
2643#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_SAS 0x01
2644#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_SATA 0x02
2645
2646#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_EXP_ADDR RT_BIT(11)
2647#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_SETTINGS_PRESERV_REQUIRED RT_BIT(12)
2648#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_LIMIT_RATE_15GB RT_BIT(13)
2649#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_LIMIT_RATE_30GB RT_BIT(14)
2650#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SAS_SELF_TEST_ENABLED RT_BIT(15)
2651
2652#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_TBL_LNKS_ALLOW RT_BIT(0)
2653#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_RST_NO_AFFIL RT_BIT(1)
2654#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_RST_SELF_AFFIL RT_BIT(2)
2655#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_RST_OTHER_AFFIL RT_BIT(3)
2656#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_RST_PORT_EN_ONLY RT_BIT(4)
2657#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_HIDE_NON_ZERO_PHYS RT_BIT(5)
2658#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_ASYNC_NOTIF RT_BIT(6)
2659#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_MULT_PORTS_ILL_SAME_DOMAIN RT_BIT(7)
2660
2661#define LSILOGICSCSI_SASIOUNIT1_MISSING_DEVICE_DELAY_UNITS_16_SEC RT_BIT(7)
2662#define LSILOGICSCSI_SASIOUNIT1_MISSING_DEVICE_DELAY_SET(x) ((x) & 0x7F)
2663#define LSILOGICSCSI_SASIOUNIT1_MISSING_DEVICE_DELAY_GET(x) ((x) & 0x7F)
2664
2665#define LSILOGICSCSI_SASIOUNIT1_PORT_CONFIGURATION_AUTO RT_BIT(0)
2666#define LSILOGICSCSI_SASIOUNIT1_PORT_CONFIGURATION_IOC1 RT_BIT(2)
2667
2668#define LSILOGICSCSI_SASIOUNIT1_PHY_RX_INVERT RT_BIT(0)
2669#define LSILOGICSCSI_SASIOUNIT1_PHY_TX_INVERT RT_BIT(1)
2670#define LSILOGICSCSI_SASIOUNIT1_PHY_DISABLE RT_BIT(2)
2671
2672#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_SET(x) ((x) & 0x0F)
2673#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_GET(x) ((x) & 0x0F)
2674#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_SET(x) (((x) & 0x0F) << 4)
2675#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_GET(x) ((x >> 4) & 0x0F)
2676#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_15GB 0x8
2677#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_30GB 0x9
2678
2679#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_SET(x) ((x) & 0x3)
2680#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_GET(x) ((x) & 0x3)
2681#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_NO 0x0
2682#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_END 0x1
2683#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_EDGE_EXPANDER 0x2
2684#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_FANOUT_EXPANDER 0x3
2685#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SMP_INITIATOR RT_BIT(4)
2686#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_STP_INITIATOR RT_BIT(5)
2687#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SSP_INITIATOR RT_BIT(6)
2688#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SMP_TARGET RT_BIT(8)
2689#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_STP_TARGET RT_BIT(9)
2690#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SSP_TARGET RT_BIT(10)
2691#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_DIRECT_ATTACHED RT_BIT(11)
2692#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_LSI RT_BIT(12)
2693#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_ATAPI RT_BIT(13)
2694#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SEP RT_BIT(14)
2695
2696/**
2697 * SAS I/O unit page 2 - Read/Write
2698 */
2699#pragma pack(1)
2700typedef struct MptConfigurationPageSASIOUnit2
2701{
2702 /** Union. */
2703 union
2704 {
2705 /** Byte view - variable. */
2706 uint8_t abPageData[1];
2707 /** Field view. */
2708 struct
2709 {
2710 /** The omnipresent header. */
2711 MptExtendedConfigurationPageHeader ExtHeader;
2712 /** Device numbers per enclosure */
2713 uint8_t u8NumDevsPerEnclosure;
2714 /** Boot device wait time */
2715 uint8_t u8BootDeviceWaitTime;
2716 /** Reserved */
2717 uint16_t u16Reserved;
2718 /** Maximum number of persistent Bus and target ID mappings */
2719 uint16_t u16MaxPersistentIDs;
2720 /** Number of persistent IDs used */
2721 uint16_t u16NumPersistentIDsUsed;
2722 /** Status */
2723 uint8_t u8Status;
2724 /** Flags */
2725 uint8_t u8Flags;
2726 /** Maximum number of physical mapped IDs */
2727 uint16_t u16MaxNumPhysicalMappedIDs;
2728 } fields;
2729 } u;
2730} MptConfigurationPageSASIOUnit2, *PMptConfigurationPageSASIOUnit2;
2731#pragma pack()
2732AssertCompileSize(MptConfigurationPageSASIOUnit2, 20);
2733
2734#define LSILOGICSCSI_SASIOUNIT2_STATUS_PERSISTENT_MAP_TBL_FULL RT_BIT(0)
2735#define LSILOGICSCSI_SASIOUNIT2_STATUS_PERSISTENT_MAP_DISABLED RT_BIT(1)
2736#define LSILOGICSCSI_SASIOUNIT2_STATUS_PERSISTENT_ENC_DEV_UNMAPPED RT_BIT(2)
2737#define LSILOGICSCSI_SASIOUNIT2_STATUS_PERSISTENT_DEV_LIMIT_EXCEEDED RT_BIT(3)
2738
2739#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_MAP_DISABLE RT_BIT(0)
2740#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_SET(x) ((x & 0x7) << 1)
2741#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_GET(x) ((x >> 1) & 0x7)
2742#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_NO 0x0
2743#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_DIRECT_ATTACHED 0x1
2744#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_ENC 0x2
2745#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_HOST 0x7
2746#define LSILOGICSCSI_SASIOUNIT2_FLAGS_RESERVE_TARGET_ID_ZERO RT_BIT(4)
2747#define LSILOGICSCSI_SASIOUNIT2_FLAGS_START_SLOT_NUMBER_ONE RT_BIT(5)
2748
2749/**
2750 * SAS I/O unit page 3 - Read/Write
2751 */
2752#pragma pack(1)
2753typedef struct MptConfigurationPageSASIOUnit3
2754{
2755 /** Union. */
2756 union
2757 {
2758 /** Byte view - variable. */
2759 uint8_t abPageData[1];
2760 /** Field view. */
2761 struct
2762 {
2763 /** The omnipresent header. */
2764 MptExtendedConfigurationPageHeader ExtHeader;
2765 /** Reserved */
2766 uint32_t u32Reserved;
2767 uint32_t u32MaxInvalidDwordCount;
2768 uint32_t u32InvalidDwordCountTime;
2769 uint32_t u32MaxRunningDisparityErrorCount;
2770 uint32_t u32RunningDisparityErrorTime;
2771 uint32_t u32MaxLossDwordSynchCount;
2772 uint32_t u32LossDwordSynchCountTime;
2773 uint32_t u32MaxPhysResetProblemCount;
2774 uint32_t u32PhyResetProblemTime;
2775 } fields;
2776 } u;
2777} MptConfigurationPageSASIOUnit3, *PMptConfigurationPageSASIOUnit3;
2778#pragma pack()
2779AssertCompileSize(MptConfigurationPageSASIOUnit3, 44);
2780
2781/**
2782 * SAS PHY page 0 - Readonly
2783 */
2784#pragma pack(1)
2785typedef struct MptConfigurationPageSASPHY0
2786{
2787 /** Union. */
2788 union
2789 {
2790 /** Byte view - variable. */
2791 uint8_t abPageData[1];
2792 /** Field view. */
2793 struct
2794 {
2795 /** The omnipresent header. */
2796 MptExtendedConfigurationPageHeader ExtHeader;
2797 /** Owner dev handle. */
2798 uint16_t u16OwnerDevHandle;
2799 /** Reserved */
2800 uint16_t u16Reserved0;
2801 /** SAS address */
2802 SASADDRESS SASAddress;
2803 /** Attached device handle */
2804 uint16_t u16AttachedDevHandle;
2805 /** Attached phy identifier */
2806 uint8_t u8AttachedPhyIdentifier;
2807 /** Reserved */
2808 uint8_t u8Reserved1;
2809 /** Attached device information */
2810 uint32_t u32AttachedDeviceInfo;
2811 /** Programmed link rate */
2812 uint8_t u8ProgrammedLinkRate;
2813 /** Hardware link rate */
2814 uint8_t u8HwLinkRate;
2815 /** Change count */
2816 uint8_t u8ChangeCount;
2817 /** Flags */
2818 uint8_t u8Flags;
2819 /** Phy information */
2820 uint32_t u32PhyInfo;
2821 } fields;
2822 } u;
2823} MptConfigurationPageSASPHY0, *PMptConfigurationPageSASPHY0;
2824#pragma pack()
2825AssertCompileSize(MptConfigurationPageSASPHY0, 36);
2826
2827#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_SET(x) ((x) & 0x3)
2828#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_GET(x) ((x) & 0x3)
2829#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_NO 0x0
2830#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_END 0x1
2831#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_EDGE_EXPANDER 0x2
2832#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_FANOUT_EXPANDER 0x3
2833#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SMP_INITIATOR RT_BIT(4)
2834#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_STP_INITIATOR RT_BIT(5)
2835#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SSP_INITIATOR RT_BIT(6)
2836#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SMP_TARGET RT_BIT(8)
2837#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_STP_TARGET RT_BIT(9)
2838#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SSP_TARGET RT_BIT(10)
2839#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_DIRECT_ATTACHED RT_BIT(11)
2840#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_LSI RT_BIT(12)
2841#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_ATAPI RT_BIT(13)
2842#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SEP RT_BIT(14)
2843
2844/**
2845 * SAS PHY page 1 - Readonly
2846 */
2847#pragma pack(1)
2848typedef struct MptConfigurationPageSASPHY1
2849{
2850 /** Union. */
2851 union
2852 {
2853 /** Byte view - variable. */
2854 uint8_t abPageData[1];
2855 /** Field view. */
2856 struct
2857 {
2858 /** The omnipresent header. */
2859 MptExtendedConfigurationPageHeader ExtHeader;
2860 /** Reserved */
2861 uint32_t u32Reserved0;
2862 uint32_t u32InvalidDwordCound;
2863 uint32_t u32RunningDisparityErrorCount;
2864 uint32_t u32LossDwordSynchCount;
2865 uint32_t u32PhyResetProblemCount;
2866 } fields;
2867 } u;
2868} MptConfigurationPageSASPHY1, *PMptConfigurationPageSASPHY1;
2869#pragma pack()
2870AssertCompileSize(MptConfigurationPageSASPHY1, 28);
2871
2872/**
2873 * SAS Device page 0 - Readonly
2874 */
2875#pragma pack(1)
2876typedef struct MptConfigurationPageSASDevice0
2877{
2878 /** Union. */
2879 union
2880 {
2881 /** Byte view - variable. */
2882 uint8_t abPageData[1];
2883 /** Field view. */
2884 struct
2885 {
2886 /** The omnipresent header. */
2887 MptExtendedConfigurationPageHeader ExtHeader;
2888 /** Slot number */
2889 uint16_t u16Slot;
2890 /** Enclosure handle. */
2891 uint16_t u16EnclosureHandle;
2892 /** SAS address */
2893 SASADDRESS SASAddress;
2894 /** Parent device handle */
2895 uint16_t u16ParentDevHandle;
2896 /** Phy number */
2897 uint8_t u8PhyNum;
2898 /** Access status */
2899 uint8_t u8AccessStatus;
2900 /** Device handle */
2901 uint16_t u16DevHandle;
2902 /** Target ID */
2903 uint8_t u8TargetID;
2904 /** Bus */
2905 uint8_t u8Bus;
2906 /** Device info */
2907 uint32_t u32DeviceInfo;
2908 /** Flags */
2909 uint16_t u16Flags;
2910 /** Physical port */
2911 uint8_t u8PhysicalPort;
2912 /** Reserved */
2913 uint8_t u8Reserved0;
2914 } fields;
2915 } u;
2916} MptConfigurationPageSASDevice0, *PMptConfigurationPageSASDevice0;
2917#pragma pack()
2918AssertCompileSize(MptConfigurationPageSASDevice0, 36);
2919
2920#define LSILOGICSCSI_SASDEVICE0_STATUS_NO_ERRORS (0x00)
2921
2922#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_SET(x) ((x) & 0x3)
2923#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_GET(x) ((x) & 0x3)
2924#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_NO 0x0
2925#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_END 0x1
2926#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_EDGE_EXPANDER 0x2
2927#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_FANOUT_EXPANDER 0x3
2928#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SMP_INITIATOR RT_BIT(4)
2929#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_STP_INITIATOR RT_BIT(5)
2930#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SSP_INITIATOR RT_BIT(6)
2931#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SMP_TARGET RT_BIT(8)
2932#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_STP_TARGET RT_BIT(9)
2933#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SSP_TARGET RT_BIT(10)
2934#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_DIRECT_ATTACHED RT_BIT(11)
2935#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_LSI RT_BIT(12)
2936#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_ATAPI RT_BIT(13)
2937#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SEP RT_BIT(14)
2938
2939#define LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_PRESENT (RT_BIT(0))
2940#define LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_MAPPED_TO_BUS_AND_TARGET_ID (RT_BIT(1))
2941#define LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_MAPPING_PERSISTENT (RT_BIT(2))
2942
2943/**
2944 * SAS Device page 1 - Readonly
2945 */
2946#pragma pack(1)
2947typedef struct MptConfigurationPageSASDevice1
2948{
2949 /** Union. */
2950 union
2951 {
2952 /** Byte view - variable. */
2953 uint8_t abPageData[1];
2954 /** Field view. */
2955 struct
2956 {
2957 /** The omnipresent header. */
2958 MptExtendedConfigurationPageHeader ExtHeader;
2959 /** Reserved */
2960 uint32_t u32Reserved0;
2961 /** SAS address */
2962 SASADDRESS SASAddress;
2963 /** Reserved */
2964 uint32_t u32Reserved;
2965 /** Device handle */
2966 uint16_t u16DevHandle;
2967 /** Target ID */
2968 uint8_t u8TargetID;
2969 /** Bus */
2970 uint8_t u8Bus;
2971 /** Initial REgister device FIS */
2972 uint32_t au32InitialRegDeviceFIS[5];
2973 } fields;
2974 } u;
2975} MptConfigurationPageSASDevice1, *PMptConfigurationPageSASDevice1;
2976#pragma pack()
2977AssertCompileSize(MptConfigurationPageSASDevice1, 48);
2978
2979/**
2980 * SAS Device page 2 - Read/Write persistent
2981 */
2982#pragma pack(1)
2983typedef struct MptConfigurationPageSASDevice2
2984{
2985 /** Union. */
2986 union
2987 {
2988 /** Byte view - variable. */
2989 uint8_t abPageData[1];
2990 /** Field view. */
2991 struct
2992 {
2993 /** The omnipresent header. */
2994 MptExtendedConfigurationPageHeader ExtHeader;
2995 /** Physical identifier */
2996 SASADDRESS SASAddress;
2997 /** Enclosure mapping */
2998 uint32_t u32EnclosureMapping;
2999 } fields;
3000 } u;
3001} MptConfigurationPageSASDevice2, *PMptConfigurationPageSASDevice2;
3002#pragma pack()
3003AssertCompileSize(MptConfigurationPageSASDevice2, 20);
3004
3005/**
3006 * A device entitiy containing all pages.
3007 */
3008typedef struct MptSASDevice
3009{
3010 /** Pointer to the next device if any. */
3011 struct MptSASDevice *pNext;
3012 /** Pointer to the previous device if any. */
3013 struct MptSASDevice *pPrev;
3014
3015 MptConfigurationPageSASDevice0 SASDevicePage0;
3016 MptConfigurationPageSASDevice1 SASDevicePage1;
3017 MptConfigurationPageSASDevice2 SASDevicePage2;
3018} MptSASDevice, *PMptSASDevice;
3019
3020/**
3021 * SAS Expander page 0 - Readonly
3022 */
3023#pragma pack(1)
3024typedef struct MptConfigurationPageSASExpander0
3025{
3026 /** Union. */
3027 union
3028 {
3029 /** Byte view - variable. */
3030 uint8_t abPageData[1];
3031 /** Field view. */
3032 struct
3033 {
3034 /** The omnipresent header. */
3035 MptExtendedConfigurationPageHeader ExtHeader;
3036 /** Physical port */
3037 uint8_t u8PhysicalPort;
3038 /** Reserved */
3039 uint8_t u8Reserved0;
3040 /** Enclosure handle */
3041 uint16_t u16EnclosureHandle;
3042 /** SAS address */
3043 SASADDRESS SASAddress;
3044 /** Discovery status */
3045 uint32_t u32DiscoveryStatus;
3046 /** Device handle. */
3047 uint16_t u16DevHandle;
3048 /** Parent device handle */
3049 uint16_t u16ParentDevHandle;
3050 /** Expander change count */
3051 uint16_t u16ExpanderChangeCount;
3052 /** Expander route indexes */
3053 uint16_t u16ExpanderRouteIndexes;
3054 /** Number of PHys in this expander */
3055 uint8_t u8NumPhys;
3056 /** SAS level */
3057 uint8_t u8SASLevel;
3058 /** Flags */
3059 uint8_t u8Flags;
3060 /** Reserved */
3061 uint8_t u8Reserved1;
3062 } fields;
3063 } u;
3064} MptConfigurationPageSASExpander0, *PMptConfigurationPageSASExpander0;
3065#pragma pack()
3066AssertCompileSize(MptConfigurationPageSASExpander0, 36);
3067
3068/**
3069 * SAS Expander page 1 - Readonly
3070 */
3071#pragma pack(1)
3072typedef struct MptConfigurationPageSASExpander1
3073{
3074 /** Union. */
3075 union
3076 {
3077 /** Byte view - variable. */
3078 uint8_t abPageData[1];
3079 /** Field view. */
3080 struct
3081 {
3082 /** The omnipresent header. */
3083 MptExtendedConfigurationPageHeader ExtHeader;
3084 /** Physical port */
3085 uint8_t u8PhysicalPort;
3086 /** Reserved */
3087 uint8_t u8Reserved0[3];
3088 /** Number of PHYs */
3089 uint8_t u8NumPhys;
3090 /** Number of the Phy the information in this page is for. */
3091 uint8_t u8Phy;
3092 /** Number of routing table entries */
3093 uint16_t u16NumTableEntriesProgrammed;
3094 /** Programmed link rate */
3095 uint8_t u8ProgrammedLinkRate;
3096 /** Hardware link rate */
3097 uint8_t u8HwLinkRate;
3098 /** Attached device handle */
3099 uint16_t u16AttachedDevHandle;
3100 /** Phy information */
3101 uint32_t u32PhyInfo;
3102 /** Attached device information */
3103 uint32_t u32AttachedDeviceInfo;
3104 /** Owner device handle. */
3105 uint16_t u16OwnerDevHandle;
3106 /** Change count */
3107 uint8_t u8ChangeCount;
3108 /** Negotiated link rate */
3109 uint8_t u8NegotiatedLinkRate;
3110 /** Phy identifier */
3111 uint8_t u8PhyIdentifier;
3112 /** Attached phy identifier */
3113 uint8_t u8AttachedPhyIdentifier;
3114 /** Reserved */
3115 uint8_t u8Reserved1;
3116 /** Discovery information */
3117 uint8_t u8DiscoveryInfo;
3118 /** Reserved */
3119 uint32_t u32Reserved;
3120 } fields;
3121 } u;
3122} MptConfigurationPageSASExpander1, *PMptConfigurationPageSASExpander1;
3123#pragma pack()
3124AssertCompileSize(MptConfigurationPageSASExpander1, 40);
3125
3126/**
3127 * Structure of all supported pages for the SCSI SPI controller.
3128 * Used to load the device state from older versions.
3129 */
3130typedef struct MptConfigurationPagesSupported_SSM_V2
3131{
3132 MptConfigurationPageManufacturing0 ManufacturingPage0;
3133 MptConfigurationPageManufacturing1 ManufacturingPage1;
3134 MptConfigurationPageManufacturing2 ManufacturingPage2;
3135 MptConfigurationPageManufacturing3 ManufacturingPage3;
3136 MptConfigurationPageManufacturing4 ManufacturingPage4;
3137 MptConfigurationPageIOUnit0 IOUnitPage0;
3138 MptConfigurationPageIOUnit1 IOUnitPage1;
3139 MptConfigurationPageIOUnit2 IOUnitPage2;
3140 MptConfigurationPageIOUnit3 IOUnitPage3;
3141 MptConfigurationPageIOC0 IOCPage0;
3142 MptConfigurationPageIOC1 IOCPage1;
3143 MptConfigurationPageIOC2 IOCPage2;
3144 MptConfigurationPageIOC3 IOCPage3;
3145 MptConfigurationPageIOC4 IOCPage4;
3146 MptConfigurationPageIOC6 IOCPage6;
3147 struct
3148 {
3149 MptConfigurationPageSCSISPIPort0 SCSISPIPortPage0;
3150 MptConfigurationPageSCSISPIPort1 SCSISPIPortPage1;
3151 MptConfigurationPageSCSISPIPort2 SCSISPIPortPage2;
3152 } aPortPages[1]; /* Currently only one port supported. */
3153 struct
3154 {
3155 struct
3156 {
3157 MptConfigurationPageSCSISPIDevice0 SCSISPIDevicePage0;
3158 MptConfigurationPageSCSISPIDevice1 SCSISPIDevicePage1;
3159 MptConfigurationPageSCSISPIDevice2 SCSISPIDevicePage2;
3160 MptConfigurationPageSCSISPIDevice3 SCSISPIDevicePage3;
3161 } aDevicePages[LSILOGICSCSI_PCI_SPI_DEVICES_MAX];
3162 } aBuses[1]; /* Only one bus at the moment. */
3163} MptConfigurationPagesSupported_SSM_V2, *PMptConfigurationPagesSupported_SSM_V2;
3164
3165typedef struct MptConfigurationPagesSpi
3166{
3167 struct
3168 {
3169 MptConfigurationPageSCSISPIPort0 SCSISPIPortPage0;
3170 MptConfigurationPageSCSISPIPort1 SCSISPIPortPage1;
3171 MptConfigurationPageSCSISPIPort2 SCSISPIPortPage2;
3172 } aPortPages[1]; /* Currently only one port supported. */
3173 struct
3174 {
3175 struct
3176 {
3177 MptConfigurationPageSCSISPIDevice0 SCSISPIDevicePage0;
3178 MptConfigurationPageSCSISPIDevice1 SCSISPIDevicePage1;
3179 MptConfigurationPageSCSISPIDevice2 SCSISPIDevicePage2;
3180 MptConfigurationPageSCSISPIDevice3 SCSISPIDevicePage3;
3181 } aDevicePages[LSILOGICSCSI_PCI_SPI_DEVICES_MAX];
3182 } aBuses[1]; /* Only one bus at the moment. */
3183} MptConfigurationPagesSpi, *PMptConfigurationPagesSpi;
3184
3185typedef struct MptPHY
3186{
3187 MptConfigurationPageSASPHY0 SASPHYPage0;
3188 MptConfigurationPageSASPHY1 SASPHYPage1;
3189} MptPHY, *PMptPHY;
3190
3191#pragma pack(1)
3192typedef struct MptConfigurationPagesSas
3193{
3194 /** Size of the manufacturing page 7 */
3195 uint32_t cbManufacturingPage7;
3196 /** Pointer to the manufacturing page 7 */
3197 PMptConfigurationPageManufacturing7 pManufacturingPage7;
3198 /** Size of the I/O unit page 0 */
3199 uint32_t cbSASIOUnitPage0;
3200 /** Pointer to the I/O unit page 0 */
3201 PMptConfigurationPageSASIOUnit0 pSASIOUnitPage0;
3202 /** Size of the I/O unit page 1 */
3203 uint32_t cbSASIOUnitPage1;
3204 /** Pointer to the I/O unit page 1 */
3205 PMptConfigurationPageSASIOUnit1 pSASIOUnitPage1;
3206 /** I/O unit page 2 */
3207 MptConfigurationPageSASIOUnit2 SASIOUnitPage2;
3208 /** I/O unit page 3 */
3209 MptConfigurationPageSASIOUnit3 SASIOUnitPage3;
3210
3211 /** Number of PHYs in the array. */
3212 uint32_t cPHYs;
3213 /** Pointer to an array of per PHYS pages. */
3214 R3PTRTYPE(PMptPHY) paPHYs;
3215
3216 /** Number of devices detected. */
3217 uint32_t cDevices;
3218 /** Pointer to the first SAS device. */
3219 R3PTRTYPE(PMptSASDevice) pSASDeviceHead;
3220 /** Pointer to the last SAS device. */
3221 R3PTRTYPE(PMptSASDevice) pSASDeviceTail;
3222} MptConfigurationPagesSas, *PMptConfigurationPagesSas;
3223#pragma pack()
3224
3225/**
3226 * Structure of all supported pages for both controllers.
3227 */
3228typedef struct MptConfigurationPagesSupported
3229{
3230 MptConfigurationPageManufacturing0 ManufacturingPage0;
3231 MptConfigurationPageManufacturing1 ManufacturingPage1;
3232 MptConfigurationPageManufacturing2 ManufacturingPage2;
3233 MptConfigurationPageManufacturing3 ManufacturingPage3;
3234 MptConfigurationPageManufacturing4 ManufacturingPage4;
3235 MptConfigurationPageManufacturing5 ManufacturingPage5;
3236 MptConfigurationPageManufacturing6 ManufacturingPage6;
3237 MptConfigurationPageManufacturing8 ManufacturingPage8;
3238 MptConfigurationPageManufacturing9 ManufacturingPage9;
3239 MptConfigurationPageManufacturing10 ManufacturingPage10;
3240 MptConfigurationPageIOUnit0 IOUnitPage0;
3241 MptConfigurationPageIOUnit1 IOUnitPage1;
3242 MptConfigurationPageIOUnit2 IOUnitPage2;
3243 MptConfigurationPageIOUnit3 IOUnitPage3;
3244 MptConfigurationPageIOUnit4 IOUnitPage4;
3245 MptConfigurationPageIOC0 IOCPage0;
3246 MptConfigurationPageIOC1 IOCPage1;
3247 MptConfigurationPageIOC2 IOCPage2;
3248 MptConfigurationPageIOC3 IOCPage3;
3249 MptConfigurationPageIOC4 IOCPage4;
3250 MptConfigurationPageIOC6 IOCPage6;
3251 /* BIOS page 0 is not described */
3252 MptConfigurationPageBIOS1 BIOSPage1;
3253 MptConfigurationPageBIOS2 BIOSPage2;
3254 /* BIOS page 3 is not described */
3255 MptConfigurationPageBIOS4 BIOSPage4;
3256
3257 /** Controller dependent data. */
3258 union
3259 {
3260 MptConfigurationPagesSpi SpiPages;
3261 MptConfigurationPagesSas SasPages;
3262 } u;
3263} MptConfigurationPagesSupported, *PMptConfigurationPagesSupported;
3264
3265/**
3266 * Initializes a page header.
3267 */
3268#define MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags) \
3269 (pg)->u.fields.Header.u8PageType = flags; \
3270 (pg)->u.fields.Header.u8PageNumber = nr; \
3271 (pg)->u.fields.Header.u8PageLength = sizeof(type) / 4
3272
3273#define MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(pg, type, nr, flags) \
3274 MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags | MPT_CONFIGURATION_PAGE_TYPE_MANUFACTURING)
3275
3276#define MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(pg, type, nr, flags) \
3277 MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags | MPT_CONFIGURATION_PAGE_TYPE_IO_UNIT)
3278
3279#define MPT_CONFIG_PAGE_HEADER_INIT_IOC(pg, type, nr, flags) \
3280 MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags | MPT_CONFIGURATION_PAGE_TYPE_IOC)
3281
3282#define MPT_CONFIG_PAGE_HEADER_INIT_BIOS(pg, type, nr, flags) \
3283 MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags | MPT_CONFIGURATION_PAGE_TYPE_BIOS)
3284
3285/**
3286 * Initializes a extended page header.
3287 */
3288#define MPT_CONFIG_EXTENDED_PAGE_HEADER_INIT(pg, cb, nr, flags, exttype) \
3289 (pg)->u.fields.ExtHeader.u8PageType = flags | MPT_CONFIGURATION_PAGE_TYPE_EXTENDED; \
3290 (pg)->u.fields.ExtHeader.u8PageNumber = nr; \
3291 (pg)->u.fields.ExtHeader.u8ExtPageType = exttype; \
3292 (pg)->u.fields.ExtHeader.u16ExtPageLength = cb / 4
3293
3294/**
3295 * Possible SG element types.
3296 */
3297enum MPTSGENTRYTYPE
3298{
3299 MPTSGENTRYTYPE_TRANSACTION_CONTEXT = 0x00,
3300 MPTSGENTRYTYPE_SIMPLE = 0x01,
3301 MPTSGENTRYTYPE_CHAIN = 0x03
3302};
3303
3304/**
3305 * Register interface.
3306 */
3307
3308/**
3309 * Defined states that the SCSI controller can have.
3310 */
3311typedef enum LSILOGICSTATE
3312{
3313 /** Reset state. */
3314 LSILOGICSTATE_RESET = 0x00,
3315 /** Ready state. */
3316 LSILOGICSTATE_READY = 0x01,
3317 /** Operational state. */
3318 LSILOGICSTATE_OPERATIONAL = 0x02,
3319 /** Fault state. */
3320 LSILOGICSTATE_FAULT = 0x04,
3321 /** 32bit size hack */
3322 LSILOGICSTATE_32BIT_HACK = 0x7fffffff
3323} LSILOGICSTATE;
3324
3325/**
3326 * Which entity needs to initialize the controller
3327 * to get into the operational state.
3328 */
3329typedef enum LSILOGICWHOINIT
3330{
3331 /** Not initialized. */
3332 LSILOGICWHOINIT_NOT_INITIALIZED = 0x00,
3333 /** System BIOS. */
3334 LSILOGICWHOINIT_SYSTEM_BIOS = 0x01,
3335 /** ROM Bios. */
3336 LSILOGICWHOINIT_ROM_BIOS = 0x02,
3337 /** PCI Peer. */
3338 LSILOGICWHOINIT_PCI_PEER = 0x03,
3339 /** Host driver. */
3340 LSILOGICWHOINIT_HOST_DRIVER = 0x04,
3341 /** Manufacturing. */
3342 LSILOGICWHOINIT_MANUFACTURING = 0x05,
3343 /** 32bit size hack. */
3344 LSILOGICWHOINIT_32BIT_HACK = 0x7fffffff
3345} LSILOGICWHOINIT;
3346
3347
3348/**
3349 * IOC status codes.
3350 */
3351#define LSILOGIC_IOCSTATUS_SUCCESS 0x0000
3352#define LSILOGIC_IOCSTATUS_INVALID_FUNCTION 0x0001
3353#define LSILOGIC_IOCSTATUS_BUSY 0x0002
3354#define LSILOGIC_IOCSTATUS_INVALID_SGL 0x0003
3355#define LSILOGIC_IOCSTATUS_INTERNAL_ERROR 0x0004
3356#define LSILOGIC_IOCSTATUS_RESERVED 0x0005
3357#define LSILOGIC_IOCSTATUS_INSUFFICIENT_RESOURCES 0x0006
3358#define LSILOGIC_IOCSTATUS_INVALID_FIELD 0x0007
3359#define LSILOGIC_IOCSTATUS_INVALID_STATE 0x0008
3360#define LSILOGIC_IOCSTATUS_OP_STATE_NOT_SUPPOTED 0x0009
3361
3362/**
3363 * Size of the I/O and MMIO space.
3364 */
3365#define LSILOGIC_PCI_SPACE_IO_SIZE 256
3366#define LSILOGIC_PCI_SPACE_MEM_SIZE 128 * _1K
3367
3368/**
3369 * Doorbell register - Used to get the status of the controller and
3370 * initialise it.
3371 */
3372#define LSILOGIC_REG_DOORBELL 0x00
3373# define LSILOGIC_REG_DOORBELL_SET_STATE(enmState) (((enmState) & 0x0f) << 28)
3374# define LSILOGIC_REG_DOORBELL_SET_USED(fUsed) (((fUsed) ? 1 : 0) << 27)
3375# define LSILOGIC_REG_DOORBELL_SET_WHOINIT(enmWhoInit) (((enmWhoInit) & 0x07) << 24)
3376# define LSILOGIC_REG_DOORBELL_SET_FAULT_CODE(u16Code) (u16Code)
3377# define LSILOGIC_REG_DOORBELL_GET_FUNCTION(x) (((x) & 0xff000000) >> 24)
3378# define LSILOGIC_REG_DOORBELL_GET_SIZE(x) (((x) & 0x00ff0000) >> 16)
3379
3380/**
3381 * Functions which can be passed through the system doorbell.
3382 */
3383#define LSILOGIC_DOORBELL_FUNCTION_IOC_MSG_UNIT_RESET 0x40
3384#define LSILOGIC_DOORBELL_FUNCTION_IO_UNIT_RESET 0x41
3385#define LSILOGIC_DOORBELL_FUNCTION_HANDSHAKE 0x42
3386#define LSILOGIC_DOORBELL_FUNCTION_REPLY_FRAME_REMOVAL 0x43
3387
3388/**
3389 * Write sequence register for the diagnostic register.
3390 */
3391#define LSILOGIC_REG_WRITE_SEQUENCE 0x04
3392
3393/**
3394 * Diagnostic register - used to reset the controller.
3395 */
3396#define LSILOGIC_REG_HOST_DIAGNOSTIC 0x08
3397# define LSILOGIC_REG_HOST_DIAGNOSTIC_DIAG_MEM_ENABLE (RT_BIT(0))
3398# define LSILOGIC_REG_HOST_DIAGNOSTIC_DISABLE_ARM (RT_BIT(1))
3399# define LSILOGIC_REG_HOST_DIAGNOSTIC_RESET_ADAPTER (RT_BIT(2))
3400# define LSILOGIC_REG_HOST_DIAGNOSTIC_DIAG_RW_ENABLE (RT_BIT(4))
3401# define LSILOGIC_REG_HOST_DIAGNOSTIC_RESET_HISTORY (RT_BIT(5))
3402# define LSILOGIC_REG_HOST_DIAGNOSTIC_FLASH_BAD_SIG (RT_BIT(6))
3403# define LSILOGIC_REG_HOST_DIAGNOSTIC_DRWE (RT_BIT(7))
3404# define LSILOGIC_REG_HOST_DIAGNOSTIC_PREVENT_IOC_BOOT (RT_BIT(9))
3405# define LSILOGIC_REG_HOST_DIAGNOSTIC_CLEAR_FLASH_BAD_SIG (RT_BIT(10))
3406
3407#define LSILOGIC_REG_TEST_BASE_ADDRESS 0x0c
3408#define LSILOGIC_REG_DIAG_RW_DATA 0x10
3409#define LSILOGIC_REG_DIAG_RW_ADDRESS 0x14
3410
3411/**
3412 * Interrupt status register.
3413 */
3414#define LSILOGIC_REG_HOST_INTR_STATUS 0x30
3415# define LSILOGIC_REG_HOST_INTR_STATUS_W_MASK (RT_BIT(3))
3416# define LSILOGIC_REG_HOST_INTR_STATUS_DOORBELL_STS (RT_BIT(31))
3417# define LSILOGIC_REG_HOST_INTR_STATUS_REPLY_INTR (RT_BIT(3))
3418# define LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL (RT_BIT(0))
3419
3420/**
3421 * Interrupt mask register.
3422 */
3423#define LSILOGIC_REG_HOST_INTR_MASK 0x34
3424# define LSILOGIC_REG_HOST_INTR_MASK_W_MASK (RT_BIT(0) | RT_BIT(3) | RT_BIT(8) | RT_BIT(9))
3425# define LSILOGIC_REG_HOST_INTR_MASK_IRQ_ROUTING (RT_BIT(8) | RT_BIT(9))
3426# define LSILOGIC_REG_HOST_INTR_MASK_DOORBELL RT_BIT(0)
3427# define LSILOGIC_REG_HOST_INTR_MASK_REPLY RT_BIT(3)
3428
3429/**
3430 * Queue registers.
3431 */
3432#define LSILOGIC_REG_REQUEST_QUEUE 0x40
3433#define LSILOGIC_REG_REPLY_QUEUE 0x44
3434
3435#endif /* __DEVLSILOGICSCSI_H__ */
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