VirtualBox

source: vbox/trunk/src/VBox/Devices/Storage/DevATA.cpp@ 56992

Last change on this file since 56992 was 56992, checked in by vboxsync, 9 years ago

Devices: Log & Assertion formatting fixes.

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1/* $Id: DevATA.cpp 56992 2015-07-18 23:01:44Z vboxsync $ */
2/** @file
3 * VBox storage devices: ATA/ATAPI controller device (disk and cdrom).
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Defined Constants And Macros *
21*******************************************************************************/
22/** Temporary instrumentation for tracking down potential virtual disk
23 * write performance issues. */
24#undef VBOX_INSTRUMENT_DMA_WRITES
25
26/** @name The SSM saved state versions.
27 * @{
28 */
29/** The current saved state version. */
30#define ATA_SAVED_STATE_VERSION 20
31/** The saved state version used by VirtualBox 3.0.
32 * This lacks the config part and has the type at the and. */
33#define ATA_SAVED_STATE_VERSION_VBOX_30 19
34#define ATA_SAVED_STATE_VERSION_WITH_BOOL_TYPE 18
35#define ATA_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE 16
36#define ATA_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS 17
37/** @} */
38
39
40/*******************************************************************************
41* Header Files *
42*******************************************************************************/
43#define LOG_GROUP LOG_GROUP_DEV_IDE
44#include <VBox/vmm/pdmdev.h>
45#include <iprt/assert.h>
46#include <iprt/string.h>
47#ifdef IN_RING3
48# include <iprt/uuid.h>
49# include <iprt/semaphore.h>
50# include <iprt/thread.h>
51# include <iprt/time.h>
52# include <iprt/alloc.h>
53#endif /* IN_RING3 */
54#include <iprt/critsect.h>
55#include <iprt/asm.h>
56#include <VBox/vmm/stam.h>
57#include <VBox/vmm/mm.h>
58#include <VBox/vmm/pgm.h>
59
60#include <VBox/sup.h>
61#include <VBox/scsi.h>
62
63#include "PIIX3ATABmDma.h"
64#include "ide.h"
65#include "ATAPIPassthrough.h"
66#include "VBoxDD.h"
67
68
69/*******************************************************************************
70* Defined Constants And Macros *
71*******************************************************************************/
72/**
73 * Maximum number of sectors to transfer in a READ/WRITE MULTIPLE request.
74 * Set to 1 to disable multi-sector read support. According to the ATA
75 * specification this must be a power of 2 and it must fit in an 8 bit
76 * value. Thus the only valid values are 1, 2, 4, 8, 16, 32, 64 and 128.
77 */
78#define ATA_MAX_MULT_SECTORS 128
79
80/**
81 * Fastest PIO mode supported by the drive.
82 */
83#define ATA_PIO_MODE_MAX 4
84/**
85 * Fastest MDMA mode supported by the drive.
86 */
87#define ATA_MDMA_MODE_MAX 2
88/**
89 * Fastest UDMA mode supported by the drive.
90 */
91#define ATA_UDMA_MODE_MAX 6
92
93/** ATAPI sense info size. */
94#define ATAPI_SENSE_SIZE 64
95
96/** The maximum number of release log entries per device. */
97#define MAX_LOG_REL_ERRORS 1024
98
99/* MediaEventStatus */
100#define ATA_EVENT_STATUS_UNCHANGED 0 /**< medium event status not changed */
101#define ATA_EVENT_STATUS_MEDIA_NEW 1 /**< new medium inserted */
102#define ATA_EVENT_STATUS_MEDIA_REMOVED 2 /**< medium removed */
103#define ATA_EVENT_STATUS_MEDIA_CHANGED 3 /**< medium was removed + new medium was inserted */
104#define ATA_EVENT_STATUS_MEDIA_EJECT_REQUESTED 4 /**< medium eject requested (eject button pressed) */
105
106/* Media track type */
107#define ATA_MEDIA_TYPE_UNKNOWN 0 /**< unknown CD type */
108#define ATA_MEDIA_NO_DISC 0x70 /**< Door closed, no medium */
109
110/*******************************************************************************
111* Structures and Typedefs *
112*******************************************************************************/
113/**
114 * The state of an ATA device.
115 *
116 * @implements PDMIBASE
117 * @implements PDMIBLOCKPORT
118 * @implements PDMIMOUNTNOTIFY
119 */
120typedef struct ATADevState
121{
122 /** Flag indicating whether the current command uses LBA48 mode. */
123 bool fLBA48;
124 /** Flag indicating whether this drive implements the ATAPI command set. */
125 bool fATAPI;
126 /** Set if this interface has asserted the IRQ. */
127 bool fIrqPending;
128 /** Currently configured number of sectors in a multi-sector transfer. */
129 uint8_t cMultSectors;
130 /** PCHS disk geometry. */
131 PDMMEDIAGEOMETRY PCHSGeometry;
132 /** Total number of sectors on this disk. */
133 uint64_t cTotalSectors;
134 /** Sector size of the medium. */
135 uint32_t cbSector;
136 /** Number of sectors to transfer per IRQ. */
137 uint32_t cSectorsPerIRQ;
138
139 /** ATA/ATAPI register 1: feature (write-only). */
140 uint8_t uATARegFeature;
141 /** ATA/ATAPI register 1: feature, high order byte. */
142 uint8_t uATARegFeatureHOB;
143 /** ATA/ATAPI register 1: error (read-only). */
144 uint8_t uATARegError;
145 /** ATA/ATAPI register 2: sector count (read/write). */
146 uint8_t uATARegNSector;
147 /** ATA/ATAPI register 2: sector count, high order byte. */
148 uint8_t uATARegNSectorHOB;
149 /** ATA/ATAPI register 3: sector (read/write). */
150 uint8_t uATARegSector;
151 /** ATA/ATAPI register 3: sector, high order byte. */
152 uint8_t uATARegSectorHOB;
153 /** ATA/ATAPI register 4: cylinder low (read/write). */
154 uint8_t uATARegLCyl;
155 /** ATA/ATAPI register 4: cylinder low, high order byte. */
156 uint8_t uATARegLCylHOB;
157 /** ATA/ATAPI register 5: cylinder high (read/write). */
158 uint8_t uATARegHCyl;
159 /** ATA/ATAPI register 5: cylinder high, high order byte. */
160 uint8_t uATARegHCylHOB;
161 /** ATA/ATAPI register 6: select drive/head (read/write). */
162 uint8_t uATARegSelect;
163 /** ATA/ATAPI register 7: status (read-only). */
164 uint8_t uATARegStatus;
165 /** ATA/ATAPI register 7: command (write-only). */
166 uint8_t uATARegCommand;
167 /** ATA/ATAPI drive control register (write-only). */
168 uint8_t uATARegDevCtl;
169
170 /** Currently active transfer mode (MDMA/UDMA) and speed. */
171 uint8_t uATATransferMode;
172 /** Current transfer direction. */
173 uint8_t uTxDir;
174 /** Index of callback for begin transfer. */
175 uint8_t iBeginTransfer;
176 /** Index of callback for source/sink of data. */
177 uint8_t iSourceSink;
178 /** Flag indicating whether the current command transfers data in DMA mode. */
179 bool fDMA;
180 /** Set to indicate that ATAPI transfer semantics must be used. */
181 bool fATAPITransfer;
182
183 /** Total ATA/ATAPI transfer size, shared PIO/DMA. */
184 uint32_t cbTotalTransfer;
185 /** Elementary ATA/ATAPI transfer size, shared PIO/DMA. */
186 uint32_t cbElementaryTransfer;
187 /** Maximum ATAPI elementary transfer size, PIO only. */
188 uint32_t cbPIOTransferLimit;
189 /** ATAPI passthrough transfer size, shared PIO/DMA */
190 uint32_t cbAtapiPassthroughTransfer;
191 /** Current read/write buffer position, shared PIO/DMA. */
192 uint32_t iIOBufferCur;
193 /** First element beyond end of valid buffer content, shared PIO/DMA. */
194 uint32_t iIOBufferEnd;
195 /** Align the following fields correctly. */
196 uint32_t Alignment0;
197
198 /** ATA/ATAPI current PIO read/write transfer position. Not shared with DMA for safety reasons. */
199 uint32_t iIOBufferPIODataStart;
200 /** ATA/ATAPI current PIO read/write transfer end. Not shared with DMA for safety reasons. */
201 uint32_t iIOBufferPIODataEnd;
202
203 /** ATAPI current LBA position. */
204 uint32_t iATAPILBA;
205 /** ATAPI current sector size. */
206 uint32_t cbATAPISector;
207 /** ATAPI current command. */
208 uint8_t aATAPICmd[ATAPI_PACKET_SIZE];
209 /** ATAPI sense data. */
210 uint8_t abATAPISense[ATAPI_SENSE_SIZE];
211 /** HACK: Countdown till we report a newly unmounted drive as mounted. */
212 uint8_t cNotifiedMediaChange;
213 /** The same for GET_EVENT_STATUS for mechanism */
214 volatile uint32_t MediaEventStatus;
215
216 /** Media type if known. */
217 volatile uint32_t MediaTrackType;
218
219 /** The status LED state for this drive. */
220 PDMLED Led;
221
222 /** Size of I/O buffer. */
223 uint32_t cbIOBuffer;
224 /** Pointer to the I/O buffer. */
225 R3PTRTYPE(uint8_t *) pbIOBufferR3;
226 /** Pointer to the I/O buffer. */
227 R0PTRTYPE(uint8_t *) pbIOBufferR0;
228 /** Pointer to the I/O buffer. */
229 RCPTRTYPE(uint8_t *) pbIOBufferRC;
230
231 RTRCPTR Aligmnent1; /**< Align the statistics at an 8-byte boundary. */
232
233 /*
234 * No data that is part of the saved state after this point!!!!!
235 */
236
237 /* Release statistics: number of ATA DMA commands. */
238 STAMCOUNTER StatATADMA;
239 /* Release statistics: number of ATA PIO commands. */
240 STAMCOUNTER StatATAPIO;
241 /* Release statistics: number of ATAPI PIO commands. */
242 STAMCOUNTER StatATAPIDMA;
243 /* Release statistics: number of ATAPI PIO commands. */
244 STAMCOUNTER StatATAPIPIO;
245#ifdef VBOX_INSTRUMENT_DMA_WRITES
246 /* Release statistics: number of DMA sector writes and the time spent. */
247 STAMPROFILEADV StatInstrVDWrites;
248#endif
249
250 /** Statistics: number of read operations and the time spent reading. */
251 STAMPROFILEADV StatReads;
252 /** Statistics: number of bytes read. */
253 STAMCOUNTER StatBytesRead;
254 /** Statistics: number of write operations and the time spent writing. */
255 STAMPROFILEADV StatWrites;
256 /** Statistics: number of bytes written. */
257 STAMCOUNTER StatBytesWritten;
258 /** Statistics: number of flush operations and the time spend flushing. */
259 STAMPROFILE StatFlushes;
260
261 /** Mark the drive as having a non-rotational medium (i.e. as a SSD). */
262 bool fNonRotational;
263 /** Enable passing through commands directly to the ATAPI drive. */
264 bool fATAPIPassthrough;
265 /** Flag whether to overwrite inquiry data in passthrough mode. */
266 bool fOverwriteInquiry;
267 /** Number of errors we've reported to the release log.
268 * This is to prevent flooding caused by something going horribly wrong.
269 * this value against MAX_LOG_REL_ERRORS in places likely to cause floods
270 * like the ones we currently seeing on the linux smoke tests (2006-11-10). */
271 uint32_t cErrors;
272 /** Timestamp of last started command. 0 if no command pending. */
273 uint64_t u64CmdTS;
274
275 /** Pointer to the attached driver's base interface. */
276 R3PTRTYPE(PPDMIBASE) pDrvBase;
277 /** Pointer to the attached driver's block interface. */
278 R3PTRTYPE(PPDMIBLOCK) pDrvBlock;
279 /** Pointer to the attached driver's block bios interface. */
280 R3PTRTYPE(PPDMIBLOCKBIOS) pDrvBlockBios;
281 /** Pointer to the attached driver's mount interface.
282 * This is NULL if the driver isn't a removable unit. */
283 R3PTRTYPE(PPDMIMOUNT) pDrvMount;
284 /** The base interface. */
285 PDMIBASE IBase;
286 /** The block port interface. */
287 PDMIBLOCKPORT IPort;
288 /** The mount notify interface. */
289 PDMIMOUNTNOTIFY IMountNotify;
290 /** The LUN #. */
291 RTUINT iLUN;
292 RTUINT Alignment2; /**< Align pDevInsR3 correctly. */
293 /** Pointer to device instance. */
294 PPDMDEVINSR3 pDevInsR3;
295 /** Pointer to controller instance. */
296 R3PTRTYPE(struct ATACONTROLLER *) pControllerR3;
297 /** Pointer to device instance. */
298 PPDMDEVINSR0 pDevInsR0;
299 /** Pointer to controller instance. */
300 R0PTRTYPE(struct ATACONTROLLER *) pControllerR0;
301 /** Pointer to device instance. */
302 PPDMDEVINSRC pDevInsRC;
303 /** Pointer to controller instance. */
304 RCPTRTYPE(struct ATACONTROLLER *) pControllerRC;
305
306 /** The serial number to use for IDENTIFY DEVICE commands. */
307 char szSerialNumber[ATA_SERIAL_NUMBER_LENGTH+1];
308 /** The firmware revision to use for IDENTIFY DEVICE commands. */
309 char szFirmwareRevision[ATA_FIRMWARE_REVISION_LENGTH+1];
310 /** The model number to use for IDENTIFY DEVICE commands. */
311 char szModelNumber[ATA_MODEL_NUMBER_LENGTH+1];
312 /** The vendor identification string for SCSI INQUIRY commands. */
313 char szInquiryVendorId[ATAPI_INQUIRY_VENDOR_ID_LENGTH+1];
314 /** The product identification string for SCSI INQUIRY commands. */
315 char szInquiryProductId[ATAPI_INQUIRY_PRODUCT_ID_LENGTH+1];
316 /** The revision string for SCSI INQUIRY commands. */
317 char szInquiryRevision[ATAPI_INQUIRY_REVISION_LENGTH+1];
318 /** The current tracklist of the loaded medium if passthrough is used. */
319 R3PTRTYPE(PTRACKLIST) pTrackList;
320
321 uint8_t abAlignment4[HC_ARCH_BITS == 64 ? 7 : 3];
322} ATADevState;
323AssertCompileMemberAlignment(ATADevState, cTotalSectors, 8);
324AssertCompileMemberAlignment(ATADevState, StatATADMA, 8);
325AssertCompileMemberAlignment(ATADevState, u64CmdTS, 8);
326AssertCompileMemberAlignment(ATADevState, pDevInsR3, 8);
327AssertCompileMemberAlignment(ATADevState, szSerialNumber, 8);
328AssertCompileSizeAlignment(ATADevState, 8);
329
330
331typedef struct ATATransferRequest
332{
333 uint8_t iIf;
334 uint8_t iBeginTransfer;
335 uint8_t iSourceSink;
336 uint32_t cbTotalTransfer;
337 uint8_t uTxDir;
338} ATATransferRequest;
339
340
341typedef struct ATAAbortRequest
342{
343 uint8_t iIf;
344 bool fResetDrive;
345} ATAAbortRequest;
346
347
348typedef enum
349{
350 /** Begin a new transfer. */
351 ATA_AIO_NEW = 0,
352 /** Continue a DMA transfer. */
353 ATA_AIO_DMA,
354 /** Continue a PIO transfer. */
355 ATA_AIO_PIO,
356 /** Reset the drives on current controller, stop all transfer activity. */
357 ATA_AIO_RESET_ASSERTED,
358 /** Reset the drives on current controller, resume operation. */
359 ATA_AIO_RESET_CLEARED,
360 /** Abort the current transfer of a particular drive. */
361 ATA_AIO_ABORT
362} ATAAIO;
363
364
365typedef struct ATARequest
366{
367 ATAAIO ReqType;
368 union
369 {
370 ATATransferRequest t;
371 ATAAbortRequest a;
372 } u;
373} ATARequest;
374
375
376typedef struct ATACONTROLLER
377{
378 /** The base of the first I/O Port range. */
379 RTIOPORT IOPortBase1;
380 /** The base of the second I/O Port range. (0 if none) */
381 RTIOPORT IOPortBase2;
382 /** The assigned IRQ. */
383 RTUINT irq;
384 /** Access critical section */
385 PDMCRITSECT lock;
386
387 /** Selected drive. */
388 uint8_t iSelectedIf;
389 /** The interface on which to handle async I/O. */
390 uint8_t iAIOIf;
391 /** The state of the async I/O thread. */
392 uint8_t uAsyncIOState;
393 /** Flag indicating whether the next transfer is part of the current command. */
394 bool fChainedTransfer;
395 /** Set when the reset processing is currently active on this controller. */
396 bool fReset;
397 /** Flag whether the current transfer needs to be redone. */
398 bool fRedo;
399 /** Flag whether the redo suspend has been finished. */
400 bool fRedoIdle;
401 /** Flag whether the DMA operation to be redone is the final transfer. */
402 bool fRedoDMALastDesc;
403 /** The BusMaster DMA state. */
404 BMDMAState BmDma;
405 /** Pointer to first DMA descriptor. */
406 RTGCPHYS32 pFirstDMADesc;
407 /** Pointer to last DMA descriptor. */
408 RTGCPHYS32 pLastDMADesc;
409 /** Pointer to current DMA buffer (for redo operations). */
410 RTGCPHYS32 pRedoDMABuffer;
411 /** Size of current DMA buffer (for redo operations). */
412 uint32_t cbRedoDMABuffer;
413
414 /** The ATA/ATAPI interfaces of this controller. */
415 ATADevState aIfs[2];
416
417 /** Pointer to device instance. */
418 PPDMDEVINSR3 pDevInsR3;
419 /** Pointer to device instance. */
420 PPDMDEVINSR0 pDevInsR0;
421 /** Pointer to device instance. */
422 PPDMDEVINSRC pDevInsRC;
423
424 /** Set when the destroying the device instance and the thread must exit. */
425 uint32_t volatile fShutdown;
426 /** The async I/O thread handle. NIL_RTTHREAD if no thread. */
427 RTTHREAD AsyncIOThread;
428 /** The event semaphore the thread is waiting on for requests. */
429 SUPSEMEVENT hAsyncIOSem;
430 /** The support driver session handle. */
431 PSUPDRVSESSION pSupDrvSession;
432 /** The request queue for the AIO thread. One element is always unused. */
433 ATARequest aAsyncIORequests[4];
434 /** The position at which to insert a new request for the AIO thread. */
435 volatile uint8_t AsyncIOReqHead;
436 /** The position at which to get a new request for the AIO thread. */
437 volatile uint8_t AsyncIOReqTail;
438 /** Whether to call PDMDevHlpAsyncNotificationCompleted when idle. */
439 bool volatile fSignalIdle;
440 uint8_t Alignment3[1]; /**< Explicit padding of the 1 byte gap. */
441 /** Magic delay before triggering interrupts in DMA mode. */
442 uint32_t DelayIRQMillies;
443 /** The event semaphore the thread is waiting on during suspended I/O. */
444 RTSEMEVENT SuspendIOSem;
445 /** The lock protecting the request queue. */
446 PDMCRITSECT AsyncIORequestLock;
447#if 0 /*HC_ARCH_BITS == 32*/
448 uint32_t Alignment0;
449#endif
450
451 /** Timestamp we started the reset. */
452 uint64_t u64ResetTime;
453
454 /* Statistics */
455 STAMCOUNTER StatAsyncOps;
456 uint64_t StatAsyncMinWait;
457 uint64_t StatAsyncMaxWait;
458 STAMCOUNTER StatAsyncTimeUS;
459 STAMPROFILEADV StatAsyncTime;
460 STAMPROFILE StatLockWait;
461} ATACONTROLLER, *PATACONTROLLER;
462AssertCompileMemberAlignment(ATACONTROLLER, lock, 8);
463AssertCompileMemberAlignment(ATACONTROLLER, aIfs, 8);
464AssertCompileMemberAlignment(ATACONTROLLER, u64ResetTime, 8);
465AssertCompileMemberAlignment(ATACONTROLLER, StatAsyncOps, 8);
466AssertCompileMemberAlignment(ATACONTROLLER, AsyncIORequestLock, 8);
467AssertCompileSizeAlignment(ATACONTROLLER, 8);
468
469typedef enum CHIPSET
470{
471 /** PIIX3 chipset, must be 0 for saved state compatibility */
472 CHIPSET_PIIX3 = 0,
473 /** PIIX4 chipset, must be 1 for saved state compatibility */
474 CHIPSET_PIIX4 = 1,
475 /** ICH6 chipset */
476 CHIPSET_ICH6 = 2
477} CHIPSET;
478
479/**
480 * The state of the ATA PCI device.
481 *
482 * @extends PCIDEVICE
483 * @implements PDMILEDPORTS
484 */
485typedef struct PCIATAState
486{
487 PCIDEVICE dev;
488 /** The controllers. */
489 ATACONTROLLER aCts[2];
490 /** Pointer to device instance. */
491 PPDMDEVINSR3 pDevIns;
492 /** Status LUN: Base interface. */
493 PDMIBASE IBase;
494 /** Status LUN: Leds interface. */
495 PDMILEDPORTS ILeds;
496 /** Status LUN: Partner of ILeds. */
497 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
498 /** Status LUN: Media Notify. */
499 R3PTRTYPE(PPDMIMEDIANOTIFY) pMediaNotify;
500 /** Flag whether RC is enabled. */
501 bool fRCEnabled;
502 /** Flag whether R0 is enabled. */
503 bool fR0Enabled;
504 /** Flag indicating chipset being emulated. */
505 uint8_t u8Type;
506 bool Alignment0[HC_ARCH_BITS == 64 ? 5 : 1 ]; /**< Align the struct size. */
507} PCIATAState;
508
509#define PDMIBASE_2_PCIATASTATE(pInterface) ( (PCIATAState *)((uintptr_t)(pInterface) - RT_OFFSETOF(PCIATAState, IBase)) )
510#define PDMILEDPORTS_2_PCIATASTATE(pInterface) ( (PCIATAState *)((uintptr_t)(pInterface) - RT_OFFSETOF(PCIATAState, ILeds)) )
511#define PDMIBLOCKPORT_2_ATASTATE(pInterface) ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IPort)) )
512#define PDMIMOUNT_2_ATASTATE(pInterface) ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IMount)) )
513#define PDMIMOUNTNOTIFY_2_ATASTATE(pInterface) ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IMountNotify)) )
514#define PCIDEV_2_PCIATASTATE(pPciDev) ( (PCIATAState *)(pPciDev) )
515
516#define ATACONTROLLER_IDX(pController) ( (pController) - PDMINS_2_DATA(CONTROLLER_2_DEVINS(pController), PCIATAState *)->aCts )
517
518#define ATADEVSTATE_2_CONTROLLER(pIf) ( (pIf)->CTX_SUFF(pController) )
519#define ATADEVSTATE_2_DEVINS(pIf) ( (pIf)->CTX_SUFF(pDevIns) )
520#define CONTROLLER_2_DEVINS(pController) ( (pController)->CTX_SUFF(pDevIns) )
521#define PDMIBASE_2_ATASTATE(pInterface) ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IBase)) )
522#define PDMIBLOCKPORT_2_ATASTATE(pInterface) ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IPort)) )
523
524#ifndef VBOX_DEVICE_STRUCT_TESTCASE
525/*******************************************************************************
526 * Internal Functions *
527 ******************************************************************************/
528RT_C_DECLS_BEGIN
529
530PDMBOTHCBDECL(int) ataIOPortWrite1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
531PDMBOTHCBDECL(int) ataIOPortRead1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *u32, unsigned cb);
532PDMBOTHCBDECL(int) ataIOPortWriteStr1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint8_t const *pbSrc,
533 uint32_t *pcTransfers, unsigned cb);
534PDMBOTHCBDECL(int) ataIOPortReadStr1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint8_t *pbDst,
535 uint32_t *pcTransfers, unsigned cb);
536PDMBOTHCBDECL(int) ataIOPortWrite1Other(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
537PDMBOTHCBDECL(int) ataIOPortRead1Other(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *u32, unsigned cb);
538PDMBOTHCBDECL(int) ataIOPortWrite2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
539PDMBOTHCBDECL(int) ataIOPortRead2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *u32, unsigned cb);
540PDMBOTHCBDECL(int) ataBMDMAIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
541PDMBOTHCBDECL(int) ataBMDMAIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
542RT_C_DECLS_END
543
544
545
546DECLINLINE(void) ataSetStatusValue(ATADevState *s, uint8_t stat)
547{
548 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
549
550 /* Freeze status register contents while processing RESET. */
551 if (!pCtl->fReset)
552 {
553 s->uATARegStatus = stat;
554 Log2(("%s: LUN#%d status %#04x\n", __FUNCTION__, s->iLUN, s->uATARegStatus));
555 }
556}
557
558
559DECLINLINE(void) ataSetStatus(ATADevState *s, uint8_t stat)
560{
561 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
562
563 /* Freeze status register contents while processing RESET. */
564 if (!pCtl->fReset)
565 {
566 s->uATARegStatus |= stat;
567 Log2(("%s: LUN#%d status %#04x\n", __FUNCTION__, s->iLUN, s->uATARegStatus));
568 }
569}
570
571
572DECLINLINE(void) ataUnsetStatus(ATADevState *s, uint8_t stat)
573{
574 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
575
576 /* Freeze status register contents while processing RESET. */
577 if (!pCtl->fReset)
578 {
579 s->uATARegStatus &= ~stat;
580 Log2(("%s: LUN#%d status %#04x\n", __FUNCTION__, s->iLUN, s->uATARegStatus));
581 }
582}
583
584#if defined(IN_RING3) || defined(IN_RING0)
585
586# ifdef IN_RING3
587typedef void (*PBeginTransferFunc)(ATADevState *);
588typedef bool (*PSourceSinkFunc)(ATADevState *);
589
590static void ataR3ReadWriteSectorsBT(ATADevState *);
591static void ataR3PacketBT(ATADevState *);
592static void atapiR3CmdBT(ATADevState *);
593static void atapiR3PassthroughCmdBT(ATADevState *);
594
595static bool ataR3IdentifySS(ATADevState *);
596static bool ataR3FlushSS(ATADevState *);
597static bool ataR3ReadSectorsSS(ATADevState *);
598static bool ataR3WriteSectorsSS(ATADevState *);
599static bool ataR3ExecuteDeviceDiagnosticSS(ATADevState *);
600static bool ataR3TrimSS(ATADevState *);
601static bool ataR3PacketSS(ATADevState *);
602static bool atapiR3GetConfigurationSS(ATADevState *);
603static bool atapiR3GetEventStatusNotificationSS(ATADevState *);
604static bool atapiR3IdentifySS(ATADevState *);
605static bool atapiR3InquirySS(ATADevState *);
606static bool atapiR3MechanismStatusSS(ATADevState *);
607static bool atapiR3ModeSenseErrorRecoverySS(ATADevState *);
608static bool atapiR3ModeSenseCDStatusSS(ATADevState *);
609static bool atapiR3ReadSS(ATADevState *);
610static bool atapiR3ReadCapacitySS(ATADevState *);
611static bool atapiR3ReadDiscInformationSS(ATADevState *);
612static bool atapiR3ReadTOCNormalSS(ATADevState *);
613static bool atapiR3ReadTOCMultiSS(ATADevState *);
614static bool atapiR3ReadTOCRawSS(ATADevState *);
615static bool atapiR3ReadTrackInformationSS(ATADevState *);
616static bool atapiR3RequestSenseSS(ATADevState *);
617static bool atapiR3PassthroughSS(ATADevState *);
618static bool atapiR3ReadDVDStructureSS(ATADevState *);
619# endif /* IN_RING3 */
620
621/**
622 * Begin of transfer function indexes for g_apfnBeginTransFuncs.
623 */
624typedef enum ATAFNBT
625{
626 ATAFN_BT_NULL = 0,
627 ATAFN_BT_READ_WRITE_SECTORS,
628 ATAFN_BT_PACKET,
629 ATAFN_BT_ATAPI_CMD,
630 ATAFN_BT_ATAPI_PASSTHROUGH_CMD,
631 ATAFN_BT_MAX
632} ATAFNBT;
633
634# ifdef IN_RING3
635/**
636 * Array of end transfer functions, the index is ATAFNET.
637 * Make sure ATAFNET and this array match!
638 */
639static const PBeginTransferFunc g_apfnBeginTransFuncs[ATAFN_BT_MAX] =
640{
641 NULL,
642 ataR3ReadWriteSectorsBT,
643 ataR3PacketBT,
644 atapiR3CmdBT,
645 atapiR3PassthroughCmdBT,
646};
647# endif /* IN_RING3 */
648
649/**
650 * Source/sink function indexes for g_apfnSourceSinkFuncs.
651 */
652typedef enum ATAFNSS
653{
654 ATAFN_SS_NULL = 0,
655 ATAFN_SS_IDENTIFY,
656 ATAFN_SS_FLUSH,
657 ATAFN_SS_READ_SECTORS,
658 ATAFN_SS_WRITE_SECTORS,
659 ATAFN_SS_EXECUTE_DEVICE_DIAGNOSTIC,
660 ATAFN_SS_TRIM,
661 ATAFN_SS_PACKET,
662 ATAFN_SS_ATAPI_GET_CONFIGURATION,
663 ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION,
664 ATAFN_SS_ATAPI_IDENTIFY,
665 ATAFN_SS_ATAPI_INQUIRY,
666 ATAFN_SS_ATAPI_MECHANISM_STATUS,
667 ATAFN_SS_ATAPI_MODE_SENSE_ERROR_RECOVERY,
668 ATAFN_SS_ATAPI_MODE_SENSE_CD_STATUS,
669 ATAFN_SS_ATAPI_READ,
670 ATAFN_SS_ATAPI_READ_CAPACITY,
671 ATAFN_SS_ATAPI_READ_DISC_INFORMATION,
672 ATAFN_SS_ATAPI_READ_TOC_NORMAL,
673 ATAFN_SS_ATAPI_READ_TOC_MULTI,
674 ATAFN_SS_ATAPI_READ_TOC_RAW,
675 ATAFN_SS_ATAPI_READ_TRACK_INFORMATION,
676 ATAFN_SS_ATAPI_REQUEST_SENSE,
677 ATAFN_SS_ATAPI_PASSTHROUGH,
678 ATAFN_SS_ATAPI_READ_DVD_STRUCTURE,
679 ATAFN_SS_MAX
680} ATAFNSS;
681
682# ifdef IN_RING3
683/**
684 * Array of source/sink functions, the index is ATAFNSS.
685 * Make sure ATAFNSS and this array match!
686 */
687static const PSourceSinkFunc g_apfnSourceSinkFuncs[ATAFN_SS_MAX] =
688{
689 NULL,
690 ataR3IdentifySS,
691 ataR3FlushSS,
692 ataR3ReadSectorsSS,
693 ataR3WriteSectorsSS,
694 ataR3ExecuteDeviceDiagnosticSS,
695 ataR3TrimSS,
696 ataR3PacketSS,
697 atapiR3GetConfigurationSS,
698 atapiR3GetEventStatusNotificationSS,
699 atapiR3IdentifySS,
700 atapiR3InquirySS,
701 atapiR3MechanismStatusSS,
702 atapiR3ModeSenseErrorRecoverySS,
703 atapiR3ModeSenseCDStatusSS,
704 atapiR3ReadSS,
705 atapiR3ReadCapacitySS,
706 atapiR3ReadDiscInformationSS,
707 atapiR3ReadTOCNormalSS,
708 atapiR3ReadTOCMultiSS,
709 atapiR3ReadTOCRawSS,
710 atapiR3ReadTrackInformationSS,
711 atapiR3RequestSenseSS,
712 atapiR3PassthroughSS,
713 atapiR3ReadDVDStructureSS
714};
715# endif /* IN_RING3 */
716
717
718static const ATARequest g_ataDMARequest = { ATA_AIO_DMA, { { 0, 0, 0, 0, 0 } } };
719static const ATARequest g_ataPIORequest = { ATA_AIO_PIO, { { 0, 0, 0, 0, 0 } } };
720static const ATARequest g_ataResetARequest = { ATA_AIO_RESET_ASSERTED, { { 0, 0, 0, 0, 0 } } };
721static const ATARequest g_ataResetCRequest = { ATA_AIO_RESET_CLEARED, { { 0, 0, 0, 0, 0 } } };
722
723# ifdef IN_RING3
724static void ataR3AsyncIOClearRequests(PATACONTROLLER pCtl)
725{
726 int rc = PDMCritSectEnter(&pCtl->AsyncIORequestLock, VINF_SUCCESS);
727 AssertRC(rc);
728
729 pCtl->AsyncIOReqHead = 0;
730 pCtl->AsyncIOReqTail = 0;
731
732 rc = PDMCritSectLeave(&pCtl->AsyncIORequestLock);
733 AssertRC(rc);
734}
735# endif /* IN_RING3 */
736
737static void ataHCAsyncIOPutRequest(PATACONTROLLER pCtl, const ATARequest *pReq)
738{
739 int rc = PDMCritSectEnter(&pCtl->AsyncIORequestLock, VINF_SUCCESS);
740 AssertRC(rc);
741
742 Assert((pCtl->AsyncIOReqHead + 1) % RT_ELEMENTS(pCtl->aAsyncIORequests) != pCtl->AsyncIOReqTail);
743 memcpy(&pCtl->aAsyncIORequests[pCtl->AsyncIOReqHead], pReq, sizeof(*pReq));
744 pCtl->AsyncIOReqHead++;
745 pCtl->AsyncIOReqHead %= RT_ELEMENTS(pCtl->aAsyncIORequests);
746
747 rc = PDMCritSectLeave(&pCtl->AsyncIORequestLock);
748 AssertRC(rc);
749
750 rc = PDMHCCritSectScheduleExitEvent(&pCtl->lock, pCtl->hAsyncIOSem);
751 if (RT_FAILURE(rc))
752 {
753 rc = SUPSemEventSignal(pCtl->pSupDrvSession, pCtl->hAsyncIOSem);
754 AssertRC(rc);
755 }
756}
757
758# ifdef IN_RING3
759
760static const ATARequest *ataR3AsyncIOGetCurrentRequest(PATACONTROLLER pCtl)
761{
762 const ATARequest *pReq;
763
764 int rc = PDMCritSectEnter(&pCtl->AsyncIORequestLock, VINF_SUCCESS);
765 AssertRC(rc);
766
767 if (pCtl->AsyncIOReqHead != pCtl->AsyncIOReqTail)
768 pReq = &pCtl->aAsyncIORequests[pCtl->AsyncIOReqTail];
769 else
770 pReq = NULL;
771
772 rc = PDMCritSectLeave(&pCtl->AsyncIORequestLock);
773 AssertRC(rc);
774 return pReq;
775}
776
777
778/**
779 * Remove the request with the given type, as it's finished. The request
780 * is not removed blindly, as this could mean a RESET request that is not
781 * yet processed (but has cleared the request queue) is lost.
782 *
783 * @param pCtl Controller for which to remove the request.
784 * @param ReqType Type of the request to remove.
785 */
786static void ataR3AsyncIORemoveCurrentRequest(PATACONTROLLER pCtl, ATAAIO ReqType)
787{
788 int rc = PDMCritSectEnter(&pCtl->AsyncIORequestLock, VINF_SUCCESS);
789 AssertRC(rc);
790
791 if (pCtl->AsyncIOReqHead != pCtl->AsyncIOReqTail && pCtl->aAsyncIORequests[pCtl->AsyncIOReqTail].ReqType == ReqType)
792 {
793 pCtl->AsyncIOReqTail++;
794 pCtl->AsyncIOReqTail %= RT_ELEMENTS(pCtl->aAsyncIORequests);
795 }
796
797 rc = PDMCritSectLeave(&pCtl->AsyncIORequestLock);
798 AssertRC(rc);
799}
800
801
802/**
803 * Dump the request queue for a particular controller. First dump the queue
804 * contents, then the already processed entries, as long as they haven't been
805 * overwritten.
806 *
807 * @param pCtl Controller for which to dump the queue.
808 */
809static void ataR3AsyncIODumpRequests(PATACONTROLLER pCtl)
810{
811 int rc = PDMCritSectEnter(&pCtl->AsyncIORequestLock, VINF_SUCCESS);
812 AssertRC(rc);
813
814 LogRel(("PIIX3 ATA: Ctl#%d: request queue dump (topmost is current):\n", ATACONTROLLER_IDX(pCtl)));
815 uint8_t curr = pCtl->AsyncIOReqTail;
816 do
817 {
818 if (curr == pCtl->AsyncIOReqHead)
819 LogRel(("PIIX3 ATA: Ctl#%d: processed requests (topmost is oldest):\n", ATACONTROLLER_IDX(pCtl)));
820 switch (pCtl->aAsyncIORequests[curr].ReqType)
821 {
822 case ATA_AIO_NEW:
823 LogRel(("new transfer request, iIf=%d iBeginTransfer=%d iSourceSink=%d cbTotalTransfer=%d uTxDir=%d\n", pCtl->aAsyncIORequests[curr].u.t.iIf, pCtl->aAsyncIORequests[curr].u.t.iBeginTransfer, pCtl->aAsyncIORequests[curr].u.t.iSourceSink, pCtl->aAsyncIORequests[curr].u.t.cbTotalTransfer, pCtl->aAsyncIORequests[curr].u.t.uTxDir));
824 break;
825 case ATA_AIO_DMA:
826 LogRel(("dma transfer continuation\n"));
827 break;
828 case ATA_AIO_PIO:
829 LogRel(("pio transfer continuation\n"));
830 break;
831 case ATA_AIO_RESET_ASSERTED:
832 LogRel(("reset asserted request\n"));
833 break;
834 case ATA_AIO_RESET_CLEARED:
835 LogRel(("reset cleared request\n"));
836 break;
837 case ATA_AIO_ABORT:
838 LogRel(("abort request, iIf=%d fResetDrive=%d\n", pCtl->aAsyncIORequests[curr].u.a.iIf, pCtl->aAsyncIORequests[curr].u.a.fResetDrive));
839 break;
840 default:
841 LogRel(("unknown request %d\n", pCtl->aAsyncIORequests[curr].ReqType));
842 }
843 curr = (curr + 1) % RT_ELEMENTS(pCtl->aAsyncIORequests);
844 } while (curr != pCtl->AsyncIOReqTail);
845
846 rc = PDMCritSectLeave(&pCtl->AsyncIORequestLock);
847 AssertRC(rc);
848}
849
850
851/**
852 * Checks whether the request queue for a particular controller is empty
853 * or whether a particular controller is idle.
854 *
855 * @param pCtl Controller for which to check the queue.
856 * @param fStrict If set then the controller is checked to be idle.
857 */
858static bool ataR3AsyncIOIsIdle(PATACONTROLLER pCtl, bool fStrict)
859{
860 int rc = PDMCritSectEnter(&pCtl->AsyncIORequestLock, VINF_SUCCESS);
861 AssertRC(rc);
862
863 bool fIdle = pCtl->fRedoIdle;
864 if (!fIdle)
865 fIdle = (pCtl->AsyncIOReqHead == pCtl->AsyncIOReqTail);
866 if (fStrict)
867 fIdle &= (pCtl->uAsyncIOState == ATA_AIO_NEW);
868
869 rc = PDMCritSectLeave(&pCtl->AsyncIORequestLock);
870 AssertRC(rc);
871 return fIdle;
872}
873
874
875/**
876 * Send a transfer request to the async I/O thread.
877 *
878 * @param s Pointer to the ATA device state data.
879 * @param cbTotalTransfer Data transfer size.
880 * @param uTxDir Data transfer direction.
881 * @param iBeginTransfer Index of BeginTransfer callback.
882 * @param iSourceSink Index of SourceSink callback.
883 * @param fChainedTransfer Whether this is a transfer that is part of the previous command/transfer.
884 */
885static void ataR3StartTransfer(ATADevState *s, uint32_t cbTotalTransfer, uint8_t uTxDir, ATAFNBT iBeginTransfer,
886 ATAFNSS iSourceSink, bool fChainedTransfer)
887{
888 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
889 ATARequest Req;
890
891 Assert(PDMCritSectIsOwner(&pCtl->lock));
892
893 /* Do not issue new requests while the RESET line is asserted. */
894 if (pCtl->fReset)
895 {
896 Log2(("%s: Ctl#%d: suppressed new request as RESET is active\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
897 return;
898 }
899
900 /* If the controller is already doing something else right now, ignore
901 * the command that is being submitted. Some broken guests issue commands
902 * twice (e.g. the Linux kernel that comes with Acronis True Image 8). */
903 if (!fChainedTransfer && !ataR3AsyncIOIsIdle(pCtl, true /*fStrict*/))
904 {
905 Log(("%s: Ctl#%d: ignored command %#04x, controller state %d\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), s->uATARegCommand, pCtl->uAsyncIOState));
906 LogRel(("PIIX3 IDE: guest issued command %#04x while controller busy\n", s->uATARegCommand));
907 return;
908 }
909
910 Req.ReqType = ATA_AIO_NEW;
911 if (fChainedTransfer)
912 Req.u.t.iIf = pCtl->iAIOIf;
913 else
914 Req.u.t.iIf = pCtl->iSelectedIf;
915 Req.u.t.cbTotalTransfer = cbTotalTransfer;
916 Req.u.t.uTxDir = uTxDir;
917 Req.u.t.iBeginTransfer = iBeginTransfer;
918 Req.u.t.iSourceSink = iSourceSink;
919 ataSetStatusValue(s, ATA_STAT_BUSY);
920 pCtl->fChainedTransfer = fChainedTransfer;
921
922 /*
923 * Kick the worker thread into action.
924 */
925 Log2(("%s: Ctl#%d: message to async I/O thread, new request\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
926 ataHCAsyncIOPutRequest(pCtl, &Req);
927}
928
929
930/**
931 * Send an abort command request to the async I/O thread.
932 *
933 * @param s Pointer to the ATA device state data.
934 * @param fResetDrive Whether to reset the drive or just abort a command.
935 */
936static void ataR3AbortCurrentCommand(ATADevState *s, bool fResetDrive)
937{
938 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
939 ATARequest Req;
940
941 Assert(PDMCritSectIsOwner(&pCtl->lock));
942
943 /* Do not issue new requests while the RESET line is asserted. */
944 if (pCtl->fReset)
945 {
946 Log2(("%s: Ctl#%d: suppressed aborting command as RESET is active\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
947 return;
948 }
949
950 Req.ReqType = ATA_AIO_ABORT;
951 Req.u.a.iIf = pCtl->iSelectedIf;
952 Req.u.a.fResetDrive = fResetDrive;
953 ataSetStatus(s, ATA_STAT_BUSY);
954 Log2(("%s: Ctl#%d: message to async I/O thread, abort command on LUN#%d\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), s->iLUN));
955 ataHCAsyncIOPutRequest(pCtl, &Req);
956}
957# endif /* IN_RING3 */
958
959static void ataHCSetIRQ(ATADevState *s)
960{
961 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
962 PPDMDEVINS pDevIns = ATADEVSTATE_2_DEVINS(s);
963
964 if (!(s->uATARegDevCtl & ATA_DEVCTL_DISABLE_IRQ))
965 {
966 Log2(("%s: LUN#%d asserting IRQ\n", __FUNCTION__, s->iLUN));
967 /* The BMDMA unit unconditionally sets BM_STATUS_INT if the interrupt
968 * line is asserted. It monitors the line for a rising edge. */
969 if (!s->fIrqPending)
970 pCtl->BmDma.u8Status |= BM_STATUS_INT;
971 /* Only actually set the IRQ line if updating the currently selected drive. */
972 if (s == &pCtl->aIfs[pCtl->iSelectedIf])
973 {
974 /** @todo experiment with adaptive IRQ delivery: for reads it is
975 * better to wait for IRQ delivery, as it reduces latency. */
976 if (pCtl->irq == 16)
977 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
978 else
979 PDMDevHlpISASetIrq(pDevIns, pCtl->irq, 1);
980 }
981 }
982 s->fIrqPending = true;
983}
984
985#endif /* IN_RING0 || IN_RING3 */
986
987static void ataUnsetIRQ(ATADevState *s)
988{
989 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
990 PPDMDEVINS pDevIns = ATADEVSTATE_2_DEVINS(s);
991
992 if (!(s->uATARegDevCtl & ATA_DEVCTL_DISABLE_IRQ))
993 {
994 Log2(("%s: LUN#%d deasserting IRQ\n", __FUNCTION__, s->iLUN));
995 /* Only actually unset the IRQ line if updating the currently selected drive. */
996 if (s == &pCtl->aIfs[pCtl->iSelectedIf])
997 {
998 if (pCtl->irq == 16)
999 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
1000 else
1001 PDMDevHlpISASetIrq(pDevIns, pCtl->irq, 0);
1002 }
1003 }
1004 s->fIrqPending = false;
1005}
1006
1007#if defined(IN_RING0) || defined(IN_RING3)
1008
1009static void ataHCPIOTransferStart(ATADevState *s, uint32_t start, uint32_t size)
1010{
1011 Log2(("%s: LUN#%d start %d size %d\n", __FUNCTION__, s->iLUN, start, size));
1012 s->iIOBufferPIODataStart = start;
1013 s->iIOBufferPIODataEnd = start + size;
1014 ataSetStatus(s, ATA_STAT_DRQ | ATA_STAT_SEEK);
1015 ataUnsetStatus(s, ATA_STAT_BUSY);
1016}
1017
1018
1019static void ataHCPIOTransferStop(ATADevState *s)
1020{
1021 Log2(("%s: LUN#%d\n", __FUNCTION__, s->iLUN));
1022 if (s->fATAPITransfer)
1023 {
1024 s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
1025 Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector));
1026 ataHCSetIRQ(s);
1027 s->fATAPITransfer = false;
1028 }
1029 s->cbTotalTransfer = 0;
1030 s->cbElementaryTransfer = 0;
1031 s->iIOBufferPIODataStart = 0;
1032 s->iIOBufferPIODataEnd = 0;
1033 s->iBeginTransfer = ATAFN_BT_NULL;
1034 s->iSourceSink = ATAFN_SS_NULL;
1035}
1036
1037
1038static void ataHCPIOTransferLimitATAPI(ATADevState *s)
1039{
1040 uint32_t cbLimit, cbTransfer;
1041
1042 cbLimit = s->cbPIOTransferLimit;
1043 /* Use maximum transfer size if the guest requested 0. Avoids a hang. */
1044 if (cbLimit == 0)
1045 cbLimit = 0xfffe;
1046 Log2(("%s: byte count limit=%d\n", __FUNCTION__, cbLimit));
1047 if (cbLimit == 0xffff)
1048 cbLimit--;
1049 cbTransfer = RT_MIN(s->cbTotalTransfer, s->iIOBufferEnd - s->iIOBufferCur);
1050 if (cbTransfer > cbLimit)
1051 {
1052 /* Byte count limit for clipping must be even in this case */
1053 if (cbLimit & 1)
1054 cbLimit--;
1055 cbTransfer = cbLimit;
1056 }
1057 s->uATARegLCyl = cbTransfer;
1058 s->uATARegHCyl = cbTransfer >> 8;
1059 s->cbElementaryTransfer = cbTransfer;
1060}
1061
1062# ifdef IN_RING3
1063
1064static uint32_t ataR3GetNSectors(ATADevState *s)
1065{
1066 /* 0 means either 256 (LBA28) or 65536 (LBA48) sectors. */
1067 if (s->fLBA48)
1068 {
1069 if (!s->uATARegNSector && !s->uATARegNSectorHOB)
1070 return 65536;
1071 else
1072 return s->uATARegNSectorHOB << 8 | s->uATARegNSector;
1073 }
1074 else
1075 {
1076 if (!s->uATARegNSector)
1077 return 256;
1078 else
1079 return s->uATARegNSector;
1080 }
1081}
1082
1083
1084static void ataR3PadString(uint8_t *pbDst, const char *pbSrc, uint32_t cbSize)
1085{
1086 for (uint32_t i = 0; i < cbSize; i++)
1087 {
1088 if (*pbSrc)
1089 pbDst[i ^ 1] = *pbSrc++;
1090 else
1091 pbDst[i ^ 1] = ' ';
1092 }
1093}
1094
1095
1096static void ataR3SCSIPadStr(uint8_t *pbDst, const char *pbSrc, uint32_t cbSize)
1097{
1098 for (uint32_t i = 0; i < cbSize; i++)
1099 {
1100 if (*pbSrc)
1101 pbDst[i] = *pbSrc++;
1102 else
1103 pbDst[i] = ' ';
1104 }
1105}
1106
1107
1108DECLINLINE(void) ataH2BE_U16(uint8_t *pbBuf, uint16_t val)
1109{
1110 pbBuf[0] = val >> 8;
1111 pbBuf[1] = val;
1112}
1113
1114
1115DECLINLINE(void) ataH2BE_U24(uint8_t *pbBuf, uint32_t val)
1116{
1117 pbBuf[0] = val >> 16;
1118 pbBuf[1] = val >> 8;
1119 pbBuf[2] = val;
1120}
1121
1122
1123DECLINLINE(void) ataH2BE_U32(uint8_t *pbBuf, uint32_t val)
1124{
1125 pbBuf[0] = val >> 24;
1126 pbBuf[1] = val >> 16;
1127 pbBuf[2] = val >> 8;
1128 pbBuf[3] = val;
1129}
1130
1131
1132DECLINLINE(uint16_t) ataBE2H_U16(const uint8_t *pbBuf)
1133{
1134 return (pbBuf[0] << 8) | pbBuf[1];
1135}
1136
1137
1138DECLINLINE(uint32_t) ataBE2H_U24(const uint8_t *pbBuf)
1139{
1140 return (pbBuf[0] << 16) | (pbBuf[1] << 8) | pbBuf[2];
1141}
1142
1143
1144DECLINLINE(uint32_t) ataBE2H_U32(const uint8_t *pbBuf)
1145{
1146 return (pbBuf[0] << 24) | (pbBuf[1] << 16) | (pbBuf[2] << 8) | pbBuf[3];
1147}
1148
1149
1150DECLINLINE(void) ataLBA2MSF(uint8_t *pbBuf, uint32_t iATAPILBA)
1151{
1152 iATAPILBA += 150;
1153 pbBuf[0] = (iATAPILBA / 75) / 60;
1154 pbBuf[1] = (iATAPILBA / 75) % 60;
1155 pbBuf[2] = iATAPILBA % 75;
1156}
1157
1158
1159DECLINLINE(uint32_t) ataMSF2LBA(const uint8_t *pbBuf)
1160{
1161 return (pbBuf[0] * 60 + pbBuf[1]) * 75 + pbBuf[2];
1162}
1163
1164/**
1165 * Compares two MSF values.
1166 *
1167 * @returns 1 if the first value is greater than the second value.
1168 * 0 if both are equal
1169 * -1 if the first value is smaller than the second value.
1170 */
1171DECLINLINE(int) atapiCmpMSF(const uint8_t *pbMSF1, const uint8_t *pbMSF2)
1172{
1173 int iRes = 0;
1174
1175 for (unsigned i = 0; i < 3; i++)
1176 {
1177 if (pbMSF1[i] < pbMSF2[i])
1178 {
1179 iRes = -1;
1180 break;
1181 }
1182 else if (pbMSF1[i] > pbMSF2[i])
1183 {
1184 iRes = 1;
1185 break;
1186 }
1187 }
1188
1189 return iRes;
1190}
1191
1192static void ataR3CmdOK(ATADevState *s, uint8_t status)
1193{
1194 s->uATARegError = 0; /* Not needed by ATA spec, but cannot hurt. */
1195 ataSetStatusValue(s, ATA_STAT_READY | status);
1196}
1197
1198
1199static void ataR3CmdError(ATADevState *s, uint8_t uErrorCode)
1200{
1201 Log(("%s: code=%#x\n", __FUNCTION__, uErrorCode));
1202 Assert(uErrorCode);
1203 s->uATARegError = uErrorCode;
1204 ataSetStatusValue(s, ATA_STAT_READY | ATA_STAT_ERR);
1205 s->cbTotalTransfer = 0;
1206 s->cbElementaryTransfer = 0;
1207 s->iIOBufferCur = 0;
1208 s->iIOBufferEnd = 0;
1209 s->uTxDir = PDMBLOCKTXDIR_NONE;
1210 s->iBeginTransfer = ATAFN_BT_NULL;
1211 s->iSourceSink = ATAFN_SS_NULL;
1212}
1213
1214static uint32_t ataR3Checksum(void* ptr, size_t count)
1215{
1216 uint8_t u8Sum = 0xa5, *p = (uint8_t*)ptr;
1217 size_t i;
1218
1219 for (i = 0; i < count; i++)
1220 {
1221 u8Sum += *p++;
1222 }
1223
1224 return (uint8_t)-(int32_t)u8Sum;
1225}
1226
1227static bool ataR3IdentifySS(ATADevState *s)
1228{
1229 uint16_t *p;
1230
1231 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
1232 Assert(s->cbElementaryTransfer == 512);
1233
1234 p = (uint16_t *)s->CTX_SUFF(pbIOBuffer);
1235 memset(p, 0, 512);
1236 p[0] = RT_H2LE_U16(0x0040);
1237 p[1] = RT_H2LE_U16(RT_MIN(s->PCHSGeometry.cCylinders, 16383));
1238 p[3] = RT_H2LE_U16(s->PCHSGeometry.cHeads);
1239 /* Block size; obsolete, but required for the BIOS. */
1240 p[5] = RT_H2LE_U16(s->cbSector);
1241 p[6] = RT_H2LE_U16(s->PCHSGeometry.cSectors);
1242 ataR3PadString((uint8_t *)(p + 10), s->szSerialNumber, ATA_SERIAL_NUMBER_LENGTH); /* serial number */
1243 p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
1244 p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
1245 p[22] = RT_H2LE_U16(0); /* ECC bytes per sector */
1246 ataR3PadString((uint8_t *)(p + 23), s->szFirmwareRevision, ATA_FIRMWARE_REVISION_LENGTH); /* firmware version */
1247 ataR3PadString((uint8_t *)(p + 27), s->szModelNumber, ATA_MODEL_NUMBER_LENGTH); /* model */
1248# if ATA_MAX_MULT_SECTORS > 1
1249 p[47] = RT_H2LE_U16(0x8000 | ATA_MAX_MULT_SECTORS);
1250# endif
1251 p[48] = RT_H2LE_U16(1); /* dword I/O, used by the BIOS */
1252 p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
1253 p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
1254 p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
1255 p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
1256 p[53] = RT_H2LE_U16(1 | 1 << 1 | 1 << 2); /* words 54-58,64-70,88 valid */
1257 p[54] = RT_H2LE_U16(RT_MIN(s->PCHSGeometry.cCylinders, 16383));
1258 p[55] = RT_H2LE_U16(s->PCHSGeometry.cHeads);
1259 p[56] = RT_H2LE_U16(s->PCHSGeometry.cSectors);
1260 p[57] = RT_H2LE_U16( RT_MIN(s->PCHSGeometry.cCylinders, 16383)
1261 * s->PCHSGeometry.cHeads
1262 * s->PCHSGeometry.cSectors);
1263 p[58] = RT_H2LE_U16( RT_MIN(s->PCHSGeometry.cCylinders, 16383)
1264 * s->PCHSGeometry.cHeads
1265 * s->PCHSGeometry.cSectors >> 16);
1266 if (s->cMultSectors)
1267 p[59] = RT_H2LE_U16(0x100 | s->cMultSectors);
1268 if (s->cTotalSectors <= (1 << 28) - 1)
1269 {
1270 p[60] = RT_H2LE_U16(s->cTotalSectors);
1271 p[61] = RT_H2LE_U16(s->cTotalSectors >> 16);
1272 }
1273 else
1274 {
1275 /* Report maximum number of sectors possible with LBA28 */
1276 p[60] = RT_H2LE_U16(((1 << 28) - 1) & 0xffff);
1277 p[61] = RT_H2LE_U16(((1 << 28) - 1) >> 16);
1278 }
1279 p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, s->uATATransferMode)); /* MDMA modes supported / mode enabled */
1280 p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
1281 p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
1282 p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
1283 p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
1284 p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
1285 if ( s->pDrvBlock->pfnDiscard
1286 || s->cbSector != 512
1287 || s->fNonRotational)
1288 {
1289 p[80] = RT_H2LE_U16(0x1f0); /* support everything up to ATA/ATAPI-8 ACS */
1290 p[81] = RT_H2LE_U16(0x28); /* conforms to ATA/ATAPI-8 ACS */
1291 }
1292 else
1293 {
1294 p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
1295 p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
1296 }
1297 p[82] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* supports power management, write cache and look-ahead */
1298 if (s->cTotalSectors <= (1 << 28) - 1)
1299 p[83] = RT_H2LE_U16(1 << 14 | 1 << 12); /* supports FLUSH CACHE */
1300 else
1301 p[83] = RT_H2LE_U16(1 << 14 | 1 << 10 | 1 << 12 | 1 << 13); /* supports LBA48, FLUSH CACHE and FLUSH CACHE EXT */
1302 p[84] = RT_H2LE_U16(1 << 14);
1303 p[85] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* enabled power management, write cache and look-ahead */
1304 if (s->cTotalSectors <= (1 << 28) - 1)
1305 p[86] = RT_H2LE_U16(1 << 12); /* enabled FLUSH CACHE */
1306 else
1307 p[86] = RT_H2LE_U16(1 << 10 | 1 << 12 | 1 << 13); /* enabled LBA48, FLUSH CACHE and FLUSH CACHE EXT */
1308 p[87] = RT_H2LE_U16(1 << 14);
1309 p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, s->uATATransferMode)); /* UDMA modes supported / mode enabled */
1310 p[93] = RT_H2LE_U16((1 | 1 << 1) << ((s->iLUN & 1) == 0 ? 0 : 8) | 1 << 13 | 1 << 14);
1311 if (s->cTotalSectors > (1 << 28) - 1)
1312 {
1313 p[100] = RT_H2LE_U16(s->cTotalSectors);
1314 p[101] = RT_H2LE_U16(s->cTotalSectors >> 16);
1315 p[102] = RT_H2LE_U16(s->cTotalSectors >> 32);
1316 p[103] = RT_H2LE_U16(s->cTotalSectors >> 48);
1317 }
1318
1319 if (s->cbSector != 512)
1320 {
1321 uint32_t cSectorSizeInWords = s->cbSector / sizeof(uint16_t);
1322 /* Enable reporting of logical sector size. */
1323 p[106] |= RT_H2LE_U16(RT_BIT(12) | RT_BIT(14));
1324 p[117] = RT_H2LE_U16(cSectorSizeInWords);
1325 p[118] = RT_H2LE_U16(cSectorSizeInWords >> 16);
1326 }
1327
1328 if (s->pDrvBlock->pfnDiscard) /** @todo: Set bit 14 in word 69 too? (Deterministic read after TRIM). */
1329 p[169] = RT_H2LE_U16(1); /* DATA SET MANAGEMENT command supported. */
1330 if (s->fNonRotational)
1331 p[217] = RT_H2LE_U16(1); /* Non-rotational medium */
1332 uint32_t uCsum = ataR3Checksum(p, 510);
1333 p[255] = RT_H2LE_U16(0xa5 | (uCsum << 8)); /* Integrity word */
1334 s->iSourceSink = ATAFN_SS_NULL;
1335 ataR3CmdOK(s, ATA_STAT_SEEK);
1336 return false;
1337}
1338
1339
1340static bool ataR3FlushSS(ATADevState *s)
1341{
1342 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
1343 int rc;
1344
1345 Assert(s->uTxDir == PDMBLOCKTXDIR_NONE);
1346 Assert(!s->cbElementaryTransfer);
1347
1348 PDMCritSectLeave(&pCtl->lock);
1349
1350 STAM_PROFILE_START(&s->StatFlushes, f);
1351 rc = s->pDrvBlock->pfnFlush(s->pDrvBlock);
1352 AssertRC(rc);
1353 STAM_PROFILE_STOP(&s->StatFlushes, f);
1354
1355 STAM_PROFILE_START(&pCtl->StatLockWait, a);
1356 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
1357 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
1358 ataR3CmdOK(s, 0);
1359 return false;
1360}
1361
1362static bool atapiR3IdentifySS(ATADevState *s)
1363{
1364 uint16_t *p;
1365
1366 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
1367 Assert(s->cbElementaryTransfer == 512);
1368
1369 p = (uint16_t *)s->CTX_SUFF(pbIOBuffer);
1370 memset(p, 0, 512);
1371 /* Removable CDROM, 3ms response, 12 byte packets */
1372 p[0] = RT_H2LE_U16(2 << 14 | 5 << 8 | 1 << 7 | 0 << 5 | 0 << 0);
1373 ataR3PadString((uint8_t *)(p + 10), s->szSerialNumber, ATA_SERIAL_NUMBER_LENGTH); /* serial number */
1374 p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
1375 p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
1376 ataR3PadString((uint8_t *)(p + 23), s->szFirmwareRevision, ATA_FIRMWARE_REVISION_LENGTH); /* firmware version */
1377 ataR3PadString((uint8_t *)(p + 27), s->szModelNumber, ATA_MODEL_NUMBER_LENGTH); /* model */
1378 p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
1379 p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
1380 p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
1381 p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
1382 p[53] = RT_H2LE_U16(1 << 1 | 1 << 2); /* words 64-70,88 are valid */
1383 p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, s->uATATransferMode)); /* MDMA modes supported / mode enabled */
1384 p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
1385 p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
1386 p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
1387 p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
1388 p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
1389 p[73] = RT_H2LE_U16(0x003e); /* ATAPI CDROM major */
1390 p[74] = RT_H2LE_U16(9); /* ATAPI CDROM minor */
1391 p[75] = RT_H2LE_U16(1); /* queue depth 1 */
1392 p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
1393 p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
1394 p[82] = RT_H2LE_U16(1 << 4 | 1 << 9); /* supports packet command set and DEVICE RESET */
1395 p[83] = RT_H2LE_U16(1 << 14);
1396 p[84] = RT_H2LE_U16(1 << 14);
1397 p[85] = RT_H2LE_U16(1 << 4 | 1 << 9); /* enabled packet command set and DEVICE RESET */
1398 p[86] = RT_H2LE_U16(0);
1399 p[87] = RT_H2LE_U16(1 << 14);
1400 p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, s->uATATransferMode)); /* UDMA modes supported / mode enabled */
1401 p[93] = RT_H2LE_U16((1 | 1 << 1) << ((s->iLUN & 1) == 0 ? 0 : 8) | 1 << 13 | 1 << 14);
1402 /* According to ATAPI-5 spec:
1403 *
1404 * The use of this word is optional.
1405 * If bits 7:0 of this word contain the signature A5h, bits 15:8
1406 * contain the data
1407 * structure checksum.
1408 * The data structure checksum is the twos complement of the sum of
1409 * all bytes in words 0 through 254 and the byte consisting of
1410 * bits 7:0 in word 255.
1411 * Each byte shall be added with unsigned arithmetic,
1412 * and overflow shall be ignored.
1413 * The sum of all 512 bytes is zero when the checksum is correct.
1414 */
1415 uint32_t uCsum = ataR3Checksum(p, 510);
1416 p[255] = RT_H2LE_U16(0xa5 | (uCsum << 8)); /* Integrity word */
1417
1418 s->iSourceSink = ATAFN_SS_NULL;
1419 ataR3CmdOK(s, ATA_STAT_SEEK);
1420 return false;
1421}
1422
1423
1424static void ataR3SetSignature(ATADevState *s)
1425{
1426 s->uATARegSelect &= 0xf0; /* clear head */
1427 /* put signature */
1428 s->uATARegNSector = 1;
1429 s->uATARegSector = 1;
1430 if (s->fATAPI)
1431 {
1432 s->uATARegLCyl = 0x14;
1433 s->uATARegHCyl = 0xeb;
1434 }
1435 else if (s->pDrvBlock)
1436 {
1437 s->uATARegLCyl = 0;
1438 s->uATARegHCyl = 0;
1439 }
1440 else
1441 {
1442 s->uATARegLCyl = 0xff;
1443 s->uATARegHCyl = 0xff;
1444 }
1445}
1446
1447
1448static uint64_t ataR3GetSector(ATADevState *s)
1449{
1450 uint64_t iLBA;
1451 if (s->uATARegSelect & 0x40)
1452 {
1453 /* any LBA variant */
1454 if (s->fLBA48)
1455 {
1456 /* LBA48 */
1457 iLBA = ((uint64_t)s->uATARegHCylHOB << 40) |
1458 ((uint64_t)s->uATARegLCylHOB << 32) |
1459 ((uint64_t)s->uATARegSectorHOB << 24) |
1460 ((uint64_t)s->uATARegHCyl << 16) |
1461 ((uint64_t)s->uATARegLCyl << 8) |
1462 s->uATARegSector;
1463 }
1464 else
1465 {
1466 /* LBA */
1467 iLBA = ((s->uATARegSelect & 0x0f) << 24) | (s->uATARegHCyl << 16) |
1468 (s->uATARegLCyl << 8) | s->uATARegSector;
1469 }
1470 }
1471 else
1472 {
1473 /* CHS */
1474 iLBA = ((s->uATARegHCyl << 8) | s->uATARegLCyl) * s->PCHSGeometry.cHeads * s->PCHSGeometry.cSectors +
1475 (s->uATARegSelect & 0x0f) * s->PCHSGeometry.cSectors +
1476 (s->uATARegSector - 1);
1477 }
1478 return iLBA;
1479}
1480
1481static void ataR3SetSector(ATADevState *s, uint64_t iLBA)
1482{
1483 uint32_t cyl, r;
1484 if (s->uATARegSelect & 0x40)
1485 {
1486 /* any LBA variant */
1487 if (s->fLBA48)
1488 {
1489 /* LBA48 */
1490 s->uATARegHCylHOB = iLBA >> 40;
1491 s->uATARegLCylHOB = iLBA >> 32;
1492 s->uATARegSectorHOB = iLBA >> 24;
1493 s->uATARegHCyl = iLBA >> 16;
1494 s->uATARegLCyl = iLBA >> 8;
1495 s->uATARegSector = iLBA;
1496 }
1497 else
1498 {
1499 /* LBA */
1500 s->uATARegSelect = (s->uATARegSelect & 0xf0) | (iLBA >> 24);
1501 s->uATARegHCyl = (iLBA >> 16);
1502 s->uATARegLCyl = (iLBA >> 8);
1503 s->uATARegSector = (iLBA);
1504 }
1505 }
1506 else
1507 {
1508 /* CHS */
1509 cyl = iLBA / (s->PCHSGeometry.cHeads * s->PCHSGeometry.cSectors);
1510 r = iLBA % (s->PCHSGeometry.cHeads * s->PCHSGeometry.cSectors);
1511 s->uATARegHCyl = cyl >> 8;
1512 s->uATARegLCyl = cyl;
1513 s->uATARegSelect = (s->uATARegSelect & 0xf0) | ((r / s->PCHSGeometry.cSectors) & 0x0f);
1514 s->uATARegSector = (r % s->PCHSGeometry.cSectors) + 1;
1515 }
1516}
1517
1518
1519static void ataR3WarningDiskFull(PPDMDEVINS pDevIns)
1520{
1521 int rc;
1522 LogRel(("PIIX3 ATA: Host disk full\n"));
1523 rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevATA_DISKFULL",
1524 N_("Host system reported disk full. VM execution is suspended. You can resume after freeing some space"));
1525 AssertRC(rc);
1526}
1527
1528static void ataR3WarningFileTooBig(PPDMDEVINS pDevIns)
1529{
1530 int rc;
1531 LogRel(("PIIX3 ATA: File too big\n"));
1532 rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevATA_FILETOOBIG",
1533 N_("Host system reported that the file size limit of the host file system has been exceeded. VM execution is suspended. You need to move your virtual hard disk to a filesystem which allows bigger files"));
1534 AssertRC(rc);
1535}
1536
1537static void ataR3WarningISCSI(PPDMDEVINS pDevIns)
1538{
1539 int rc;
1540 LogRel(("PIIX3 ATA: iSCSI target unavailable\n"));
1541 rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevATA_ISCSIDOWN",
1542 N_("The iSCSI target has stopped responding. VM execution is suspended. You can resume when it is available again"));
1543 AssertRC(rc);
1544}
1545
1546static bool ataR3IsRedoSetWarning(ATADevState *s, int rc)
1547{
1548 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
1549 Assert(!PDMCritSectIsOwner(&pCtl->lock));
1550 if (rc == VERR_DISK_FULL)
1551 {
1552 pCtl->fRedoIdle = true;
1553 ataR3WarningDiskFull(ATADEVSTATE_2_DEVINS(s));
1554 return true;
1555 }
1556 if (rc == VERR_FILE_TOO_BIG)
1557 {
1558 pCtl->fRedoIdle = true;
1559 ataR3WarningFileTooBig(ATADEVSTATE_2_DEVINS(s));
1560 return true;
1561 }
1562 if (rc == VERR_BROKEN_PIPE || rc == VERR_NET_CONNECTION_REFUSED)
1563 {
1564 pCtl->fRedoIdle = true;
1565 /* iSCSI connection abort (first error) or failure to reestablish
1566 * connection (second error). Pause VM. On resume we'll retry. */
1567 ataR3WarningISCSI(ATADEVSTATE_2_DEVINS(s));
1568 return true;
1569 }
1570 if (rc == VERR_VD_DEK_MISSING)
1571 {
1572 /* Error message already set. */
1573 pCtl->fRedoIdle = true;
1574 return true;
1575 }
1576
1577 return false;
1578}
1579
1580
1581static int ataR3ReadSectors(ATADevState *s, uint64_t u64Sector, void *pvBuf,
1582 uint32_t cSectors, bool *pfRedo)
1583{
1584 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
1585 int rc;
1586
1587 PDMCritSectLeave(&pCtl->lock);
1588
1589 STAM_PROFILE_ADV_START(&s->StatReads, r);
1590 s->Led.Asserted.s.fReading = s->Led.Actual.s.fReading = 1;
1591 rc = s->pDrvBlock->pfnRead(s->pDrvBlock, u64Sector * s->cbSector, pvBuf, cSectors * s->cbSector);
1592 s->Led.Actual.s.fReading = 0;
1593 STAM_PROFILE_ADV_STOP(&s->StatReads, r);
1594 Log4(("ataR3ReadSectors: rc=%Rrc cSectors=%#x u64Sector=%llu\n%.*Rhxd\n",
1595 rc, cSectors, u64Sector, cSectors * s->cbSector, pvBuf));
1596
1597 STAM_REL_COUNTER_ADD(&s->StatBytesRead, cSectors * s->cbSector);
1598
1599 if (RT_SUCCESS(rc))
1600 *pfRedo = false;
1601 else
1602 *pfRedo = ataR3IsRedoSetWarning(s, rc);
1603
1604 STAM_PROFILE_START(&pCtl->StatLockWait, a);
1605 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
1606 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
1607 return rc;
1608}
1609
1610
1611static int ataR3WriteSectors(ATADevState *s, uint64_t u64Sector,
1612 const void *pvBuf, uint32_t cSectors, bool *pfRedo)
1613{
1614 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
1615 int rc;
1616
1617 PDMCritSectLeave(&pCtl->lock);
1618
1619 STAM_PROFILE_ADV_START(&s->StatWrites, w);
1620 s->Led.Asserted.s.fWriting = s->Led.Actual.s.fWriting = 1;
1621# ifdef VBOX_INSTRUMENT_DMA_WRITES
1622 if (s->fDMA)
1623 STAM_PROFILE_ADV_START(&s->StatInstrVDWrites, vw);
1624# endif
1625 rc = s->pDrvBlock->pfnWrite(s->pDrvBlock, u64Sector * s->cbSector, pvBuf, cSectors * s->cbSector);
1626# ifdef VBOX_INSTRUMENT_DMA_WRITES
1627 if (s->fDMA)
1628 STAM_PROFILE_ADV_STOP(&s->StatInstrVDWrites, vw);
1629# endif
1630 s->Led.Actual.s.fWriting = 0;
1631 STAM_PROFILE_ADV_STOP(&s->StatWrites, w);
1632 Log4(("ataR3WriteSectors: rc=%Rrc cSectors=%#x u64Sector=%llu\n%.*Rhxd\n",
1633 rc, cSectors, u64Sector, cSectors * s->cbSector, pvBuf));
1634
1635 STAM_REL_COUNTER_ADD(&s->StatBytesWritten, cSectors * s->cbSector);
1636
1637 if (RT_SUCCESS(rc))
1638 *pfRedo = false;
1639 else
1640 *pfRedo = ataR3IsRedoSetWarning(s, rc);
1641
1642 STAM_PROFILE_START(&pCtl->StatLockWait, a);
1643 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
1644 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
1645 return rc;
1646}
1647
1648
1649static void ataR3ReadWriteSectorsBT(ATADevState *s)
1650{
1651 uint32_t cSectors;
1652
1653 cSectors = s->cbTotalTransfer / s->cbSector;
1654 if (cSectors > s->cSectorsPerIRQ)
1655 s->cbElementaryTransfer = s->cSectorsPerIRQ * s->cbSector;
1656 else
1657 s->cbElementaryTransfer = cSectors * s->cbSector;
1658 if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE)
1659 ataR3CmdOK(s, 0);
1660}
1661
1662
1663static bool ataR3ReadSectorsSS(ATADevState *s)
1664{
1665 int rc;
1666 uint32_t cSectors;
1667 uint64_t iLBA;
1668 bool fRedo;
1669
1670 cSectors = s->cbElementaryTransfer / s->cbSector;
1671 Assert(cSectors);
1672 iLBA = ataR3GetSector(s);
1673 Log(("%s: %d sectors at LBA %d\n", __FUNCTION__, cSectors, iLBA));
1674 rc = ataR3ReadSectors(s, iLBA, s->CTX_SUFF(pbIOBuffer), cSectors, &fRedo);
1675 if (RT_SUCCESS(rc))
1676 {
1677 ataR3SetSector(s, iLBA + cSectors);
1678 if (s->cbElementaryTransfer == s->cbTotalTransfer)
1679 s->iSourceSink = ATAFN_SS_NULL;
1680 ataR3CmdOK(s, ATA_STAT_SEEK);
1681 }
1682 else
1683 {
1684 if (fRedo)
1685 return fRedo;
1686 if (s->cErrors++ < MAX_LOG_REL_ERRORS)
1687 LogRel(("PIIX3 ATA: LUN#%d: disk read error (rc=%Rrc iSector=%#RX64 cSectors=%#RX32)\n",
1688 s->iLUN, rc, iLBA, cSectors));
1689
1690 /*
1691 * Check if we got interrupted. We don't need to set status variables
1692 * because the request was aborted.
1693 */
1694 if (rc != VERR_INTERRUPTED)
1695 ataR3CmdError(s, ID_ERR);
1696 }
1697 return false;
1698}
1699
1700
1701static bool ataR3WriteSectorsSS(ATADevState *s)
1702{
1703 int rc;
1704 uint32_t cSectors;
1705 uint64_t iLBA;
1706 bool fRedo;
1707
1708 cSectors = s->cbElementaryTransfer / s->cbSector;
1709 Assert(cSectors);
1710 iLBA = ataR3GetSector(s);
1711 Log(("%s: %d sectors at LBA %d\n", __FUNCTION__, cSectors, iLBA));
1712 rc = ataR3WriteSectors(s, iLBA, s->CTX_SUFF(pbIOBuffer), cSectors, &fRedo);
1713 if (RT_SUCCESS(rc))
1714 {
1715 ataR3SetSector(s, iLBA + cSectors);
1716 if (!s->cbTotalTransfer)
1717 s->iSourceSink = ATAFN_SS_NULL;
1718 ataR3CmdOK(s, ATA_STAT_SEEK);
1719 }
1720 else
1721 {
1722 if (fRedo)
1723 return fRedo;
1724 if (s->cErrors++ < MAX_LOG_REL_ERRORS)
1725 LogRel(("PIIX3 ATA: LUN#%d: disk write error (rc=%Rrc iSector=%#RX64 cSectors=%#RX32)\n",
1726 s->iLUN, rc, iLBA, cSectors));
1727
1728 /*
1729 * Check if we got interrupted. We don't need to set status variables
1730 * because the request was aborted.
1731 */
1732 if (rc != VERR_INTERRUPTED)
1733 ataR3CmdError(s, ID_ERR);
1734 }
1735 return false;
1736}
1737
1738
1739static void atapiR3CmdOK(ATADevState *s)
1740{
1741 s->uATARegError = 0;
1742 ataSetStatusValue(s, ATA_STAT_READY);
1743 s->uATARegNSector = (s->uATARegNSector & ~7)
1744 | ((s->uTxDir != PDMBLOCKTXDIR_TO_DEVICE) ? ATAPI_INT_REASON_IO : 0)
1745 | (!s->cbTotalTransfer ? ATAPI_INT_REASON_CD : 0);
1746 Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector));
1747
1748 memset(s->abATAPISense, '\0', sizeof(s->abATAPISense));
1749 s->abATAPISense[0] = 0x70 | (1 << 7);
1750 s->abATAPISense[7] = 10;
1751}
1752
1753
1754static void atapiR3CmdError(ATADevState *s, const uint8_t *pabATAPISense, size_t cbATAPISense)
1755{
1756 Log(("%s: sense=%#x (%s) asc=%#x ascq=%#x (%s)\n", __FUNCTION__, pabATAPISense[2] & 0x0f, SCSISenseText(pabATAPISense[2] & 0x0f),
1757 pabATAPISense[12], pabATAPISense[13], SCSISenseExtText(pabATAPISense[12], pabATAPISense[13])));
1758 s->uATARegError = pabATAPISense[2] << 4;
1759 ataSetStatusValue(s, ATA_STAT_READY | ATA_STAT_ERR);
1760 s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
1761 Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector));
1762 memset(s->abATAPISense, '\0', sizeof(s->abATAPISense));
1763 memcpy(s->abATAPISense, pabATAPISense, RT_MIN(cbATAPISense, sizeof(s->abATAPISense)));
1764 s->cbTotalTransfer = 0;
1765 s->cbElementaryTransfer = 0;
1766 s->cbAtapiPassthroughTransfer = 0;
1767 s->iIOBufferCur = 0;
1768 s->iIOBufferEnd = 0;
1769 s->uTxDir = PDMBLOCKTXDIR_NONE;
1770 s->iBeginTransfer = ATAFN_BT_NULL;
1771 s->iSourceSink = ATAFN_SS_NULL;
1772}
1773
1774
1775/** @todo deprecated function - doesn't provide enough info. Replace by direct
1776 * calls to atapiR3CmdError() with full data. */
1777static void atapiR3CmdErrorSimple(ATADevState *s, uint8_t uATAPISenseKey, uint8_t uATAPIASC)
1778{
1779 uint8_t abATAPISense[ATAPI_SENSE_SIZE];
1780 memset(abATAPISense, '\0', sizeof(abATAPISense));
1781 abATAPISense[0] = 0x70 | (1 << 7);
1782 abATAPISense[2] = uATAPISenseKey & 0x0f;
1783 abATAPISense[7] = 10;
1784 abATAPISense[12] = uATAPIASC;
1785 atapiR3CmdError(s, abATAPISense, sizeof(abATAPISense));
1786}
1787
1788
1789static void atapiR3CmdBT(ATADevState *s)
1790{
1791 s->fATAPITransfer = true;
1792 s->cbElementaryTransfer = s->cbTotalTransfer;
1793 s->cbAtapiPassthroughTransfer = s->cbTotalTransfer;
1794 s->cbPIOTransferLimit = s->uATARegLCyl | (s->uATARegHCyl << 8);
1795 if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE)
1796 atapiR3CmdOK(s);
1797}
1798
1799
1800static void atapiR3PassthroughCmdBT(ATADevState *s)
1801{
1802 /** @todo implement an algorithm for correctly determining the read and
1803 * write sector size without sending additional commands to the drive.
1804 * This should be doable by saving processing the configuration requests
1805 * and replies. */
1806# if 0
1807 if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE)
1808 {
1809 uint8_t cmd = s->aATAPICmd[0];
1810 if (cmd == SCSI_WRITE_10 || cmd == SCSI_WRITE_12 || cmd == SCSI_WRITE_AND_VERIFY_10)
1811 {
1812 uint8_t aModeSenseCmd[10];
1813 uint8_t aModeSenseResult[16];
1814 uint8_t uDummySense;
1815 uint32_t cbTransfer;
1816 int rc;
1817
1818 cbTransfer = sizeof(aModeSenseResult);
1819 aModeSenseCmd[0] = SCSI_MODE_SENSE_10;
1820 aModeSenseCmd[1] = 0x08; /* disable block descriptor = 1 */
1821 aModeSenseCmd[2] = (SCSI_PAGECONTROL_CURRENT << 6) | SCSI_MODEPAGE_WRITE_PARAMETER;
1822 aModeSenseCmd[3] = 0; /* subpage code */
1823 aModeSenseCmd[4] = 0; /* reserved */
1824 aModeSenseCmd[5] = 0; /* reserved */
1825 aModeSenseCmd[6] = 0; /* reserved */
1826 aModeSenseCmd[7] = cbTransfer >> 8;
1827 aModeSenseCmd[8] = cbTransfer & 0xff;
1828 aModeSenseCmd[9] = 0; /* control */
1829 rc = s->pDrvBlock->pfnSendCmd(s->pDrvBlock, aModeSenseCmd, PDMBLOCKTXDIR_FROM_DEVICE, aModeSenseResult, &cbTransfer, &uDummySense, 500);
1830 if (RT_FAILURE(rc))
1831 {
1832 atapiR3CmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_NONE);
1833 return;
1834 }
1835 /* Select sector size based on the current data block type. */
1836 switch (aModeSenseResult[12] & 0x0f)
1837 {
1838 case 0:
1839 s->cbATAPISector = 2352;
1840 break;
1841 case 1:
1842 s->cbATAPISector = 2368;
1843 break;
1844 case 2:
1845 case 3:
1846 s->cbATAPISector = 2448;
1847 break;
1848 case 8:
1849 case 10:
1850 s->cbATAPISector = 2048;
1851 break;
1852 case 9:
1853 s->cbATAPISector = 2336;
1854 break;
1855 case 11:
1856 s->cbATAPISector = 2056;
1857 break;
1858 case 12:
1859 s->cbATAPISector = 2324;
1860 break;
1861 case 13:
1862 s->cbATAPISector = 2332;
1863 break;
1864 default:
1865 s->cbATAPISector = 0;
1866 }
1867 Log2(("%s: sector size %d\n", __FUNCTION__, s->cbATAPISector));
1868 s->cbTotalTransfer *= s->cbATAPISector;
1869 if (s->cbTotalTransfer == 0)
1870 s->uTxDir = PDMBLOCKTXDIR_NONE;
1871 }
1872 }
1873# endif
1874 atapiR3CmdBT(s);
1875}
1876
1877static bool atapiR3ReadSS(ATADevState *s)
1878{
1879 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
1880 int rc = VINF_SUCCESS;
1881 uint32_t cbTransfer, cSectors;
1882
1883 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
1884 cbTransfer = RT_MIN(s->cbTotalTransfer, s->cbIOBuffer);
1885 cSectors = cbTransfer / s->cbATAPISector;
1886 Assert(cSectors * s->cbATAPISector <= cbTransfer);
1887 Log(("%s: %d sectors at LBA %d\n", __FUNCTION__, cSectors, s->iATAPILBA));
1888
1889 PDMCritSectLeave(&pCtl->lock);
1890
1891 STAM_PROFILE_ADV_START(&s->StatReads, r);
1892 s->Led.Asserted.s.fReading = s->Led.Actual.s.fReading = 1;
1893 switch (s->cbATAPISector)
1894 {
1895 case 2048:
1896 rc = s->pDrvBlock->pfnRead(s->pDrvBlock, (uint64_t)s->iATAPILBA * s->cbATAPISector, s->CTX_SUFF(pbIOBuffer), s->cbATAPISector * cSectors);
1897 break;
1898 case 2352:
1899 {
1900 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
1901
1902 for (uint32_t i = s->iATAPILBA; i < s->iATAPILBA + cSectors; i++)
1903 {
1904 /* Sync bytes, see 4.2.3.8 CD Main Channel Block Formats */
1905 *pbBuf++ = 0x00;
1906 memset(pbBuf, 0xff, 10);
1907 pbBuf += 10;
1908 *pbBuf++ = 0x00;
1909 /* MSF */
1910 ataLBA2MSF(pbBuf, i);
1911 pbBuf += 3;
1912 *pbBuf++ = 0x01; /* mode 1 data */
1913 /* data */
1914 rc = s->pDrvBlock->pfnRead(s->pDrvBlock, (uint64_t)i * 2048, pbBuf, 2048);
1915 if (RT_FAILURE(rc))
1916 break;
1917 pbBuf += 2048;
1918 /**
1919 * @todo: maybe compute ECC and parity, layout is:
1920 * 2072 4 EDC
1921 * 2076 172 P parity symbols
1922 * 2248 104 Q parity symbols
1923 */
1924 memset(pbBuf, 0, 280);
1925 pbBuf += 280;
1926 }
1927 break;
1928 }
1929 default:
1930 break;
1931 }
1932 s->Led.Actual.s.fReading = 0;
1933 STAM_PROFILE_ADV_STOP(&s->StatReads, r);
1934
1935 STAM_PROFILE_START(&pCtl->StatLockWait, a);
1936 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
1937 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
1938
1939 if (RT_SUCCESS(rc))
1940 {
1941 STAM_REL_COUNTER_ADD(&s->StatBytesRead, s->cbATAPISector * cSectors);
1942
1943 /* The initial buffer end value has been set up based on the total
1944 * transfer size. But the I/O buffer size limits what can actually be
1945 * done in one transfer, so set the actual value of the buffer end. */
1946 s->cbElementaryTransfer = cbTransfer;
1947 if (cbTransfer >= s->cbTotalTransfer)
1948 s->iSourceSink = ATAFN_SS_NULL;
1949 atapiR3CmdOK(s);
1950 s->iATAPILBA += cSectors;
1951 }
1952 else
1953 {
1954 if (s->cErrors++ < MAX_LOG_REL_ERRORS)
1955 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM read error, %d sectors at LBA %d\n", s->iLUN, cSectors, s->iATAPILBA));
1956
1957 /*
1958 * Check if we got interrupted. We don't need to set status variables
1959 * because the request was aborted.
1960 */
1961 if (rc != VERR_INTERRUPTED)
1962 atapiR3CmdErrorSimple(s, SCSI_SENSE_MEDIUM_ERROR, SCSI_ASC_READ_ERROR);
1963 }
1964 return false;
1965}
1966
1967/**
1968 * Sets the given media track type.
1969 */
1970static uint32_t ataR3MediumTypeSet(ATADevState *s, uint32_t MediaTrackType)
1971{
1972 return ASMAtomicXchgU32(&s->MediaTrackType, MediaTrackType);
1973}
1974
1975static bool atapiR3PassthroughSS(ATADevState *s)
1976{
1977 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
1978 int rc = VINF_SUCCESS;
1979 uint8_t abATAPISense[ATAPI_SENSE_SIZE];
1980 uint32_t cbTransfer;
1981 PSTAMPROFILEADV pProf = NULL;
1982
1983 cbTransfer = RT_MIN(s->cbAtapiPassthroughTransfer, s->cbIOBuffer);
1984
1985 if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE)
1986 Log3(("ATAPI PT data write (%d): %.*Rhxs\n", cbTransfer, cbTransfer, s->CTX_SUFF(pbIOBuffer)));
1987
1988 /* Simple heuristics: if there is at least one sector of data
1989 * to transfer, it's worth updating the LEDs. */
1990 if (cbTransfer >= 2048)
1991 {
1992 if (s->uTxDir != PDMBLOCKTXDIR_TO_DEVICE)
1993 {
1994 s->Led.Asserted.s.fReading = s->Led.Actual.s.fReading = 1;
1995 pProf = &s->StatReads;
1996 }
1997 else
1998 {
1999 s->Led.Asserted.s.fWriting = s->Led.Actual.s.fWriting = 1;
2000 pProf = &s->StatWrites;
2001 }
2002 }
2003
2004 PDMCritSectLeave(&pCtl->lock);
2005
2006# if defined(LOG_ENABLED)
2007 char szBuf[1024];
2008
2009 memset(szBuf, 0, sizeof(szBuf));
2010
2011 switch (s->aATAPICmd[0])
2012 {
2013 case SCSI_MODE_SELECT_10:
2014 {
2015 size_t cbBlkDescLength = ataBE2H_U16(&s->CTX_SUFF(pbIOBuffer)[6]);
2016
2017 SCSILogModePage(szBuf, sizeof(szBuf) - 1,
2018 s->CTX_SUFF(pbIOBuffer) + 8 + cbBlkDescLength,
2019 cbTransfer - 8 - cbBlkDescLength);
2020 break;
2021 }
2022 case SCSI_SEND_CUE_SHEET:
2023 {
2024 SCSILogCueSheet(szBuf, sizeof(szBuf) - 1,
2025 s->CTX_SUFF(pbIOBuffer), cbTransfer);
2026 break;
2027 }
2028 default:
2029 break;
2030 }
2031
2032 Log2(("%s\n", szBuf));
2033# endif
2034
2035 if (pProf) { STAM_PROFILE_ADV_START(pProf, b); }
2036 if ( cbTransfer > SCSI_MAX_BUFFER_SIZE
2037 || s->cbElementaryTransfer > s->cbIOBuffer)
2038 {
2039 /* Linux accepts commands with up to 100KB of data, but expects
2040 * us to handle commands with up to 128KB of data. The usual
2041 * imbalance of powers. */
2042 uint8_t aATAPICmd[ATAPI_PACKET_SIZE];
2043 uint32_t iATAPILBA, cSectors, cReqSectors, cbCurrTX;
2044 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2045 uint32_t cSectorsMax; /**< Maximum amount of sectors to read without exceeding the I/O buffer. */
2046
2047 Assert(s->cbATAPISector);
2048 cSectorsMax = cbTransfer / s->cbATAPISector;
2049 Assert(cSectorsMax * s->cbATAPISector <= s->cbIOBuffer);
2050
2051 switch (s->aATAPICmd[0])
2052 {
2053 case SCSI_READ_10:
2054 case SCSI_WRITE_10:
2055 case SCSI_WRITE_AND_VERIFY_10:
2056 iATAPILBA = ataBE2H_U32(s->aATAPICmd + 2);
2057 cSectors = ataBE2H_U16(s->aATAPICmd + 7);
2058 break;
2059 case SCSI_READ_12:
2060 case SCSI_WRITE_12:
2061 iATAPILBA = ataBE2H_U32(s->aATAPICmd + 2);
2062 cSectors = ataBE2H_U32(s->aATAPICmd + 6);
2063 break;
2064 case SCSI_READ_CD:
2065 iATAPILBA = ataBE2H_U32(s->aATAPICmd + 2);
2066 cSectors = ataBE2H_U24(s->aATAPICmd + 6);
2067 break;
2068 case SCSI_READ_CD_MSF:
2069 iATAPILBA = ataMSF2LBA(s->aATAPICmd + 3);
2070 cSectors = ataMSF2LBA(s->aATAPICmd + 6) - iATAPILBA;
2071 break;
2072 default:
2073 AssertMsgFailed(("Don't know how to split command %#04x\n", s->aATAPICmd[0]));
2074 if (s->cErrors++ < MAX_LOG_REL_ERRORS)
2075 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough split error\n", s->iLUN));
2076 atapiR3CmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
2077 {
2078 STAM_PROFILE_START(&pCtl->StatLockWait, a);
2079 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
2080 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
2081 }
2082 return false;
2083 }
2084 cSectorsMax = RT_MIN(cSectorsMax, cSectors);
2085 memcpy(aATAPICmd, s->aATAPICmd, ATAPI_PACKET_SIZE);
2086 cReqSectors = 0;
2087 for (uint32_t i = cSectorsMax; i > 0; i -= cReqSectors)
2088 {
2089 if (i * s->cbATAPISector > SCSI_MAX_BUFFER_SIZE)
2090 cReqSectors = SCSI_MAX_BUFFER_SIZE / s->cbATAPISector;
2091 else
2092 cReqSectors = i;
2093 cbCurrTX = s->cbATAPISector * cReqSectors;
2094 switch (s->aATAPICmd[0])
2095 {
2096 case SCSI_READ_10:
2097 case SCSI_WRITE_10:
2098 case SCSI_WRITE_AND_VERIFY_10:
2099 ataH2BE_U32(aATAPICmd + 2, iATAPILBA);
2100 ataH2BE_U16(aATAPICmd + 7, cReqSectors);
2101 break;
2102 case SCSI_READ_12:
2103 case SCSI_WRITE_12:
2104 ataH2BE_U32(aATAPICmd + 2, iATAPILBA);
2105 ataH2BE_U32(aATAPICmd + 6, cReqSectors);
2106 break;
2107 case SCSI_READ_CD:
2108 ataH2BE_U32(aATAPICmd + 2, iATAPILBA);
2109 ataH2BE_U24(aATAPICmd + 6, cReqSectors);
2110 break;
2111 case SCSI_READ_CD_MSF:
2112 ataLBA2MSF(aATAPICmd + 3, iATAPILBA);
2113 ataLBA2MSF(aATAPICmd + 6, iATAPILBA + cReqSectors);
2114 break;
2115 }
2116 rc = s->pDrvBlock->pfnSendCmd(s->pDrvBlock, aATAPICmd, (PDMBLOCKTXDIR)s->uTxDir, pbBuf, &cbCurrTX, abATAPISense, sizeof(abATAPISense), 30000 /**< @todo timeout */);
2117 if (rc != VINF_SUCCESS)
2118 break;
2119 iATAPILBA += cReqSectors;
2120 pbBuf += s->cbATAPISector * cReqSectors;
2121 }
2122
2123 if (RT_SUCCESS(rc))
2124 {
2125 /* Adjust ATAPI command for the next call. */
2126 switch (s->aATAPICmd[0])
2127 {
2128 case SCSI_READ_10:
2129 case SCSI_WRITE_10:
2130 case SCSI_WRITE_AND_VERIFY_10:
2131 ataH2BE_U32(s->aATAPICmd + 2, iATAPILBA);
2132 ataH2BE_U16(s->aATAPICmd + 7, cSectors - cSectorsMax);
2133 break;
2134 case SCSI_READ_12:
2135 case SCSI_WRITE_12:
2136 ataH2BE_U32(s->aATAPICmd + 2, iATAPILBA);
2137 ataH2BE_U32(s->aATAPICmd + 6, cSectors - cSectorsMax);
2138 break;
2139 case SCSI_READ_CD:
2140 ataH2BE_U32(s->aATAPICmd + 2, iATAPILBA);
2141 ataH2BE_U24(s->aATAPICmd + 6, cSectors - cSectorsMax);
2142 break;
2143 case SCSI_READ_CD_MSF:
2144 ataLBA2MSF(s->aATAPICmd + 3, iATAPILBA);
2145 ataLBA2MSF(s->aATAPICmd + 6, iATAPILBA + cSectors - cSectorsMax);
2146 break;
2147 default:
2148 AssertMsgFailed(("Don't know how to split command %#04x\n", s->aATAPICmd[0]));
2149 if (s->cErrors++ < MAX_LOG_REL_ERRORS)
2150 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough split error\n", s->iLUN));
2151 atapiR3CmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
2152 return false;
2153 }
2154 }
2155 }
2156 else
2157 rc = s->pDrvBlock->pfnSendCmd(s->pDrvBlock, s->aATAPICmd, (PDMBLOCKTXDIR)s->uTxDir, s->CTX_SUFF(pbIOBuffer), &cbTransfer, abATAPISense, sizeof(abATAPISense), 30000 /**< @todo timeout */);
2158 if (pProf) { STAM_PROFILE_ADV_STOP(pProf, b); }
2159
2160 STAM_PROFILE_START(&pCtl->StatLockWait, a);
2161 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
2162 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
2163
2164 /* Update the LEDs and the read/write statistics. */
2165 if (cbTransfer >= 2048)
2166 {
2167 if (s->uTxDir != PDMBLOCKTXDIR_TO_DEVICE)
2168 {
2169 s->Led.Actual.s.fReading = 0;
2170 STAM_REL_COUNTER_ADD(&s->StatBytesRead, cbTransfer);
2171 }
2172 else
2173 {
2174 s->Led.Actual.s.fWriting = 0;
2175 STAM_REL_COUNTER_ADD(&s->StatBytesWritten, cbTransfer);
2176 }
2177 }
2178
2179 if (RT_SUCCESS(rc))
2180 {
2181 /* Do post processing for certain commands. */
2182 switch (s->aATAPICmd[0])
2183 {
2184 case SCSI_SEND_CUE_SHEET:
2185 case SCSI_READ_TOC_PMA_ATIP:
2186 {
2187 if (!s->pTrackList)
2188 rc = ATAPIPassthroughTrackListCreateEmpty(&s->pTrackList);
2189
2190 if (RT_SUCCESS(rc))
2191 rc = ATAPIPassthroughTrackListUpdate(s->pTrackList, s->aATAPICmd, s->CTX_SUFF(pbIOBuffer));
2192
2193 if ( RT_FAILURE(rc)
2194 && s->cErrors++ < MAX_LOG_REL_ERRORS)
2195 LogRel(("ATA: Error (%Rrc) while updating the tracklist during %s, burning the disc might fail\n",
2196 rc, s->aATAPICmd[0] == SCSI_SEND_CUE_SHEET ? "SEND CUE SHEET" : "READ TOC/PMA/ATIP"));
2197 break;
2198 }
2199 case SCSI_SYNCHRONIZE_CACHE:
2200 {
2201 if (s->pTrackList)
2202 ATAPIPassthroughTrackListClear(s->pTrackList);
2203 break;
2204 }
2205 }
2206
2207 if (s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE)
2208 {
2209 Assert(cbTransfer <= s->cbAtapiPassthroughTransfer);
2210 /*
2211 * Reply with the same amount of data as the real drive
2212 * but only if the command wasn't split.
2213 */
2214# if 0 /// @todo This destroys commands where cbTotalTransfer > cbIOBuffer
2215 if (s->cbElementaryTransfer < s->cbIOBuffer)
2216 s->cbTotalTransfer = cbTransfer;
2217# endif
2218
2219 if ( s->aATAPICmd[0] == SCSI_INQUIRY
2220 && s->fOverwriteInquiry)
2221 {
2222 /* Make sure that the real drive cannot be identified.
2223 * Motivation: changing the VM configuration should be as
2224 * invisible as possible to the guest. */
2225 Log3(("ATAPI PT inquiry data before (%d): %.*Rhxs\n", cbTransfer, cbTransfer, s->CTX_SUFF(pbIOBuffer)));
2226 ataR3SCSIPadStr(s->CTX_SUFF(pbIOBuffer) + 8, "VBOX", 8);
2227 ataR3SCSIPadStr(s->CTX_SUFF(pbIOBuffer) + 16, "CD-ROM", 16);
2228 ataR3SCSIPadStr(s->CTX_SUFF(pbIOBuffer) + 32, "1.0", 4);
2229 }
2230
2231 if (cbTransfer)
2232 Log3(("ATAPI PT data read (%d): %.*Rhxs\n", cbTransfer, cbTransfer, s->CTX_SUFF(pbIOBuffer)));
2233 }
2234
2235 /* The initial buffer end value has been set up based on the total
2236 * transfer size. But the I/O buffer size limits what can actually be
2237 * done in one transfer, so set the actual value of the buffer end. */
2238 s->cbElementaryTransfer = cbTransfer;
2239 if (cbTransfer >= s->cbAtapiPassthroughTransfer)
2240 {
2241 s->iSourceSink = ATAFN_SS_NULL;
2242 atapiR3CmdOK(s);
2243 }
2244 }
2245 else
2246 {
2247 if (s->cErrors < MAX_LOG_REL_ERRORS)
2248 {
2249 uint8_t u8Cmd = s->aATAPICmd[0];
2250 do
2251 {
2252 /* don't log superfluous errors */
2253 if ( rc == VERR_DEV_IO_ERROR
2254 && ( u8Cmd == SCSI_TEST_UNIT_READY
2255 || u8Cmd == SCSI_READ_CAPACITY
2256 || u8Cmd == SCSI_READ_DVD_STRUCTURE
2257 || u8Cmd == SCSI_READ_TOC_PMA_ATIP))
2258 break;
2259 s->cErrors++;
2260 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough cmd=%#04x sense=%d ASC=%#02x ASCQ=%#02x %Rrc\n",
2261 s->iLUN, u8Cmd, abATAPISense[2] & 0x0f, abATAPISense[12], abATAPISense[13], rc));
2262 } while (0);
2263 }
2264 atapiR3CmdError(s, abATAPISense, sizeof(abATAPISense));
2265 }
2266 return false;
2267}
2268
2269/** @todo Revise ASAP. */
2270static bool atapiR3ReadDVDStructureSS(ATADevState *s)
2271{
2272 uint8_t *buf = s->CTX_SUFF(pbIOBuffer);
2273 int media = s->aATAPICmd[1];
2274 int format = s->aATAPICmd[7];
2275
2276 uint16_t max_len = ataBE2H_U16(&s->aATAPICmd[8]);
2277
2278 memset(buf, 0, max_len);
2279
2280 switch (format) {
2281 case 0x00:
2282 case 0x01:
2283 case 0x02:
2284 case 0x03:
2285 case 0x04:
2286 case 0x05:
2287 case 0x06:
2288 case 0x07:
2289 case 0x08:
2290 case 0x09:
2291 case 0x0a:
2292 case 0x0b:
2293 case 0x0c:
2294 case 0x0d:
2295 case 0x0e:
2296 case 0x0f:
2297 case 0x10:
2298 case 0x11:
2299 case 0x30:
2300 case 0x31:
2301 case 0xff:
2302 if (media == 0)
2303 {
2304 int uASC = SCSI_ASC_NONE;
2305
2306 switch (format)
2307 {
2308 case 0x0: /* Physical format information */
2309 {
2310 int layer = s->aATAPICmd[6];
2311 uint64_t total_sectors;
2312
2313 if (layer != 0)
2314 {
2315 uASC = -SCSI_ASC_INV_FIELD_IN_CMD_PACKET;
2316 break;
2317 }
2318
2319 total_sectors = s->cTotalSectors;
2320 total_sectors >>= 2;
2321 if (total_sectors == 0)
2322 {
2323 uASC = -SCSI_ASC_MEDIUM_NOT_PRESENT;
2324 break;
2325 }
2326
2327 buf[4] = 1; /* DVD-ROM, part version 1 */
2328 buf[5] = 0xf; /* 120mm disc, minimum rate unspecified */
2329 buf[6] = 1; /* one layer, read-only (per MMC-2 spec) */
2330 buf[7] = 0; /* default densities */
2331
2332 /* FIXME: 0x30000 per spec? */
2333 ataH2BE_U32(buf + 8, 0); /* start sector */
2334 ataH2BE_U32(buf + 12, total_sectors - 1); /* end sector */
2335 ataH2BE_U32(buf + 16, total_sectors - 1); /* l0 end sector */
2336
2337 /* Size of buffer, not including 2 byte size field */
2338 ataH2BE_U32(&buf[0], 2048 + 2);
2339
2340 /* 2k data + 4 byte header */
2341 uASC = (2048 + 4);
2342 break;
2343 }
2344 case 0x01: /* DVD copyright information */
2345 buf[4] = 0; /* no copyright data */
2346 buf[5] = 0; /* no region restrictions */
2347
2348 /* Size of buffer, not including 2 byte size field */
2349 ataH2BE_U16(buf, 4 + 2);
2350
2351 /* 4 byte header + 4 byte data */
2352 uASC = (4 + 4);
2353 break;
2354
2355 case 0x03: /* BCA information - invalid field for no BCA info */
2356 uASC = -SCSI_ASC_INV_FIELD_IN_CMD_PACKET;
2357 break;
2358
2359 case 0x04: /* DVD disc manufacturing information */
2360 /* Size of buffer, not including 2 byte size field */
2361 ataH2BE_U16(buf, 2048 + 2);
2362
2363 /* 2k data + 4 byte header */
2364 uASC = (2048 + 4);
2365 break;
2366 case 0xff:
2367 /*
2368 * This lists all the command capabilities above. Add new ones
2369 * in order and update the length and buffer return values.
2370 */
2371
2372 buf[4] = 0x00; /* Physical format */
2373 buf[5] = 0x40; /* Not writable, is readable */
2374 ataH2BE_U16((buf + 6), 2048 + 4);
2375
2376 buf[8] = 0x01; /* Copyright info */
2377 buf[9] = 0x40; /* Not writable, is readable */
2378 ataH2BE_U16((buf + 10), 4 + 4);
2379
2380 buf[12] = 0x03; /* BCA info */
2381 buf[13] = 0x40; /* Not writable, is readable */
2382 ataH2BE_U16((buf + 14), 188 + 4);
2383
2384 buf[16] = 0x04; /* Manufacturing info */
2385 buf[17] = 0x40; /* Not writable, is readable */
2386 ataH2BE_U16((buf + 18), 2048 + 4);
2387
2388 /* Size of buffer, not including 2 byte size field */
2389 ataH2BE_U16(buf, 16 + 2);
2390
2391 /* data written + 4 byte header */
2392 uASC = (16 + 4);
2393 break;
2394 default: /* TODO: formats beyond DVD-ROM requires */
2395 uASC = -SCSI_ASC_INV_FIELD_IN_CMD_PACKET;
2396 }
2397
2398 if (uASC < 0)
2399 {
2400 s->iSourceSink = ATAFN_SS_NULL;
2401 atapiR3CmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, -uASC);
2402 return false;
2403 }
2404 break;
2405 }
2406 /* TODO: BD support, fall through for now */
2407
2408 /* Generic disk structures */
2409 case 0x80: /* TODO: AACS volume identifier */
2410 case 0x81: /* TODO: AACS media serial number */
2411 case 0x82: /* TODO: AACS media identifier */
2412 case 0x83: /* TODO: AACS media key block */
2413 case 0x90: /* TODO: List of recognized format layers */
2414 case 0xc0: /* TODO: Write protection status */
2415 default:
2416 s->iSourceSink = ATAFN_SS_NULL;
2417 atapiR3CmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST,
2418 SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
2419 return false;
2420 }
2421
2422 s->iSourceSink = ATAFN_SS_NULL;
2423 atapiR3CmdOK(s);
2424 return false;
2425}
2426
2427static bool atapiR3ReadSectors(ATADevState *s, uint32_t iATAPILBA, uint32_t cSectors, uint32_t cbSector)
2428{
2429 Assert(cSectors > 0);
2430 s->iATAPILBA = iATAPILBA;
2431 s->cbATAPISector = cbSector;
2432 ataR3StartTransfer(s, cSectors * cbSector, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ, true);
2433 return false;
2434}
2435
2436
2437static bool atapiR3ReadCapacitySS(ATADevState *s)
2438{
2439 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2440
2441 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2442 Assert(s->cbElementaryTransfer <= 8);
2443 ataH2BE_U32(pbBuf, s->cTotalSectors - 1);
2444 ataH2BE_U32(pbBuf + 4, 2048);
2445 s->iSourceSink = ATAFN_SS_NULL;
2446 atapiR3CmdOK(s);
2447 return false;
2448}
2449
2450
2451static bool atapiR3ReadDiscInformationSS(ATADevState *s)
2452{
2453 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2454
2455 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2456 Assert(s->cbElementaryTransfer <= 34);
2457 memset(pbBuf, '\0', 34);
2458 ataH2BE_U16(pbBuf, 32);
2459 pbBuf[2] = (0 << 4) | (3 << 2) | (2 << 0); /* not erasable, complete session, complete disc */
2460 pbBuf[3] = 1; /* number of first track */
2461 pbBuf[4] = 1; /* number of sessions (LSB) */
2462 pbBuf[5] = 1; /* first track number in last session (LSB) */
2463 pbBuf[6] = 1; /* last track number in last session (LSB) */
2464 pbBuf[7] = (0 << 7) | (0 << 6) | (1 << 5) | (0 << 2) | (0 << 0); /* disc id not valid, disc bar code not valid, unrestricted use, not dirty, not RW medium */
2465 pbBuf[8] = 0; /* disc type = CD-ROM */
2466 pbBuf[9] = 0; /* number of sessions (MSB) */
2467 pbBuf[10] = 0; /* number of sessions (MSB) */
2468 pbBuf[11] = 0; /* number of sessions (MSB) */
2469 ataH2BE_U32(pbBuf + 16, 0x00ffffff); /* last session lead-in start time is not available */
2470 ataH2BE_U32(pbBuf + 20, 0x00ffffff); /* last possible start time for lead-out is not available */
2471 s->iSourceSink = ATAFN_SS_NULL;
2472 atapiR3CmdOK(s);
2473 return false;
2474}
2475
2476
2477static bool atapiR3ReadTrackInformationSS(ATADevState *s)
2478{
2479 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2480
2481 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2482 Assert(s->cbElementaryTransfer <= 36);
2483 /* Accept address/number type of 1 only, and only track 1 exists. */
2484 if ((s->aATAPICmd[1] & 0x03) != 1 || ataBE2H_U32(&s->aATAPICmd[2]) != 1)
2485 {
2486 atapiR3CmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
2487 return false;
2488 }
2489 memset(pbBuf, '\0', 36);
2490 ataH2BE_U16(pbBuf, 34);
2491 pbBuf[2] = 1; /* track number (LSB) */
2492 pbBuf[3] = 1; /* session number (LSB) */
2493 pbBuf[5] = (0 << 5) | (0 << 4) | (4 << 0); /* not damaged, primary copy, data track */
2494 pbBuf[6] = (0 << 7) | (0 << 6) | (0 << 5) | (0 << 6) | (1 << 0); /* not reserved track, not blank, not packet writing, not fixed packet, data mode 1 */
2495 pbBuf[7] = (0 << 1) | (0 << 0); /* last recorded address not valid, next recordable address not valid */
2496 ataH2BE_U32(pbBuf + 8, 0); /* track start address is 0 */
2497 ataH2BE_U32(pbBuf + 24, s->cTotalSectors); /* track size */
2498 pbBuf[32] = 0; /* track number (MSB) */
2499 pbBuf[33] = 0; /* session number (MSB) */
2500 s->iSourceSink = ATAFN_SS_NULL;
2501 atapiR3CmdOK(s);
2502 return false;
2503}
2504
2505static uint32_t atapiR3GetConfigurationFillFeatureListProfiles(ATADevState *s, uint8_t *pbBuf, size_t cbBuf)
2506{
2507 if (cbBuf < 3*4)
2508 return 0;
2509
2510 ataH2BE_U16(pbBuf, 0x0); /* feature 0: list of profiles supported */
2511 pbBuf[2] = (0 << 2) | (1 << 1) | (1 << 0); /* version 0, persistent, current */
2512 pbBuf[3] = 8; /* additional bytes for profiles */
2513 /* The MMC-3 spec says that DVD-ROM read capability should be reported
2514 * before CD-ROM read capability. */
2515 ataH2BE_U16(pbBuf + 4, 0x10); /* profile: read-only DVD */
2516 pbBuf[6] = (0 << 0); /* NOT current profile */
2517 ataH2BE_U16(pbBuf + 8, 0x08); /* profile: read only CD */
2518 pbBuf[10] = (1 << 0); /* current profile */
2519
2520 return 3*4; /* Header + 2 profiles entries */
2521}
2522
2523static uint32_t atapiR3GetConfigurationFillFeatureCore(ATADevState *s, uint8_t *pbBuf, size_t cbBuf)
2524{
2525 if (cbBuf < 12)
2526 return 0;
2527
2528 ataH2BE_U16(pbBuf, 0x1); /* feature 0001h: Core Feature */
2529 pbBuf[2] = (0x2 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
2530 pbBuf[3] = 8; /* Additional length */
2531 ataH2BE_U16(pbBuf + 4, 0x00000002); /* Physical interface ATAPI. */
2532 pbBuf[8] = RT_BIT(0); /* DBE */
2533 /* Rest is reserved. */
2534
2535 return 12;
2536}
2537
2538static uint32_t atapiR3GetConfigurationFillFeatureMorphing(ATADevState *s, uint8_t *pbBuf, size_t cbBuf)
2539{
2540 if (cbBuf < 8)
2541 return 0;
2542
2543 ataH2BE_U16(pbBuf, 0x2); /* feature 0002h: Morphing Feature */
2544 pbBuf[2] = (0x1 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
2545 pbBuf[3] = 4; /* Additional length */
2546 pbBuf[4] = RT_BIT(1) | 0x0; /* OCEvent | !ASYNC */
2547 /* Rest is reserved. */
2548
2549 return 8;
2550}
2551
2552static uint32_t atapiR3GetConfigurationFillFeatureRemovableMedium(ATADevState *s, uint8_t *pbBuf, size_t cbBuf)
2553{
2554 if (cbBuf < 8)
2555 return 0;
2556
2557 ataH2BE_U16(pbBuf, 0x3); /* feature 0003h: Removable Medium Feature */
2558 pbBuf[2] = (0x2 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
2559 pbBuf[3] = 4; /* Additional length */
2560 /* Tray type loading | Load | Eject | !Pvnt Jmpr | !DBML | Lock */
2561 pbBuf[4] = (0x2 << 5) | RT_BIT(4) | RT_BIT(3) | (0x0 << 2) | (0x0 << 1) | RT_BIT(0);
2562 /* Rest is reserved. */
2563
2564 return 8;
2565}
2566
2567static uint32_t atapiR3GetConfigurationFillFeatureRandomReadable (ATADevState *s, uint8_t *pbBuf, size_t cbBuf)
2568{
2569 if (cbBuf < 12)
2570 return 0;
2571
2572 ataH2BE_U16(pbBuf, 0x10); /* feature 0010h: Random Readable Feature */
2573 pbBuf[2] = (0x0 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
2574 pbBuf[3] = 8; /* Additional length */
2575 ataH2BE_U32(pbBuf + 4, 2048); /* Logical block size. */
2576 ataH2BE_U16(pbBuf + 8, 0x10); /* Blocking (0x10 for DVD, CD is not defined). */
2577 pbBuf[10] = 0; /* PP not present */
2578 /* Rest is reserved. */
2579
2580 return 12;
2581}
2582
2583static uint32_t atapiR3GetConfigurationFillFeatureCDRead(ATADevState *s, uint8_t *pbBuf, size_t cbBuf)
2584{
2585 if (cbBuf < 8)
2586 return 0;
2587
2588 ataH2BE_U16(pbBuf, 0x1e); /* feature 001Eh: CD Read Feature */
2589 pbBuf[2] = (0x2 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
2590 pbBuf[3] = 0; /* Additional length */
2591 pbBuf[4] = (0x0 << 7) | (0x0 << 1) | 0x0; /* !DAP | !C2-Flags | !CD-Text. */
2592 /* Rest is reserved. */
2593
2594 return 8;
2595}
2596
2597static uint32_t atapiR3GetConfigurationFillFeaturePowerManagement(ATADevState *s, uint8_t *pbBuf, size_t cbBuf)
2598{
2599 if (cbBuf < 4)
2600 return 0;
2601
2602 ataH2BE_U16(pbBuf, 0x100); /* feature 0100h: Power Management Feature */
2603 pbBuf[2] = (0x0 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
2604 pbBuf[3] = 0; /* Additional length */
2605
2606 return 4;
2607}
2608
2609static uint32_t atapiR3GetConfigurationFillFeatureTimeout(ATADevState *s, uint8_t *pbBuf, size_t cbBuf)
2610{
2611 if (cbBuf < 8)
2612 return 0;
2613
2614 ataH2BE_U16(pbBuf, 0x105); /* feature 0105h: Timeout Feature */
2615 pbBuf[2] = (0x0 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
2616 pbBuf[3] = 4; /* Additional length */
2617 pbBuf[4] = 0x0; /* !Group3 */
2618
2619 return 8;
2620}
2621
2622static bool atapiR3GetConfigurationSS(ATADevState *s)
2623{
2624 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2625 uint32_t cbBuf = s->cbIOBuffer;
2626 uint32_t cbCopied = 0;
2627 uint16_t u16Sfn = ataBE2H_U16(&s->aATAPICmd[2]);
2628
2629 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2630 Assert(s->cbElementaryTransfer <= 80);
2631 /* Accept valid request types only, and only starting feature 0. */
2632 if ((s->aATAPICmd[1] & 0x03) == 3 || u16Sfn != 0)
2633 {
2634 atapiR3CmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
2635 return false;
2636 }
2637 memset(pbBuf, '\0', cbBuf);
2638 /** @todo implement switching between CD-ROM and DVD-ROM profile (the only
2639 * way to differentiate them right now is based on the image size). */
2640 if (s->cTotalSectors)
2641 ataH2BE_U16(pbBuf + 6, 0x08); /* current profile: read-only CD */
2642 else
2643 ataH2BE_U16(pbBuf + 6, 0x00); /* current profile: none -> no media */
2644 cbBuf -= 8;
2645 pbBuf += 8;
2646
2647 cbCopied = atapiR3GetConfigurationFillFeatureListProfiles(s, pbBuf, cbBuf);
2648 cbBuf -= cbCopied;
2649 pbBuf += cbCopied;
2650
2651 cbCopied = atapiR3GetConfigurationFillFeatureCore(s, pbBuf, cbBuf);
2652 cbBuf -= cbCopied;
2653 pbBuf += cbCopied;
2654
2655 cbCopied = atapiR3GetConfigurationFillFeatureMorphing(s, pbBuf, cbBuf);
2656 cbBuf -= cbCopied;
2657 pbBuf += cbCopied;
2658
2659 cbCopied = atapiR3GetConfigurationFillFeatureRemovableMedium(s, pbBuf, cbBuf);
2660 cbBuf -= cbCopied;
2661 pbBuf += cbCopied;
2662
2663 cbCopied = atapiR3GetConfigurationFillFeatureRandomReadable (s, pbBuf, cbBuf);
2664 cbBuf -= cbCopied;
2665 pbBuf += cbCopied;
2666
2667 cbCopied = atapiR3GetConfigurationFillFeatureCDRead(s, pbBuf, cbBuf);
2668 cbBuf -= cbCopied;
2669 pbBuf += cbCopied;
2670
2671 cbCopied = atapiR3GetConfigurationFillFeaturePowerManagement(s, pbBuf, cbBuf);
2672 cbBuf -= cbCopied;
2673 pbBuf += cbCopied;
2674
2675 cbCopied = atapiR3GetConfigurationFillFeatureTimeout(s, pbBuf, cbBuf);
2676 cbBuf -= cbCopied;
2677 pbBuf += cbCopied;
2678
2679 /* Set data length now - the field is not included in the final length. */
2680 ataH2BE_U32(s->CTX_SUFF(pbIOBuffer), s->cbIOBuffer - cbBuf - 4);
2681
2682 /* Other profiles we might want to add in the future: 0x40 (BD-ROM) and 0x50 (HDDVD-ROM) */
2683 s->iSourceSink = ATAFN_SS_NULL;
2684 atapiR3CmdOK(s);
2685 return false;
2686}
2687
2688
2689static bool atapiR3GetEventStatusNotificationSS(ATADevState *s)
2690{
2691 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2692
2693 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2694 Assert(s->cbElementaryTransfer <= 8);
2695
2696 if (!(s->aATAPICmd[1] & 1))
2697 {
2698 /* no asynchronous operation supported */
2699 atapiR3CmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
2700 return false;
2701 }
2702
2703 uint32_t OldStatus, NewStatus;
2704 do
2705 {
2706 OldStatus = ASMAtomicReadU32(&s->MediaEventStatus);
2707 NewStatus = ATA_EVENT_STATUS_UNCHANGED;
2708 switch (OldStatus)
2709 {
2710 case ATA_EVENT_STATUS_MEDIA_NEW:
2711 /* mount */
2712 ataH2BE_U16(pbBuf + 0, 6);
2713 pbBuf[2] = 0x04; /* media */
2714 pbBuf[3] = 0x5e; /* supported = busy|media|external|power|operational */
2715 pbBuf[4] = 0x02; /* new medium */
2716 pbBuf[5] = 0x02; /* medium present / door closed */
2717 pbBuf[6] = 0x00;
2718 pbBuf[7] = 0x00;
2719 break;
2720
2721 case ATA_EVENT_STATUS_MEDIA_CHANGED:
2722 case ATA_EVENT_STATUS_MEDIA_REMOVED:
2723 /* umount */
2724 ataH2BE_U16(pbBuf + 0, 6);
2725 pbBuf[2] = 0x04; /* media */
2726 pbBuf[3] = 0x5e; /* supported = busy|media|external|power|operational */
2727 pbBuf[4] = 0x03; /* media removal */
2728 pbBuf[5] = 0x00; /* medium absent / door closed */
2729 pbBuf[6] = 0x00;
2730 pbBuf[7] = 0x00;
2731 if (OldStatus == ATA_EVENT_STATUS_MEDIA_CHANGED)
2732 NewStatus = ATA_EVENT_STATUS_MEDIA_NEW;
2733 break;
2734
2735 case ATA_EVENT_STATUS_MEDIA_EJECT_REQUESTED: /* currently unused */
2736 ataH2BE_U16(pbBuf + 0, 6);
2737 pbBuf[2] = 0x04; /* media */
2738 pbBuf[3] = 0x5e; /* supported = busy|media|external|power|operational */
2739 pbBuf[4] = 0x01; /* eject requested (eject button pressed) */
2740 pbBuf[5] = 0x02; /* medium present / door closed */
2741 pbBuf[6] = 0x00;
2742 pbBuf[7] = 0x00;
2743 break;
2744
2745 case ATA_EVENT_STATUS_UNCHANGED:
2746 default:
2747 ataH2BE_U16(pbBuf + 0, 6);
2748 pbBuf[2] = 0x01; /* operational change request / notification */
2749 pbBuf[3] = 0x5e; /* supported = busy|media|external|power|operational */
2750 pbBuf[4] = 0x00;
2751 pbBuf[5] = 0x00;
2752 pbBuf[6] = 0x00;
2753 pbBuf[7] = 0x00;
2754 break;
2755 }
2756 } while (!ASMAtomicCmpXchgU32(&s->MediaEventStatus, NewStatus, OldStatus));
2757
2758 s->iSourceSink = ATAFN_SS_NULL;
2759 atapiR3CmdOK(s);
2760 return false;
2761}
2762
2763
2764static bool atapiR3InquirySS(ATADevState *s)
2765{
2766 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2767
2768 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2769 Assert(s->cbElementaryTransfer <= 36);
2770 pbBuf[0] = 0x05; /* CD-ROM */
2771 pbBuf[1] = 0x80; /* removable */
2772# if 1/*ndef VBOX*/ /** @todo implement MESN + AENC. (async notification on removal and stuff.) */
2773 pbBuf[2] = 0x00; /* ISO */
2774 pbBuf[3] = 0x21; /* ATAPI-2 (XXX: put ATAPI-4 ?) */
2775# else
2776 pbBuf[2] = 0x00; /* ISO */
2777 pbBuf[3] = 0x91; /* format 1, MESN=1, AENC=9 ??? */
2778# endif
2779 pbBuf[4] = 31; /* additional length */
2780 pbBuf[5] = 0; /* reserved */
2781 pbBuf[6] = 0; /* reserved */
2782 pbBuf[7] = 0; /* reserved */
2783 ataR3SCSIPadStr(pbBuf + 8, s->szInquiryVendorId, 8);
2784 ataR3SCSIPadStr(pbBuf + 16, s->szInquiryProductId, 16);
2785 ataR3SCSIPadStr(pbBuf + 32, s->szInquiryRevision, 4);
2786 s->iSourceSink = ATAFN_SS_NULL;
2787 atapiR3CmdOK(s);
2788 return false;
2789}
2790
2791
2792static bool atapiR3ModeSenseErrorRecoverySS(ATADevState *s)
2793{
2794 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2795
2796 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2797 Assert(s->cbElementaryTransfer <= 16);
2798 ataH2BE_U16(&pbBuf[0], 16 + 6);
2799 pbBuf[2] = (uint8_t)s->MediaTrackType;
2800 pbBuf[3] = 0;
2801 pbBuf[4] = 0;
2802 pbBuf[5] = 0;
2803 pbBuf[6] = 0;
2804 pbBuf[7] = 0;
2805
2806 pbBuf[8] = 0x01;
2807 pbBuf[9] = 0x06;
2808 pbBuf[10] = 0x00; /* Maximum error recovery */
2809 pbBuf[11] = 0x05; /* 5 retries */
2810 pbBuf[12] = 0x00;
2811 pbBuf[13] = 0x00;
2812 pbBuf[14] = 0x00;
2813 pbBuf[15] = 0x00;
2814 s->iSourceSink = ATAFN_SS_NULL;
2815 atapiR3CmdOK(s);
2816 return false;
2817}
2818
2819
2820static bool atapiR3ModeSenseCDStatusSS(ATADevState *s)
2821{
2822 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2823
2824 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2825 Assert(s->cbElementaryTransfer <= 40);
2826 ataH2BE_U16(&pbBuf[0], 38);
2827 pbBuf[2] = (uint8_t)s->MediaTrackType;
2828 pbBuf[3] = 0;
2829 pbBuf[4] = 0;
2830 pbBuf[5] = 0;
2831 pbBuf[6] = 0;
2832 pbBuf[7] = 0;
2833
2834 pbBuf[8] = 0x2a;
2835 pbBuf[9] = 30; /* page length */
2836 pbBuf[10] = 0x08; /* DVD-ROM read support */
2837 pbBuf[11] = 0x00; /* no write support */
2838 /* The following claims we support audio play. This is obviously false,
2839 * but the Linux generic CDROM support makes many features depend on this
2840 * capability. If it's not set, this causes many things to be disabled. */
2841 pbBuf[12] = 0x71; /* multisession support, mode 2 form 1/2 support, audio play */
2842 pbBuf[13] = 0x00; /* no subchannel reads supported */
2843 pbBuf[14] = (1 << 0) | (1 << 3) | (1 << 5); /* lock supported, eject supported, tray type loading mechanism */
2844 if (s->pDrvMount->pfnIsLocked(s->pDrvMount))
2845 pbBuf[14] |= 1 << 1; /* report lock state */
2846 pbBuf[15] = 0; /* no subchannel reads supported, no separate audio volume control, no changer etc. */
2847 ataH2BE_U16(&pbBuf[16], 5632); /* (obsolete) claim 32x speed support */
2848 ataH2BE_U16(&pbBuf[18], 2); /* number of audio volume levels */
2849 ataH2BE_U16(&pbBuf[20], s->cbIOBuffer / _1K); /* buffer size supported in Kbyte */
2850 ataH2BE_U16(&pbBuf[22], 5632); /* (obsolete) current read speed 32x */
2851 pbBuf[24] = 0; /* reserved */
2852 pbBuf[25] = 0; /* reserved for digital audio (see idx 15) */
2853 ataH2BE_U16(&pbBuf[26], 0); /* (obsolete) maximum write speed */
2854 ataH2BE_U16(&pbBuf[28], 0); /* (obsolete) current write speed */
2855 ataH2BE_U16(&pbBuf[30], 0); /* copy management revision supported 0=no CSS */
2856 pbBuf[32] = 0; /* reserved */
2857 pbBuf[33] = 0; /* reserved */
2858 pbBuf[34] = 0; /* reserved */
2859 pbBuf[35] = 1; /* rotation control CAV */
2860 ataH2BE_U16(&pbBuf[36], 0); /* current write speed */
2861 ataH2BE_U16(&pbBuf[38], 0); /* number of write speed performance descriptors */
2862 s->iSourceSink = ATAFN_SS_NULL;
2863 atapiR3CmdOK(s);
2864 return false;
2865}
2866
2867
2868static bool atapiR3RequestSenseSS(ATADevState *s)
2869{
2870 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2871
2872 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2873 memset(pbBuf, '\0', s->cbElementaryTransfer);
2874 memcpy(pbBuf, s->abATAPISense, RT_MIN(s->cbElementaryTransfer, sizeof(s->abATAPISense)));
2875 s->iSourceSink = ATAFN_SS_NULL;
2876 atapiR3CmdOK(s);
2877 return false;
2878}
2879
2880
2881static bool atapiR3MechanismStatusSS(ATADevState *s)
2882{
2883 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2884
2885 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2886 Assert(s->cbElementaryTransfer <= 8);
2887 ataH2BE_U16(pbBuf, 0);
2888 /* no current LBA */
2889 pbBuf[2] = 0;
2890 pbBuf[3] = 0;
2891 pbBuf[4] = 0;
2892 pbBuf[5] = 1;
2893 ataH2BE_U16(pbBuf + 6, 0);
2894 s->iSourceSink = ATAFN_SS_NULL;
2895 atapiR3CmdOK(s);
2896 return false;
2897}
2898
2899
2900static bool atapiR3ReadTOCNormalSS(ATADevState *s)
2901{
2902 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer), *q, iStartTrack;
2903 bool fMSF;
2904 uint32_t cbSize;
2905
2906 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2907 fMSF = (s->aATAPICmd[1] >> 1) & 1;
2908 iStartTrack = s->aATAPICmd[6];
2909 if (iStartTrack > 1 && iStartTrack != 0xaa)
2910 {
2911 atapiR3CmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
2912 return false;
2913 }
2914 q = pbBuf + 2;
2915 *q++ = 1; /* first session */
2916 *q++ = 1; /* last session */
2917 if (iStartTrack <= 1)
2918 {
2919 *q++ = 0; /* reserved */
2920 *q++ = 0x14; /* ADR, control */
2921 *q++ = 1; /* track number */
2922 *q++ = 0; /* reserved */
2923 if (fMSF)
2924 {
2925 *q++ = 0; /* reserved */
2926 ataLBA2MSF(q, 0);
2927 q += 3;
2928 }
2929 else
2930 {
2931 /* sector 0 */
2932 ataH2BE_U32(q, 0);
2933 q += 4;
2934 }
2935 }
2936 /* lead out track */
2937 *q++ = 0; /* reserved */
2938 *q++ = 0x14; /* ADR, control */
2939 *q++ = 0xaa; /* track number */
2940 *q++ = 0; /* reserved */
2941 if (fMSF)
2942 {
2943 *q++ = 0; /* reserved */
2944 ataLBA2MSF(q, s->cTotalSectors);
2945 q += 3;
2946 }
2947 else
2948 {
2949 ataH2BE_U32(q, s->cTotalSectors);
2950 q += 4;
2951 }
2952 cbSize = q - pbBuf;
2953 ataH2BE_U16(pbBuf, cbSize - 2);
2954 if (cbSize < s->cbTotalTransfer)
2955 s->cbTotalTransfer = cbSize;
2956 s->iSourceSink = ATAFN_SS_NULL;
2957 atapiR3CmdOK(s);
2958 return false;
2959}
2960
2961
2962static bool atapiR3ReadTOCMultiSS(ATADevState *s)
2963{
2964 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2965 bool fMSF;
2966
2967 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2968 Assert(s->cbElementaryTransfer <= 12);
2969 fMSF = (s->aATAPICmd[1] >> 1) & 1;
2970 /* multi session: only a single session defined */
2971/** @todo double-check this stuff against what a real drive says for a CD-ROM (not a CD-R) with only a single data session. Maybe solve the problem with "cdrdao read-toc" not being able to figure out whether numbers are in BCD or hex. */
2972 memset(pbBuf, 0, 12);
2973 pbBuf[1] = 0x0a;
2974 pbBuf[2] = 0x01;
2975 pbBuf[3] = 0x01;
2976 pbBuf[5] = 0x14; /* ADR, control */
2977 pbBuf[6] = 1; /* first track in last complete session */
2978 if (fMSF)
2979 {
2980 pbBuf[8] = 0; /* reserved */
2981 ataLBA2MSF(&pbBuf[9], 0);
2982 }
2983 else
2984 {
2985 /* sector 0 */
2986 ataH2BE_U32(pbBuf + 8, 0);
2987 }
2988 s->iSourceSink = ATAFN_SS_NULL;
2989 atapiR3CmdOK(s);
2990 return false;
2991}
2992
2993
2994static bool atapiR3ReadTOCRawSS(ATADevState *s)
2995{
2996 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer), *q, iStartTrack;
2997 bool fMSF;
2998 uint32_t cbSize;
2999
3000 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
3001 fMSF = (s->aATAPICmd[1] >> 1) & 1;
3002 iStartTrack = s->aATAPICmd[6];
3003
3004 q = pbBuf + 2;
3005 *q++ = 1; /* first session */
3006 *q++ = 1; /* last session */
3007
3008 *q++ = 1; /* session number */
3009 *q++ = 0x14; /* data track */
3010 *q++ = 0; /* track number */
3011 *q++ = 0xa0; /* first track in program area */
3012 *q++ = 0; /* min */
3013 *q++ = 0; /* sec */
3014 *q++ = 0; /* frame */
3015 *q++ = 0;
3016 *q++ = 1; /* first track */
3017 *q++ = 0x00; /* disk type CD-DA or CD data */
3018 *q++ = 0;
3019
3020 *q++ = 1; /* session number */
3021 *q++ = 0x14; /* data track */
3022 *q++ = 0; /* track number */
3023 *q++ = 0xa1; /* last track in program area */
3024 *q++ = 0; /* min */
3025 *q++ = 0; /* sec */
3026 *q++ = 0; /* frame */
3027 *q++ = 0;
3028 *q++ = 1; /* last track */
3029 *q++ = 0;
3030 *q++ = 0;
3031
3032 *q++ = 1; /* session number */
3033 *q++ = 0x14; /* data track */
3034 *q++ = 0; /* track number */
3035 *q++ = 0xa2; /* lead-out */
3036 *q++ = 0; /* min */
3037 *q++ = 0; /* sec */
3038 *q++ = 0; /* frame */
3039 if (fMSF)
3040 {
3041 *q++ = 0; /* reserved */
3042 ataLBA2MSF(q, s->cTotalSectors);
3043 q += 3;
3044 }
3045 else
3046 {
3047 ataH2BE_U32(q, s->cTotalSectors);
3048 q += 4;
3049 }
3050
3051 *q++ = 1; /* session number */
3052 *q++ = 0x14; /* ADR, control */
3053 *q++ = 0; /* track number */
3054 *q++ = 1; /* point */
3055 *q++ = 0; /* min */
3056 *q++ = 0; /* sec */
3057 *q++ = 0; /* frame */
3058 if (fMSF)
3059 {
3060 *q++ = 0; /* reserved */
3061 ataLBA2MSF(q, 0);
3062 q += 3;
3063 }
3064 else
3065 {
3066 /* sector 0 */
3067 ataH2BE_U32(q, 0);
3068 q += 4;
3069 }
3070
3071 cbSize = q - pbBuf;
3072 ataH2BE_U16(pbBuf, cbSize - 2);
3073 if (cbSize < s->cbTotalTransfer)
3074 s->cbTotalTransfer = cbSize;
3075 s->iSourceSink = ATAFN_SS_NULL;
3076 atapiR3CmdOK(s);
3077 return false;
3078}
3079
3080
3081static void atapiR3ParseCmdVirtualATAPI(ATADevState *s)
3082{
3083 const uint8_t *pbPacket;
3084 uint8_t *pbBuf;
3085 uint32_t cbMax;
3086
3087 pbPacket = s->aATAPICmd;
3088 pbBuf = s->CTX_SUFF(pbIOBuffer);
3089 switch (pbPacket[0])
3090 {
3091 case SCSI_TEST_UNIT_READY:
3092 if (s->cNotifiedMediaChange > 0)
3093 {
3094 if (s->cNotifiedMediaChange-- > 2)
3095 atapiR3CmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3096 else
3097 atapiR3CmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3098 }
3099 else if (s->pDrvMount->pfnIsMounted(s->pDrvMount))
3100 atapiR3CmdOK(s);
3101 else
3102 atapiR3CmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3103 break;
3104 case SCSI_GET_EVENT_STATUS_NOTIFICATION:
3105 cbMax = ataBE2H_U16(pbPacket + 7);
3106 ataR3StartTransfer(s, RT_MIN(cbMax, 8), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION, true);
3107 break;
3108 case SCSI_MODE_SENSE_10:
3109 {
3110 uint8_t uPageControl, uPageCode;
3111 cbMax = ataBE2H_U16(pbPacket + 7);
3112 uPageControl = pbPacket[2] >> 6;
3113 uPageCode = pbPacket[2] & 0x3f;
3114 switch (uPageControl)
3115 {
3116 case SCSI_PAGECONTROL_CURRENT:
3117 switch (uPageCode)
3118 {
3119 case SCSI_MODEPAGE_ERROR_RECOVERY:
3120 ataR3StartTransfer(s, RT_MIN(cbMax, 16), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MODE_SENSE_ERROR_RECOVERY, true);
3121 break;
3122 case SCSI_MODEPAGE_CD_STATUS:
3123 ataR3StartTransfer(s, RT_MIN(cbMax, 40), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MODE_SENSE_CD_STATUS, true);
3124 break;
3125 default:
3126 goto error_cmd;
3127 }
3128 break;
3129 case SCSI_PAGECONTROL_CHANGEABLE:
3130 goto error_cmd;
3131 case SCSI_PAGECONTROL_DEFAULT:
3132 goto error_cmd;
3133 default:
3134 case SCSI_PAGECONTROL_SAVED:
3135 atapiR3CmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_SAVING_PARAMETERS_NOT_SUPPORTED);
3136 break;
3137 }
3138 break;
3139 }
3140 case SCSI_REQUEST_SENSE:
3141 cbMax = pbPacket[4];
3142 ataR3StartTransfer(s, RT_MIN(cbMax, 18), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_REQUEST_SENSE, true);
3143 break;
3144 case SCSI_PREVENT_ALLOW_MEDIUM_REMOVAL:
3145 if (s->pDrvMount->pfnIsMounted(s->pDrvMount))
3146 {
3147 if (pbPacket[4] & 1)
3148 s->pDrvMount->pfnLock(s->pDrvMount);
3149 else
3150 s->pDrvMount->pfnUnlock(s->pDrvMount);
3151 atapiR3CmdOK(s);
3152 }
3153 else
3154 atapiR3CmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3155 break;
3156 case SCSI_READ_10:
3157 case SCSI_READ_12:
3158 {
3159 uint32_t cSectors, iATAPILBA;
3160
3161 if (s->cNotifiedMediaChange > 0)
3162 {
3163 s->cNotifiedMediaChange-- ;
3164 atapiR3CmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3165 break;
3166 }
3167 else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
3168 {
3169 atapiR3CmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3170 break;
3171 }
3172 if (pbPacket[0] == SCSI_READ_10)
3173 cSectors = ataBE2H_U16(pbPacket + 7);
3174 else
3175 cSectors = ataBE2H_U32(pbPacket + 6);
3176 iATAPILBA = ataBE2H_U32(pbPacket + 2);
3177 if (cSectors == 0)
3178 {
3179 atapiR3CmdOK(s);
3180 break;
3181 }
3182 if ((uint64_t)iATAPILBA + cSectors > s->cTotalSectors)
3183 {
3184 /* Rate limited logging, one log line per second. For
3185 * guests that insist on reading from places outside the
3186 * valid area this often generates too many release log
3187 * entries otherwise. */
3188 static uint64_t uLastLogTS = 0;
3189 if (RTTimeMilliTS() >= uLastLogTS + 1000)
3190 {
3191 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM block number %Ld invalid (READ)\n", s->iLUN, (uint64_t)iATAPILBA + cSectors));
3192 uLastLogTS = RTTimeMilliTS();
3193 }
3194 atapiR3CmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
3195 break;
3196 }
3197 atapiR3ReadSectors(s, iATAPILBA, cSectors, 2048);
3198 break;
3199 }
3200 case SCSI_READ_CD:
3201 {
3202 uint32_t cSectors, iATAPILBA;
3203
3204 if (s->cNotifiedMediaChange > 0)
3205 {
3206 s->cNotifiedMediaChange-- ;
3207 atapiR3CmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3208 break;
3209 }
3210 else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
3211 {
3212 atapiR3CmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3213 break;
3214 }
3215 cSectors = (pbPacket[6] << 16) | (pbPacket[7] << 8) | pbPacket[8];
3216 iATAPILBA = ataBE2H_U32(pbPacket + 2);
3217 if (cSectors == 0)
3218 {
3219 atapiR3CmdOK(s);
3220 break;
3221 }
3222 if ((uint64_t)iATAPILBA + cSectors > s->cTotalSectors)
3223 {
3224 /* Rate limited logging, one log line per second. For
3225 * guests that insist on reading from places outside the
3226 * valid area this often generates too many release log
3227 * entries otherwise. */
3228 static uint64_t uLastLogTS = 0;
3229 if (RTTimeMilliTS() >= uLastLogTS + 1000)
3230 {
3231 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM block number %Ld invalid (READ CD)\n", s->iLUN, (uint64_t)iATAPILBA + cSectors));
3232 uLastLogTS = RTTimeMilliTS();
3233 }
3234 atapiR3CmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
3235 break;
3236 }
3237 switch (pbPacket[9] & 0xf8)
3238 {
3239 case 0x00:
3240 /* nothing */
3241 atapiR3CmdOK(s);
3242 break;
3243 case 0x10:
3244 /* normal read */
3245 atapiR3ReadSectors(s, iATAPILBA, cSectors, 2048);
3246 break;
3247 case 0xf8:
3248 /* read all data */
3249 atapiR3ReadSectors(s, iATAPILBA, cSectors, 2352);
3250 break;
3251 default:
3252 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM sector format not supported (%#x)\n", s->iLUN, pbPacket[9] & 0xf8));
3253 atapiR3CmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3254 break;
3255 }
3256 break;
3257 }
3258 case SCSI_SEEK_10:
3259 {
3260 uint32_t iATAPILBA;
3261 if (s->cNotifiedMediaChange > 0)
3262 {
3263 s->cNotifiedMediaChange-- ;
3264 atapiR3CmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3265 break;
3266 }
3267 else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
3268 {
3269 atapiR3CmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3270 break;
3271 }
3272 iATAPILBA = ataBE2H_U32(pbPacket + 2);
3273 if (iATAPILBA > s->cTotalSectors)
3274 {
3275 /* Rate limited logging, one log line per second. For
3276 * guests that insist on seeking to places outside the
3277 * valid area this often generates too many release log
3278 * entries otherwise. */
3279 static uint64_t uLastLogTS = 0;
3280 if (RTTimeMilliTS() >= uLastLogTS + 1000)
3281 {
3282 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM block number %Ld invalid (SEEK)\n", s->iLUN, (uint64_t)iATAPILBA));
3283 uLastLogTS = RTTimeMilliTS();
3284 }
3285 atapiR3CmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
3286 break;
3287 }
3288 atapiR3CmdOK(s);
3289 ataSetStatus(s, ATA_STAT_SEEK); /* Linux expects this. */
3290 break;
3291 }
3292 case SCSI_START_STOP_UNIT:
3293 {
3294 int rc = VINF_SUCCESS;
3295 switch (pbPacket[4] & 3)
3296 {
3297 case 0: /* 00 - Stop motor */
3298 case 1: /* 01 - Start motor */
3299 break;
3300 case 2: /* 10 - Eject media */
3301 {
3302 /* This must be done from EMT. */
3303 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
3304 PPDMDEVINS pDevIns = ATADEVSTATE_2_DEVINS(s);
3305 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
3306
3307 PDMCritSectLeave(&pCtl->lock);
3308 rc = VMR3ReqPriorityCallWait(PDMDevHlpGetVM(pDevIns), VMCPUID_ANY,
3309 (PFNRT)s->pDrvMount->pfnUnmount, 3,
3310 s->pDrvMount, false /*=fForce*/, true /*=fEject*/);
3311 Assert(RT_SUCCESS(rc) || rc == VERR_PDM_MEDIA_LOCKED || rc == VERR_PDM_MEDIA_NOT_MOUNTED);
3312 if (RT_SUCCESS(rc) && pThis->pMediaNotify)
3313 {
3314 rc = VMR3ReqCallNoWait(PDMDevHlpGetVM(pDevIns), VMCPUID_ANY,
3315 (PFNRT)pThis->pMediaNotify->pfnEjected, 2,
3316 pThis->pMediaNotify, s->iLUN);
3317 AssertRC(rc);
3318 }
3319 {
3320 STAM_PROFILE_START(&pCtl->StatLockWait, a);
3321 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
3322 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
3323 }
3324 break;
3325 }
3326 case 3: /* 11 - Load media */
3327 /** @todo rc = s->pDrvMount->pfnLoadMedia(s->pDrvMount) */
3328 break;
3329 }
3330 if (RT_SUCCESS(rc))
3331 atapiR3CmdOK(s);
3332 else
3333 atapiR3CmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIA_LOAD_OR_EJECT_FAILED);
3334 break;
3335 }
3336 case SCSI_MECHANISM_STATUS:
3337 {
3338 cbMax = ataBE2H_U16(pbPacket + 8);
3339 ataR3StartTransfer(s, RT_MIN(cbMax, 8), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MECHANISM_STATUS, true);
3340 break;
3341 }
3342 case SCSI_READ_TOC_PMA_ATIP:
3343 {
3344 uint8_t format;
3345
3346 if (s->cNotifiedMediaChange > 0)
3347 {
3348 s->cNotifiedMediaChange-- ;
3349 atapiR3CmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3350 break;
3351 }
3352 else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
3353 {
3354 atapiR3CmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3355 break;
3356 }
3357 cbMax = ataBE2H_U16(pbPacket + 7);
3358 /* SCSI MMC-3 spec says format is at offset 2 (lower 4 bits),
3359 * but Linux kernel uses offset 9 (topmost 2 bits). Hope that
3360 * the other field is clear... */
3361 format = (pbPacket[2] & 0xf) | (pbPacket[9] >> 6);
3362 switch (format)
3363 {
3364 case 0:
3365 ataR3StartTransfer(s, cbMax, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TOC_NORMAL, true);
3366 break;
3367 case 1:
3368 ataR3StartTransfer(s, RT_MIN(cbMax, 12), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TOC_MULTI, true);
3369 break;
3370 case 2:
3371 ataR3StartTransfer(s, cbMax, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TOC_RAW, true);
3372 break;
3373 default:
3374 error_cmd:
3375 atapiR3CmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3376 break;
3377 }
3378 break;
3379 }
3380 case SCSI_READ_CAPACITY:
3381 if (s->cNotifiedMediaChange > 0)
3382 {
3383 s->cNotifiedMediaChange-- ;
3384 atapiR3CmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3385 break;
3386 }
3387 else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
3388 {
3389 atapiR3CmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3390 break;
3391 }
3392 ataR3StartTransfer(s, 8, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_CAPACITY, true);
3393 break;
3394 case SCSI_READ_DISC_INFORMATION:
3395 if (s->cNotifiedMediaChange > 0)
3396 {
3397 s->cNotifiedMediaChange-- ;
3398 atapiR3CmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3399 break;
3400 }
3401 else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
3402 {
3403 atapiR3CmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3404 break;
3405 }
3406 cbMax = ataBE2H_U16(pbPacket + 7);
3407 ataR3StartTransfer(s, RT_MIN(cbMax, 34), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_DISC_INFORMATION, true);
3408 break;
3409 case SCSI_READ_TRACK_INFORMATION:
3410 if (s->cNotifiedMediaChange > 0)
3411 {
3412 s->cNotifiedMediaChange-- ;
3413 atapiR3CmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3414 break;
3415 }
3416 else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
3417 {
3418 atapiR3CmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3419 break;
3420 }
3421 cbMax = ataBE2H_U16(pbPacket + 7);
3422 ataR3StartTransfer(s, RT_MIN(cbMax, 36), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TRACK_INFORMATION, true);
3423 break;
3424 case SCSI_GET_CONFIGURATION:
3425 /* No media change stuff here, it can confuse Linux guests. */
3426 cbMax = ataBE2H_U16(pbPacket + 7);
3427 ataR3StartTransfer(s, RT_MIN(cbMax, 80), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_GET_CONFIGURATION, true);
3428 break;
3429 case SCSI_INQUIRY:
3430 cbMax = ataBE2H_U16(pbPacket + 3);
3431 ataR3StartTransfer(s, RT_MIN(cbMax, 36), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_INQUIRY, true);
3432 break;
3433 case SCSI_READ_DVD_STRUCTURE:
3434 {
3435 cbMax = ataBE2H_U16(pbPacket + 8);
3436 ataR3StartTransfer(s, RT_MIN(cbMax, 4), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_DVD_STRUCTURE, true);
3437 break;
3438 }
3439 default:
3440 atapiR3CmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
3441 break;
3442 }
3443}
3444
3445
3446/*
3447 * Parse ATAPI commands, passing them directly to the CD/DVD drive.
3448 */
3449static void atapiR3ParseCmdPassthrough(ATADevState *s)
3450{
3451 const uint8_t *pbPacket;
3452 uint8_t *pbBuf;
3453 uint32_t cSectors, iATAPILBA;
3454 uint32_t cbTransfer = 0;
3455 PDMBLOCKTXDIR uTxDir = PDMBLOCKTXDIR_NONE;
3456
3457 pbPacket = s->aATAPICmd;
3458 pbBuf = s->CTX_SUFF(pbIOBuffer);
3459 switch (pbPacket[0])
3460 {
3461 case SCSI_BLANK:
3462 goto sendcmd;
3463 case SCSI_CLOSE_TRACK_SESSION:
3464 goto sendcmd;
3465 case SCSI_ERASE_10:
3466 iATAPILBA = ataBE2H_U32(pbPacket + 2);
3467 cbTransfer = ataBE2H_U16(pbPacket + 7);
3468 Log2(("ATAPI PT: lba %d\n", iATAPILBA));
3469 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3470 goto sendcmd;
3471 case SCSI_FORMAT_UNIT:
3472 cbTransfer = s->uATARegLCyl | (s->uATARegHCyl << 8); /* use ATAPI transfer length */
3473 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3474 goto sendcmd;
3475 case SCSI_GET_CONFIGURATION:
3476 cbTransfer = ataBE2H_U16(pbPacket + 7);
3477 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3478 goto sendcmd;
3479 case SCSI_GET_EVENT_STATUS_NOTIFICATION:
3480 cbTransfer = ataBE2H_U16(pbPacket + 7);
3481 if (ASMAtomicReadU32(&s->MediaEventStatus) != ATA_EVENT_STATUS_UNCHANGED)
3482 {
3483 ataR3StartTransfer(s, RT_MIN(cbTransfer, 8), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION, true);
3484 break;
3485 }
3486 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3487 goto sendcmd;
3488 case SCSI_GET_PERFORMANCE:
3489 cbTransfer = s->uATARegLCyl | (s->uATARegHCyl << 8); /* use ATAPI transfer length */
3490 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3491 goto sendcmd;
3492 case SCSI_INQUIRY:
3493 cbTransfer = ataBE2H_U16(pbPacket + 3);
3494 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3495 goto sendcmd;
3496 case SCSI_LOAD_UNLOAD_MEDIUM:
3497 goto sendcmd;
3498 case SCSI_MECHANISM_STATUS:
3499 cbTransfer = ataBE2H_U16(pbPacket + 8);
3500 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3501 goto sendcmd;
3502 case SCSI_MODE_SELECT_10:
3503 cbTransfer = ataBE2H_U16(pbPacket + 7);
3504 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3505 goto sendcmd;
3506 case SCSI_MODE_SENSE_10:
3507 cbTransfer = ataBE2H_U16(pbPacket + 7);
3508 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3509 goto sendcmd;
3510 case SCSI_PAUSE_RESUME:
3511 goto sendcmd;
3512 case SCSI_PLAY_AUDIO_10:
3513 goto sendcmd;
3514 case SCSI_PLAY_AUDIO_12:
3515 goto sendcmd;
3516 case SCSI_PLAY_AUDIO_MSF:
3517 goto sendcmd;
3518 case SCSI_PREVENT_ALLOW_MEDIUM_REMOVAL:
3519 /** @todo do not forget to unlock when a VM is shut down */
3520 goto sendcmd;
3521 case SCSI_READ_10:
3522 iATAPILBA = ataBE2H_U32(pbPacket + 2);
3523 cSectors = ataBE2H_U16(pbPacket + 7);
3524 Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
3525 s->cbATAPISector = 2048;
3526 cbTransfer = cSectors * s->cbATAPISector;
3527 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3528 goto sendcmd;
3529 case SCSI_READ_12:
3530 iATAPILBA = ataBE2H_U32(pbPacket + 2);
3531 cSectors = ataBE2H_U32(pbPacket + 6);
3532 Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
3533 s->cbATAPISector = 2048;
3534 cbTransfer = cSectors * s->cbATAPISector;
3535 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3536 goto sendcmd;
3537 case SCSI_READ_BUFFER:
3538 cbTransfer = ataBE2H_U24(pbPacket + 6);
3539 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3540 goto sendcmd;
3541 case SCSI_READ_BUFFER_CAPACITY:
3542 cbTransfer = ataBE2H_U16(pbPacket + 7);
3543 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3544 goto sendcmd;
3545 case SCSI_READ_CAPACITY:
3546 cbTransfer = 8;
3547 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3548 goto sendcmd;
3549 case SCSI_READ_CD:
3550 case SCSI_READ_CD_MSF:
3551 {
3552 /* Get sector size based on the expected sector type field. */
3553 switch ((pbPacket[1] >> 2) & 0x7)
3554 {
3555 case 0x0: /* All types. */
3556 {
3557 uint32_t iLbaStart;
3558
3559 if (pbPacket[0] == SCSI_READ_CD)
3560 iLbaStart = ataBE2H_U32(&pbPacket[2]);
3561 else
3562 iLbaStart = ataMSF2LBA(&pbPacket[3]);
3563
3564 if (s->pTrackList)
3565 s->cbATAPISector = ATAPIPassthroughTrackListGetSectorSizeFromLba(s->pTrackList, iLbaStart);
3566 else
3567 s->cbATAPISector = 2048; /* Might be incorrect if we couldn't determine the type. */
3568 break;
3569 }
3570 case 0x1: /* CD-DA */
3571 s->cbATAPISector = 2352;
3572 break;
3573 case 0x2: /* Mode 1 */
3574 s->cbATAPISector = 2048;
3575 break;
3576 case 0x3: /* Mode 2 formless */
3577 s->cbATAPISector = 2336;
3578 break;
3579 case 0x4: /* Mode 2 form 1 */
3580 s->cbATAPISector = 2048;
3581 break;
3582 case 0x5: /* Mode 2 form 2 */
3583 s->cbATAPISector = 2324;
3584 break;
3585 default: /* Reserved */
3586 AssertMsgFailed(("Unknown sector type\n"));
3587 s->cbATAPISector = 0; /** @todo we should probably fail the command here already. */
3588 }
3589
3590 if (pbPacket[0] == SCSI_READ_CD)
3591 cbTransfer = ataBE2H_U24(pbPacket + 6) * s->cbATAPISector;
3592 else /* SCSI_READ_MSF */
3593 {
3594 cSectors = ataMSF2LBA(pbPacket + 6) - ataMSF2LBA(pbPacket + 3);
3595 if (cSectors > 32)
3596 cSectors = 32; /* Limit transfer size to 64~74K. Safety first. In any case this can only harm software doing CDDA extraction. */
3597 cbTransfer = cSectors * s->cbATAPISector;
3598 }
3599 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3600 goto sendcmd;
3601 }
3602 case SCSI_READ_DISC_INFORMATION:
3603 cbTransfer = ataBE2H_U16(pbPacket + 7);
3604 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3605 goto sendcmd;
3606 case SCSI_READ_DVD_STRUCTURE:
3607 cbTransfer = ataBE2H_U16(pbPacket + 8);
3608 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3609 goto sendcmd;
3610 case SCSI_READ_FORMAT_CAPACITIES:
3611 cbTransfer = ataBE2H_U16(pbPacket + 7);
3612 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3613 goto sendcmd;
3614 case SCSI_READ_SUBCHANNEL:
3615 cbTransfer = ataBE2H_U16(pbPacket + 7);
3616 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3617 goto sendcmd;
3618 case SCSI_READ_TOC_PMA_ATIP:
3619 cbTransfer = ataBE2H_U16(pbPacket + 7);
3620 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3621 goto sendcmd;
3622 case SCSI_READ_TRACK_INFORMATION:
3623 cbTransfer = ataBE2H_U16(pbPacket + 7);
3624 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3625 goto sendcmd;
3626 case SCSI_REPAIR_TRACK:
3627 goto sendcmd;
3628 case SCSI_REPORT_KEY:
3629 cbTransfer = ataBE2H_U16(pbPacket + 8);
3630 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3631 goto sendcmd;
3632 case SCSI_REQUEST_SENSE:
3633 cbTransfer = pbPacket[4];
3634 if ((s->abATAPISense[2] & 0x0f) != SCSI_SENSE_NONE)
3635 {
3636 ataR3StartTransfer(s, RT_MIN(cbTransfer, 18), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_REQUEST_SENSE, true);
3637 break;
3638 }
3639 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3640 goto sendcmd;
3641 case SCSI_RESERVE_TRACK:
3642 goto sendcmd;
3643 case SCSI_SCAN:
3644 goto sendcmd;
3645 case SCSI_SEEK_10:
3646 goto sendcmd;
3647 case SCSI_SEND_CUE_SHEET:
3648 cbTransfer = ataBE2H_U24(pbPacket + 6);
3649 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3650 goto sendcmd;
3651 case SCSI_SEND_DVD_STRUCTURE:
3652 cbTransfer = ataBE2H_U16(pbPacket + 8);
3653 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3654 goto sendcmd;
3655 case SCSI_SEND_EVENT:
3656 cbTransfer = ataBE2H_U16(pbPacket + 8);
3657 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3658 goto sendcmd;
3659 case SCSI_SEND_KEY:
3660 cbTransfer = ataBE2H_U16(pbPacket + 8);
3661 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3662 goto sendcmd;
3663 case SCSI_SEND_OPC_INFORMATION:
3664 cbTransfer = ataBE2H_U16(pbPacket + 7);
3665 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3666 goto sendcmd;
3667 case SCSI_SET_CD_SPEED:
3668 goto sendcmd;
3669 case SCSI_SET_READ_AHEAD:
3670 goto sendcmd;
3671 case SCSI_SET_STREAMING:
3672 cbTransfer = ataBE2H_U16(pbPacket + 9);
3673 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3674 goto sendcmd;
3675 case SCSI_START_STOP_UNIT:
3676 goto sendcmd;
3677 case SCSI_STOP_PLAY_SCAN:
3678 goto sendcmd;
3679 case SCSI_SYNCHRONIZE_CACHE:
3680 goto sendcmd;
3681 case SCSI_TEST_UNIT_READY:
3682 goto sendcmd;
3683 case SCSI_VERIFY_10:
3684 goto sendcmd;
3685 case SCSI_WRITE_10:
3686 case SCSI_WRITE_AND_VERIFY_10:
3687 iATAPILBA = ataBE2H_U32(pbPacket + 2);
3688 cSectors = ataBE2H_U16(pbPacket + 7);
3689 if (s->pTrackList)
3690 s->cbATAPISector = ATAPIPassthroughTrackListGetSectorSizeFromLba(s->pTrackList, iATAPILBA);
3691 else
3692 s->cbATAPISector = 2048;
3693 Log2(("ATAPI PT: lba %d sectors %d sector size %d\n", iATAPILBA, cSectors, s->cbATAPISector));
3694 cbTransfer = cSectors * s->cbATAPISector;
3695 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3696 goto sendcmd;
3697 case SCSI_WRITE_12:
3698 iATAPILBA = ataBE2H_U32(pbPacket + 2);
3699 cSectors = ataBE2H_U32(pbPacket + 6);
3700 if (s->pTrackList)
3701 s->cbATAPISector = ATAPIPassthroughTrackListGetSectorSizeFromLba(s->pTrackList, iATAPILBA);
3702 else
3703 s->cbATAPISector = 2048;
3704 Log2(("ATAPI PT: lba %d sectors %d sector size %d\n", iATAPILBA, cSectors, s->cbATAPISector));
3705 cbTransfer = cSectors * s->cbATAPISector;
3706 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3707 goto sendcmd;
3708 case SCSI_WRITE_BUFFER:
3709 switch (pbPacket[1] & 0x1f)
3710 {
3711 case 0x04: /* download microcode */
3712 case 0x05: /* download microcode and save */
3713 case 0x06: /* download microcode with offsets */
3714 case 0x07: /* download microcode with offsets and save */
3715 case 0x0e: /* download microcode with offsets and defer activation */
3716 case 0x0f: /* activate deferred microcode */
3717 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough command attempted to update firmware, blocked\n", s->iLUN));
3718 atapiR3CmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3719 break;
3720 default:
3721 cbTransfer = ataBE2H_U16(pbPacket + 6);
3722 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3723 goto sendcmd;
3724 }
3725 break;
3726 case SCSI_REPORT_LUNS: /* Not part of MMC-3, but used by Windows. */
3727 cbTransfer = ataBE2H_U32(pbPacket + 6);
3728 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3729 goto sendcmd;
3730 case SCSI_REZERO_UNIT:
3731 /* Obsolete command used by cdrecord. What else would one expect?
3732 * This command is not sent to the drive, it is handled internally,
3733 * as the Linux kernel doesn't like it (message "scsi: unknown
3734 * opcode 0x01" in syslog) and replies with a sense code of 0,
3735 * which sends cdrecord to an endless loop. */
3736 atapiR3CmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
3737 break;
3738 default:
3739 LogRel(("PIIX3 ATA: LUN#%d: passthrough unimplemented for command %#x\n", s->iLUN, pbPacket[0]));
3740 atapiR3CmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
3741 break;
3742 sendcmd:
3743 /*
3744 * Send a command to the drive, passing data in/out as required.
3745 * Commands which exceed the I/O buffer size are split below
3746 * or aborted if splitting is not implemented.
3747 */
3748 Log2(("ATAPI PT: max size %d\n", cbTransfer));
3749 if (cbTransfer == 0)
3750 uTxDir = PDMBLOCKTXDIR_NONE;
3751 ataR3StartTransfer(s, cbTransfer, uTxDir, ATAFN_BT_ATAPI_PASSTHROUGH_CMD, ATAFN_SS_ATAPI_PASSTHROUGH, true);
3752 }
3753}
3754
3755
3756static void atapiR3ParseCmd(ATADevState *s)
3757{
3758 const uint8_t *pbPacket;
3759
3760 pbPacket = s->aATAPICmd;
3761# ifdef DEBUG
3762 Log(("%s: LUN#%d DMA=%d CMD=%#04x \"%s\"\n", __FUNCTION__, s->iLUN, s->fDMA, pbPacket[0], SCSICmdText(pbPacket[0])));
3763# else /* !DEBUG */
3764 Log(("%s: LUN#%d DMA=%d CMD=%#04x\n", __FUNCTION__, s->iLUN, s->fDMA, pbPacket[0]));
3765# endif /* !DEBUG */
3766 Log2(("%s: limit=%#x packet: %.*Rhxs\n", __FUNCTION__, s->uATARegLCyl | (s->uATARegHCyl << 8), ATAPI_PACKET_SIZE, pbPacket));
3767
3768 if (s->fATAPIPassthrough)
3769 atapiR3ParseCmdPassthrough(s);
3770 else
3771 atapiR3ParseCmdVirtualATAPI(s);
3772}
3773
3774
3775static bool ataR3PacketSS(ATADevState *s)
3776{
3777 s->fDMA = !!(s->uATARegFeature & 1);
3778 memcpy(s->aATAPICmd, s->CTX_SUFF(pbIOBuffer), ATAPI_PACKET_SIZE);
3779 s->uTxDir = PDMBLOCKTXDIR_NONE;
3780 s->cbTotalTransfer = 0;
3781 s->cbElementaryTransfer = 0;
3782 s->cbAtapiPassthroughTransfer = 0;
3783 atapiR3ParseCmd(s);
3784 return false;
3785}
3786
3787
3788/**
3789 * SCSI_GET_EVENT_STATUS_NOTIFICATION should return "medium removed" event
3790 * from now on, regardless if there was a medium inserted or not.
3791 */
3792static void ataR3MediumRemoved(ATADevState *s)
3793{
3794 ASMAtomicWriteU32(&s->MediaEventStatus, ATA_EVENT_STATUS_MEDIA_REMOVED);
3795}
3796
3797
3798/**
3799 * SCSI_GET_EVENT_STATUS_NOTIFICATION should return "medium inserted". If
3800 * there was already a medium inserted, don't forget to send the "medium
3801 * removed" event first.
3802 */
3803static void ataR3MediumInserted(ATADevState *s)
3804{
3805 uint32_t OldStatus, NewStatus;
3806 do
3807 {
3808 OldStatus = ASMAtomicReadU32(&s->MediaEventStatus);
3809 switch (OldStatus)
3810 {
3811 case ATA_EVENT_STATUS_MEDIA_CHANGED:
3812 case ATA_EVENT_STATUS_MEDIA_REMOVED:
3813 /* no change, we will send "medium removed" + "medium inserted" */
3814 NewStatus = ATA_EVENT_STATUS_MEDIA_CHANGED;
3815 break;
3816 default:
3817 NewStatus = ATA_EVENT_STATUS_MEDIA_NEW;
3818 break;
3819 }
3820 } while (!ASMAtomicCmpXchgU32(&s->MediaEventStatus, NewStatus, OldStatus));
3821}
3822
3823
3824/**
3825 * @interface_method_impl{PDMIMOUNTNOTIFY, pfnMountNotify}
3826 */
3827static DECLCALLBACK(void) ataR3MountNotify(PPDMIMOUNTNOTIFY pInterface)
3828{
3829 ATADevState *pIf = PDMIMOUNTNOTIFY_2_ATASTATE(pInterface);
3830 Log(("%s: changing LUN#%d\n", __FUNCTION__, pIf->iLUN));
3831
3832 /* Ignore the call if we're called while being attached. */
3833 if (!pIf->pDrvBlock)
3834 return;
3835
3836 if (pIf->fATAPI)
3837 pIf->cTotalSectors = pIf->pDrvBlock->pfnGetSize(pIf->pDrvBlock) / 2048;
3838 else
3839 pIf->cTotalSectors = pIf->pDrvBlock->pfnGetSize(pIf->pDrvBlock) / pIf->cbSector;
3840
3841 LogRel(("PIIX3 ATA: LUN#%d: CD/DVD, total number of sectors %Ld, passthrough unchanged\n", pIf->iLUN, pIf->cTotalSectors));
3842
3843 /* Report media changed in TEST UNIT and other (probably incorrect) places. */
3844 if (pIf->cNotifiedMediaChange < 2)
3845 pIf->cNotifiedMediaChange = 1;
3846 ataR3MediumInserted(pIf);
3847 ataR3MediumTypeSet(pIf, ATA_MEDIA_TYPE_UNKNOWN);
3848}
3849
3850/**
3851 * @interface_method_impl{PDMIMOUNTNOTIFY, pfnUnmountNotify}
3852 */
3853static DECLCALLBACK(void) ataR3UnmountNotify(PPDMIMOUNTNOTIFY pInterface)
3854{
3855 ATADevState *pIf = PDMIMOUNTNOTIFY_2_ATASTATE(pInterface);
3856 Log(("%s:\n", __FUNCTION__));
3857 pIf->cTotalSectors = 0;
3858
3859 /*
3860 * Whatever I do, XP will not use the GET MEDIA STATUS nor the EVENT stuff.
3861 * However, it will respond to TEST UNIT with a 0x6 0x28 (media changed) sense code.
3862 * So, we'll give it 4 TEST UNIT command to catch up, two which the media is not
3863 * present and 2 in which it is changed.
3864 */
3865 pIf->cNotifiedMediaChange = 1;
3866 ataR3MediumRemoved(pIf);
3867 ataR3MediumTypeSet(pIf, ATA_MEDIA_NO_DISC);
3868}
3869
3870static void ataR3PacketBT(ATADevState *s)
3871{
3872 s->cbElementaryTransfer = s->cbTotalTransfer;
3873 s->cbAtapiPassthroughTransfer = s->cbTotalTransfer;
3874 s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_CD;
3875 Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector));
3876 ataSetStatusValue(s, ATA_STAT_READY);
3877}
3878
3879
3880static void ataR3ResetDevice(ATADevState *s)
3881{
3882 s->cMultSectors = ATA_MAX_MULT_SECTORS;
3883 s->cNotifiedMediaChange = 0;
3884 ASMAtomicWriteU32(&s->MediaEventStatus, ATA_EVENT_STATUS_UNCHANGED);
3885 ASMAtomicWriteU32(&s->MediaTrackType, ATA_MEDIA_TYPE_UNKNOWN);
3886 ataUnsetIRQ(s);
3887
3888 s->uATARegSelect = 0x20;
3889 ataSetStatusValue(s, ATA_STAT_READY);
3890 ataR3SetSignature(s);
3891 s->cbTotalTransfer = 0;
3892 s->cbElementaryTransfer = 0;
3893 s->cbAtapiPassthroughTransfer = 0;
3894 s->iIOBufferPIODataStart = 0;
3895 s->iIOBufferPIODataEnd = 0;
3896 s->iBeginTransfer = ATAFN_BT_NULL;
3897 s->iSourceSink = ATAFN_SS_NULL;
3898 s->fDMA = false;
3899 s->fATAPITransfer = false;
3900 s->uATATransferMode = ATA_MODE_UDMA | 2; /* PIIX3 supports only up to UDMA2 */
3901
3902 s->uATARegFeature = 0;
3903}
3904
3905
3906static bool ataR3ExecuteDeviceDiagnosticSS(ATADevState *s)
3907{
3908 ataR3SetSignature(s);
3909 if (s->fATAPI)
3910 ataSetStatusValue(s, 0); /* NOTE: READY is _not_ set */
3911 else
3912 ataSetStatusValue(s, ATA_STAT_READY | ATA_STAT_SEEK);
3913 s->uATARegError = 0x01;
3914 return false;
3915}
3916
3917
3918static int ataR3TrimSectors(ATADevState *s, uint64_t u64Sector, uint32_t cSectors,
3919 bool *pfRedo)
3920{
3921 RTRANGE TrimRange;
3922 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
3923 int rc;
3924
3925 PDMCritSectLeave(&pCtl->lock);
3926
3927 TrimRange.offStart = u64Sector * s->cbSector;
3928 TrimRange.cbRange = cSectors * s->cbSector;
3929
3930 s->Led.Asserted.s.fWriting = s->Led.Actual.s.fWriting = 1;
3931 rc = s->pDrvBlock->pfnDiscard(s->pDrvBlock, &TrimRange, 1);
3932 s->Led.Actual.s.fWriting = 0;
3933
3934 if (RT_SUCCESS(rc))
3935 *pfRedo = false;
3936 else
3937 *pfRedo = ataR3IsRedoSetWarning(s, rc);
3938
3939 STAM_PROFILE_START(&pCtl->StatLockWait, a);
3940 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
3941 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
3942 return rc;
3943}
3944
3945
3946static bool ataR3TrimSS(ATADevState *s)
3947{
3948 int rc = VERR_GENERAL_FAILURE;
3949 uint32_t cRangesMax;
3950 uint64_t *pu64Range = (uint64_t *)s->CTX_SUFF(pbIOBuffer);
3951 bool fRedo = false;
3952
3953 cRangesMax = s->cbElementaryTransfer / sizeof(uint64_t);
3954 Assert(cRangesMax);
3955
3956 while (cRangesMax-- > 0)
3957 {
3958 if (ATA_RANGE_LENGTH_GET(*pu64Range) == 0)
3959 break;
3960
3961 rc = ataR3TrimSectors(s, *pu64Range & ATA_RANGE_LBA_MASK,
3962 ATA_RANGE_LENGTH_GET(*pu64Range), &fRedo);
3963 if (RT_FAILURE(rc))
3964 break;
3965
3966 pu64Range++;
3967 }
3968
3969 if (RT_SUCCESS(rc))
3970 {
3971 s->iSourceSink = ATAFN_SS_NULL;
3972 ataR3CmdOK(s, ATA_STAT_SEEK);
3973 }
3974 else
3975 {
3976 if (fRedo)
3977 return fRedo;
3978 if (s->cErrors++ < MAX_LOG_REL_ERRORS)
3979 LogRel(("PIIX3 ATA: LUN#%d: disk trim error (rc=%Rrc iSector=%#RX64 cSectors=%#RX32)\n",
3980 s->iLUN, rc, *pu64Range & ATA_RANGE_LBA_MASK, ATA_RANGE_LENGTH_GET(*pu64Range)));
3981
3982 /*
3983 * Check if we got interrupted. We don't need to set status variables
3984 * because the request was aborted.
3985 */
3986 if (rc != VERR_INTERRUPTED)
3987 ataR3CmdError(s, ID_ERR);
3988 }
3989
3990 return false;
3991}
3992
3993
3994static void ataR3ParseCmd(ATADevState *s, uint8_t cmd)
3995{
3996# ifdef DEBUG
3997 Log(("%s: LUN#%d CMD=%#04x \"%s\"\n", __FUNCTION__, s->iLUN, cmd, ATACmdText(cmd)));
3998# else /* !DEBUG */
3999 Log(("%s: LUN#%d CMD=%#04x\n", __FUNCTION__, s->iLUN, cmd));
4000# endif /* !DEBUG */
4001 s->fLBA48 = false;
4002 s->fDMA = false;
4003 if (cmd == ATA_IDLE_IMMEDIATE)
4004 {
4005 /* Detect Linux timeout recovery, first tries IDLE IMMEDIATE (which
4006 * would overwrite the failing command unfortunately), then RESET. */
4007 int32_t uCmdWait = -1;
4008 uint64_t uNow = RTTimeNanoTS();
4009 if (s->u64CmdTS)
4010 uCmdWait = (uNow - s->u64CmdTS) / 1000;
4011 LogRel(("PIIX3 ATA: LUN#%d: IDLE IMMEDIATE, CmdIf=%#04x (%d usec ago)\n",
4012 s->iLUN, s->uATARegCommand, uCmdWait));
4013 }
4014 s->uATARegCommand = cmd;
4015 switch (cmd)
4016 {
4017 case ATA_IDENTIFY_DEVICE:
4018 if (s->pDrvBlock && !s->fATAPI)
4019 ataR3StartTransfer(s, 512, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_NULL, ATAFN_SS_IDENTIFY, false);
4020 else
4021 {
4022 if (s->fATAPI)
4023 ataR3SetSignature(s);
4024 ataR3CmdError(s, ABRT_ERR);
4025 ataUnsetStatus(s, ATA_STAT_READY);
4026 ataHCSetIRQ(s); /* Shortcut, do not use AIO thread. */
4027 }
4028 break;
4029 case ATA_RECALIBRATE:
4030 if (s->fATAPI)
4031 goto abort_cmd;
4032 /* fall through */
4033 case ATA_INITIALIZE_DEVICE_PARAMETERS:
4034 ataR3CmdOK(s, ATA_STAT_SEEK);
4035 ataHCSetIRQ(s); /* Shortcut, do not use AIO thread. */
4036 break;
4037 case ATA_SET_MULTIPLE_MODE:
4038 if ( s->uATARegNSector != 0
4039 && ( s->uATARegNSector > ATA_MAX_MULT_SECTORS
4040 || (s->uATARegNSector & (s->uATARegNSector - 1)) != 0))
4041 {
4042 ataR3CmdError(s, ABRT_ERR);
4043 }
4044 else
4045 {
4046 Log2(("%s: set multi sector count to %d\n", __FUNCTION__, s->uATARegNSector));
4047 s->cMultSectors = s->uATARegNSector;
4048 ataR3CmdOK(s, 0);
4049 }
4050 ataHCSetIRQ(s); /* Shortcut, do not use AIO thread. */
4051 break;
4052 case ATA_READ_VERIFY_SECTORS_EXT:
4053 s->fLBA48 = true;
4054 case ATA_READ_VERIFY_SECTORS:
4055 case ATA_READ_VERIFY_SECTORS_WITHOUT_RETRIES:
4056 /* do sector number check ? */
4057 ataR3CmdOK(s, ATA_STAT_SEEK);
4058 ataHCSetIRQ(s); /* Shortcut, do not use AIO thread. */
4059 break;
4060 case ATA_READ_SECTORS_EXT:
4061 s->fLBA48 = true;
4062 case ATA_READ_SECTORS:
4063 case ATA_READ_SECTORS_WITHOUT_RETRIES:
4064 if (!s->pDrvBlock || s->fATAPI)
4065 goto abort_cmd;
4066 s->cSectorsPerIRQ = 1;
4067 ataR3StartTransfer(s, ataR3GetNSectors(s) * s->cbSector, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_READ_SECTORS, false);
4068 break;
4069 case ATA_WRITE_SECTORS_EXT:
4070 s->fLBA48 = true;
4071 case ATA_WRITE_SECTORS:
4072 case ATA_WRITE_SECTORS_WITHOUT_RETRIES:
4073 if (!s->pDrvBlock || s->fATAPI)
4074 goto abort_cmd;
4075 s->cSectorsPerIRQ = 1;
4076 ataR3StartTransfer(s, ataR3GetNSectors(s) * s->cbSector, PDMBLOCKTXDIR_TO_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_WRITE_SECTORS, false);
4077 break;
4078 case ATA_READ_MULTIPLE_EXT:
4079 s->fLBA48 = true;
4080 case ATA_READ_MULTIPLE:
4081 if (!s->pDrvBlock || !s->cMultSectors || s->fATAPI)
4082 goto abort_cmd;
4083 s->cSectorsPerIRQ = s->cMultSectors;
4084 ataR3StartTransfer(s, ataR3GetNSectors(s) * s->cbSector, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_READ_SECTORS, false);
4085 break;
4086 case ATA_WRITE_MULTIPLE_EXT:
4087 s->fLBA48 = true;
4088 case ATA_WRITE_MULTIPLE:
4089 if (!s->pDrvBlock || !s->cMultSectors || s->fATAPI)
4090 goto abort_cmd;
4091 s->cSectorsPerIRQ = s->cMultSectors;
4092 ataR3StartTransfer(s, ataR3GetNSectors(s) * s->cbSector, PDMBLOCKTXDIR_TO_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_WRITE_SECTORS, false);
4093 break;
4094 case ATA_READ_DMA_EXT:
4095 s->fLBA48 = true;
4096 case ATA_READ_DMA:
4097 case ATA_READ_DMA_WITHOUT_RETRIES:
4098 if (!s->pDrvBlock || s->fATAPI)
4099 goto abort_cmd;
4100 s->cSectorsPerIRQ = ATA_MAX_MULT_SECTORS;
4101 s->fDMA = true;
4102 ataR3StartTransfer(s, ataR3GetNSectors(s) * s->cbSector, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_READ_SECTORS, false);
4103 break;
4104 case ATA_WRITE_DMA_EXT:
4105 s->fLBA48 = true;
4106 case ATA_WRITE_DMA:
4107 case ATA_WRITE_DMA_WITHOUT_RETRIES:
4108 if (!s->pDrvBlock || s->fATAPI)
4109 goto abort_cmd;
4110 s->cSectorsPerIRQ = ATA_MAX_MULT_SECTORS;
4111 s->fDMA = true;
4112 ataR3StartTransfer(s, ataR3GetNSectors(s) * s->cbSector, PDMBLOCKTXDIR_TO_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_WRITE_SECTORS, false);
4113 break;
4114 case ATA_READ_NATIVE_MAX_ADDRESS_EXT:
4115 s->fLBA48 = true;
4116 ataR3SetSector(s, s->cTotalSectors - 1);
4117 ataR3CmdOK(s, 0);
4118 ataHCSetIRQ(s); /* Shortcut, do not use AIO thread. */
4119 break;
4120 case ATA_SEEK: /* Used by the SCO OpenServer. Command is marked as obsolete */
4121 ataR3CmdOK(s, 0);
4122 ataHCSetIRQ(s); /* Shortcut, do not use AIO thread. */
4123 break;
4124 case ATA_READ_NATIVE_MAX_ADDRESS:
4125 ataR3SetSector(s, RT_MIN(s->cTotalSectors, 1 << 28) - 1);
4126 ataR3CmdOK(s, 0);
4127 ataHCSetIRQ(s); /* Shortcut, do not use AIO thread. */
4128 break;
4129 case ATA_CHECK_POWER_MODE:
4130 s->uATARegNSector = 0xff; /* drive active or idle */
4131 ataR3CmdOK(s, 0);
4132 ataHCSetIRQ(s); /* Shortcut, do not use AIO thread. */
4133 break;
4134 case ATA_SET_FEATURES:
4135 Log2(("%s: feature=%#x\n", __FUNCTION__, s->uATARegFeature));
4136 if (!s->pDrvBlock)
4137 goto abort_cmd;
4138 switch (s->uATARegFeature)
4139 {
4140 case 0x02: /* write cache enable */
4141 Log2(("%s: write cache enable\n", __FUNCTION__));
4142 ataR3CmdOK(s, ATA_STAT_SEEK);
4143 ataHCSetIRQ(s); /* Shortcut, do not use AIO thread. */
4144 break;
4145 case 0xaa: /* read look-ahead enable */
4146 Log2(("%s: read look-ahead enable\n", __FUNCTION__));
4147 ataR3CmdOK(s, ATA_STAT_SEEK);
4148 ataHCSetIRQ(s); /* Shortcut, do not use AIO thread. */
4149 break;
4150 case 0x55: /* read look-ahead disable */
4151 Log2(("%s: read look-ahead disable\n", __FUNCTION__));
4152 ataR3CmdOK(s, ATA_STAT_SEEK);
4153 ataHCSetIRQ(s); /* Shortcut, do not use AIO thread. */
4154 break;
4155 case 0xcc: /* reverting to power-on defaults enable */
4156 Log2(("%s: revert to power-on defaults enable\n", __FUNCTION__));
4157 ataR3CmdOK(s, ATA_STAT_SEEK);
4158 ataHCSetIRQ(s); /* Shortcut, do not use AIO thread. */
4159 break;
4160 case 0x66: /* reverting to power-on defaults disable */
4161 Log2(("%s: revert to power-on defaults disable\n", __FUNCTION__));
4162 ataR3CmdOK(s, ATA_STAT_SEEK);
4163 ataHCSetIRQ(s); /* Shortcut, do not use AIO thread. */
4164 break;
4165 case 0x82: /* write cache disable */
4166 Log2(("%s: write cache disable\n", __FUNCTION__));
4167 /* As per the ATA/ATAPI-6 specs, a write cache disable
4168 * command MUST flush the write buffers to disc. */
4169 ataR3StartTransfer(s, 0, PDMBLOCKTXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_FLUSH, false);
4170 break;
4171 case 0x03: { /* set transfer mode */
4172 Log2(("%s: transfer mode %#04x\n", __FUNCTION__, s->uATARegNSector));
4173 switch (s->uATARegNSector & 0xf8)
4174 {
4175 case 0x00: /* PIO default */
4176 case 0x08: /* PIO mode */
4177 break;
4178 case ATA_MODE_MDMA: /* MDMA mode */
4179 s->uATATransferMode = (s->uATARegNSector & 0xf8) | RT_MIN(s->uATARegNSector & 0x07, ATA_MDMA_MODE_MAX);
4180 break;
4181 case ATA_MODE_UDMA: /* UDMA mode */
4182 s->uATATransferMode = (s->uATARegNSector & 0xf8) | RT_MIN(s->uATARegNSector & 0x07, ATA_UDMA_MODE_MAX);
4183 break;
4184 default:
4185 goto abort_cmd;
4186 }
4187 ataR3CmdOK(s, ATA_STAT_SEEK);
4188 ataHCSetIRQ(s); /* Shortcut, do not use AIO thread. */
4189 break;
4190 }
4191 default:
4192 goto abort_cmd;
4193 }
4194 /*
4195 * OS/2 workarond:
4196 * The OS/2 IDE driver from MCP2 appears to rely on the feature register being
4197 * reset here. According to the specification, this is a driver bug as the register
4198 * contents are undefined after the call. This means we can just as well reset it.
4199 */
4200 s->uATARegFeature = 0;
4201 break;
4202 case ATA_FLUSH_CACHE_EXT:
4203 case ATA_FLUSH_CACHE:
4204 if (!s->pDrvBlock || s->fATAPI)
4205 goto abort_cmd;
4206 ataR3StartTransfer(s, 0, PDMBLOCKTXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_FLUSH, false);
4207 break;
4208 case ATA_STANDBY_IMMEDIATE:
4209 ataR3CmdOK(s, 0);
4210 ataHCSetIRQ(s); /* Shortcut, do not use AIO thread. */
4211 break;
4212 case ATA_IDLE_IMMEDIATE:
4213 LogRel(("PIIX3 ATA: LUN#%d: aborting current command\n", s->iLUN));
4214 ataR3AbortCurrentCommand(s, false);
4215 break;
4216 case ATA_SLEEP:
4217 ataR3CmdOK(s, 0);
4218 ataHCSetIRQ(s);
4219 break;
4220 /* ATAPI commands */
4221 case ATA_IDENTIFY_PACKET_DEVICE:
4222 if (s->fATAPI)
4223 ataR3StartTransfer(s, 512, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_NULL, ATAFN_SS_ATAPI_IDENTIFY, false);
4224 else
4225 {
4226 ataR3CmdError(s, ABRT_ERR);
4227 ataHCSetIRQ(s); /* Shortcut, do not use AIO thread. */
4228 }
4229 break;
4230 case ATA_EXECUTE_DEVICE_DIAGNOSTIC:
4231 ataR3StartTransfer(s, 0, PDMBLOCKTXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_EXECUTE_DEVICE_DIAGNOSTIC, false);
4232 break;
4233 case ATA_DEVICE_RESET:
4234 if (!s->fATAPI)
4235 goto abort_cmd;
4236 LogRel(("PIIX3 ATA: LUN#%d: performing device RESET\n", s->iLUN));
4237 ataR3AbortCurrentCommand(s, true);
4238 break;
4239 case ATA_PACKET:
4240 if (!s->fATAPI)
4241 goto abort_cmd;
4242 /* overlapping commands not supported */
4243 if (s->uATARegFeature & 0x02)
4244 goto abort_cmd;
4245 ataR3StartTransfer(s, ATAPI_PACKET_SIZE, PDMBLOCKTXDIR_TO_DEVICE, ATAFN_BT_PACKET, ATAFN_SS_PACKET, false);
4246 break;
4247 case ATA_DATA_SET_MANAGEMENT:
4248 if (!s->pDrvBlock || !s->pDrvBlock->pfnDiscard)
4249 goto abort_cmd;
4250 if ( !(s->uATARegFeature & UINT8_C(0x01))
4251 || (s->uATARegFeature & ~UINT8_C(0x01)))
4252 goto abort_cmd;
4253 s->fDMA = true;
4254 ataR3StartTransfer(s, (s->uATARegNSectorHOB << 8 | s->uATARegNSector) * s->cbSector, PDMBLOCKTXDIR_TO_DEVICE, ATAFN_BT_NULL, ATAFN_SS_TRIM, false);
4255 break;
4256 default:
4257 abort_cmd:
4258 ataR3CmdError(s, ABRT_ERR);
4259 if (s->fATAPI)
4260 ataUnsetStatus(s, ATA_STAT_READY);
4261 ataHCSetIRQ(s); /* Shortcut, do not use AIO thread. */
4262 break;
4263 }
4264}
4265
4266# endif /* IN_RING3 */
4267#endif /* IN_RING0 || IN_RING3 */
4268
4269/*
4270 * Note: There are four distinct cases of port I/O handling depending on
4271 * which devices (if any) are attached to an IDE channel:
4272 *
4273 * 1) No device attached. No response to writes or reads (i.e. reads return
4274 * all bits set).
4275 *
4276 * 2) Both devices attached. Reads and writes are processed normally.
4277 *
4278 * 3) Device 0 only. If device 0 is selected, normal behavior applies. But
4279 * if Device 1 is selected, writes are still directed to Device 0 (except
4280 * commands are not executed), reads from control/command registers are
4281 * directed to Device 0, but status/alt status reads return 0. If Device 1
4282 * is a PACKET device, all reads return 0. See ATAPI-6 clause 9.16.1 and
4283 * Table 18 in clause 7.1.
4284 *
4285 * 4) Device 1 only - non-standard(!). Device 1 can't tell if Device 0 is
4286 * present or not and behaves the same. That means if Device 0 is selected,
4287 * Device 1 responds to writes (except commands are not executed) but does
4288 * not respond to reads. If Device 1 selected, normal behavior applies.
4289 * See ATAPI-6 clause 9.16.2 and Table 15 in clause 7.1.
4290 */
4291
4292static int ataIOPortWriteU8(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
4293{
4294 Log2(("%s: LUN#%d write addr=%#x val=%#04x\n", __FUNCTION__, pCtl->aIfs[pCtl->iSelectedIf].iLUN, addr, val));
4295 addr &= 7;
4296 switch (addr)
4297 {
4298 case 0:
4299 break;
4300 case 1: /* feature register */
4301 /* NOTE: data is written to the two drives */
4302 pCtl->aIfs[0].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
4303 pCtl->aIfs[1].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
4304 pCtl->aIfs[0].uATARegFeatureHOB = pCtl->aIfs[0].uATARegFeature;
4305 pCtl->aIfs[1].uATARegFeatureHOB = pCtl->aIfs[1].uATARegFeature;
4306 pCtl->aIfs[0].uATARegFeature = val;
4307 pCtl->aIfs[1].uATARegFeature = val;
4308 break;
4309 case 2: /* sector count */
4310 pCtl->aIfs[0].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
4311 pCtl->aIfs[1].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
4312 pCtl->aIfs[0].uATARegNSectorHOB = pCtl->aIfs[0].uATARegNSector;
4313 pCtl->aIfs[1].uATARegNSectorHOB = pCtl->aIfs[1].uATARegNSector;
4314 pCtl->aIfs[0].uATARegNSector = val;
4315 pCtl->aIfs[1].uATARegNSector = val;
4316 break;
4317 case 3: /* sector number */
4318 pCtl->aIfs[0].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
4319 pCtl->aIfs[1].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
4320 pCtl->aIfs[0].uATARegSectorHOB = pCtl->aIfs[0].uATARegSector;
4321 pCtl->aIfs[1].uATARegSectorHOB = pCtl->aIfs[1].uATARegSector;
4322 pCtl->aIfs[0].uATARegSector = val;
4323 pCtl->aIfs[1].uATARegSector = val;
4324 break;
4325 case 4: /* cylinder low */
4326 pCtl->aIfs[0].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
4327 pCtl->aIfs[1].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
4328 pCtl->aIfs[0].uATARegLCylHOB = pCtl->aIfs[0].uATARegLCyl;
4329 pCtl->aIfs[1].uATARegLCylHOB = pCtl->aIfs[1].uATARegLCyl;
4330 pCtl->aIfs[0].uATARegLCyl = val;
4331 pCtl->aIfs[1].uATARegLCyl = val;
4332 break;
4333 case 5: /* cylinder high */
4334 pCtl->aIfs[0].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
4335 pCtl->aIfs[1].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
4336 pCtl->aIfs[0].uATARegHCylHOB = pCtl->aIfs[0].uATARegHCyl;
4337 pCtl->aIfs[1].uATARegHCylHOB = pCtl->aIfs[1].uATARegHCyl;
4338 pCtl->aIfs[0].uATARegHCyl = val;
4339 pCtl->aIfs[1].uATARegHCyl = val;
4340 break;
4341 case 6: /* drive/head */
4342 pCtl->aIfs[0].uATARegSelect = (val & ~0x10) | 0xa0;
4343 pCtl->aIfs[1].uATARegSelect = (val | 0x10) | 0xa0;
4344 if (((val >> 4) & 1) != pCtl->iSelectedIf)
4345 {
4346 PPDMDEVINS pDevIns = CONTROLLER_2_DEVINS(pCtl);
4347
4348 /* select another drive */
4349 pCtl->iSelectedIf = (val >> 4) & 1;
4350 /* The IRQ line is multiplexed between the two drives, so
4351 * update the state when switching to another drive. Only need
4352 * to update interrupt line if it is enabled and there is a
4353 * state change. */
4354 if ( !(pCtl->aIfs[pCtl->iSelectedIf].uATARegDevCtl & ATA_DEVCTL_DISABLE_IRQ)
4355 && ( pCtl->aIfs[pCtl->iSelectedIf].fIrqPending
4356 != pCtl->aIfs[pCtl->iSelectedIf ^ 1].fIrqPending))
4357 {
4358 if (pCtl->aIfs[pCtl->iSelectedIf].fIrqPending)
4359 {
4360 Log2(("%s: LUN#%d asserting IRQ (drive select change)\n", __FUNCTION__, pCtl->aIfs[pCtl->iSelectedIf].iLUN));
4361 /* The BMDMA unit unconditionally sets BM_STATUS_INT if
4362 * the interrupt line is asserted. It monitors the line
4363 * for a rising edge. */
4364 pCtl->BmDma.u8Status |= BM_STATUS_INT;
4365 if (pCtl->irq == 16)
4366 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4367 else
4368 PDMDevHlpISASetIrq(pDevIns, pCtl->irq, 1);
4369 }
4370 else
4371 {
4372 Log2(("%s: LUN#%d deasserting IRQ (drive select change)\n", __FUNCTION__, pCtl->aIfs[pCtl->iSelectedIf].iLUN));
4373 if (pCtl->irq == 16)
4374 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
4375 else
4376 PDMDevHlpISASetIrq(pDevIns, pCtl->irq, 0);
4377 }
4378 }
4379 }
4380 break;
4381 default:
4382 case 7: /* command */
4383 /* ignore commands to non-existent device */
4384 if (pCtl->iSelectedIf && !pCtl->aIfs[pCtl->iSelectedIf].pDrvBlock)
4385 break;
4386#ifndef IN_RING3
4387 /* Don't do anything complicated in GC */
4388 return VINF_IOM_R3_IOPORT_WRITE;
4389#else /* IN_RING3 */
4390 ataR3ParseCmd(&pCtl->aIfs[pCtl->iSelectedIf], val);
4391#endif /* !IN_RING3 */
4392 }
4393 return VINF_SUCCESS;
4394}
4395
4396
4397static int ataIOPortReadU8(PATACONTROLLER pCtl, uint32_t addr, uint32_t *pu32)
4398{
4399 ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
4400 uint32_t val;
4401 bool fHOB;
4402
4403 /* Check if the guest is reading from a non-existent device. */
4404 if (!s->pDrvBlock)
4405 {
4406 if (pCtl->iSelectedIf) /* Device 1 selected, Device 0 responding for it. */
4407 {
4408 if (!pCtl->aIfs[0].pDrvBlock) /** @todo this case should never get here! */
4409 {
4410 Log2(("%s: addr=%#x: no device on channel\n", __FUNCTION__, addr));
4411 return VERR_IOM_IOPORT_UNUSED;
4412 }
4413 if (((addr & 7) != 1) && pCtl->aIfs[0].fATAPI) {
4414 Log2(("%s: addr=%#x, val=0: LUN#%d not attached/LUN#%d ATAPI\n", __FUNCTION__, addr,
4415 s->iLUN, pCtl->aIfs[0].iLUN));
4416 *pu32 = 0;
4417 return VINF_SUCCESS;
4418 }
4419 /* Else handle normally. */
4420 }
4421 else /* Device 0 selected (but not present). */
4422 {
4423 Log2(("%s: addr=%#x: LUN#%d not attached\n", __FUNCTION__, addr, s->iLUN));
4424 return VERR_IOM_IOPORT_UNUSED;
4425 }
4426 }
4427 fHOB = !!(s->uATARegDevCtl & (1 << 7));
4428 switch (addr & 7)
4429 {
4430 case 0: /* data register */
4431 val = 0xff;
4432 break;
4433 case 1: /* error register */
4434 /* The ATA specification is very terse when it comes to specifying
4435 * the precise effects of reading back the error/feature register.
4436 * The error register (read-only) shares the register number with
4437 * the feature register (write-only), so it seems that it's not
4438 * necessary to support the usual HOB readback here. */
4439 if (!s->pDrvBlock)
4440 val = 0;
4441 else
4442 val = s->uATARegError;
4443 break;
4444 case 2: /* sector count */
4445 if (fHOB)
4446 val = s->uATARegNSectorHOB;
4447 else
4448 val = s->uATARegNSector;
4449 break;
4450 case 3: /* sector number */
4451 if (fHOB)
4452 val = s->uATARegSectorHOB;
4453 else
4454 val = s->uATARegSector;
4455 break;
4456 case 4: /* cylinder low */
4457 if (fHOB)
4458 val = s->uATARegLCylHOB;
4459 else
4460 val = s->uATARegLCyl;
4461 break;
4462 case 5: /* cylinder high */
4463 if (fHOB)
4464 val = s->uATARegHCylHOB;
4465 else
4466 val = s->uATARegHCyl;
4467 break;
4468 case 6: /* drive/head */
4469 /* This register must always work as long as there is at least
4470 * one drive attached to the controller. It is common between
4471 * both drives anyway (completely identical content). */
4472 if (!pCtl->aIfs[0].pDrvBlock && !pCtl->aIfs[1].pDrvBlock)
4473 val = 0;
4474 else
4475 val = s->uATARegSelect;
4476 break;
4477 default:
4478 case 7: /* primary status */
4479 {
4480 /* Counter for number of busy status seen in GC in a row. */
4481 static unsigned cBusy = 0;
4482
4483 if (!s->pDrvBlock)
4484 val = 0;
4485 else
4486 val = s->uATARegStatus;
4487
4488 /* Give the async I/O thread an opportunity to make progress,
4489 * don't let it starve by guests polling frequently. EMT has a
4490 * lower priority than the async I/O thread, but sometimes the
4491 * host OS doesn't care. With some guests we are only allowed to
4492 * be busy for about 5 milliseconds in some situations. Note that
4493 * this is no guarantee for any other VBox thread getting
4494 * scheduled, so this just lowers the CPU load a bit when drives
4495 * are busy. It cannot help with timing problems. */
4496 if (val & ATA_STAT_BUSY)
4497 {
4498#ifdef IN_RING3
4499 cBusy = 0;
4500 PDMCritSectLeave(&pCtl->lock);
4501
4502#ifndef RT_OS_WINDOWS
4503 /*
4504 * The thread might be stuck in an I/O operation
4505 * due to a high I/O load on the host. (see @bugref{3301})
4506 * To perform the reset successfully
4507 * we interrupt the operation by sending a signal to the thread
4508 * if the thread didn't responded in 10ms.
4509 * This works only on POSIX hosts (Windows has a CancelSynchronousIo function which
4510 * does the same but it was introduced with Vista) but so far
4511 * this hang was only observed on Linux and Mac OS X.
4512 *
4513 * This is a workaround and needs to be solved properly.
4514 */
4515 if (pCtl->fReset)
4516 {
4517 uint64_t u64ResetTimeStop = RTTimeMilliTS();
4518
4519 if ((u64ResetTimeStop - pCtl->u64ResetTime) >= 10)
4520 {
4521 LogRel(("PIIX3 ATA LUN#%d: Async I/O thread probably stuck in operation, interrupting\n", s->iLUN));
4522 pCtl->u64ResetTime = u64ResetTimeStop;
4523 RTThreadPoke(pCtl->AsyncIOThread);
4524 }
4525 }
4526#endif
4527
4528 RTThreadYield();
4529
4530 {
4531 STAM_PROFILE_START(&pCtl->StatLockWait, a);
4532 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
4533 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
4534 }
4535
4536 val = s->uATARegStatus;
4537#else /* !IN_RING3 */
4538 /* Cannot yield CPU in raw-mode and ring-0 context. And switching
4539 * to host context for each and every busy status is too costly,
4540 * especially on SMP systems where we don't gain much by
4541 * yielding the CPU to someone else. */
4542 if (++cBusy >= 20)
4543 {
4544 cBusy = 0;
4545 return VINF_IOM_R3_IOPORT_READ;
4546 }
4547#endif /* !IN_RING3 */
4548 }
4549 else
4550 cBusy = 0;
4551 ataUnsetIRQ(s);
4552 break;
4553 }
4554 }
4555 Log2(("%s: LUN#%d addr=%#x val=%#04x\n", __FUNCTION__, s->iLUN, addr, val));
4556 *pu32 = val;
4557 return VINF_SUCCESS;
4558}
4559
4560
4561static uint32_t ataStatusRead(PATACONTROLLER pCtl, uint32_t addr)
4562{
4563 ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
4564 uint32_t val;
4565
4566 //@todo: The handler should not be even registered if there
4567 // is no device on an IDE channel.
4568 if (!pCtl->aIfs[0].pDrvBlock && !pCtl->aIfs[1].pDrvBlock)
4569 val = 0xff;
4570 else if (pCtl->iSelectedIf == 1 && !s->pDrvBlock)
4571 val = 0; /* Device 1 selected, Device 0 responding for it. */
4572 else
4573 val = s->uATARegStatus;
4574 Log2(("%s: addr=%#x val=%#04x\n", __FUNCTION__, addr, val));
4575 return val;
4576}
4577
4578static int ataControlWrite(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
4579{
4580#ifndef IN_RING3
4581 if ((val ^ pCtl->aIfs[0].uATARegDevCtl) & ATA_DEVCTL_RESET)
4582 return VINF_IOM_R3_IOPORT_WRITE; /* The RESET stuff is too complicated for RC+R0. */
4583#endif /* !IN_RING3 */
4584
4585 Log2(("%s: addr=%#x val=%#04x\n", __FUNCTION__, addr, val));
4586 /* RESET is common for both drives attached to a controller. */
4587 if ( !(pCtl->aIfs[0].uATARegDevCtl & ATA_DEVCTL_RESET)
4588 && (val & ATA_DEVCTL_RESET))
4589 {
4590#ifdef IN_RING3
4591 /* Software RESET low to high */
4592 int32_t uCmdWait0 = -1;
4593 int32_t uCmdWait1 = -1;
4594 uint64_t uNow = RTTimeNanoTS();
4595 if (pCtl->aIfs[0].u64CmdTS)
4596 uCmdWait0 = (uNow - pCtl->aIfs[0].u64CmdTS) / 1000;
4597 if (pCtl->aIfs[1].u64CmdTS)
4598 uCmdWait1 = (uNow - pCtl->aIfs[1].u64CmdTS) / 1000;
4599 LogRel(("PIIX3 ATA: Ctl#%d: RESET, DevSel=%d AIOIf=%d CmdIf0=%#04x (%d usec ago) CmdIf1=%#04x (%d usec ago)\n",
4600 ATACONTROLLER_IDX(pCtl), pCtl->iSelectedIf, pCtl->iAIOIf,
4601 pCtl->aIfs[0].uATARegCommand, uCmdWait0,
4602 pCtl->aIfs[1].uATARegCommand, uCmdWait1));
4603 pCtl->fReset = true;
4604 /* Everything must be done after the reset flag is set, otherwise
4605 * there are unavoidable races with the currently executing request
4606 * (which might just finish in the mean time). */
4607 pCtl->fChainedTransfer = false;
4608 for (uint32_t i = 0; i < RT_ELEMENTS(pCtl->aIfs); i++)
4609 {
4610 ataR3ResetDevice(&pCtl->aIfs[i]);
4611 /* The following cannot be done using ataSetStatusValue() since the
4612 * reset flag is already set, which suppresses all status changes. */
4613 pCtl->aIfs[i].uATARegStatus = ATA_STAT_BUSY | ATA_STAT_SEEK;
4614 Log2(("%s: LUN#%d status %#04x\n", __FUNCTION__, pCtl->aIfs[i].iLUN, pCtl->aIfs[i].uATARegStatus));
4615 pCtl->aIfs[i].uATARegError = 0x01;
4616 }
4617 ataR3AsyncIOClearRequests(pCtl);
4618 Log2(("%s: Ctl#%d: message to async I/O thread, resetA\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
4619 if (val & ATA_DEVCTL_HOB)
4620 {
4621 val &= ~ATA_DEVCTL_HOB;
4622 Log2(("%s: ignored setting HOB\n", __FUNCTION__));
4623 }
4624
4625 /* Save the timestamp we started the reset. */
4626 pCtl->u64ResetTime = RTTimeMilliTS();
4627
4628 /* Issue the reset request now. */
4629 ataHCAsyncIOPutRequest(pCtl, &g_ataResetARequest);
4630#else /* !IN_RING3 */
4631 AssertMsgFailed(("RESET handling is too complicated for GC\n"));
4632#endif /* IN_RING3 */
4633 }
4634 else if ( (pCtl->aIfs[0].uATARegDevCtl & ATA_DEVCTL_RESET)
4635 && !(val & ATA_DEVCTL_RESET))
4636 {
4637#ifdef IN_RING3
4638 /* Software RESET high to low */
4639 Log(("%s: deasserting RESET\n", __FUNCTION__));
4640 Log2(("%s: Ctl#%d: message to async I/O thread, resetC\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
4641 if (val & ATA_DEVCTL_HOB)
4642 {
4643 val &= ~ATA_DEVCTL_HOB;
4644 Log2(("%s: ignored setting HOB\n", __FUNCTION__));
4645 }
4646 ataHCAsyncIOPutRequest(pCtl, &g_ataResetCRequest);
4647#else /* !IN_RING3 */
4648 AssertMsgFailed(("RESET handling is too complicated for GC\n"));
4649#endif /* IN_RING3 */
4650 }
4651
4652 /* Change of interrupt disable flag. Update interrupt line if interrupt
4653 * is pending on the current interface. */
4654 if ( ((val ^ pCtl->aIfs[0].uATARegDevCtl) & ATA_DEVCTL_DISABLE_IRQ)
4655 && pCtl->aIfs[pCtl->iSelectedIf].fIrqPending)
4656 {
4657 if (!(val & ATA_DEVCTL_DISABLE_IRQ))
4658 {
4659 Log2(("%s: LUN#%d asserting IRQ (interrupt disable change)\n", __FUNCTION__, pCtl->aIfs[pCtl->iSelectedIf].iLUN));
4660 /* The BMDMA unit unconditionally sets BM_STATUS_INT if the
4661 * interrupt line is asserted. It monitors the line for a rising
4662 * edge. */
4663 pCtl->BmDma.u8Status |= BM_STATUS_INT;
4664 if (pCtl->irq == 16)
4665 PDMDevHlpPCISetIrq(CONTROLLER_2_DEVINS(pCtl), 0, 1);
4666 else
4667 PDMDevHlpISASetIrq(CONTROLLER_2_DEVINS(pCtl), pCtl->irq, 1);
4668 }
4669 else
4670 {
4671 Log2(("%s: LUN#%d deasserting IRQ (interrupt disable change)\n", __FUNCTION__, pCtl->aIfs[pCtl->iSelectedIf].iLUN));
4672 if (pCtl->irq == 16)
4673 PDMDevHlpPCISetIrq(CONTROLLER_2_DEVINS(pCtl), 0, 0);
4674 else
4675 PDMDevHlpISASetIrq(CONTROLLER_2_DEVINS(pCtl), pCtl->irq, 0);
4676 }
4677 }
4678
4679 if (val & ATA_DEVCTL_HOB)
4680 Log2(("%s: set HOB\n", __FUNCTION__));
4681
4682 pCtl->aIfs[0].uATARegDevCtl = val;
4683 pCtl->aIfs[1].uATARegDevCtl = val;
4684
4685 return VINF_SUCCESS;
4686}
4687
4688#if defined(IN_RING0) || defined(IN_RING3)
4689
4690static void ataHCPIOTransfer(PATACONTROLLER pCtl)
4691{
4692 ATADevState *s;
4693
4694 s = &pCtl->aIfs[pCtl->iAIOIf];
4695 Log3(("%s: if=%p\n", __FUNCTION__, s));
4696
4697 if (s->cbTotalTransfer && s->iIOBufferCur > s->iIOBufferEnd)
4698 {
4699# ifdef IN_RING3
4700 LogRel(("PIIX3 ATA: LUN#%d: %s data in the middle of a PIO transfer - VERY SLOW\n", s->iLUN, s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE ? "loading" : "storing"));
4701 /* Any guest OS that triggers this case has a pathetic ATA driver.
4702 * In a real system it would block the CPU via IORDY, here we do it
4703 * very similarly by not continuing with the current instruction
4704 * until the transfer to/from the storage medium is completed. */
4705 if (s->iSourceSink != ATAFN_SS_NULL)
4706 {
4707 bool fRedo;
4708 uint8_t status = s->uATARegStatus;
4709 ataSetStatusValue(s, ATA_STAT_BUSY);
4710 Log2(("%s: calling source/sink function\n", __FUNCTION__));
4711 fRedo = g_apfnSourceSinkFuncs[s->iSourceSink](s);
4712 pCtl->fRedo = fRedo;
4713 if (RT_UNLIKELY(fRedo))
4714 return;
4715 ataSetStatusValue(s, status);
4716 s->iIOBufferCur = 0;
4717 s->iIOBufferEnd = s->cbElementaryTransfer;
4718 }
4719# else
4720 AssertReleaseFailed();
4721# endif
4722 }
4723 if (s->cbTotalTransfer)
4724 {
4725 if (s->fATAPITransfer)
4726 ataHCPIOTransferLimitATAPI(s);
4727
4728 if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE && s->cbElementaryTransfer > s->cbTotalTransfer)
4729 s->cbElementaryTransfer = s->cbTotalTransfer;
4730
4731 Log2(("%s: %s tx_size=%d elem_tx_size=%d index=%d end=%d\n",
4732 __FUNCTION__, s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE ? "T2I" : "I2T",
4733 s->cbTotalTransfer, s->cbElementaryTransfer,
4734 s->iIOBufferCur, s->iIOBufferEnd));
4735 ataHCPIOTransferStart(s, s->iIOBufferCur, s->cbElementaryTransfer);
4736 s->cbTotalTransfer -= s->cbElementaryTransfer;
4737 s->iIOBufferCur += s->cbElementaryTransfer;
4738
4739 if (s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE && s->cbElementaryTransfer > s->cbTotalTransfer)
4740 s->cbElementaryTransfer = s->cbTotalTransfer;
4741 }
4742 else
4743 ataHCPIOTransferStop(s);
4744}
4745
4746
4747DECLINLINE(void) ataHCPIOTransferFinish(PATACONTROLLER pCtl, ATADevState *s)
4748{
4749 /* Do not interfere with RESET processing if the PIO transfer finishes
4750 * while the RESET line is asserted. */
4751 if (pCtl->fReset)
4752 {
4753 Log2(("%s: Ctl#%d: suppressed continuing PIO transfer as RESET is active\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
4754 return;
4755 }
4756
4757 if ( s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE
4758 || ( s->iSourceSink != ATAFN_SS_NULL
4759 && s->iIOBufferCur >= s->iIOBufferEnd))
4760 {
4761 /* Need to continue the transfer in the async I/O thread. This is
4762 * the case for write operations or generally for not yet finished
4763 * transfers (some data might need to be read). */
4764 ataUnsetStatus(s, ATA_STAT_READY | ATA_STAT_DRQ);
4765 ataSetStatus(s, ATA_STAT_BUSY);
4766
4767 Log2(("%s: Ctl#%d: message to async I/O thread, continuing PIO transfer\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
4768 ataHCAsyncIOPutRequest(pCtl, &g_ataPIORequest);
4769 }
4770 else
4771 {
4772 /* Either everything finished (though some data might still be pending)
4773 * or some data is pending before the next read is due. */
4774
4775 /* Continue a previously started transfer. */
4776 ataUnsetStatus(s, ATA_STAT_DRQ);
4777 ataSetStatus(s, ATA_STAT_READY);
4778
4779 if (s->cbTotalTransfer)
4780 {
4781 /* There is more to transfer, happens usually for large ATAPI
4782 * reads - the protocol limits the chunk size to 65534 bytes. */
4783 ataHCPIOTransfer(pCtl);
4784 ataHCSetIRQ(s);
4785 }
4786 else
4787 {
4788 Log2(("%s: Ctl#%d: skipping message to async I/O thread, ending PIO transfer\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
4789 /* Finish PIO transfer. */
4790 ataHCPIOTransfer(pCtl);
4791 Assert(!pCtl->fRedo);
4792 }
4793 }
4794}
4795
4796#endif /* IN_RING0 || IN_RING3 */
4797
4798/**
4799 * Fallback for ataCopyPioData124 that handles unaligned and out of bounds cases.
4800 *
4801 * @param pIf The device interface to work with.
4802 * @param pbDst The destination buffer.
4803 * @param pbSrc The source buffer.
4804 * @param cbCopy The number of bytes to copy, either 1, 2 or 4 bytes.
4805 */
4806DECL_NO_INLINE(static, void) ataCopyPioData124Slow(ATADevState *pIf, uint8_t *pbDst, const uint8_t *pbSrc, uint32_t cbCopy)
4807{
4808 uint32_t const offStart = pIf->iIOBufferPIODataStart;
4809 uint32_t const offNext = offStart + cbCopy;
4810
4811 if (offStart + cbCopy > pIf->cbIOBuffer)
4812 {
4813 Log(("%s: cbCopy=%#x offStart=%#x cbIOBuffer=%#x offNext=%#x (iIOBufferPIODataEnd=%#x)\n",
4814 __FUNCTION__, cbCopy, offStart, pIf->cbIOBuffer, offNext, pIf->iIOBufferPIODataEnd));
4815 if (offStart < pIf->cbIOBuffer)
4816 cbCopy = pIf->cbIOBuffer - offStart;
4817 else
4818 cbCopy = 0;
4819 }
4820
4821 switch (cbCopy)
4822 {
4823 case 4: pbDst[3] = pbSrc[3]; /* fall thru */
4824 case 3: pbDst[2] = pbSrc[2]; /* fall thru */
4825 case 2: pbDst[1] = pbSrc[1]; /* fall thru */
4826 case 1: pbDst[0] = pbSrc[0]; /* fall thru */
4827 case 0: break;
4828 default: AssertFailed(); /* impossible */
4829 }
4830
4831 pIf->iIOBufferPIODataStart = offNext;
4832
4833}
4834
4835
4836/**
4837 * Work for ataDataWrite & ataDataRead that copies data without using memcpy.
4838 *
4839 * This also updates pIf->iIOBufferPIODataStart.
4840 *
4841 * The two buffers are either stack (32-bit aligned) or somewhere within
4842 * pIf->pbIOBuffer.
4843 *
4844 * @param pIf The device interface to work with.
4845 * @param pbDst The destination buffer.
4846 * @param pbSrc The source buffer.
4847 * @param cbCopy The number of bytes to copy, either 1, 2 or 4 bytes.
4848 */
4849DECLINLINE(void) ataCopyPioData124(ATADevState *pIf, uint8_t *pbDst, const uint8_t *pbSrc, uint32_t cbCopy)
4850{
4851 /*
4852 * Quick bounds checking can be done by checking that the pbIOBuffer offset
4853 * (iIOBufferPIODataStart) is aligned at the transfer size (which is ASSUMED
4854 * to be 1, 2 or 4). However, since we're paranoid and don't currently
4855 * trust iIOBufferPIODataEnd to be within bounds, we current check against the
4856 * IO buffer size too.
4857 */
4858 Assert(cbCopy == 1 || cbCopy == 2 || cbCopy == 4);
4859 uint32_t const offStart = pIf->iIOBufferPIODataStart;
4860 if (RT_LIKELY( !(offStart & (cbCopy - 1))
4861 && offStart + cbCopy <= pIf->cbIOBuffer))
4862 {
4863 switch (cbCopy)
4864 {
4865 case 4: *(uint32_t *)pbDst = *(uint32_t const *)pbSrc; break;
4866 case 2: *(uint16_t *)pbDst = *(uint16_t const *)pbSrc; break;
4867 case 1: *pbDst = *pbSrc; break;
4868 }
4869 pIf->iIOBufferPIODataStart = offStart + cbCopy;
4870 }
4871 else
4872 ataCopyPioData124Slow(pIf, pbDst, pbSrc, cbCopy);
4873}
4874
4875
4876/**
4877 * Port I/O Handler for primary port range OUT operations.
4878 * @see FNIOMIOPORTOUT for details.
4879 */
4880PDMBOTHCBDECL(int) ataIOPortWrite1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
4881{
4882 uint32_t i = (uint32_t)(uintptr_t)pvUser;
4883 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
4884 PATACONTROLLER pCtl = &pThis->aCts[i];
4885
4886 Assert(i < 2);
4887 Assert(Port == pCtl->IOPortBase1);
4888 Assert(cb == 2 || cb == 4); /* Writes to the data port may be 16-bit or 32-bit. */
4889
4890 int rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_R3_IOPORT_WRITE);
4891 if (rc == VINF_SUCCESS)
4892 {
4893 ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
4894
4895 if (s->iIOBufferPIODataStart < s->iIOBufferPIODataEnd)
4896 {
4897 Assert(s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE);
4898 uint8_t *pbDst = s->CTX_SUFF(pbIOBuffer) + s->iIOBufferPIODataStart;
4899 uint8_t const *pbSrc = (uint8_t const *)&u32;
4900
4901#ifdef IN_RC
4902 /* Raw-mode: The ataHCPIOTransfer following the last transfer unit
4903 requires I/O thread signalling, we must go to ring-3 for that. */
4904 if (s->iIOBufferPIODataStart + cb < s->iIOBufferPIODataEnd)
4905 ataCopyPioData124(s, pbDst, pbSrc, cb);
4906 else
4907 rc = VINF_IOM_R3_IOPORT_WRITE;
4908
4909#elif defined(IN_RING0)
4910 /* Ring-0: We can do I/O thread signalling here, however for paranoid reasons
4911 triggered by a special case in ataHCPIOTransferFinish, we take extra care here. */
4912 if (s->iIOBufferPIODataStart + cb < s->iIOBufferPIODataEnd)
4913 ataCopyPioData124(s, pbDst, pbSrc, cb);
4914 else if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE) /* paranoia */
4915 {
4916 ataCopyPioData124(s, pbDst, pbSrc, cb);
4917 ataHCPIOTransferFinish(pCtl, s);
4918 }
4919 else
4920 {
4921 Log(("%s: Unexpected\n",__FUNCTION__));
4922 rc = VINF_IOM_R3_IOPORT_WRITE;
4923 }
4924
4925#else /* IN_RING 3*/
4926 ataCopyPioData124(s, pbDst, pbSrc, cb);
4927 if (s->iIOBufferPIODataStart >= s->iIOBufferPIODataEnd)
4928 ataHCPIOTransferFinish(pCtl, s);
4929#endif /* IN_RING 3*/
4930 }
4931 else
4932 Log2(("%s: DUMMY data\n", __FUNCTION__));
4933
4934 Log3(("%s: addr=%#x val=%.*Rhxs rc=%d\n", __FUNCTION__, Port, cb, &u32, rc));
4935 PDMCritSectLeave(&pCtl->lock);
4936 }
4937 else
4938 Log3(("%s: addr=%#x -> %d\n", __FUNCTION__, Port, rc));
4939 return rc;
4940}
4941
4942
4943/**
4944 * Port I/O Handler for primary port range IN operations.
4945 * @see FNIOMIOPORTIN for details.
4946 */
4947PDMBOTHCBDECL(int) ataIOPortRead1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
4948{
4949 uint32_t i = (uint32_t)(uintptr_t)pvUser;
4950 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
4951 PATACONTROLLER pCtl = &pThis->aCts[i];
4952
4953 Assert(i < 2);
4954 Assert(Port == pCtl->IOPortBase1);
4955
4956 /* Reads from the data register may be 16-bit or 32-bit. Byte accesses are
4957 upgraded to word. */
4958 Assert(cb == 1 || cb == 2 || cb == 4);
4959 uint32_t cbActual = cb != 1 ? cb : 2;
4960 *pu32 = 0;
4961
4962 int rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_R3_IOPORT_READ);
4963 if (rc == VINF_SUCCESS)
4964 {
4965 ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
4966
4967 if (s->iIOBufferPIODataStart < s->iIOBufferPIODataEnd)
4968 {
4969 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
4970 uint8_t const *pbSrc = s->CTX_SUFF(pbIOBuffer) + s->iIOBufferPIODataStart;
4971 uint8_t *pbDst = (uint8_t *)pu32;
4972
4973#ifdef IN_RC
4974 /* All but the last transfer unit is simple enough for RC, but
4975 * sending a request to the async IO thread is too complicated. */
4976 if (s->iIOBufferPIODataStart + cbActual < s->iIOBufferPIODataEnd)
4977 ataCopyPioData124(s, pbDst, pbSrc, cbActual);
4978 else
4979 rc = VINF_IOM_R3_IOPORT_READ;
4980
4981#elif defined(IN_RING0)
4982 /* Ring-0: We can do I/O thread signalling here. However there is one
4983 case in ataHCPIOTransfer that does a LogRel and would (but not from
4984 here) call directly into the driver code. We detect that odd case
4985 here cand return to ring-3 to handle it. */
4986 if (s->iIOBufferPIODataStart + cbActual < s->iIOBufferPIODataEnd)
4987 ataCopyPioData124(s, pbDst, pbSrc, cbActual);
4988 else if ( s->cbTotalTransfer == 0
4989 || s->iSourceSink != ATAFN_SS_NULL
4990 || s->iIOBufferCur <= s->iIOBufferEnd)
4991 {
4992 ataCopyPioData124(s, pbDst, pbSrc, cbActual);
4993 ataHCPIOTransferFinish(pCtl, s);
4994 }
4995 else
4996 {
4997 Log(("%s: Unexpected\n",__FUNCTION__));
4998 rc = VINF_IOM_R3_IOPORT_READ;
4999 }
5000
5001#else /* IN_RING3 */
5002 ataCopyPioData124(s, pbDst, pbSrc, cbActual);
5003 if (s->iIOBufferPIODataStart >= s->iIOBufferPIODataEnd)
5004 ataHCPIOTransferFinish(pCtl, s);
5005#endif /* IN_RING3 */
5006
5007 /* Just to be on the safe side (caller takes care of this, really). */
5008 if (cb == 1)
5009 *pu32 &= 0xff;
5010 }
5011 else
5012 {
5013 Log2(("%s: DUMMY data\n", __FUNCTION__));
5014 memset(pu32, 0xff, cb);
5015 }
5016 Log3(("%s: addr=%#x val=%.*Rhxs rc=%d\n", __FUNCTION__, Port, cb, pu32, rc));
5017
5018 PDMCritSectLeave(&pCtl->lock);
5019 }
5020 else
5021 Log3(("%s: addr=%#x -> %d\n", __FUNCTION__, Port, rc));
5022
5023 return rc;
5024}
5025
5026
5027/**
5028 * Port I/O Handler for primary port range IN string operations.
5029 * @see FNIOMIOPORTINSTRING for details.
5030 */
5031PDMBOTHCBDECL(int) ataIOPortReadStr1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint8_t *pbDst,
5032 uint32_t *pcTransfers, unsigned cb)
5033{
5034 uint32_t i = (uint32_t)(uintptr_t)pvUser;
5035 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
5036 PATACONTROLLER pCtl = &pThis->aCts[i];
5037
5038 Assert(i < 2);
5039 Assert(Port == pCtl->IOPortBase1);
5040 Assert(*pcTransfers > 0);
5041
5042 int rc;
5043 if (cb == 2 || cb == 4)
5044 {
5045 rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_R3_IOPORT_READ);
5046 if (rc == VINF_SUCCESS)
5047 {
5048 ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
5049
5050 uint32_t const offStart = s->iIOBufferPIODataStart;
5051 if (offStart < s->iIOBufferPIODataEnd)
5052 {
5053 /*
5054 * Figure how much we can copy. Usually it's the same as the request.
5055 * The last transfer unit cannot be handled in RC, as it involves
5056 * thread communication. In R0 we let the non-string callback handle it,
5057 * and ditto for overflows/dummy data.
5058 */
5059 uint32_t cAvailable = (s->iIOBufferPIODataEnd - offStart) / cb;
5060#ifndef IN_RING3
5061 if (cAvailable > 0)
5062 cAvailable--;
5063#endif
5064 uint32_t const cRequested = *pcTransfers;
5065 if (cAvailable > cRequested)
5066 cAvailable = cRequested;
5067 uint32_t const cbTransfer = cAvailable * cb;
5068 if ( offStart + cbTransfer <= s->cbIOBuffer
5069 && cbTransfer > 0)
5070 {
5071 /*
5072 * Do the transfer.
5073 */
5074 uint8_t const *pbSrc = s->CTX_SUFF(pbIOBuffer) + offStart;
5075 memcpy(pbDst, pbSrc, cbTransfer);
5076 Log3(("%s: addr=%#x cb=%#x cbTransfer=%#x val=%.*Rhxd\n",
5077 __FUNCTION__, Port, cb, cbTransfer, cbTransfer, pbSrc));
5078 s->iIOBufferPIODataStart = offStart + cbTransfer;
5079
5080#ifdef IN_RING3
5081 if (s->iIOBufferPIODataStart >= s->iIOBufferPIODataEnd)
5082 ataHCPIOTransferFinish(pCtl, s);
5083#endif
5084 *pcTransfers = cRequested - cAvailable;
5085 }
5086 else
5087 Log2(("ataIOPortReadStr1Data: DUMMY/Overflow!\n"));
5088 }
5089 else
5090 {
5091 /*
5092 * Dummy read (shouldn't happen) return 0xff like the non-string handler.
5093 */
5094 Log2(("ataIOPortReadStr1Data: DUMMY data (%#x bytes)\n", *pcTransfers * cb));
5095 memset(pbDst, 0xff, *pcTransfers * cb);
5096 *pcTransfers = 0;
5097 }
5098
5099 PDMCritSectLeave(&pCtl->lock);
5100 }
5101 }
5102 /*
5103 * Let the non-string I/O callback handle 1 byte reads.
5104 */
5105 else
5106 {
5107 Log2(("ataIOPortReadStr1Data: 1 byte read (%#x transfers)\n", *pcTransfers));
5108 AssertFailed();
5109 rc = VINF_SUCCESS;
5110 }
5111 return rc;
5112}
5113
5114
5115/**
5116 * Port I/O Handler for primary port range OUT string operations.
5117 * @see FNIOMIOPORTOUTSTRING for details.
5118 */
5119PDMBOTHCBDECL(int) ataIOPortWriteStr1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint8_t const *pbSrc,
5120 uint32_t *pcTransfers, unsigned cb)
5121{
5122 uint32_t i = (uint32_t)(uintptr_t)pvUser;
5123 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
5124 PATACONTROLLER pCtl = &pThis->aCts[i];
5125
5126 Assert(i < 2);
5127 Assert(Port == pCtl->IOPortBase1);
5128 Assert(*pcTransfers > 0);
5129
5130 int rc;
5131 if (cb == 2 || cb == 4)
5132 {
5133 rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_R3_IOPORT_WRITE);
5134 if (rc == VINF_SUCCESS)
5135 {
5136 ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
5137
5138 uint32_t const offStart = s->iIOBufferPIODataStart;
5139 if (offStart < s->iIOBufferPIODataEnd)
5140 {
5141 /*
5142 * Figure how much we can copy. Usually it's the same as the request.
5143 * The last transfer unit cannot be handled in RC, as it involves
5144 * thread communication. In R0 we let the non-string callback handle it,
5145 * and ditto for overflows/dummy data.
5146 */
5147 uint32_t cAvailable = (s->iIOBufferPIODataEnd - offStart) / cb;
5148#ifndef IN_RING3
5149 if (cAvailable)
5150 cAvailable--;
5151#endif
5152 uint32_t const cRequested = *pcTransfers;
5153 if (cAvailable > cRequested)
5154 cAvailable = cRequested;
5155 uint32_t const cbTransfer = cAvailable * cb;
5156 if ( offStart + cbTransfer <= s->cbIOBuffer
5157 && cbTransfer)
5158 {
5159 /*
5160 * Do the transfer.
5161 */
5162 void *pvDst = s->CTX_SUFF(pbIOBuffer) + offStart;
5163 memcpy(pvDst, pbSrc, cbTransfer);
5164 Log3(("%s: addr=%#x val=%.*Rhxs\n", __FUNCTION__, Port, cbTransfer, pvDst));
5165 s->iIOBufferPIODataStart = offStart + cbTransfer;
5166
5167#ifdef IN_RING3
5168 if (s->iIOBufferPIODataStart >= s->iIOBufferPIODataEnd)
5169 ataHCPIOTransferFinish(pCtl, s);
5170#endif
5171 *pcTransfers = cRequested - cAvailable;
5172 }
5173 else
5174 Log2(("ataIOPortWriteStr1Data: DUMMY/Overflow!\n"));
5175 }
5176 else
5177 {
5178 Log2(("ataIOPortWriteStr1Data: DUMMY data (%#x bytes)\n", *pcTransfers * cb));
5179 *pcTransfers = 0;
5180 }
5181
5182 PDMCritSectLeave(&pCtl->lock);
5183 }
5184 }
5185 /*
5186 * Let the non-string I/O callback handle 1 byte reads.
5187 */
5188 else
5189 {
5190 Log2(("ataIOPortWriteStr1Data: 1 byte write (%#x transfers)\n", *pcTransfers));
5191 AssertFailed();
5192 rc = VINF_SUCCESS;
5193 }
5194
5195 return rc;
5196}
5197
5198
5199#ifdef IN_RING3
5200
5201static void ataR3DMATransferStop(ATADevState *s)
5202{
5203 s->cbTotalTransfer = 0;
5204 s->cbElementaryTransfer = 0;
5205 s->iBeginTransfer = ATAFN_BT_NULL;
5206 s->iSourceSink = ATAFN_SS_NULL;
5207}
5208
5209
5210/**
5211 * Perform the entire DMA transfer in one go (unless a source/sink operation
5212 * has to be redone or a RESET comes in between). Unlike the PIO counterpart
5213 * this function cannot handle empty transfers.
5214 *
5215 * @param pCtl Controller for which to perform the transfer.
5216 */
5217static void ataR3DMATransfer(PATACONTROLLER pCtl)
5218{
5219 PPDMDEVINS pDevIns = CONTROLLER_2_DEVINS(pCtl);
5220 ATADevState *s = &pCtl->aIfs[pCtl->iAIOIf];
5221 bool fRedo;
5222 RTGCPHYS32 pDesc;
5223 uint32_t cbTotalTransfer, cbElementaryTransfer;
5224 uint32_t iIOBufferCur, iIOBufferEnd;
5225 uint32_t dmalen;
5226 PDMBLOCKTXDIR uTxDir;
5227 bool fLastDesc = false;
5228
5229 Assert(sizeof(BMDMADesc) == 8);
5230
5231 fRedo = pCtl->fRedo;
5232 if (RT_LIKELY(!fRedo))
5233 Assert(s->cbTotalTransfer);
5234 uTxDir = (PDMBLOCKTXDIR)s->uTxDir;
5235 cbTotalTransfer = s->cbTotalTransfer;
5236 cbElementaryTransfer = s->cbElementaryTransfer;
5237 iIOBufferCur = s->iIOBufferCur;
5238 iIOBufferEnd = s->iIOBufferEnd;
5239
5240 /* The DMA loop is designed to hold the lock only when absolutely
5241 * necessary. This avoids long freezes should the guest access the
5242 * ATA registers etc. for some reason. */
5243 PDMCritSectLeave(&pCtl->lock);
5244
5245 Log2(("%s: %s tx_size=%d elem_tx_size=%d index=%d end=%d\n",
5246 __FUNCTION__, uTxDir == PDMBLOCKTXDIR_FROM_DEVICE ? "T2I" : "I2T",
5247 cbTotalTransfer, cbElementaryTransfer,
5248 iIOBufferCur, iIOBufferEnd));
5249 for (pDesc = pCtl->pFirstDMADesc; pDesc <= pCtl->pLastDMADesc; pDesc += sizeof(BMDMADesc))
5250 {
5251 BMDMADesc DMADesc;
5252 RTGCPHYS32 pBuffer;
5253 uint32_t cbBuffer;
5254
5255 if (RT_UNLIKELY(fRedo))
5256 {
5257 pBuffer = pCtl->pRedoDMABuffer;
5258 cbBuffer = pCtl->cbRedoDMABuffer;
5259 fLastDesc = pCtl->fRedoDMALastDesc;
5260 }
5261 else
5262 {
5263 PDMDevHlpPhysRead(pDevIns, pDesc, &DMADesc, sizeof(BMDMADesc));
5264 pBuffer = RT_LE2H_U32(DMADesc.pBuffer);
5265 cbBuffer = RT_LE2H_U32(DMADesc.cbBuffer);
5266 fLastDesc = !!(cbBuffer & 0x80000000);
5267 cbBuffer &= 0xfffe;
5268 if (cbBuffer == 0)
5269 cbBuffer = 0x10000;
5270 if (cbBuffer > cbTotalTransfer)
5271 cbBuffer = cbTotalTransfer;
5272 }
5273
5274 while (RT_UNLIKELY(fRedo) || (cbBuffer && cbTotalTransfer))
5275 {
5276 if (RT_LIKELY(!fRedo))
5277 {
5278 dmalen = RT_MIN(cbBuffer, iIOBufferEnd - iIOBufferCur);
5279 Log2(("%s: DMA desc %#010x: addr=%#010x size=%#010x orig_size=%#010x\n", __FUNCTION__,
5280 (int)pDesc, pBuffer, cbBuffer, RT_LE2H_U32(DMADesc.cbBuffer) & 0xfffe));
5281
5282 PCIATAState *pATAState = PDMINS_2_DATA(pDevIns, PCIATAState *);
5283 AssertPtr(pATAState);
5284 if (uTxDir == PDMBLOCKTXDIR_FROM_DEVICE)
5285 PDMDevHlpPCIPhysWrite(pDevIns, pBuffer, s->CTX_SUFF(pbIOBuffer) + iIOBufferCur, dmalen);
5286 else
5287 PDMDevHlpPCIPhysRead(pDevIns, pBuffer, s->CTX_SUFF(pbIOBuffer) + iIOBufferCur, dmalen);
5288
5289 iIOBufferCur += dmalen;
5290 cbTotalTransfer -= dmalen;
5291 cbBuffer -= dmalen;
5292 pBuffer += dmalen;
5293 }
5294 if ( iIOBufferCur == iIOBufferEnd
5295 && (uTxDir == PDMBLOCKTXDIR_TO_DEVICE || cbTotalTransfer))
5296 {
5297 if (uTxDir == PDMBLOCKTXDIR_FROM_DEVICE && cbElementaryTransfer > cbTotalTransfer)
5298 cbElementaryTransfer = cbTotalTransfer;
5299
5300 {
5301 STAM_PROFILE_START(&pCtl->StatLockWait, a);
5302 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
5303 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
5304 }
5305
5306 /* The RESET handler could have cleared the DMA transfer
5307 * state (since we didn't hold the lock until just now
5308 * the guest can continue in parallel). If so, the state
5309 * is already set up so the loop is exited immediately. */
5310 if (s->iSourceSink != ATAFN_SS_NULL)
5311 {
5312 s->iIOBufferCur = iIOBufferCur;
5313 s->iIOBufferEnd = iIOBufferEnd;
5314 s->cbElementaryTransfer = cbElementaryTransfer;
5315 s->cbTotalTransfer = cbTotalTransfer;
5316 Log2(("%s: calling source/sink function\n", __FUNCTION__));
5317 fRedo = g_apfnSourceSinkFuncs[s->iSourceSink](s);
5318 if (RT_UNLIKELY(fRedo))
5319 {
5320 pCtl->pFirstDMADesc = pDesc;
5321 pCtl->pRedoDMABuffer = pBuffer;
5322 pCtl->cbRedoDMABuffer = cbBuffer;
5323 pCtl->fRedoDMALastDesc = fLastDesc;
5324 }
5325 else
5326 {
5327 cbTotalTransfer = s->cbTotalTransfer;
5328 cbElementaryTransfer = s->cbElementaryTransfer;
5329
5330 if (uTxDir == PDMBLOCKTXDIR_TO_DEVICE && cbElementaryTransfer > cbTotalTransfer)
5331 cbElementaryTransfer = cbTotalTransfer;
5332 iIOBufferCur = 0;
5333 iIOBufferEnd = cbElementaryTransfer;
5334 }
5335 pCtl->fRedo = fRedo;
5336 }
5337 else
5338 {
5339 /* This forces the loop to exit immediately. */
5340 pDesc = pCtl->pLastDMADesc + 1;
5341 }
5342
5343 PDMCritSectLeave(&pCtl->lock);
5344 if (RT_UNLIKELY(fRedo))
5345 break;
5346 }
5347 }
5348
5349 if (RT_UNLIKELY(fRedo))
5350 break;
5351
5352 /* end of transfer */
5353 if (!cbTotalTransfer || fLastDesc)
5354 break;
5355
5356 {
5357 STAM_PROFILE_START(&pCtl->StatLockWait, a);
5358 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
5359 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
5360 }
5361
5362 if (!(pCtl->BmDma.u8Cmd & BM_CMD_START) || pCtl->fReset)
5363 {
5364 LogRel(("PIIX3 ATA: Ctl#%d: ABORT DMA%s\n", ATACONTROLLER_IDX(pCtl), pCtl->fReset ? " due to RESET" : ""));
5365 if (!pCtl->fReset)
5366 ataR3DMATransferStop(s);
5367 /* This forces the loop to exit immediately. */
5368 pDesc = pCtl->pLastDMADesc + 1;
5369 }
5370
5371 PDMCritSectLeave(&pCtl->lock);
5372 }
5373
5374 {
5375 STAM_PROFILE_START(&pCtl->StatLockWait, a);
5376 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
5377 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
5378 }
5379
5380 if (RT_UNLIKELY(fRedo))
5381 return;
5382
5383 if (fLastDesc)
5384 pCtl->BmDma.u8Status &= ~BM_STATUS_DMAING;
5385 s->cbTotalTransfer = cbTotalTransfer;
5386 s->cbElementaryTransfer = cbElementaryTransfer;
5387 s->iIOBufferCur = iIOBufferCur;
5388 s->iIOBufferEnd = iIOBufferEnd;
5389}
5390
5391/**
5392 * Signal PDM that we're idle (if we actually are).
5393 *
5394 * @param pCtl The controller.
5395 */
5396static void ataR3AsyncSignalIdle(PATACONTROLLER pCtl)
5397{
5398 /*
5399 * Take the lock here and recheck the idle indicator to avoid
5400 * unnecessary work and racing ataR3WaitForAsyncIOIsIdle.
5401 */
5402 int rc = PDMCritSectEnter(&pCtl->AsyncIORequestLock, VINF_SUCCESS);
5403 AssertRC(rc);
5404
5405 if ( pCtl->fSignalIdle
5406 && ataR3AsyncIOIsIdle(pCtl, false /*fStrict*/))
5407 {
5408 PDMDevHlpAsyncNotificationCompleted(pCtl->pDevInsR3);
5409 RTThreadUserSignal(pCtl->AsyncIOThread); /* for ataR3Construct/ataR3ResetCommon. */
5410 }
5411
5412 rc = PDMCritSectLeave(&pCtl->AsyncIORequestLock);
5413 AssertRC(rc);
5414}
5415
5416/**
5417 * Async I/O thread for an interface.
5418 *
5419 * Once upon a time this was readable code with several loops and a different
5420 * semaphore for each purpose. But then came the "how can one save the state in
5421 * the middle of a PIO transfer" question. The solution was to use an ASM,
5422 * which is what's there now.
5423 */
5424static DECLCALLBACK(int) ataR3AsyncIOThread(RTTHREAD ThreadSelf, void *pvUser)
5425{
5426 const ATARequest *pReq;
5427 uint64_t u64TS = 0; /* shut up gcc */
5428 uint64_t uWait;
5429 int rc = VINF_SUCCESS;
5430 PATACONTROLLER pCtl = (PATACONTROLLER)pvUser;
5431 ATADevState *s;
5432
5433 pReq = NULL;
5434 pCtl->fChainedTransfer = false;
5435 while (!pCtl->fShutdown)
5436 {
5437 /* Keep this thread from doing anything as long as EMT is suspended. */
5438 while (pCtl->fRedoIdle)
5439 {
5440 if (pCtl->fSignalIdle)
5441 ataR3AsyncSignalIdle(pCtl);
5442 rc = RTSemEventWait(pCtl->SuspendIOSem, RT_INDEFINITE_WAIT);
5443 /* Continue if we got a signal by RTThreadPoke().
5444 * We will get notified if there is a request to process.
5445 */
5446 if (RT_UNLIKELY(rc == VERR_INTERRUPTED))
5447 continue;
5448 if (RT_FAILURE(rc) || pCtl->fShutdown)
5449 break;
5450
5451 pCtl->fRedoIdle = false;
5452 }
5453
5454 /* Wait for work. */
5455 while (pReq == NULL)
5456 {
5457 if (pCtl->fSignalIdle)
5458 ataR3AsyncSignalIdle(pCtl);
5459 rc = SUPSemEventWaitNoResume(pCtl->pSupDrvSession, pCtl->hAsyncIOSem, RT_INDEFINITE_WAIT);
5460 /* Continue if we got a signal by RTThreadPoke().
5461 * We will get notified if there is a request to process.
5462 */
5463 if (RT_UNLIKELY(rc == VERR_INTERRUPTED))
5464 continue;
5465 if (RT_FAILURE(rc) || RT_UNLIKELY(pCtl->fShutdown))
5466 break;
5467
5468 pReq = ataR3AsyncIOGetCurrentRequest(pCtl);
5469 }
5470
5471 if (RT_FAILURE(rc) || pCtl->fShutdown)
5472 break;
5473
5474 if (pReq == NULL)
5475 continue;
5476
5477 ATAAIO ReqType = pReq->ReqType;
5478
5479 Log2(("%s: Ctl#%d: state=%d, req=%d\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), pCtl->uAsyncIOState, ReqType));
5480 if (pCtl->uAsyncIOState != ReqType)
5481 {
5482 /* The new state is not the state that was expected by the normal
5483 * state changes. This is either a RESET/ABORT or there's something
5484 * really strange going on. */
5485 if ( (pCtl->uAsyncIOState == ATA_AIO_PIO || pCtl->uAsyncIOState == ATA_AIO_DMA)
5486 && (ReqType == ATA_AIO_PIO || ReqType == ATA_AIO_DMA))
5487 {
5488 /* Incorrect sequence of PIO/DMA states. Dump request queue. */
5489 ataR3AsyncIODumpRequests(pCtl);
5490 }
5491 AssertReleaseMsg(ReqType == ATA_AIO_RESET_ASSERTED || ReqType == ATA_AIO_RESET_CLEARED || ReqType == ATA_AIO_ABORT || pCtl->uAsyncIOState == ReqType, ("I/O state inconsistent: state=%d request=%d\n", pCtl->uAsyncIOState, ReqType));
5492 }
5493
5494 /* Do our work. */
5495 {
5496 STAM_PROFILE_START(&pCtl->StatLockWait, a);
5497 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
5498 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
5499 }
5500
5501 if (pCtl->uAsyncIOState == ATA_AIO_NEW && !pCtl->fChainedTransfer)
5502 {
5503 u64TS = RTTimeNanoTS();
5504#if defined(DEBUG) || defined(VBOX_WITH_STATISTICS)
5505 STAM_PROFILE_ADV_START(&pCtl->StatAsyncTime, a);
5506#endif
5507 }
5508
5509 switch (ReqType)
5510 {
5511 case ATA_AIO_NEW:
5512
5513 pCtl->iAIOIf = pReq->u.t.iIf;
5514 s = &pCtl->aIfs[pCtl->iAIOIf];
5515 s->cbTotalTransfer = pReq->u.t.cbTotalTransfer;
5516 s->uTxDir = pReq->u.t.uTxDir;
5517 s->iBeginTransfer = pReq->u.t.iBeginTransfer;
5518 s->iSourceSink = pReq->u.t.iSourceSink;
5519 s->iIOBufferEnd = 0;
5520 s->u64CmdTS = u64TS;
5521
5522 if (s->fATAPI)
5523 {
5524 if (pCtl->fChainedTransfer)
5525 {
5526 /* Only count the actual transfers, not the PIO
5527 * transfer of the ATAPI command bytes. */
5528 if (s->fDMA)
5529 STAM_REL_COUNTER_INC(&s->StatATAPIDMA);
5530 else
5531 STAM_REL_COUNTER_INC(&s->StatATAPIPIO);
5532 }
5533 }
5534 else
5535 {
5536 if (s->fDMA)
5537 STAM_REL_COUNTER_INC(&s->StatATADMA);
5538 else
5539 STAM_REL_COUNTER_INC(&s->StatATAPIO);
5540 }
5541
5542 pCtl->fChainedTransfer = false;
5543
5544 if (s->iBeginTransfer != ATAFN_BT_NULL)
5545 {
5546 Log2(("%s: Ctl#%d: calling begin transfer function\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
5547 g_apfnBeginTransFuncs[s->iBeginTransfer](s);
5548 s->iBeginTransfer = ATAFN_BT_NULL;
5549 if (s->uTxDir != PDMBLOCKTXDIR_FROM_DEVICE)
5550 s->iIOBufferEnd = s->cbElementaryTransfer;
5551 }
5552 else
5553 {
5554 s->cbElementaryTransfer = s->cbTotalTransfer;
5555 s->iIOBufferEnd = s->cbTotalTransfer;
5556 }
5557 s->iIOBufferCur = 0;
5558
5559 if (s->uTxDir != PDMBLOCKTXDIR_TO_DEVICE)
5560 {
5561 if (s->iSourceSink != ATAFN_SS_NULL)
5562 {
5563 bool fRedo;
5564 Log2(("%s: Ctl#%d: calling source/sink function\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
5565 fRedo = g_apfnSourceSinkFuncs[s->iSourceSink](s);
5566 pCtl->fRedo = fRedo;
5567 if (RT_UNLIKELY(fRedo && !pCtl->fReset))
5568 {
5569 /* Operation failed at the initial transfer, restart
5570 * everything from scratch by resending the current
5571 * request. Occurs very rarely, not worth optimizing. */
5572 LogRel(("%s: Ctl#%d: redo entire operation\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
5573 ataHCAsyncIOPutRequest(pCtl, pReq);
5574 break;
5575 }
5576 }
5577 else
5578 ataR3CmdOK(s, 0);
5579 s->iIOBufferEnd = s->cbElementaryTransfer;
5580
5581 }
5582
5583 /* Do not go into the transfer phase if RESET is asserted.
5584 * The CritSect is released while waiting for the host OS
5585 * to finish the I/O, thus RESET is possible here. Most
5586 * important: do not change uAsyncIOState. */
5587 if (pCtl->fReset)
5588 break;
5589
5590 if (s->fDMA)
5591 {
5592 if (s->cbTotalTransfer)
5593 {
5594 ataSetStatus(s, ATA_STAT_DRQ);
5595
5596 pCtl->uAsyncIOState = ATA_AIO_DMA;
5597 /* If BMDMA is already started, do the transfer now. */
5598 if (pCtl->BmDma.u8Cmd & BM_CMD_START)
5599 {
5600 Log2(("%s: Ctl#%d: message to async I/O thread, continuing DMA transfer immediately\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
5601 ataHCAsyncIOPutRequest(pCtl, &g_ataDMARequest);
5602 }
5603 }
5604 else
5605 {
5606 Assert(s->uTxDir == PDMBLOCKTXDIR_NONE); /* Any transfer which has an initial transfer size of 0 must be marked as such. */
5607 /* Finish DMA transfer. */
5608 ataR3DMATransferStop(s);
5609 ataHCSetIRQ(s);
5610 pCtl->uAsyncIOState = ATA_AIO_NEW;
5611 }
5612 }
5613 else
5614 {
5615 if (s->cbTotalTransfer)
5616 {
5617 ataHCPIOTransfer(pCtl);
5618 Assert(!pCtl->fRedo);
5619 if (s->fATAPITransfer || s->uTxDir != PDMBLOCKTXDIR_TO_DEVICE)
5620 ataHCSetIRQ(s);
5621
5622 if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE || s->iSourceSink != ATAFN_SS_NULL)
5623 {
5624 /* Write operations and not yet finished transfers
5625 * must be completed in the async I/O thread. */
5626 pCtl->uAsyncIOState = ATA_AIO_PIO;
5627 }
5628 else
5629 {
5630 /* Finished read operation can be handled inline
5631 * in the end of PIO transfer handling code. Linux
5632 * depends on this, as it waits only briefly for
5633 * devices to become ready after incoming data
5634 * transfer. Cannot find anything in the ATA spec
5635 * that backs this assumption, but as all kernels
5636 * are affected (though most of the time it does
5637 * not cause any harm) this must work. */
5638 pCtl->uAsyncIOState = ATA_AIO_NEW;
5639 }
5640 }
5641 else
5642 {
5643 Assert(s->uTxDir == PDMBLOCKTXDIR_NONE); /* Any transfer which has an initial transfer size of 0 must be marked as such. */
5644 /* Finish PIO transfer. */
5645 ataHCPIOTransfer(pCtl);
5646 Assert(!pCtl->fRedo);
5647 if (!s->fATAPITransfer)
5648 ataHCSetIRQ(s);
5649 pCtl->uAsyncIOState = ATA_AIO_NEW;
5650 }
5651 }
5652 break;
5653
5654 case ATA_AIO_DMA:
5655 {
5656 BMDMAState *bm = &pCtl->BmDma;
5657 s = &pCtl->aIfs[pCtl->iAIOIf]; /* Do not remove or there's an instant crash after loading the saved state */
5658 ATAFNSS iOriginalSourceSink = (ATAFNSS)s->iSourceSink; /* Used by the hack below, but gets reset by then. */
5659
5660 if (s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE)
5661 AssertRelease(bm->u8Cmd & BM_CMD_WRITE);
5662 else
5663 AssertRelease(!(bm->u8Cmd & BM_CMD_WRITE));
5664
5665 if (RT_LIKELY(!pCtl->fRedo))
5666 {
5667 /* The specs say that the descriptor table must not cross a
5668 * 4K boundary. */
5669 pCtl->pFirstDMADesc = bm->pvAddr;
5670 pCtl->pLastDMADesc = RT_ALIGN_32(bm->pvAddr + 1, _4K) - sizeof(BMDMADesc);
5671 }
5672 ataR3DMATransfer(pCtl);
5673
5674 if (RT_UNLIKELY(pCtl->fRedo && !pCtl->fReset))
5675 {
5676 LogRel(("PIIX3 ATA: Ctl#%d: redo DMA operation\n", ATACONTROLLER_IDX(pCtl)));
5677 ataHCAsyncIOPutRequest(pCtl, &g_ataDMARequest);
5678 break;
5679 }
5680
5681 /* The infamous delay IRQ hack. */
5682 if ( iOriginalSourceSink == ATAFN_SS_WRITE_SECTORS
5683 && s->cbTotalTransfer == 0
5684 && pCtl->DelayIRQMillies)
5685 {
5686 /* Delay IRQ for writing. Required to get the Win2K
5687 * installation work reliably (otherwise it crashes,
5688 * usually during component install). So far no better
5689 * solution has been found. */
5690 Log(("%s: delay IRQ hack\n", __FUNCTION__));
5691 PDMCritSectLeave(&pCtl->lock);
5692 RTThreadSleep(pCtl->DelayIRQMillies);
5693 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
5694 }
5695
5696 ataUnsetStatus(s, ATA_STAT_DRQ);
5697 Assert(!pCtl->fChainedTransfer);
5698 Assert(s->iSourceSink == ATAFN_SS_NULL);
5699 if (s->fATAPITransfer)
5700 {
5701 s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
5702 Log2(("%s: Ctl#%d: interrupt reason %#04x\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), s->uATARegNSector));
5703 s->fATAPITransfer = false;
5704 }
5705 ataHCSetIRQ(s);
5706 pCtl->uAsyncIOState = ATA_AIO_NEW;
5707 break;
5708 }
5709
5710 case ATA_AIO_PIO:
5711 s = &pCtl->aIfs[pCtl->iAIOIf]; /* Do not remove or there's an instant crash after loading the saved state */
5712
5713 if (s->iSourceSink != ATAFN_SS_NULL)
5714 {
5715 bool fRedo;
5716 Log2(("%s: Ctl#%d: calling source/sink function\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
5717 fRedo = g_apfnSourceSinkFuncs[s->iSourceSink](s);
5718 pCtl->fRedo = fRedo;
5719 if (RT_UNLIKELY(fRedo && !pCtl->fReset))
5720 {
5721 LogRel(("PIIX3 ATA: Ctl#%d: redo PIO operation\n", ATACONTROLLER_IDX(pCtl)));
5722 ataHCAsyncIOPutRequest(pCtl, &g_ataPIORequest);
5723 break;
5724 }
5725 s->iIOBufferCur = 0;
5726 s->iIOBufferEnd = s->cbElementaryTransfer;
5727 }
5728 else
5729 {
5730 /* Continue a previously started transfer. */
5731 ataUnsetStatus(s, ATA_STAT_BUSY);
5732 ataSetStatus(s, ATA_STAT_READY);
5733 }
5734
5735 /* It is possible that the drives on this controller get RESET
5736 * during the above call to the source/sink function. If that's
5737 * the case, don't restart the transfer and don't finish it the
5738 * usual way. RESET handling took care of all that already.
5739 * Most important: do not change uAsyncIOState. */
5740 if (pCtl->fReset)
5741 break;
5742
5743 if (s->cbTotalTransfer)
5744 {
5745 ataHCPIOTransfer(pCtl);
5746 ataHCSetIRQ(s);
5747
5748 if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE || s->iSourceSink != ATAFN_SS_NULL)
5749 {
5750 /* Write operations and not yet finished transfers
5751 * must be completed in the async I/O thread. */
5752 pCtl->uAsyncIOState = ATA_AIO_PIO;
5753 }
5754 else
5755 {
5756 /* Finished read operation can be handled inline
5757 * in the end of PIO transfer handling code. Linux
5758 * depends on this, as it waits only briefly for
5759 * devices to become ready after incoming data
5760 * transfer. Cannot find anything in the ATA spec
5761 * that backs this assumption, but as all kernels
5762 * are affected (though most of the time it does
5763 * not cause any harm) this must work. */
5764 pCtl->uAsyncIOState = ATA_AIO_NEW;
5765 }
5766 }
5767 else
5768 {
5769 /* Finish PIO transfer. */
5770 ataHCPIOTransfer(pCtl);
5771 if ( !pCtl->fChainedTransfer
5772 && !s->fATAPITransfer
5773 && s->uTxDir != PDMBLOCKTXDIR_FROM_DEVICE)
5774 {
5775 ataHCSetIRQ(s);
5776 }
5777 pCtl->uAsyncIOState = ATA_AIO_NEW;
5778 }
5779 break;
5780
5781 case ATA_AIO_RESET_ASSERTED:
5782 pCtl->uAsyncIOState = ATA_AIO_RESET_CLEARED;
5783 ataHCPIOTransferStop(&pCtl->aIfs[0]);
5784 ataHCPIOTransferStop(&pCtl->aIfs[1]);
5785 /* Do not change the DMA registers, they are not affected by the
5786 * ATA controller reset logic. It should be sufficient to issue a
5787 * new command, which is now possible as the state is cleared. */
5788 break;
5789
5790 case ATA_AIO_RESET_CLEARED:
5791 pCtl->uAsyncIOState = ATA_AIO_NEW;
5792 pCtl->fReset = false;
5793 /* Ensure that half-completed transfers are not redone. A reset
5794 * cancels the entire transfer, so continuing is wrong. */
5795 pCtl->fRedo = false;
5796 pCtl->fRedoDMALastDesc = false;
5797 LogRel(("PIIX3 ATA: Ctl#%d: finished processing RESET\n",
5798 ATACONTROLLER_IDX(pCtl)));
5799 for (uint32_t i = 0; i < RT_ELEMENTS(pCtl->aIfs); i++)
5800 {
5801 if (pCtl->aIfs[i].fATAPI)
5802 ataSetStatusValue(&pCtl->aIfs[i], 0); /* NOTE: READY is _not_ set */
5803 else
5804 ataSetStatusValue(&pCtl->aIfs[i], ATA_STAT_READY | ATA_STAT_SEEK);
5805 ataR3SetSignature(&pCtl->aIfs[i]);
5806 }
5807 break;
5808
5809 case ATA_AIO_ABORT:
5810 /* Abort the current command no matter what. There cannot be
5811 * any command activity on the other drive otherwise using
5812 * one thread per controller wouldn't work at all. */
5813 s = &pCtl->aIfs[pReq->u.a.iIf];
5814
5815 pCtl->uAsyncIOState = ATA_AIO_NEW;
5816 /* Do not change the DMA registers, they are not affected by the
5817 * ATA controller reset logic. It should be sufficient to issue a
5818 * new command, which is now possible as the state is cleared. */
5819 if (pReq->u.a.fResetDrive)
5820 {
5821 ataR3ResetDevice(s);
5822 ataR3ExecuteDeviceDiagnosticSS(s);
5823 }
5824 else
5825 {
5826 /* Stop any pending DMA transfer. */
5827 s->fDMA = false;
5828 ataHCPIOTransferStop(s);
5829 ataUnsetStatus(s, ATA_STAT_BUSY | ATA_STAT_DRQ | ATA_STAT_SEEK | ATA_STAT_ERR);
5830 ataSetStatus(s, ATA_STAT_READY);
5831 ataHCSetIRQ(s);
5832 }
5833 break;
5834
5835 default:
5836 AssertMsgFailed(("Undefined async I/O state %d\n", pCtl->uAsyncIOState));
5837 }
5838
5839 ataR3AsyncIORemoveCurrentRequest(pCtl, ReqType);
5840 pReq = ataR3AsyncIOGetCurrentRequest(pCtl);
5841
5842 if (pCtl->uAsyncIOState == ATA_AIO_NEW && !pCtl->fChainedTransfer)
5843 {
5844# if defined(DEBUG) || defined(VBOX_WITH_STATISTICS)
5845 STAM_PROFILE_ADV_STOP(&pCtl->StatAsyncTime, a);
5846# endif
5847
5848 u64TS = RTTimeNanoTS() - u64TS;
5849 uWait = u64TS / 1000;
5850 Log(("%s: Ctl#%d: LUN#%d finished I/O transaction in %d microseconds\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), pCtl->aIfs[pCtl->iAIOIf].iLUN, (uint32_t)(uWait)));
5851 /* Mark command as finished. */
5852 pCtl->aIfs[pCtl->iAIOIf].u64CmdTS = 0;
5853
5854 /*
5855 * Release logging of command execution times depends on the
5856 * command type. ATAPI commands often take longer (due to CD/DVD
5857 * spin up time etc.) so the threshold is different.
5858 */
5859 if (pCtl->aIfs[pCtl->iAIOIf].uATARegCommand != ATA_PACKET)
5860 {
5861 if (uWait > 8 * 1000 * 1000)
5862 {
5863 /*
5864 * Command took longer than 8 seconds. This is close
5865 * enough or over the guest's command timeout, so place
5866 * an entry in the release log to allow tracking such
5867 * timing errors (which are often caused by the host).
5868 */
5869 LogRel(("PIIX3 ATA: execution time for ATA command %#04x was %d seconds\n", pCtl->aIfs[pCtl->iAIOIf].uATARegCommand, uWait / (1000 * 1000)));
5870 }
5871 }
5872 else
5873 {
5874 if (uWait > 20 * 1000 * 1000)
5875 {
5876 /*
5877 * Command took longer than 20 seconds. This is close
5878 * enough or over the guest's command timeout, so place
5879 * an entry in the release log to allow tracking such
5880 * timing errors (which are often caused by the host).
5881 */
5882 LogRel(("PIIX3 ATA: execution time for ATAPI command %#04x was %d seconds\n", pCtl->aIfs[pCtl->iAIOIf].aATAPICmd[0], uWait / (1000 * 1000)));
5883 }
5884 }
5885
5886# if defined(DEBUG) || defined(VBOX_WITH_STATISTICS)
5887 if (uWait < pCtl->StatAsyncMinWait || !pCtl->StatAsyncMinWait)
5888 pCtl->StatAsyncMinWait = uWait;
5889 if (uWait > pCtl->StatAsyncMaxWait)
5890 pCtl->StatAsyncMaxWait = uWait;
5891
5892 STAM_COUNTER_ADD(&pCtl->StatAsyncTimeUS, uWait);
5893 STAM_COUNTER_INC(&pCtl->StatAsyncOps);
5894# endif /* DEBUG || VBOX_WITH_STATISTICS */
5895 }
5896
5897 PDMCritSectLeave(&pCtl->lock);
5898 }
5899
5900 /* Signal the ultimate idleness. */
5901 RTThreadUserSignal(pCtl->AsyncIOThread);
5902 if (pCtl->fSignalIdle)
5903 PDMDevHlpAsyncNotificationCompleted(pCtl->pDevInsR3);
5904
5905 /* Cleanup the state. */
5906 /* Do not destroy request lock yet, still needed for proper shutdown. */
5907 pCtl->fShutdown = false;
5908
5909 Log2(("%s: Ctl#%d: return %Rrc\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), rc));
5910 return rc;
5911}
5912
5913#endif /* IN_RING3 */
5914
5915static uint32_t ataBMDMACmdReadB(PATACONTROLLER pCtl, uint32_t addr)
5916{
5917 uint32_t val = pCtl->BmDma.u8Cmd;
5918 Log2(("%s: addr=%#06x val=%#04x\n", __FUNCTION__, addr, val));
5919 return val;
5920}
5921
5922
5923static void ataBMDMACmdWriteB(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
5924{
5925 Log2(("%s: addr=%#06x val=%#04x\n", __FUNCTION__, addr, val));
5926 if (!(val & BM_CMD_START))
5927 {
5928 pCtl->BmDma.u8Status &= ~BM_STATUS_DMAING;
5929 pCtl->BmDma.u8Cmd = val & (BM_CMD_START | BM_CMD_WRITE);
5930 }
5931 else
5932 {
5933#ifndef IN_RC
5934 /* Check whether the guest OS wants to change DMA direction in
5935 * mid-flight. Not allowed, according to the PIIX3 specs. */
5936 Assert(!(pCtl->BmDma.u8Status & BM_STATUS_DMAING) || !((val ^ pCtl->BmDma.u8Cmd) & 0x04));
5937 uint8_t uOldBmDmaStatus = pCtl->BmDma.u8Status;
5938 pCtl->BmDma.u8Status |= BM_STATUS_DMAING;
5939 pCtl->BmDma.u8Cmd = val & (BM_CMD_START | BM_CMD_WRITE);
5940
5941 /* Do not continue DMA transfers while the RESET line is asserted. */
5942 if (pCtl->fReset)
5943 {
5944 Log2(("%s: Ctl#%d: suppressed continuing DMA transfer as RESET is active\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
5945 return;
5946 }
5947
5948 /* Do not start DMA transfers if there's a PIO transfer going on,
5949 * or if there is already a transfer started on this controller. */
5950 if ( !pCtl->aIfs[pCtl->iSelectedIf].fDMA
5951 || (uOldBmDmaStatus & BM_STATUS_DMAING))
5952 return;
5953
5954 if (pCtl->aIfs[pCtl->iAIOIf].uATARegStatus & ATA_STAT_DRQ)
5955 {
5956 Log2(("%s: Ctl#%d: message to async I/O thread, continuing DMA transfer\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
5957 ataHCAsyncIOPutRequest(pCtl, &g_ataDMARequest);
5958 }
5959#else /* !IN_RING3 */
5960 AssertMsgFailed(("DMA START handling is too complicated for RC\n"));
5961#endif /* IN_RING3 */
5962 }
5963}
5964
5965static uint32_t ataBMDMAStatusReadB(PATACONTROLLER pCtl, uint32_t addr)
5966{
5967 uint32_t val = pCtl->BmDma.u8Status;
5968 Log2(("%s: addr=%#06x val=%#04x\n", __FUNCTION__, addr, val));
5969 return val;
5970}
5971
5972static void ataBMDMAStatusWriteB(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
5973{
5974 Log2(("%s: addr=%#06x val=%#04x\n", __FUNCTION__, addr, val));
5975 pCtl->BmDma.u8Status = (val & (BM_STATUS_D0DMA | BM_STATUS_D1DMA))
5976 | (pCtl->BmDma.u8Status & BM_STATUS_DMAING)
5977 | (pCtl->BmDma.u8Status & ~val & (BM_STATUS_ERROR | BM_STATUS_INT));
5978}
5979
5980static uint32_t ataBMDMAAddrReadL(PATACONTROLLER pCtl, uint32_t addr)
5981{
5982 uint32_t val = (uint32_t)pCtl->BmDma.pvAddr;
5983 Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val));
5984 return val;
5985}
5986
5987static void ataBMDMAAddrWriteL(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
5988{
5989 Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val));
5990 pCtl->BmDma.pvAddr = val & ~3;
5991}
5992
5993static void ataBMDMAAddrWriteLowWord(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
5994{
5995 Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val));
5996 pCtl->BmDma.pvAddr = (pCtl->BmDma.pvAddr & 0xFFFF0000) | RT_LOWORD(val & ~3);
5997
5998}
5999
6000static void ataBMDMAAddrWriteHighWord(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
6001{
6002 Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val));
6003 pCtl->BmDma.pvAddr = (RT_LOWORD(val) << 16) | RT_LOWORD(pCtl->BmDma.pvAddr);
6004}
6005
6006#define VAL(port, size) ( ((port) & 7) | ((size) << 3) )
6007
6008/**
6009 * Port I/O Handler for bus master DMA IN operations.
6010 * @see FNIOMIOPORTIN for details.
6011 */
6012PDMBOTHCBDECL(int) ataBMDMAIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
6013{
6014 uint32_t i = (uint32_t)(uintptr_t)pvUser;
6015 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6016 PATACONTROLLER pCtl = &pThis->aCts[i];
6017
6018 int rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_R3_IOPORT_READ);
6019 if (rc != VINF_SUCCESS)
6020 return rc;
6021 switch (VAL(Port, cb))
6022 {
6023 case VAL(0, 1): *pu32 = ataBMDMACmdReadB(pCtl, Port); break;
6024 case VAL(0, 2): *pu32 = ataBMDMACmdReadB(pCtl, Port); break;
6025 case VAL(2, 1): *pu32 = ataBMDMAStatusReadB(pCtl, Port); break;
6026 case VAL(2, 2): *pu32 = ataBMDMAStatusReadB(pCtl, Port); break;
6027 case VAL(4, 4): *pu32 = ataBMDMAAddrReadL(pCtl, Port); break;
6028 case VAL(0, 4):
6029 /* The SCO OpenServer tries to read 4 bytes starting from offset 0. */
6030 *pu32 = ataBMDMACmdReadB(pCtl, Port) | (ataBMDMAStatusReadB(pCtl, Port) << 16);
6031 break;
6032 default:
6033 AssertMsgFailed(("%s: Unsupported read from port %x size=%d\n", __FUNCTION__, Port, cb));
6034 PDMCritSectLeave(&pCtl->lock);
6035 return VERR_IOM_IOPORT_UNUSED;
6036 }
6037 PDMCritSectLeave(&pCtl->lock);
6038 return rc;
6039}
6040
6041/**
6042 * Port I/O Handler for bus master DMA OUT operations.
6043 * @see FNIOMIOPORTOUT for details.
6044 */
6045PDMBOTHCBDECL(int) ataBMDMAIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
6046{
6047 uint32_t i = (uint32_t)(uintptr_t)pvUser;
6048 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6049 PATACONTROLLER pCtl = &pThis->aCts[i];
6050
6051 int rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_R3_IOPORT_WRITE);
6052 if (rc != VINF_SUCCESS)
6053 return rc;
6054 switch (VAL(Port, cb))
6055 {
6056 case VAL(0, 1):
6057#ifdef IN_RC
6058 if (u32 & BM_CMD_START)
6059 {
6060 rc = VINF_IOM_R3_IOPORT_WRITE;
6061 break;
6062 }
6063#endif
6064 ataBMDMACmdWriteB(pCtl, Port, u32);
6065 break;
6066 case VAL(2, 1): ataBMDMAStatusWriteB(pCtl, Port, u32); break;
6067 case VAL(4, 4): ataBMDMAAddrWriteL(pCtl, Port, u32); break;
6068 case VAL(4, 2): ataBMDMAAddrWriteLowWord(pCtl, Port, u32); break;
6069 case VAL(6, 2): ataBMDMAAddrWriteHighWord(pCtl, Port, u32); break;
6070 default: AssertMsgFailed(("%s: Unsupported write to port %x size=%d val=%x\n", __FUNCTION__, Port, cb, u32)); break;
6071 }
6072 PDMCritSectLeave(&pCtl->lock);
6073 return rc;
6074}
6075
6076#undef VAL
6077
6078#ifdef IN_RING3
6079
6080/**
6081 * Callback function for mapping an PCI I/O region.
6082 *
6083 * @return VBox status code.
6084 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
6085 * @param iRegion The region number.
6086 * @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
6087 * I/O port, else it's a physical address.
6088 * This address is *NOT* relative to pci_mem_base like earlier!
6089 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
6090 */
6091static DECLCALLBACK(int) ataR3BMDMAIORangeMap(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion,
6092 RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
6093{
6094 PCIATAState *pThis = PCIDEV_2_PCIATASTATE(pPciDev);
6095 int rc = VINF_SUCCESS;
6096 Assert(enmType == PCI_ADDRESS_SPACE_IO);
6097 Assert(iRegion == 4);
6098 AssertMsg(RT_ALIGN(GCPhysAddress, 8) == GCPhysAddress, ("Expected 8 byte alignment. GCPhysAddress=%#x\n", GCPhysAddress));
6099
6100 /* Register the port range. */
6101 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6102 {
6103 int rc2 = PDMDevHlpIOPortRegister(pPciDev->pDevIns, (RTIOPORT)GCPhysAddress + i * 8, 8,
6104 (RTHCPTR)(uintptr_t)i, ataBMDMAIOPortWrite, ataBMDMAIOPortRead,
6105 NULL, NULL, "ATA Bus Master DMA");
6106 AssertRC(rc2);
6107 if (rc2 < rc)
6108 rc = rc2;
6109
6110 if (pThis->fRCEnabled)
6111 {
6112 rc2 = PDMDevHlpIOPortRegisterRC(pPciDev->pDevIns, (RTIOPORT)GCPhysAddress + i * 8, 8,
6113 (RTGCPTR)i, "ataBMDMAIOPortWrite", "ataBMDMAIOPortRead",
6114 NULL, NULL, "ATA Bus Master DMA");
6115 AssertRC(rc2);
6116 if (rc2 < rc)
6117 rc = rc2;
6118 }
6119 if (pThis->fR0Enabled)
6120 {
6121 rc2 = PDMDevHlpIOPortRegisterR0(pPciDev->pDevIns, (RTIOPORT)GCPhysAddress + i * 8, 8,
6122 (RTR0PTR)i, "ataBMDMAIOPortWrite", "ataBMDMAIOPortRead",
6123 NULL, NULL, "ATA Bus Master DMA");
6124 AssertRC(rc2);
6125 if (rc2 < rc)
6126 rc = rc2;
6127 }
6128 }
6129 return rc;
6130}
6131
6132
6133/* -=-=-=-=-=- PCIATAState::IBase -=-=-=-=-=- */
6134
6135/**
6136 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
6137 */
6138static DECLCALLBACK(void *) ataR3Status_QueryInterface(PPDMIBASE pInterface, const char *pszIID)
6139{
6140 PCIATAState *pThis = PDMIBASE_2_PCIATASTATE(pInterface);
6141 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
6142 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
6143 return NULL;
6144}
6145
6146
6147/* -=-=-=-=-=- PCIATAState::ILeds -=-=-=-=-=- */
6148
6149/**
6150 * Gets the pointer to the status LED of a unit.
6151 *
6152 * @returns VBox status code.
6153 * @param pInterface Pointer to the interface structure containing the called function pointer.
6154 * @param iLUN The unit which status LED we desire.
6155 * @param ppLed Where to store the LED pointer.
6156 */
6157static DECLCALLBACK(int) ataR3Status_QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
6158{
6159 PCIATAState *pThis = PDMILEDPORTS_2_PCIATASTATE(pInterface);
6160 if (iLUN < 4)
6161 {
6162 switch (iLUN)
6163 {
6164 case 0: *ppLed = &pThis->aCts[0].aIfs[0].Led; break;
6165 case 1: *ppLed = &pThis->aCts[0].aIfs[1].Led; break;
6166 case 2: *ppLed = &pThis->aCts[1].aIfs[0].Led; break;
6167 case 3: *ppLed = &pThis->aCts[1].aIfs[1].Led; break;
6168 }
6169 Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
6170 return VINF_SUCCESS;
6171 }
6172 return VERR_PDM_LUN_NOT_FOUND;
6173}
6174
6175
6176/* -=-=-=-=-=- ATADevState::IBase -=-=-=-=-=- */
6177
6178/**
6179 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
6180 */
6181static DECLCALLBACK(void *) ataR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
6182{
6183 ATADevState *pIf = PDMIBASE_2_ATASTATE(pInterface);
6184 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pIf->IBase);
6185 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBLOCKPORT, &pIf->IPort);
6186 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMOUNTNOTIFY, &pIf->IMountNotify);
6187 return NULL;
6188}
6189
6190
6191/* -=-=-=-=-=- ATADevState::IPort -=-=-=-=-=- */
6192
6193/**
6194 * @interface_method_impl{PDMIBLOCKPORT,pfnQueryDeviceLocation}
6195 */
6196static DECLCALLBACK(int) ataR3QueryDeviceLocation(PPDMIBLOCKPORT pInterface, const char **ppcszController,
6197 uint32_t *piInstance, uint32_t *piLUN)
6198{
6199 ATADevState *pIf = PDMIBLOCKPORT_2_ATASTATE(pInterface);
6200 PPDMDEVINS pDevIns = pIf->CTX_SUFF(pDevIns);
6201
6202 AssertPtrReturn(ppcszController, VERR_INVALID_POINTER);
6203 AssertPtrReturn(piInstance, VERR_INVALID_POINTER);
6204 AssertPtrReturn(piLUN, VERR_INVALID_POINTER);
6205
6206 *ppcszController = pDevIns->pReg->szName;
6207 *piInstance = pDevIns->iInstance;
6208 *piLUN = pIf->iLUN;
6209
6210 return VINF_SUCCESS;
6211}
6212
6213#endif /* IN_RING3 */
6214
6215/* -=-=-=-=-=- Wrappers -=-=-=-=-=- */
6216
6217
6218/**
6219 * Port I/O Handler for primary port range OUT operations.
6220 * @see FNIOMIOPORTOUT for details.
6221 */
6222PDMBOTHCBDECL(int) ataIOPortWrite1Other(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
6223{
6224 uint32_t i = (uint32_t)(uintptr_t)pvUser;
6225 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6226 PATACONTROLLER pCtl = &pThis->aCts[i];
6227
6228 Assert(i < 2);
6229 Assert(Port != pCtl->IOPortBase1);
6230
6231 int rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_R3_IOPORT_WRITE);
6232 if (rc == VINF_SUCCESS)
6233 {
6234 /* Writes to the other command block ports should be 8-bit only. If they
6235 * are not, the high bits are simply discarded. Undocumented, but observed
6236 * on a real PIIX4 system.
6237 */
6238 if (cb > 1)
6239 Log(("ataIOPortWrite1: suspect write to port %x val=%x size=%d\n", Port, u32, cb));
6240
6241 rc = ataIOPortWriteU8(pCtl, Port, u32);
6242
6243 PDMCritSectLeave(&pCtl->lock);
6244 }
6245 return rc;
6246}
6247
6248
6249/**
6250 * Port I/O Handler for primary port range IN operations.
6251 * @see FNIOMIOPORTIN for details.
6252 */
6253PDMBOTHCBDECL(int) ataIOPortRead1Other(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
6254{
6255 uint32_t i = (uint32_t)(uintptr_t)pvUser;
6256 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6257 PATACONTROLLER pCtl = &pThis->aCts[i];
6258
6259 Assert(i < 2);
6260 Assert(Port != pCtl->IOPortBase1);
6261
6262 int rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_R3_IOPORT_READ);
6263 if (rc == VINF_SUCCESS)
6264 {
6265 /* Reads from the other command block registers should be 8-bit only.
6266 * If they are not, the low byte is propagated to the high bits.
6267 * Undocumented, but observed on a real PIIX4 system.
6268 */
6269 rc = ataIOPortReadU8(pCtl, Port, pu32);
6270 if (cb > 1)
6271 {
6272 uint32_t pad;
6273
6274 /* Replicate the 8-bit result into the upper three bytes. */
6275 pad = *pu32 & 0xff;
6276 pad = pad | (pad << 8);
6277 pad = pad | (pad << 16);
6278 *pu32 = pad;
6279 Log(("ataIOPortRead1: suspect read from port %x size=%d\n", Port, cb));
6280 }
6281 PDMCritSectLeave(&pCtl->lock);
6282 }
6283 return rc;
6284}
6285
6286
6287/**
6288 * Port I/O Handler for secondary port range OUT operations.
6289 * @see FNIOMIOPORTOUT for details.
6290 */
6291PDMBOTHCBDECL(int) ataIOPortWrite2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
6292{
6293 uint32_t i = (uint32_t)(uintptr_t)pvUser;
6294 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6295 PATACONTROLLER pCtl = &pThis->aCts[i];
6296 int rc;
6297
6298 Assert(i < 2);
6299
6300 if (cb == 1)
6301 {
6302 rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_R3_IOPORT_WRITE);
6303 if (rc == VINF_SUCCESS)
6304 {
6305 rc = ataControlWrite(pCtl, Port, u32);
6306 PDMCritSectLeave(&pCtl->lock);
6307 }
6308 }
6309 else
6310 rc = VINF_SUCCESS;
6311 return rc;
6312}
6313
6314
6315/**
6316 * Port I/O Handler for secondary port range IN operations.
6317 * @see FNIOMIOPORTIN for details.
6318 */
6319PDMBOTHCBDECL(int) ataIOPortRead2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
6320{
6321 uint32_t i = (uint32_t)(uintptr_t)pvUser;
6322 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6323 PATACONTROLLER pCtl = &pThis->aCts[i];
6324 int rc;
6325
6326 Assert(i < 2);
6327
6328 if (cb == 1)
6329 {
6330 rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_R3_IOPORT_READ);
6331 if (rc == VINF_SUCCESS)
6332 {
6333 *pu32 = ataStatusRead(pCtl, Port);
6334 PDMCritSectLeave(&pCtl->lock);
6335 }
6336 }
6337 else
6338 rc = VERR_IOM_IOPORT_UNUSED;
6339 return rc;
6340}
6341
6342#ifdef IN_RING3
6343
6344
6345DECLINLINE(void) ataR3RelocBuffer(PPDMDEVINS pDevIns, ATADevState *s)
6346{
6347 if (s->pbIOBufferR3)
6348 s->pbIOBufferRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), s->pbIOBufferR3);
6349}
6350
6351
6352/**
6353 * Detach notification.
6354 *
6355 * The DVD drive has been unplugged.
6356 *
6357 * @param pDevIns The device instance.
6358 * @param iLUN The logical unit which is being detached.
6359 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
6360 */
6361static DECLCALLBACK(void) ataR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
6362{
6363 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6364 PATACONTROLLER pCtl;
6365 ATADevState *pIf;
6366 unsigned iController;
6367 unsigned iInterface;
6368
6369 AssertMsg(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
6370 ("PIIX3IDE: Device does not support hotplugging\n"));
6371
6372 /*
6373 * Locate the controller and stuff.
6374 */
6375 iController = iLUN / RT_ELEMENTS(pThis->aCts[0].aIfs);
6376 AssertReleaseMsg(iController < RT_ELEMENTS(pThis->aCts), ("iController=%d iLUN=%d\n", iController, iLUN));
6377 pCtl = &pThis->aCts[iController];
6378
6379 iInterface = iLUN % RT_ELEMENTS(pThis->aCts[0].aIfs);
6380 pIf = &pCtl->aIfs[iInterface];
6381
6382 /*
6383 * Zero some important members.
6384 */
6385 pIf->pDrvBase = NULL;
6386 pIf->pDrvBlock = NULL;
6387 pIf->pDrvBlockBios = NULL;
6388 pIf->pDrvMount = NULL;
6389
6390 /*
6391 * In case there was a medium inserted.
6392 */
6393 ataR3MediumRemoved(pIf);
6394}
6395
6396
6397/**
6398 * Configure a LUN.
6399 *
6400 * @returns VBox status code.
6401 * @param pDevIns The device instance.
6402 * @param pIf The ATA unit state.
6403 */
6404static int ataR3ConfigLun(PPDMDEVINS pDevIns, ATADevState *pIf)
6405{
6406 int rc = VINF_SUCCESS;
6407 PDMBLOCKTYPE enmType;
6408
6409 /*
6410 * Query Block, Bios and Mount interfaces.
6411 */
6412 pIf->pDrvBlock = PDMIBASE_QUERY_INTERFACE(pIf->pDrvBase, PDMIBLOCK);
6413 if (!pIf->pDrvBlock)
6414 {
6415 AssertMsgFailed(("Configuration error: LUN#%d hasn't a block interface!\n", pIf->iLUN));
6416 return VERR_PDM_MISSING_INTERFACE;
6417 }
6418
6419 /** @todo implement the BIOS invisible code path. */
6420 pIf->pDrvBlockBios = PDMIBASE_QUERY_INTERFACE(pIf->pDrvBase, PDMIBLOCKBIOS);
6421 if (!pIf->pDrvBlockBios)
6422 {
6423 AssertMsgFailed(("Configuration error: LUN#%d hasn't a block BIOS interface!\n", pIf->iLUN));
6424 return VERR_PDM_MISSING_INTERFACE;
6425 }
6426 pIf->pDrvMount = PDMIBASE_QUERY_INTERFACE(pIf->pDrvBase, PDMIMOUNT);
6427
6428 /*
6429 * Validate type.
6430 */
6431 enmType = pIf->pDrvBlock->pfnGetType(pIf->pDrvBlock);
6432 if ( enmType != PDMBLOCKTYPE_CDROM
6433 && enmType != PDMBLOCKTYPE_DVD
6434 && enmType != PDMBLOCKTYPE_HARD_DISK)
6435 {
6436 AssertMsgFailed(("Configuration error: LUN#%d isn't a disk or cd/dvd-rom. enmType=%d\n", pIf->iLUN, enmType));
6437 return VERR_PDM_UNSUPPORTED_BLOCK_TYPE;
6438 }
6439 if ( ( enmType == PDMBLOCKTYPE_DVD
6440 || enmType == PDMBLOCKTYPE_CDROM)
6441 && !pIf->pDrvMount)
6442 {
6443 AssertMsgFailed(("Internal error: cdrom without a mountable interface, WTF???!\n"));
6444 return VERR_INTERNAL_ERROR;
6445 }
6446 pIf->fATAPI = enmType == PDMBLOCKTYPE_DVD || enmType == PDMBLOCKTYPE_CDROM;
6447 pIf->fATAPIPassthrough = pIf->fATAPI ? (pIf->pDrvBlock->pfnSendCmd != NULL) : false;
6448
6449 /*
6450 * Allocate I/O buffer.
6451 */
6452 if (pIf->fATAPI)
6453 pIf->cbSector = 2048;
6454 else
6455 pIf->cbSector = pIf->pDrvBlock->pfnGetSectorSize(pIf->pDrvBlock);
6456
6457 PVM pVM = PDMDevHlpGetVM(pDevIns);
6458 if (pIf->cbIOBuffer)
6459 {
6460 /* Buffer is (probably) already allocated. Validate the fields,
6461 * because memory corruption can also overwrite pIf->cbIOBuffer. */
6462 if (pIf->fATAPI)
6463 AssertRelease(pIf->cbIOBuffer == _128K);
6464 else
6465 AssertRelease(pIf->cbIOBuffer == ATA_MAX_MULT_SECTORS * pIf->cbSector);
6466 Assert(pIf->pbIOBufferR3);
6467 Assert(pIf->pbIOBufferR0 == MMHyperR3ToR0(pVM, pIf->pbIOBufferR3));
6468 Assert(pIf->pbIOBufferRC == MMHyperR3ToRC(pVM, pIf->pbIOBufferR3));
6469 }
6470 else
6471 {
6472 if (pIf->fATAPI)
6473 pIf->cbIOBuffer = _128K;
6474 else
6475 pIf->cbIOBuffer = ATA_MAX_MULT_SECTORS * pIf->cbSector;
6476 Assert(!pIf->pbIOBufferR3);
6477 rc = MMR3HyperAllocOnceNoRel(pVM, pIf->cbIOBuffer, 0, MM_TAG_PDM_DEVICE_USER, (void **)&pIf->pbIOBufferR3);
6478 if (RT_FAILURE(rc))
6479 return VERR_NO_MEMORY;
6480 pIf->pbIOBufferR0 = MMHyperR3ToR0(pVM, pIf->pbIOBufferR3);
6481 pIf->pbIOBufferRC = MMHyperR3ToRC(pVM, pIf->pbIOBufferR3);
6482 }
6483
6484 /*
6485 * Init geometry (only for non-CD/DVD media).
6486 */
6487 if (pIf->fATAPI)
6488 {
6489 pIf->cTotalSectors = pIf->pDrvBlock->pfnGetSize(pIf->pDrvBlock) / pIf->cbSector;
6490 pIf->PCHSGeometry.cCylinders = 0; /* dummy */
6491 pIf->PCHSGeometry.cHeads = 0; /* dummy */
6492 pIf->PCHSGeometry.cSectors = 0; /* dummy */
6493 LogRel(("PIIX3 ATA: LUN#%d: CD/DVD, total number of sectors %Ld, passthrough %s\n", pIf->iLUN, pIf->cTotalSectors, (pIf->fATAPIPassthrough ? "enabled" : "disabled")));
6494 }
6495 else
6496 {
6497 pIf->cTotalSectors = pIf->pDrvBlock->pfnGetSize(pIf->pDrvBlock) / pIf->cbSector;
6498 rc = pIf->pDrvBlockBios->pfnGetPCHSGeometry(pIf->pDrvBlockBios,
6499 &pIf->PCHSGeometry);
6500 if (rc == VERR_PDM_MEDIA_NOT_MOUNTED)
6501 {
6502 pIf->PCHSGeometry.cCylinders = 0;
6503 pIf->PCHSGeometry.cHeads = 16; /*??*/
6504 pIf->PCHSGeometry.cSectors = 63; /*??*/
6505 }
6506 else if (rc == VERR_PDM_GEOMETRY_NOT_SET)
6507 {
6508 pIf->PCHSGeometry.cCylinders = 0; /* autodetect marker */
6509 rc = VINF_SUCCESS;
6510 }
6511 AssertRC(rc);
6512
6513 if ( pIf->PCHSGeometry.cCylinders == 0
6514 || pIf->PCHSGeometry.cHeads == 0
6515 || pIf->PCHSGeometry.cSectors == 0
6516 )
6517 {
6518 uint64_t cCylinders = pIf->cTotalSectors / (16 * 63);
6519 pIf->PCHSGeometry.cCylinders = RT_MAX(RT_MIN(cCylinders, 16383), 1);
6520 pIf->PCHSGeometry.cHeads = 16;
6521 pIf->PCHSGeometry.cSectors = 63;
6522 /* Set the disk geometry information. Ignore errors. */
6523 pIf->pDrvBlockBios->pfnSetPCHSGeometry(pIf->pDrvBlockBios,
6524 &pIf->PCHSGeometry);
6525 rc = VINF_SUCCESS;
6526 }
6527 LogRel(("PIIX3 ATA: LUN#%d: disk, PCHS=%u/%u/%u, total number of sectors %Ld\n", pIf->iLUN, pIf->PCHSGeometry.cCylinders, pIf->PCHSGeometry.cHeads, pIf->PCHSGeometry.cSectors, pIf->cTotalSectors));
6528
6529 if (pIf->pDrvBlock->pfnDiscard)
6530 LogRel(("PIIX3 ATA: LUN#%d: TRIM enabled\n", pIf->iLUN));
6531 }
6532 return rc;
6533}
6534
6535
6536/**
6537 * Attach command.
6538 *
6539 * This is called when we change block driver for the DVD drive.
6540 *
6541 * @returns VBox status code.
6542 * @param pDevIns The device instance.
6543 * @param iLUN The logical unit which is being detached.
6544 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
6545 */
6546static DECLCALLBACK(int) ataR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
6547{
6548 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6549 PATACONTROLLER pCtl;
6550 ATADevState *pIf;
6551 int rc;
6552 unsigned iController;
6553 unsigned iInterface;
6554
6555 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
6556 ("PIIX3IDE: Device does not support hotplugging\n"),
6557 VERR_INVALID_PARAMETER);
6558
6559 /*
6560 * Locate the controller and stuff.
6561 */
6562 iController = iLUN / RT_ELEMENTS(pThis->aCts[0].aIfs);
6563 AssertReleaseMsg(iController < RT_ELEMENTS(pThis->aCts), ("iController=%d iLUN=%d\n", iController, iLUN));
6564 pCtl = &pThis->aCts[iController];
6565
6566 iInterface = iLUN % RT_ELEMENTS(pThis->aCts[0].aIfs);
6567 pIf = &pCtl->aIfs[iInterface];
6568
6569 /* the usual paranoia */
6570 AssertRelease(!pIf->pDrvBase);
6571 AssertRelease(!pIf->pDrvBlock);
6572 Assert(ATADEVSTATE_2_CONTROLLER(pIf) == pCtl);
6573 Assert(pIf->iLUN == iLUN);
6574
6575 /*
6576 * Try attach the block device and get the interfaces,
6577 * required as well as optional.
6578 */
6579 rc = PDMDevHlpDriverAttach(pDevIns, pIf->iLUN, &pIf->IBase, &pIf->pDrvBase, NULL);
6580 if (RT_SUCCESS(rc))
6581 {
6582 rc = ataR3ConfigLun(pDevIns, pIf);
6583 /*
6584 * In case there is a medium inserted.
6585 */
6586 ataR3MediumInserted(pIf);
6587 ataR3MediumTypeSet(pIf, ATA_MEDIA_TYPE_UNKNOWN);
6588 }
6589 else
6590 AssertMsgFailed(("Failed to attach LUN#%d. rc=%Rrc\n", pIf->iLUN, rc));
6591
6592 if (RT_FAILURE(rc))
6593 {
6594 pIf->pDrvBase = NULL;
6595 pIf->pDrvBlock = NULL;
6596 }
6597 return rc;
6598}
6599
6600
6601/**
6602 * Resume notification.
6603 *
6604 * @returns VBox status.
6605 * @param pDevIns The device instance data.
6606 */
6607static DECLCALLBACK(void) ataR3Resume(PPDMDEVINS pDevIns)
6608{
6609 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6610 int rc;
6611
6612 Log(("%s:\n", __FUNCTION__));
6613 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6614 {
6615 if (pThis->aCts[i].fRedo && pThis->aCts[i].fRedoIdle)
6616 {
6617 rc = RTSemEventSignal(pThis->aCts[i].SuspendIOSem);
6618 AssertRC(rc);
6619 }
6620 }
6621 return;
6622}
6623
6624
6625/**
6626 * Checks if all (both) the async I/O threads have quiesced.
6627 *
6628 * @returns true on success.
6629 * @returns false when one or more threads is still processing.
6630 * @param pThis Pointer to the instance data.
6631 */
6632static bool ataR3AllAsyncIOIsIdle(PPDMDEVINS pDevIns)
6633{
6634 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6635
6636 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6637 if (pThis->aCts[i].AsyncIOThread != NIL_RTTHREAD)
6638 {
6639 bool fRc = ataR3AsyncIOIsIdle(&pThis->aCts[i], false /*fStrict*/);
6640 if (!fRc)
6641 {
6642 /* Make it signal PDM & itself when its done */
6643 PDMCritSectEnter(&pThis->aCts[i].AsyncIORequestLock, VERR_IGNORED);
6644 ASMAtomicWriteBool(&pThis->aCts[i].fSignalIdle, true);
6645 PDMCritSectLeave(&pThis->aCts[i].AsyncIORequestLock);
6646
6647 fRc = ataR3AsyncIOIsIdle(&pThis->aCts[i], false /*fStrict*/);
6648 if (!fRc)
6649 {
6650#if 0 /** @todo Need to do some time tracking here... */
6651 LogRel(("PIIX3 ATA: Ctl#%u is still executing, DevSel=%d AIOIf=%d CmdIf0=%#04x CmdIf1=%#04x\n",
6652 i, pThis->aCts[i].iSelectedIf, pThis->aCts[i].iAIOIf,
6653 pThis->aCts[i].aIfs[0].uATARegCommand, pThis->aCts[i].aIfs[1].uATARegCommand));
6654#endif
6655 return false;
6656 }
6657 }
6658 ASMAtomicWriteBool(&pThis->aCts[i].fSignalIdle, false);
6659 }
6660 return true;
6661}
6662
6663/**
6664 * Prepare state save and load operation.
6665 *
6666 * @returns VBox status code.
6667 * @param pDevIns Device instance of the device which registered the data unit.
6668 * @param pSSM SSM operation handle.
6669 */
6670static DECLCALLBACK(int) ataR3SaveLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6671{
6672 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6673
6674 /* sanity - the suspend notification will wait on the async stuff. */
6675 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6676 AssertLogRelMsgReturn(ataR3AsyncIOIsIdle(&pThis->aCts[i], false /*fStrict*/),
6677 ("i=%u\n", i),
6678 VERR_SSM_IDE_ASYNC_TIMEOUT);
6679 return VINF_SUCCESS;
6680}
6681
6682/**
6683 * @copydoc FNSSMDEVLIVEEXEC
6684 */
6685static DECLCALLBACK(int) ataR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
6686{
6687 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6688
6689 SSMR3PutU8(pSSM, pThis->u8Type);
6690 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6691 {
6692 SSMR3PutBool(pSSM, true); /* For controller enabled / disabled. */
6693 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
6694 {
6695 SSMR3PutBool(pSSM, pThis->aCts[i].aIfs[j].pDrvBase != NULL);
6696 SSMR3PutStrZ(pSSM, pThis->aCts[i].aIfs[j].szSerialNumber);
6697 SSMR3PutStrZ(pSSM, pThis->aCts[i].aIfs[j].szFirmwareRevision);
6698 SSMR3PutStrZ(pSSM, pThis->aCts[i].aIfs[j].szModelNumber);
6699 }
6700 }
6701
6702 return VINF_SSM_DONT_CALL_AGAIN;
6703}
6704
6705/**
6706 * @copydoc FNSSMDEVSAVEEXEC
6707 */
6708static DECLCALLBACK(int) ataR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6709{
6710 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6711
6712 ataR3LiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
6713
6714 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6715 {
6716 SSMR3PutU8(pSSM, pThis->aCts[i].iSelectedIf);
6717 SSMR3PutU8(pSSM, pThis->aCts[i].iAIOIf);
6718 SSMR3PutU8(pSSM, pThis->aCts[i].uAsyncIOState);
6719 SSMR3PutBool(pSSM, pThis->aCts[i].fChainedTransfer);
6720 SSMR3PutBool(pSSM, pThis->aCts[i].fReset);
6721 SSMR3PutBool(pSSM, pThis->aCts[i].fRedo);
6722 SSMR3PutBool(pSSM, pThis->aCts[i].fRedoIdle);
6723 SSMR3PutBool(pSSM, pThis->aCts[i].fRedoDMALastDesc);
6724 SSMR3PutMem(pSSM, &pThis->aCts[i].BmDma, sizeof(pThis->aCts[i].BmDma));
6725 SSMR3PutGCPhys32(pSSM, pThis->aCts[i].pFirstDMADesc);
6726 SSMR3PutGCPhys32(pSSM, pThis->aCts[i].pLastDMADesc);
6727 SSMR3PutGCPhys32(pSSM, pThis->aCts[i].pRedoDMABuffer);
6728 SSMR3PutU32(pSSM, pThis->aCts[i].cbRedoDMABuffer);
6729
6730 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
6731 {
6732 SSMR3PutBool(pSSM, pThis->aCts[i].aIfs[j].fLBA48);
6733 SSMR3PutBool(pSSM, pThis->aCts[i].aIfs[j].fATAPI);
6734 SSMR3PutBool(pSSM, pThis->aCts[i].aIfs[j].fIrqPending);
6735 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].cMultSectors);
6736 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].PCHSGeometry.cCylinders);
6737 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].PCHSGeometry.cHeads);
6738 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].PCHSGeometry.cSectors);
6739 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].cSectorsPerIRQ);
6740 SSMR3PutU64(pSSM, pThis->aCts[i].aIfs[j].cTotalSectors);
6741 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegFeature);
6742 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegFeatureHOB);
6743 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegError);
6744 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegNSector);
6745 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegNSectorHOB);
6746 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegSector);
6747 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegSectorHOB);
6748 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegLCyl);
6749 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegLCylHOB);
6750 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegHCyl);
6751 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegHCylHOB);
6752 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegSelect);
6753 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegStatus);
6754 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegCommand);
6755 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegDevCtl);
6756 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATATransferMode);
6757 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uTxDir);
6758 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].iBeginTransfer);
6759 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].iSourceSink);
6760 SSMR3PutBool(pSSM, pThis->aCts[i].aIfs[j].fDMA);
6761 SSMR3PutBool(pSSM, pThis->aCts[i].aIfs[j].fATAPITransfer);
6762 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].cbTotalTransfer);
6763 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].cbElementaryTransfer);
6764 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].iIOBufferCur);
6765 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].iIOBufferEnd);
6766 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].iIOBufferPIODataStart);
6767 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].iIOBufferPIODataEnd);
6768 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].iATAPILBA);
6769 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].cbATAPISector);
6770 SSMR3PutMem(pSSM, &pThis->aCts[i].aIfs[j].aATAPICmd, sizeof(pThis->aCts[i].aIfs[j].aATAPICmd));
6771 SSMR3PutMem(pSSM, &pThis->aCts[i].aIfs[j].abATAPISense, sizeof(pThis->aCts[i].aIfs[j].abATAPISense));
6772 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].cNotifiedMediaChange);
6773 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].MediaEventStatus);
6774 SSMR3PutMem(pSSM, &pThis->aCts[i].aIfs[j].Led, sizeof(pThis->aCts[i].aIfs[j].Led));
6775 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].cbIOBuffer);
6776 if (pThis->aCts[i].aIfs[j].cbIOBuffer)
6777 SSMR3PutMem(pSSM, pThis->aCts[i].aIfs[j].CTX_SUFF(pbIOBuffer), pThis->aCts[i].aIfs[j].cbIOBuffer);
6778 else
6779 Assert(pThis->aCts[i].aIfs[j].CTX_SUFF(pbIOBuffer) == NULL);
6780 }
6781 }
6782
6783 return SSMR3PutU32(pSSM, ~0); /* sanity/terminator */
6784}
6785
6786/**
6787 * Converts the LUN number into a message string.
6788 */
6789static const char *ataR3StringifyLun(unsigned iLun)
6790{
6791 switch (iLun)
6792 {
6793 case 0: return "primary master";
6794 case 1: return "primary slave";
6795 case 2: return "secondary master";
6796 case 3: return "secondary slave";
6797 default: AssertFailedReturn("unknown lun");
6798 }
6799}
6800
6801/**
6802 * FNSSMDEVLOADEXEC
6803 */
6804static DECLCALLBACK(int) ataR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6805{
6806 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6807 int rc;
6808 uint32_t u32;
6809
6810 if ( uVersion != ATA_SAVED_STATE_VERSION
6811 && uVersion != ATA_SAVED_STATE_VERSION_VBOX_30
6812 && uVersion != ATA_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE
6813 && uVersion != ATA_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS
6814 && uVersion != ATA_SAVED_STATE_VERSION_WITH_BOOL_TYPE)
6815 {
6816 AssertMsgFailed(("uVersion=%d\n", uVersion));
6817 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
6818 }
6819
6820 /*
6821 * Verify the configuration.
6822 */
6823 if (uVersion > ATA_SAVED_STATE_VERSION_VBOX_30)
6824 {
6825 uint8_t u8Type;
6826 rc = SSMR3GetU8(pSSM, &u8Type);
6827 AssertRCReturn(rc, rc);
6828 if (u8Type != pThis->u8Type)
6829 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: u8Type - saved=%u config=%u"), u8Type, pThis->u8Type);
6830
6831 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6832 {
6833 bool fEnabled;
6834 rc = SSMR3GetBool(pSSM, &fEnabled);
6835 AssertRCReturn(rc, rc);
6836 if (!fEnabled)
6837 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Ctr#%u onfig mismatch: fEnabled != true"), i);
6838
6839 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
6840 {
6841 ATADevState const *pIf = &pThis->aCts[i].aIfs[j];
6842
6843 bool fInUse;
6844 rc = SSMR3GetBool(pSSM, &fInUse);
6845 AssertRCReturn(rc, rc);
6846 if (fInUse != (pIf->pDrvBase != NULL))
6847 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
6848 N_("The %s VM is missing a %s device. Please make sure the source and target VMs have compatible storage configurations"),
6849 fInUse ? "target" : "source", ataR3StringifyLun(pIf->iLUN) );
6850
6851 char szSerialNumber[ATA_SERIAL_NUMBER_LENGTH+1];
6852 rc = SSMR3GetStrZ(pSSM, szSerialNumber, sizeof(szSerialNumber));
6853 AssertRCReturn(rc, rc);
6854 if (strcmp(szSerialNumber, pIf->szSerialNumber))
6855 LogRel(("PIIX3 ATA: LUN#%u config mismatch: Serial number - saved='%s' config='%s'\n",
6856 pIf->iLUN, szSerialNumber, pIf->szSerialNumber));
6857
6858 char szFirmwareRevision[ATA_FIRMWARE_REVISION_LENGTH+1];
6859 rc = SSMR3GetStrZ(pSSM, szFirmwareRevision, sizeof(szFirmwareRevision));
6860 AssertRCReturn(rc, rc);
6861 if (strcmp(szFirmwareRevision, pIf->szFirmwareRevision))
6862 LogRel(("PIIX3 ATA: LUN#%u config mismatch: Firmware revision - saved='%s' config='%s'\n",
6863 pIf->iLUN, szFirmwareRevision, pIf->szFirmwareRevision));
6864
6865 char szModelNumber[ATA_MODEL_NUMBER_LENGTH+1];
6866 rc = SSMR3GetStrZ(pSSM, szModelNumber, sizeof(szModelNumber));
6867 AssertRCReturn(rc, rc);
6868 if (strcmp(szModelNumber, pIf->szModelNumber))
6869 LogRel(("PIIX3 ATA: LUN#%u config mismatch: Model number - saved='%s' config='%s'\n",
6870 pIf->iLUN, szModelNumber, pIf->szModelNumber));
6871 }
6872 }
6873 }
6874 if (uPass != SSM_PASS_FINAL)
6875 return VINF_SUCCESS;
6876
6877 /*
6878 * Restore valid parts of the PCIATAState structure
6879 */
6880 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6881 {
6882 /* integrity check */
6883 if (!ataR3AsyncIOIsIdle(&pThis->aCts[i], false))
6884 {
6885 AssertMsgFailed(("Async I/O for controller %d is active\n", i));
6886 return VERR_INTERNAL_ERROR_4;
6887 }
6888
6889 SSMR3GetU8(pSSM, &pThis->aCts[i].iSelectedIf);
6890 SSMR3GetU8(pSSM, &pThis->aCts[i].iAIOIf);
6891 SSMR3GetU8(pSSM, &pThis->aCts[i].uAsyncIOState);
6892 SSMR3GetBool(pSSM, &pThis->aCts[i].fChainedTransfer);
6893 SSMR3GetBool(pSSM, (bool *)&pThis->aCts[i].fReset);
6894 SSMR3GetBool(pSSM, (bool *)&pThis->aCts[i].fRedo);
6895 SSMR3GetBool(pSSM, (bool *)&pThis->aCts[i].fRedoIdle);
6896 SSMR3GetBool(pSSM, (bool *)&pThis->aCts[i].fRedoDMALastDesc);
6897 SSMR3GetMem(pSSM, &pThis->aCts[i].BmDma, sizeof(pThis->aCts[i].BmDma));
6898 SSMR3GetGCPhys32(pSSM, &pThis->aCts[i].pFirstDMADesc);
6899 SSMR3GetGCPhys32(pSSM, &pThis->aCts[i].pLastDMADesc);
6900 SSMR3GetGCPhys32(pSSM, &pThis->aCts[i].pRedoDMABuffer);
6901 SSMR3GetU32(pSSM, &pThis->aCts[i].cbRedoDMABuffer);
6902
6903 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
6904 {
6905 SSMR3GetBool(pSSM, &pThis->aCts[i].aIfs[j].fLBA48);
6906 SSMR3GetBool(pSSM, &pThis->aCts[i].aIfs[j].fATAPI);
6907 SSMR3GetBool(pSSM, &pThis->aCts[i].aIfs[j].fIrqPending);
6908 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].cMultSectors);
6909 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].PCHSGeometry.cCylinders);
6910 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].PCHSGeometry.cHeads);
6911 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].PCHSGeometry.cSectors);
6912 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].cSectorsPerIRQ);
6913 SSMR3GetU64(pSSM, &pThis->aCts[i].aIfs[j].cTotalSectors);
6914 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegFeature);
6915 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegFeatureHOB);
6916 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegError);
6917 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegNSector);
6918 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegNSectorHOB);
6919 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegSector);
6920 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegSectorHOB);
6921 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegLCyl);
6922 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegLCylHOB);
6923 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegHCyl);
6924 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegHCylHOB);
6925 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegSelect);
6926 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegStatus);
6927 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegCommand);
6928 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegDevCtl);
6929 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATATransferMode);
6930 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uTxDir);
6931 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].iBeginTransfer);
6932 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].iSourceSink);
6933 SSMR3GetBool(pSSM, &pThis->aCts[i].aIfs[j].fDMA);
6934 SSMR3GetBool(pSSM, &pThis->aCts[i].aIfs[j].fATAPITransfer);
6935 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].cbTotalTransfer);
6936 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].cbElementaryTransfer);
6937 /* NB: cbPIOTransferLimit could be saved/restored but it's sufficient
6938 * to re-calculate it here, with a tiny risk that it could be
6939 * unnecessarily low for the current transfer only. Could be changed
6940 * when changing the saved state in the future.
6941 */
6942 pThis->aCts[i].aIfs[j].cbPIOTransferLimit = (pThis->aCts[i].aIfs[j].uATARegHCyl << 8) | pThis->aCts[i].aIfs[j].uATARegLCyl;
6943 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].iIOBufferCur);
6944 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].iIOBufferEnd);
6945 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].iIOBufferPIODataStart);
6946 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].iIOBufferPIODataEnd);
6947 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].iATAPILBA);
6948 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].cbATAPISector);
6949 SSMR3GetMem(pSSM, &pThis->aCts[i].aIfs[j].aATAPICmd, sizeof(pThis->aCts[i].aIfs[j].aATAPICmd));
6950 if (uVersion > ATA_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE)
6951 {
6952 SSMR3GetMem(pSSM, pThis->aCts[i].aIfs[j].abATAPISense, sizeof(pThis->aCts[i].aIfs[j].abATAPISense));
6953 }
6954 else
6955 {
6956 uint8_t uATAPISenseKey, uATAPIASC;
6957 memset(pThis->aCts[i].aIfs[j].abATAPISense, '\0', sizeof(pThis->aCts[i].aIfs[j].abATAPISense));
6958 pThis->aCts[i].aIfs[j].abATAPISense[0] = 0x70 | (1 << 7);
6959 pThis->aCts[i].aIfs[j].abATAPISense[7] = 10;
6960 SSMR3GetU8(pSSM, &uATAPISenseKey);
6961 SSMR3GetU8(pSSM, &uATAPIASC);
6962 pThis->aCts[i].aIfs[j].abATAPISense[2] = uATAPISenseKey & 0x0f;
6963 pThis->aCts[i].aIfs[j].abATAPISense[12] = uATAPIASC;
6964 }
6965 /** @todo triple-check this hack after passthrough is working */
6966 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].cNotifiedMediaChange);
6967 if (uVersion > ATA_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS)
6968 SSMR3GetU32(pSSM, (uint32_t*)&pThis->aCts[i].aIfs[j].MediaEventStatus);
6969 else
6970 pThis->aCts[i].aIfs[j].MediaEventStatus = ATA_EVENT_STATUS_UNCHANGED;
6971 SSMR3GetMem(pSSM, &pThis->aCts[i].aIfs[j].Led, sizeof(pThis->aCts[i].aIfs[j].Led));
6972 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].cbIOBuffer);
6973 if (pThis->aCts[i].aIfs[j].cbIOBuffer)
6974 {
6975 if (pThis->aCts[i].aIfs[j].CTX_SUFF(pbIOBuffer))
6976 SSMR3GetMem(pSSM, pThis->aCts[i].aIfs[j].CTX_SUFF(pbIOBuffer), pThis->aCts[i].aIfs[j].cbIOBuffer);
6977 else
6978 {
6979 LogRel(("ATA: No buffer for %d/%d\n", i, j));
6980 if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
6981 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("No buffer for %d/%d"), i, j);
6982
6983 /* skip the buffer if we're loading for the debugger / animator. */
6984 uint8_t u8Ignored;
6985 size_t cbLeft = pThis->aCts[i].aIfs[j].cbIOBuffer;
6986 while (cbLeft-- > 0)
6987 SSMR3GetU8(pSSM, &u8Ignored);
6988 }
6989 }
6990 else
6991 Assert(pThis->aCts[i].aIfs[j].CTX_SUFF(pbIOBuffer) == NULL);
6992 }
6993 }
6994 if (uVersion <= ATA_SAVED_STATE_VERSION_VBOX_30)
6995 SSMR3GetU8(pSSM, &pThis->u8Type);
6996
6997 rc = SSMR3GetU32(pSSM, &u32);
6998 if (RT_FAILURE(rc))
6999 return rc;
7000 if (u32 != ~0U)
7001 {
7002 AssertMsgFailed(("u32=%#x expected ~0\n", u32));
7003 rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
7004 return rc;
7005 }
7006
7007 return VINF_SUCCESS;
7008}
7009
7010
7011/**
7012 * Callback employed by ataSuspend and ataR3PowerOff.
7013 *
7014 * @returns true if we've quiesced, false if we're still working.
7015 * @param pDevIns The device instance.
7016 */
7017static DECLCALLBACK(bool) ataR3IsAsyncSuspendOrPowerOffDone(PPDMDEVINS pDevIns)
7018{
7019 return ataR3AllAsyncIOIsIdle(pDevIns);
7020}
7021
7022
7023/**
7024 * Common worker for ataSuspend and ataR3PowerOff.
7025 */
7026static void ataR3SuspendOrPowerOff(PPDMDEVINS pDevIns)
7027{
7028 if (!ataR3AllAsyncIOIsIdle(pDevIns))
7029 PDMDevHlpSetAsyncNotification(pDevIns, ataR3IsAsyncSuspendOrPowerOffDone);
7030}
7031
7032
7033/**
7034 * Power Off notification.
7035 *
7036 * @returns VBox status.
7037 * @param pDevIns The device instance data.
7038 */
7039static DECLCALLBACK(void) ataR3PowerOff(PPDMDEVINS pDevIns)
7040{
7041 Log(("%s:\n", __FUNCTION__));
7042 ataR3SuspendOrPowerOff(pDevIns);
7043}
7044
7045
7046/**
7047 * Suspend notification.
7048 *
7049 * @returns VBox status.
7050 * @param pDevIns The device instance data.
7051 */
7052static DECLCALLBACK(void) ataR3Suspend(PPDMDEVINS pDevIns)
7053{
7054 Log(("%s:\n", __FUNCTION__));
7055 ataR3SuspendOrPowerOff(pDevIns);
7056}
7057
7058
7059/**
7060 * Callback employed by ataR3Reset.
7061 *
7062 * @returns true if we've quiesced, false if we're still working.
7063 * @param pDevIns The device instance.
7064 */
7065static DECLCALLBACK(bool) ataR3IsAsyncResetDone(PPDMDEVINS pDevIns)
7066{
7067 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
7068
7069 if (!ataR3AllAsyncIOIsIdle(pDevIns))
7070 return false;
7071
7072 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7073 {
7074 PDMCritSectEnter(&pThis->aCts[i].lock, VERR_INTERNAL_ERROR);
7075 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
7076 ataR3ResetDevice(&pThis->aCts[i].aIfs[j]);
7077 PDMCritSectLeave(&pThis->aCts[i].lock);
7078 }
7079 return true;
7080}
7081
7082
7083/**
7084 * Common reset worker for ataR3Reset and ataR3Construct.
7085 *
7086 * @returns VBox status.
7087 * @param pDevIns The device instance data.
7088 * @param fConstruct Indicates who is calling.
7089 */
7090static int ataR3ResetCommon(PPDMDEVINS pDevIns, bool fConstruct)
7091{
7092 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
7093
7094 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7095 {
7096 PDMCritSectEnter(&pThis->aCts[i].lock, VERR_INTERNAL_ERROR);
7097
7098 pThis->aCts[i].iSelectedIf = 0;
7099 pThis->aCts[i].iAIOIf = 0;
7100 pThis->aCts[i].BmDma.u8Cmd = 0;
7101 /* Report that both drives present on the bus are in DMA mode. This
7102 * pretends that there is a BIOS that has set it up. Normal reset
7103 * default is 0x00. */
7104 pThis->aCts[i].BmDma.u8Status = (pThis->aCts[i].aIfs[0].pDrvBase != NULL ? BM_STATUS_D0DMA : 0)
7105 | (pThis->aCts[i].aIfs[1].pDrvBase != NULL ? BM_STATUS_D1DMA : 0);
7106 pThis->aCts[i].BmDma.pvAddr = 0;
7107
7108 pThis->aCts[i].fReset = true;
7109 pThis->aCts[i].fRedo = false;
7110 pThis->aCts[i].fRedoIdle = false;
7111 ataR3AsyncIOClearRequests(&pThis->aCts[i]);
7112 Log2(("%s: Ctl#%d: message to async I/O thread, reset controller\n", __FUNCTION__, i));
7113 ataHCAsyncIOPutRequest(&pThis->aCts[i], &g_ataResetARequest);
7114 ataHCAsyncIOPutRequest(&pThis->aCts[i], &g_ataResetCRequest);
7115
7116 PDMCritSectLeave(&pThis->aCts[i].lock);
7117 }
7118
7119 int rcRet = VINF_SUCCESS;
7120 if (!fConstruct)
7121 {
7122 /*
7123 * Setup asynchronous notification completion if the requests haven't
7124 * completed yet.
7125 */
7126 if (!ataR3IsAsyncResetDone(pDevIns))
7127 PDMDevHlpSetAsyncNotification(pDevIns, ataR3IsAsyncResetDone);
7128 }
7129 else
7130 {
7131 /*
7132 * Wait for the requests for complete.
7133 *
7134 * Would be real nice if we could do it all from EMT(0) and not
7135 * involve the worker threads, then we could dispense with all the
7136 * waiting and semaphore ping-pong here...
7137 */
7138 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7139 {
7140 if (pThis->aCts[i].AsyncIOThread != NIL_RTTHREAD)
7141 {
7142 int rc = PDMCritSectEnter(&pThis->aCts[i].AsyncIORequestLock, VERR_IGNORED);
7143 AssertRC(rc);
7144
7145 ASMAtomicWriteBool(&pThis->aCts[i].fSignalIdle, true);
7146 rc = RTThreadUserReset(pThis->aCts[i].AsyncIOThread);
7147 AssertRC(rc);
7148
7149 rc = PDMCritSectLeave(&pThis->aCts[i].AsyncIORequestLock);
7150 AssertRC(rc);
7151
7152 if (!ataR3AsyncIOIsIdle(&pThis->aCts[i], false /*fStrict*/))
7153 {
7154 rc = RTThreadUserWait(pThis->aCts[i].AsyncIOThread, 30*1000 /*ms*/);
7155 if (RT_FAILURE(rc))
7156 rc = RTThreadUserWait(pThis->aCts[i].AsyncIOThread, 1000 /*ms*/);
7157 if (RT_FAILURE(rc))
7158 {
7159 AssertRC(rc);
7160 rcRet = rc;
7161 }
7162 }
7163 }
7164 ASMAtomicWriteBool(&pThis->aCts[i].fSignalIdle, false);
7165 }
7166 if (RT_SUCCESS(rcRet))
7167 {
7168 rcRet = ataR3IsAsyncResetDone(pDevIns) ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
7169 AssertRC(rcRet);
7170 }
7171 }
7172 return rcRet;
7173}
7174
7175/**
7176 * Reset notification.
7177 *
7178 * @param pDevIns The device instance data.
7179 */
7180static DECLCALLBACK(void) ataR3Reset(PPDMDEVINS pDevIns)
7181{
7182 ataR3ResetCommon(pDevIns, false /*fConstruct*/);
7183}
7184
7185/**
7186 * @copydoc FNPDMDEVRELOCATE
7187 */
7188static DECLCALLBACK(void) ataR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
7189{
7190 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
7191
7192 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7193 {
7194 pThis->aCts[i].pDevInsRC += offDelta;
7195 pThis->aCts[i].aIfs[0].pDevInsRC += offDelta;
7196 pThis->aCts[i].aIfs[0].pControllerRC += offDelta;
7197 ataR3RelocBuffer(pDevIns, &pThis->aCts[i].aIfs[0]);
7198 pThis->aCts[i].aIfs[1].pDevInsRC += offDelta;
7199 pThis->aCts[i].aIfs[1].pControllerRC += offDelta;
7200 ataR3RelocBuffer(pDevIns, &pThis->aCts[i].aIfs[1]);
7201 }
7202}
7203
7204/**
7205 * Destroy a driver instance.
7206 *
7207 * Most VM resources are freed by the VM. This callback is provided so that any non-VM
7208 * resources can be freed correctly.
7209 *
7210 * @param pDevIns The device instance data.
7211 */
7212static DECLCALLBACK(int) ataR3Destruct(PPDMDEVINS pDevIns)
7213{
7214 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
7215 int rc;
7216
7217 Log(("ataR3Destruct\n"));
7218 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
7219
7220 /*
7221 * Tell the async I/O threads to terminate.
7222 */
7223 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7224 {
7225 if (pThis->aCts[i].AsyncIOThread != NIL_RTTHREAD)
7226 {
7227 ASMAtomicWriteU32(&pThis->aCts[i].fShutdown, true);
7228 rc = SUPSemEventSignal(pThis->aCts[i].pSupDrvSession, pThis->aCts[i].hAsyncIOSem);
7229 AssertRC(rc);
7230 rc = RTSemEventSignal(pThis->aCts[i].SuspendIOSem);
7231 AssertRC(rc);
7232 }
7233 }
7234
7235 /*
7236 * Wait for the threads to terminate before destroying their resources.
7237 */
7238 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7239 {
7240 if (pThis->aCts[i].AsyncIOThread != NIL_RTTHREAD)
7241 {
7242 rc = RTThreadWait(pThis->aCts[i].AsyncIOThread, 30000 /* 30 s*/, NULL);
7243 if (RT_SUCCESS(rc))
7244 pThis->aCts[i].AsyncIOThread = NIL_RTTHREAD;
7245 else
7246 LogRel(("PIIX3 ATA Dtor: Ctl#%u is still executing, DevSel=%d AIOIf=%d CmdIf0=%#04x CmdIf1=%#04x rc=%Rrc\n",
7247 i, pThis->aCts[i].iSelectedIf, pThis->aCts[i].iAIOIf,
7248 pThis->aCts[i].aIfs[0].uATARegCommand, pThis->aCts[i].aIfs[1].uATARegCommand, rc));
7249 }
7250 }
7251
7252 /*
7253 * Free resources.
7254 */
7255 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7256 {
7257 if (PDMCritSectIsInitialized(&pThis->aCts[i].AsyncIORequestLock))
7258 PDMR3CritSectDelete(&pThis->aCts[i].AsyncIORequestLock);
7259 if (pThis->aCts[i].hAsyncIOSem != NIL_SUPSEMEVENT)
7260 {
7261 SUPSemEventClose(pThis->aCts[i].pSupDrvSession, pThis->aCts[i].hAsyncIOSem);
7262 pThis->aCts[i].hAsyncIOSem = NIL_SUPSEMEVENT;
7263 }
7264 if (pThis->aCts[i].SuspendIOSem != NIL_RTSEMEVENT)
7265 {
7266 RTSemEventDestroy(pThis->aCts[i].SuspendIOSem);
7267 pThis->aCts[i].SuspendIOSem = NIL_RTSEMEVENT;
7268 }
7269
7270 /* try one final time */
7271 if (pThis->aCts[i].AsyncIOThread != NIL_RTTHREAD)
7272 {
7273 rc = RTThreadWait(pThis->aCts[i].AsyncIOThread, 1 /*ms*/, NULL);
7274 if (RT_SUCCESS(rc))
7275 {
7276 pThis->aCts[i].AsyncIOThread = NIL_RTTHREAD;
7277 LogRel(("PIIX3 ATA Dtor: Ctl#%u actually completed.\n", i));
7278 }
7279 }
7280
7281 for (uint32_t iIf = 0; iIf < RT_ELEMENTS(pThis->aCts[i].aIfs); iIf++)
7282 {
7283 if (pThis->aCts[i].aIfs[iIf].pTrackList)
7284 {
7285 ATAPIPassthroughTrackListDestroy(pThis->aCts[i].aIfs[iIf].pTrackList);
7286 pThis->aCts[i].aIfs[iIf].pTrackList = NULL;
7287 }
7288 }
7289 }
7290
7291 return VINF_SUCCESS;
7292}
7293
7294/**
7295 * Convert config value to DEVPCBIOSBOOT.
7296 *
7297 * @returns VBox status code.
7298 * @param pDevIns The device instance data.
7299 * @param pCfg Configuration handle.
7300 * @param penmChipset Where to store the chipset type.
7301 */
7302static int ataR3ControllerFromCfg(PPDMDEVINS pDevIns, PCFGMNODE pCfg, CHIPSET *penmChipset)
7303{
7304 char szType[20];
7305
7306 int rc = CFGMR3QueryStringDef(pCfg, "Type", &szType[0], sizeof(szType), "PIIX4");
7307 if (RT_FAILURE(rc))
7308 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
7309 N_("Configuration error: Querying \"Type\" as a string failed"));
7310 if (!strcmp(szType, "PIIX3"))
7311 *penmChipset = CHIPSET_PIIX3;
7312 else if (!strcmp(szType, "PIIX4"))
7313 *penmChipset = CHIPSET_PIIX4;
7314 else if (!strcmp(szType, "ICH6"))
7315 *penmChipset = CHIPSET_ICH6;
7316 else
7317 {
7318 PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
7319 N_("Configuration error: The \"Type\" value \"%s\" is unknown"),
7320 szType);
7321 rc = VERR_INTERNAL_ERROR;
7322 }
7323 return rc;
7324}
7325
7326/**
7327 * @interface_method_impl{PDMDEVREG,pfnConstruct}
7328 */
7329static DECLCALLBACK(int) ataR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
7330{
7331 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
7332 PPDMIBASE pBase;
7333 int rc;
7334 bool fRCEnabled;
7335 bool fR0Enabled;
7336 uint32_t DelayIRQMillies;
7337
7338 Assert(iInstance == 0);
7339 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7340
7341 /*
7342 * Initialize NIL handle values (for the destructor).
7343 */
7344 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7345 {
7346 pThis->aCts[i].hAsyncIOSem = NIL_SUPSEMEVENT;
7347 pThis->aCts[i].SuspendIOSem = NIL_RTSEMEVENT;
7348 pThis->aCts[i].AsyncIOThread = NIL_RTTHREAD;
7349 }
7350
7351 /*
7352 * Validate and read configuration.
7353 */
7354 if (!CFGMR3AreValuesValid(pCfg,
7355 "GCEnabled\0"
7356 "R0Enabled\0"
7357 "IRQDelay\0"
7358 "Type\0")
7359 /** @todo || invalid keys */)
7360 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
7361 N_("PIIX3 configuration error: unknown option specified"));
7362
7363 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fRCEnabled, true);
7364 if (RT_FAILURE(rc))
7365 return PDMDEV_SET_ERROR(pDevIns, rc,
7366 N_("PIIX3 configuration error: failed to read GCEnabled as boolean"));
7367 Log(("%s: fRCEnabled=%d\n", __FUNCTION__, fRCEnabled));
7368
7369 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
7370 if (RT_FAILURE(rc))
7371 return PDMDEV_SET_ERROR(pDevIns, rc,
7372 N_("PIIX3 configuration error: failed to read R0Enabled as boolean"));
7373 Log(("%s: fR0Enabled=%d\n", __FUNCTION__, fR0Enabled));
7374
7375 rc = CFGMR3QueryU32Def(pCfg, "IRQDelay", &DelayIRQMillies, 0);
7376 if (RT_FAILURE(rc))
7377 return PDMDEV_SET_ERROR(pDevIns, rc,
7378 N_("PIIX3 configuration error: failed to read IRQDelay as integer"));
7379 Log(("%s: DelayIRQMillies=%d\n", __FUNCTION__, DelayIRQMillies));
7380 Assert(DelayIRQMillies < 50);
7381
7382 CHIPSET enmChipset = CHIPSET_PIIX3;
7383 rc = ataR3ControllerFromCfg(pDevIns, pCfg, &enmChipset);
7384 if (RT_FAILURE(rc))
7385 return rc;
7386 pThis->u8Type = (uint8_t)enmChipset;
7387
7388 /*
7389 * Initialize data (most of it anyway).
7390 */
7391 /* Status LUN. */
7392 pThis->IBase.pfnQueryInterface = ataR3Status_QueryInterface;
7393 pThis->ILeds.pfnQueryStatusLed = ataR3Status_QueryStatusLed;
7394
7395 /* PCI configuration space. */
7396 PCIDevSetVendorId(&pThis->dev, 0x8086); /* Intel */
7397
7398 /*
7399 * When adding more IDE chipsets, don't forget to update pci_bios_init_device()
7400 * as it explicitly checks for PCI id for IDE controllers.
7401 */
7402 switch (pThis->u8Type)
7403 {
7404 case CHIPSET_ICH6:
7405 PCIDevSetDeviceId(&pThis->dev, 0x269e); /* ICH6 IDE */
7406 /** @todo: do we need it? Do we need anything else? */
7407 pThis->dev.config[0x48] = 0x00; /* UDMACTL */
7408 pThis->dev.config[0x4A] = 0x00; /* UDMATIM */
7409 pThis->dev.config[0x4B] = 0x00;
7410 {
7411 /*
7412 * See www.intel.com/Assets/PDF/manual/298600.pdf p. 30
7413 * Report
7414 * WR_Ping-Pong_EN: must be set
7415 * PCR0, PCR1: 80-pin primary cable reporting for both disks
7416 * SCR0, SCR1: 80-pin secondary cable reporting for both disks
7417 */
7418 uint16_t u16Config = (1<<10) | (1<<7) | (1<<6) | (1<<5) | (1<<4) ;
7419 pThis->dev.config[0x54] = u16Config & 0xff;
7420 pThis->dev.config[0x55] = u16Config >> 8;
7421 }
7422 break;
7423 case CHIPSET_PIIX4:
7424 PCIDevSetDeviceId(&pThis->dev, 0x7111); /* PIIX4 IDE */
7425 PCIDevSetRevisionId(&pThis->dev, 0x01); /* PIIX4E */
7426 pThis->dev.config[0x48] = 0x00; /* UDMACTL */
7427 pThis->dev.config[0x4A] = 0x00; /* UDMATIM */
7428 pThis->dev.config[0x4B] = 0x00;
7429 break;
7430 case CHIPSET_PIIX3:
7431 PCIDevSetDeviceId(&pThis->dev, 0x7010); /* PIIX3 IDE */
7432 break;
7433 default:
7434 AssertMsgFailed(("Unsupported IDE chipset type: %d\n", pThis->u8Type));
7435 }
7436
7437 PCIDevSetCommand( &pThis->dev, PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS | PCI_COMMAND_BUSMASTER);
7438 PCIDevSetClassProg( &pThis->dev, 0x8a); /* programming interface = PCI_IDE bus master is supported */
7439 PCIDevSetClassSub( &pThis->dev, 0x01); /* class_sub = PCI_IDE */
7440 PCIDevSetClassBase( &pThis->dev, 0x01); /* class_base = PCI_mass_storage */
7441 PCIDevSetHeaderType(&pThis->dev, 0x00);
7442
7443 pThis->pDevIns = pDevIns;
7444 pThis->fRCEnabled = fRCEnabled;
7445 pThis->fR0Enabled = fR0Enabled;
7446 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7447 {
7448 pThis->aCts[i].pDevInsR3 = pDevIns;
7449 pThis->aCts[i].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
7450 pThis->aCts[i].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
7451 pThis->aCts[i].DelayIRQMillies = (uint32_t)DelayIRQMillies;
7452 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
7453 {
7454 ATADevState *pIf = &pThis->aCts[i].aIfs[j];
7455
7456 pIf->iLUN = i * RT_ELEMENTS(pThis->aCts) + j;
7457 pIf->pDevInsR3 = pDevIns;
7458 pIf->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
7459 pIf->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
7460 pIf->pControllerR3 = &pThis->aCts[i];
7461 pIf->pControllerR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pDevIns), &pThis->aCts[i]);
7462 pIf->pControllerRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), &pThis->aCts[i]);
7463 pIf->IBase.pfnQueryInterface = ataR3QueryInterface;
7464 pIf->IMountNotify.pfnMountNotify = ataR3MountNotify;
7465 pIf->IMountNotify.pfnUnmountNotify = ataR3UnmountNotify;
7466 pIf->IPort.pfnQueryDeviceLocation = ataR3QueryDeviceLocation;
7467 pIf->Led.u32Magic = PDMLED_MAGIC;
7468 }
7469 }
7470
7471 Assert(RT_ELEMENTS(pThis->aCts) == 2);
7472 pThis->aCts[0].irq = 14;
7473 pThis->aCts[0].IOPortBase1 = 0x1f0;
7474 pThis->aCts[0].IOPortBase2 = 0x3f6;
7475 pThis->aCts[1].irq = 15;
7476 pThis->aCts[1].IOPortBase1 = 0x170;
7477 pThis->aCts[1].IOPortBase2 = 0x376;
7478
7479 /*
7480 * Set the default critical section to NOP as we lock on controller level.
7481 */
7482 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
7483 AssertRCReturn(rc, rc);
7484
7485 /*
7486 * Register the PCI device.
7487 * N.B. There's a hack in the PIIX3 PCI bridge device to assign this
7488 * device the slot next to itself.
7489 */
7490 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->dev);
7491 if (RT_FAILURE(rc))
7492 return PDMDEV_SET_ERROR(pDevIns, rc,
7493 N_("PIIX3 cannot register PCI device"));
7494 //AssertMsg(pThis->dev.devfn == 9 || iInstance != 0, ("pThis->dev.devfn=%d\n", pThis->dev.devfn));
7495 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 4, 0x10, PCI_ADDRESS_SPACE_IO, ataR3BMDMAIORangeMap);
7496 if (RT_FAILURE(rc))
7497 return PDMDEV_SET_ERROR(pDevIns, rc,
7498 N_("PIIX3 cannot register PCI I/O region for BMDMA"));
7499
7500 /*
7501 * Register the I/O ports.
7502 * The ports are all hardcoded and enforced by the PIIX3 host bridge controller.
7503 */
7504 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7505 {
7506 rc = PDMDevHlpIOPortRegister(pDevIns, pThis->aCts[i].IOPortBase1, 1, (RTHCPTR)(uintptr_t)i,
7507 ataIOPortWrite1Data, ataIOPortRead1Data,
7508 ataIOPortWriteStr1Data, ataIOPortReadStr1Data, "ATA I/O Base 1 - Data");
7509 AssertLogRelRCReturn(rc, rc);
7510 rc = PDMDevHlpIOPortRegister(pDevIns, pThis->aCts[i].IOPortBase1 + 1, 7, (RTHCPTR)(uintptr_t)i,
7511 ataIOPortWrite1Other, ataIOPortRead1Other, NULL, NULL, "ATA I/O Base 1 - Other");
7512
7513 AssertLogRelRCReturn(rc, rc);
7514 if (fRCEnabled)
7515 {
7516 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->aCts[i].IOPortBase1, 1, (RTGCPTR)i,
7517 "ataIOPortWrite1Data", "ataIOPortRead1Data",
7518 "ataIOPortWriteStr1Data", "ataIOPortReadStr1Data", "ATA I/O Base 1 - Data");
7519 AssertLogRelRCReturn(rc, rc);
7520 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->aCts[i].IOPortBase1 + 1, 7, (RTGCPTR)i,
7521 "ataIOPortWrite1Other", "ataIOPortRead1Other", NULL, NULL, "ATA I/O Base 1 - Other");
7522 AssertLogRelRCReturn(rc, rc);
7523 }
7524
7525 if (fR0Enabled)
7526 {
7527#if 0
7528 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->aCts[i].IOPortBase1, 1, (RTR0PTR)i,
7529 "ataIOPortWrite1Data", "ataIOPortRead1Data", NULL, NULL, "ATA I/O Base 1 - Data");
7530#else
7531 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->aCts[i].IOPortBase1, 1, (RTR0PTR)i,
7532 "ataIOPortWrite1Data", "ataIOPortRead1Data",
7533 "ataIOPortWriteStr1Data", "ataIOPortReadStr1Data", "ATA I/O Base 1 - Data");
7534#endif
7535 AssertLogRelRCReturn(rc, rc);
7536 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->aCts[i].IOPortBase1 + 1, 7, (RTR0PTR)i,
7537 "ataIOPortWrite1Other", "ataIOPortRead1Other", NULL, NULL, "ATA I/O Base 1 - Other");
7538 AssertLogRelRCReturn(rc, rc);
7539 }
7540
7541 rc = PDMDevHlpIOPortRegister(pDevIns, pThis->aCts[i].IOPortBase2, 1, (RTHCPTR)(uintptr_t)i,
7542 ataIOPortWrite2, ataIOPortRead2, NULL, NULL, "ATA I/O Base 2");
7543 if (RT_FAILURE(rc))
7544 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register base2 I/O handlers"));
7545
7546 if (fRCEnabled)
7547 {
7548 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->aCts[i].IOPortBase2, 1, (RTGCPTR)i,
7549 "ataIOPortWrite2", "ataIOPortRead2", NULL, NULL, "ATA I/O Base 2");
7550 if (RT_FAILURE(rc))
7551 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register base2 I/O handlers (GC)"));
7552 }
7553 if (fR0Enabled)
7554 {
7555 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->aCts[i].IOPortBase2, 1, (RTR0PTR)i,
7556 "ataIOPortWrite2", "ataIOPortRead2", NULL, NULL, "ATA I/O Base 2");
7557 if (RT_FAILURE(rc))
7558 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register base2 I/O handlers (R0)"));
7559 }
7560
7561 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
7562 {
7563 ATADevState *pIf = &pThis->aCts[i].aIfs[j];
7564 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatATADMA, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
7565 "Number of ATA DMA transfers.", "/Devices/IDE%d/ATA%d/Unit%d/DMA", iInstance, i, j);
7566 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatATAPIO, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
7567 "Number of ATA PIO transfers.", "/Devices/IDE%d/ATA%d/Unit%d/PIO", iInstance, i, j);
7568 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatATAPIDMA, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
7569 "Number of ATAPI DMA transfers.", "/Devices/IDE%d/ATA%d/Unit%d/AtapiDMA", iInstance, i, j);
7570 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatATAPIPIO, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
7571 "Number of ATAPI PIO transfers.", "/Devices/IDE%d/ATA%d/Unit%d/AtapiPIO", iInstance, i, j);
7572#ifdef VBOX_WITH_STATISTICS /** @todo release too. */
7573 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatReads, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
7574 "Profiling of the read operations.", "/Devices/IDE%d/ATA%d/Unit%d/Reads", iInstance, i, j);
7575#endif
7576 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatBytesRead, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
7577 "Amount of data read.", "/Devices/IDE%d/ATA%d/Unit%d/ReadBytes", iInstance, i, j);
7578#ifdef VBOX_INSTRUMENT_DMA_WRITES
7579 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatInstrVDWrites,STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
7580 "Profiling of the VD DMA write operations.", "/Devices/IDE%d/ATA%d/Unit%d/InstrVDWrites", iInstance, i, j);
7581#endif
7582#ifdef VBOX_WITH_STATISTICS
7583 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatWrites, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
7584 "Profiling of the write operations.", "/Devices/IDE%d/ATA%d/Unit%d/Writes", iInstance, i, j);
7585#endif
7586 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatBytesWritten, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
7587 "Amount of data written.", "/Devices/IDE%d/ATA%d/Unit%d/WrittenBytes", iInstance, i, j);
7588#ifdef VBOX_WITH_STATISTICS
7589 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatFlushes, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
7590 "Profiling of the flush operations.", "/Devices/IDE%d/ATA%d/Unit%d/Flushes", iInstance, i, j);
7591#endif
7592 }
7593#ifdef VBOX_WITH_STATISTICS /** @todo release too. */
7594 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatAsyncOps, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
7595 "The number of async operations.", "/Devices/IDE%d/ATA%d/Async/Operations", iInstance, i);
7596 /** @todo STAMUNIT_MICROSECS */
7597 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatAsyncMinWait, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
7598 "Minimum wait in microseconds.", "/Devices/IDE%d/ATA%d/Async/MinWait", iInstance, i);
7599 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatAsyncMaxWait, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
7600 "Maximum wait in microseconds.", "/Devices/IDE%d/ATA%d/Async/MaxWait", iInstance, i);
7601 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatAsyncTimeUS, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
7602 "Total time spent in microseconds.", "/Devices/IDE%d/ATA%d/Async/TotalTimeUS", iInstance, i);
7603 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatAsyncTime, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
7604 "Profiling of async operations.", "/Devices/IDE%d/ATA%d/Async/Time", iInstance, i);
7605 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatLockWait, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
7606 "Profiling of locks.", "/Devices/IDE%d/ATA%d/Async/LockWait", iInstance, i);
7607#endif /* VBOX_WITH_STATISTICS */
7608
7609 /* Initialize per-controller critical section. */
7610 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->aCts[i].lock, RT_SRC_POS, "ATA#%u-Ctl", i);
7611 AssertLogRelRCReturn(rc, rc);
7612
7613 /* Initialize per-controller async I/O request critical section. */
7614 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->aCts[i].AsyncIORequestLock, RT_SRC_POS, "ATA#%u-Req", i);
7615 AssertLogRelRCReturn(rc, rc);
7616 }
7617
7618 /*
7619 * Attach status driver (optional).
7620 */
7621 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
7622 if (RT_SUCCESS(rc))
7623 {
7624 pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
7625 pThis->pMediaNotify = PDMIBASE_QUERY_INTERFACE(pBase, PDMIMEDIANOTIFY);
7626 }
7627 else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
7628 {
7629 AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
7630 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot attach to status driver"));
7631 }
7632
7633 /*
7634 * Attach the units.
7635 */
7636 uint32_t cbTotalBuffer = 0;
7637 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
7638 {
7639 PATACONTROLLER pCtl = &pThis->aCts[i];
7640
7641 /*
7642 * Start the worker thread.
7643 */
7644 pCtl->uAsyncIOState = ATA_AIO_NEW;
7645 pCtl->pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
7646 rc = SUPSemEventCreate(pCtl->pSupDrvSession, &pCtl->hAsyncIOSem);
7647 AssertLogRelRCReturn(rc, rc);
7648 rc = RTSemEventCreate(&pCtl->SuspendIOSem);
7649 AssertLogRelRCReturn(rc, rc);
7650
7651 ataR3AsyncIOClearRequests(pCtl);
7652 rc = RTThreadCreateF(&pCtl->AsyncIOThread, ataR3AsyncIOThread, (void *)pCtl, 128*1024 /*cbStack*/,
7653 RTTHREADTYPE_IO, RTTHREADFLAGS_WAITABLE, "ATA-%u", i);
7654 AssertLogRelRCReturn(rc, rc);
7655 Assert( pCtl->AsyncIOThread != NIL_RTTHREAD && pCtl->hAsyncIOSem != NIL_SUPSEMEVENT
7656 && pCtl->SuspendIOSem != NIL_RTSEMEVENT && PDMCritSectIsInitialized(&pCtl->AsyncIORequestLock));
7657 Log(("%s: controller %d AIO thread id %#x; sem %p susp_sem %p\n", __FUNCTION__, i, pCtl->AsyncIOThread, pCtl->hAsyncIOSem, pCtl->SuspendIOSem));
7658
7659 for (uint32_t j = 0; j < RT_ELEMENTS(pCtl->aIfs); j++)
7660 {
7661 static const char *s_apszDescs[RT_ELEMENTS(pThis->aCts)][RT_ELEMENTS(pCtl->aIfs)] =
7662 {
7663 { "Primary Master", "Primary Slave" },
7664 { "Secondary Master", "Secondary Slave" }
7665 };
7666
7667 /*
7668 * Try attach the block device and get the interfaces,
7669 * required as well as optional.
7670 */
7671 ATADevState *pIf = &pCtl->aIfs[j];
7672
7673 rc = PDMDevHlpDriverAttach(pDevIns, pIf->iLUN, &pIf->IBase, &pIf->pDrvBase, s_apszDescs[i][j]);
7674 if (RT_SUCCESS(rc))
7675 {
7676 rc = ataR3ConfigLun(pDevIns, pIf);
7677 if (RT_SUCCESS(rc))
7678 {
7679 /*
7680 * Init vendor product data.
7681 */
7682 static const char *s_apszCFGMKeys[RT_ELEMENTS(pThis->aCts)][RT_ELEMENTS(pCtl->aIfs)] =
7683 {
7684 { "PrimaryMaster", "PrimarySlave" },
7685 { "SecondaryMaster", "SecondarySlave" }
7686 };
7687
7688 /* Generate a default serial number. */
7689 char szSerial[ATA_SERIAL_NUMBER_LENGTH+1];
7690 RTUUID Uuid;
7691 if (pIf->pDrvBlock)
7692 rc = pIf->pDrvBlock->pfnGetUuid(pIf->pDrvBlock, &Uuid);
7693 else
7694 RTUuidClear(&Uuid);
7695
7696 if (RT_FAILURE(rc) || RTUuidIsNull(&Uuid))
7697 {
7698 /* Generate a predictable serial for drives which don't have a UUID. */
7699 RTStrPrintf(szSerial, sizeof(szSerial), "VB%x-%04x%04x",
7700 pIf->iLUN + pDevIns->iInstance * 32,
7701 pThis->aCts[i].IOPortBase1, pThis->aCts[i].IOPortBase2);
7702 }
7703 else
7704 RTStrPrintf(szSerial, sizeof(szSerial), "VB%08x-%08x", Uuid.au32[0], Uuid.au32[3]);
7705
7706 /* Get user config if present using defaults otherwise. */
7707 PCFGMNODE pCfgNode = CFGMR3GetChild(pCfg, s_apszCFGMKeys[i][j]);
7708 rc = CFGMR3QueryStringDef(pCfgNode, "SerialNumber", pIf->szSerialNumber, sizeof(pIf->szSerialNumber),
7709 szSerial);
7710 if (RT_FAILURE(rc))
7711 {
7712 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
7713 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
7714 N_("PIIX3 configuration error: \"SerialNumber\" is longer than 20 bytes"));
7715 return PDMDEV_SET_ERROR(pDevIns, rc,
7716 N_("PIIX3 configuration error: failed to read \"SerialNumber\" as string"));
7717 }
7718
7719 rc = CFGMR3QueryStringDef(pCfgNode, "FirmwareRevision", pIf->szFirmwareRevision, sizeof(pIf->szFirmwareRevision),
7720 "1.0");
7721 if (RT_FAILURE(rc))
7722 {
7723 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
7724 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
7725 N_("PIIX3 configuration error: \"FirmwareRevision\" is longer than 8 bytes"));
7726 return PDMDEV_SET_ERROR(pDevIns, rc,
7727 N_("PIIX3 configuration error: failed to read \"FirmwareRevision\" as string"));
7728 }
7729
7730 rc = CFGMR3QueryStringDef(pCfgNode, "ModelNumber", pIf->szModelNumber, sizeof(pIf->szModelNumber),
7731 pIf->fATAPI ? "VBOX CD-ROM" : "VBOX HARDDISK");
7732 if (RT_FAILURE(rc))
7733 {
7734 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
7735 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
7736 N_("PIIX3 configuration error: \"ModelNumber\" is longer than 40 bytes"));
7737 return PDMDEV_SET_ERROR(pDevIns, rc,
7738 N_("PIIX3 configuration error: failed to read \"ModelNumber\" as string"));
7739 }
7740
7741 rc = CFGMR3QueryBoolDef(pCfgNode, "NonRotationalMedium", &pIf->fNonRotational, false);
7742 if (RT_FAILURE(rc))
7743 return PDMDEV_SET_ERROR(pDevIns, rc,
7744 N_("PIIX3 configuration error: failed to read \"NonRotationalMedium\" as boolean"));
7745
7746 /* There are three other identification strings for CD drives used for INQUIRY */
7747 if (pIf->fATAPI)
7748 {
7749 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIVendorId", pIf->szInquiryVendorId, sizeof(pIf->szInquiryVendorId),
7750 "VBOX");
7751 if (RT_FAILURE(rc))
7752 {
7753 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
7754 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
7755 N_("PIIX3 configuration error: \"ATAPIVendorId\" is longer than 16 bytes"));
7756 return PDMDEV_SET_ERROR(pDevIns, rc,
7757 N_("PIIX3 configuration error: failed to read \"ATAPIVendorId\" as string"));
7758 }
7759
7760 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIProductId", pIf->szInquiryProductId, sizeof(pIf->szInquiryProductId),
7761 "CD-ROM");
7762 if (RT_FAILURE(rc))
7763 {
7764 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
7765 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
7766 N_("PIIX3 configuration error: \"ATAPIProductId\" is longer than 16 bytes"));
7767 return PDMDEV_SET_ERROR(pDevIns, rc,
7768 N_("PIIX3 configuration error: failed to read \"ATAPIProductId\" as string"));
7769 }
7770
7771 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIRevision", pIf->szInquiryRevision, sizeof(pIf->szInquiryRevision),
7772 "1.0");
7773 if (RT_FAILURE(rc))
7774 {
7775 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
7776 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
7777 N_("PIIX3 configuration error: \"ATAPIRevision\" is longer than 4 bytes"));
7778 return PDMDEV_SET_ERROR(pDevIns, rc,
7779 N_("PIIX3 configuration error: failed to read \"ATAPIRevision\" as string"));
7780 }
7781
7782 rc = CFGMR3QueryBoolDef(pCfgNode, "OverwriteInquiry", &pIf->fOverwriteInquiry, true);
7783 if (RT_FAILURE(rc))
7784 return PDMDEV_SET_ERROR(pDevIns, rc,
7785 N_("PIIX3 configuration error: failed to read \"OverwriteInquiry\" as boolean"));
7786 }
7787 }
7788
7789 }
7790 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
7791 {
7792 pIf->pDrvBase = NULL;
7793 pIf->pDrvBlock = NULL;
7794 pIf->cbIOBuffer = 0;
7795 pIf->pbIOBufferR3 = NULL;
7796 pIf->pbIOBufferR0 = NIL_RTR0PTR;
7797 pIf->pbIOBufferRC = NIL_RTGCPTR;
7798 LogRel(("PIIX3 ATA: LUN#%d: no unit\n", pIf->iLUN));
7799 }
7800 else
7801 {
7802 switch (rc)
7803 {
7804 case VERR_ACCESS_DENIED:
7805 /* Error already cached by DrvHostBase */
7806 return rc;
7807 default:
7808 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
7809 N_("PIIX3 cannot attach drive to the %s"),
7810 s_apszDescs[i][j]);
7811 }
7812 }
7813 cbTotalBuffer += pIf->cbIOBuffer;
7814 }
7815 }
7816
7817 rc = PDMDevHlpSSMRegisterEx(pDevIns, ATA_SAVED_STATE_VERSION, sizeof(*pThis) + cbTotalBuffer, NULL,
7818 NULL, ataR3LiveExec, NULL,
7819 ataR3SaveLoadPrep, ataR3SaveExec, NULL,
7820 ataR3SaveLoadPrep, ataR3LoadExec, NULL);
7821 if (RT_FAILURE(rc))
7822 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register save state handlers"));
7823
7824 /*
7825 * Initialize the device state.
7826 */
7827 return ataR3ResetCommon(pDevIns, true /*fConstruct*/);
7828}
7829
7830
7831/**
7832 * The device registration structure.
7833 */
7834const PDMDEVREG g_DevicePIIX3IDE =
7835{
7836 /* u32Version */
7837 PDM_DEVREG_VERSION,
7838 /* szName */
7839 "piix3ide",
7840 /* szRCMod */
7841 "VBoxDDRC.rc",
7842 /* szR0Mod */
7843 "VBoxDDR0.r0",
7844 /* pszDescription */
7845 "Intel PIIX3 ATA controller.\n"
7846 " LUN #0 is primary master.\n"
7847 " LUN #1 is primary slave.\n"
7848 " LUN #2 is secondary master.\n"
7849 " LUN #3 is secondary slave.\n"
7850 " LUN #999 is the LED/Status connector.",
7851 /* fFlags */
7852 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 |
7853 PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION | PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION |
7854 PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION,
7855 /* fClass */
7856 PDM_DEVREG_CLASS_STORAGE,
7857 /* cMaxInstances */
7858 1,
7859 /* cbInstance */
7860 sizeof(PCIATAState),
7861 /* pfnConstruct */
7862 ataR3Construct,
7863 /* pfnDestruct */
7864 ataR3Destruct,
7865 /* pfnRelocate */
7866 ataR3Relocate,
7867 /* pfnMemSetup */
7868 NULL,
7869 /* pfnPowerOn */
7870 NULL,
7871 /* pfnReset */
7872 ataR3Reset,
7873 /* pfnSuspend */
7874 ataR3Suspend,
7875 /* pfnResume */
7876 ataR3Resume,
7877 /* pfnAttach */
7878 ataR3Attach,
7879 /* pfnDetach */
7880 ataR3Detach,
7881 /* pfnQueryInterface. */
7882 NULL,
7883 /* pfnInitComplete */
7884 NULL,
7885 /* pfnPowerOff */
7886 ataR3PowerOff,
7887 /* pfnSoftReset */
7888 NULL,
7889 /* u32VersionEnd */
7890 PDM_DEVREG_VERSION
7891};
7892#endif /* IN_RING3 */
7893#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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