VirtualBox

source: vbox/trunk/src/VBox/Devices/Storage/DevAHCI.cpp@ 58466

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1/* $Id: DevAHCI.cpp 58170 2015-10-12 09:27:14Z vboxsync $ */
2/** @file
3 * DevAHCI - AHCI controller device (disk and cdrom).
4 *
5 * Implements the AHCI standard 1.1
6 */
7
8/*
9 * Copyright (C) 2006-2015 Oracle Corporation
10 *
11 * This file is part of VirtualBox Open Source Edition (OSE), as
12 * available from http://www.virtualbox.org. This file is free software;
13 * you can redistribute it and/or modify it under the terms of the GNU
14 * General Public License (GPL) as published by the Free Software
15 * Foundation, in version 2 as it comes in the "COPYING" file of the
16 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18 */
19
20/** @page pg_dev_ahci AHCI - Advanced Host Controller Interface Emulation.
21 *
22 * This component implements an AHCI serial ATA controller. The device is split
23 * into two parts. The first part implements the register interface for the
24 * guest and the second one does the data transfer.
25 *
26 * The guest can access the controller in two ways. The first one is the native
27 * way implementing the registers described in the AHCI specification and is
28 * the preferred one. The second implements the I/O ports used for booting from
29 * the hard disk and for guests which don't have an AHCI SATA driver.
30 *
31 * The data is transferred in an asynchronous way using one thread per implemented
32 * port or using the new async completion interface which is still under
33 * development. [not quite up to date]
34 */
35
36
37/*********************************************************************************************************************************
38* Header Files *
39*********************************************************************************************************************************/
40#define LOG_GROUP LOG_GROUP_DEV_AHCI
41#include <VBox/vmm/pdmdev.h>
42#include <VBox/vmm/pdmqueue.h>
43#include <VBox/vmm/pdmthread.h>
44#include <VBox/vmm/pdmcritsect.h>
45#include <VBox/sup.h>
46#include <VBox/scsi.h>
47#include <iprt/assert.h>
48#include <iprt/asm.h>
49#include <iprt/string.h>
50#include <iprt/list.h>
51#ifdef IN_RING3
52# include <iprt/param.h>
53# include <iprt/thread.h>
54# include <iprt/semaphore.h>
55# include <iprt/alloc.h>
56# include <iprt/uuid.h>
57# include <iprt/time.h>
58#endif
59#include "PIIX3ATABmDma.h"
60#include "ide.h"
61#include "ATAPIPassthrough.h"
62#include "VBoxDD.h"
63
64#if defined(VBOX_WITH_DTRACE) \
65 && defined(IN_RING3) \
66 && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
67# include "dtrace/VBoxDD.h"
68#else
69# define VBOXDD_AHCI_REQ_SUBMIT(a,b,c,d) do { } while (0)
70# define VBOXDD_AHCI_REQ_SUBMIT_TIMESTAMP(a,b) do { } while (0)
71# define VBOXDD_AHCI_REQ_COMPLETED(a,b,c,d,e) do { } while (0)
72# define VBOXDD_AHCI_REQ_COMPLETED_TIMESTAMP(a,b) do { } while (0)
73#endif
74
75/** Maximum number of ports available.
76 * Spec defines 32 but we have one allocated for command completion coalescing
77 * and another for a reserved future feature.
78 */
79#define AHCI_MAX_NR_PORTS_IMPL 30
80/** Maximum number of command slots available. */
81#define AHCI_NR_COMMAND_SLOTS 32
82
83#define AHCI_MAX_ALLOC_TOO_MUCH 20
84
85/** The current saved state version. */
86#define AHCI_SAVED_STATE_VERSION 8
87/** The saved state version before changing the port reset logic in an incompatible way. */
88#define AHCI_SAVED_STATE_VERSION_PRE_PORT_RESET_CHANGES 7
89/** Saved state version before the per port hotplug port was added. */
90#define AHCI_SAVED_STATE_VERSION_PRE_HOTPLUG_FLAG 6
91/** Saved state version before legacy ATA emulation was dropped. */
92#define AHCI_SAVED_STATE_VERSION_IDE_EMULATION 5
93/** Saved state version before ATAPI support was added. */
94#define AHCI_SAVED_STATE_VERSION_PRE_ATAPI 3
95/** The saved state version use in VirtualBox 3.0 and earlier.
96 * This was before the config was added and ahciIOTasks was dropped. */
97#define AHCI_SAVED_STATE_VERSION_VBOX_30 2
98/* for Older ATA state Read handling */
99#define ATA_CTL_SAVED_STATE_VERSION 3
100#define ATA_CTL_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE 1
101#define ATA_CTL_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS 2
102
103/** The maximum number of release log entries per device. */
104#define MAX_LOG_REL_ERRORS 1024
105
106/**
107 * Maximum number of sectors to transfer in a READ/WRITE MULTIPLE request.
108 * Set to 1 to disable multi-sector read support. According to the ATA
109 * specification this must be a power of 2 and it must fit in an 8 bit
110 * value. Thus the only valid values are 1, 2, 4, 8, 16, 32, 64 and 128.
111 */
112#define ATA_MAX_MULT_SECTORS 128
113
114/**
115 * Fastest PIO mode supported by the drive.
116 */
117#define ATA_PIO_MODE_MAX 4
118/**
119 * Fastest MDMA mode supported by the drive.
120 */
121#define ATA_MDMA_MODE_MAX 2
122/**
123 * Fastest UDMA mode supported by the drive.
124 */
125#define ATA_UDMA_MODE_MAX 6
126
127/**
128 * Length of the configurable VPD data (without termination)
129 */
130#define AHCI_SERIAL_NUMBER_LENGTH 20
131#define AHCI_FIRMWARE_REVISION_LENGTH 8
132#define AHCI_MODEL_NUMBER_LENGTH 40
133#define AHCI_ATAPI_INQUIRY_VENDOR_ID_LENGTH 8
134#define AHCI_ATAPI_INQUIRY_PRODUCT_ID_LENGTH 16
135#define AHCI_ATAPI_INQUIRY_REVISION_LENGTH 4
136
137/* MediaEventStatus */
138#define ATA_EVENT_STATUS_UNCHANGED 0 /**< medium event status not changed */
139#define ATA_EVENT_STATUS_MEDIA_NEW 1 /**< new medium inserted */
140#define ATA_EVENT_STATUS_MEDIA_REMOVED 2 /**< medium removed */
141#define ATA_EVENT_STATUS_MEDIA_CHANGED 3 /**< medium was removed + new medium was inserted */
142#define ATA_EVENT_STATUS_MEDIA_EJECT_REQUESTED 4 /**< medium eject requested (eject button pressed) */
143
144/* Media track type */
145#define ATA_MEDIA_TYPE_UNKNOWN 0 /**< unknown CD type */
146
147/** ATAPI sense info size. */
148#define ATAPI_SENSE_SIZE 64
149
150/**
151 * Command Header.
152 */
153#pragma pack(1)
154typedef struct
155{
156 /** Description Information. */
157 uint32_t u32DescInf;
158 /** Command status. */
159 uint32_t u32PRDBC;
160 /** Command Table Base Address. */
161 uint32_t u32CmdTblAddr;
162 /** Command Table Base Address - upper 32-bits. */
163 uint32_t u32CmdTblAddrUp;
164 /** Reserved */
165 uint32_t u32Reserved[4];
166} CmdHdr;
167#pragma pack()
168AssertCompileSize(CmdHdr, 32);
169
170/* Defines for the command header. */
171#define AHCI_CMDHDR_PRDTL_MASK 0xffff0000
172#define AHCI_CMDHDR_PRDTL_ENTRIES(x) ((x & AHCI_CMDHDR_PRDTL_MASK) >> 16)
173#define AHCI_CMDHDR_C RT_BIT(10)
174#define AHCI_CMDHDR_B RT_BIT(9)
175#define AHCI_CMDHDR_R RT_BIT(8)
176#define AHCI_CMDHDR_P RT_BIT(7)
177#define AHCI_CMDHDR_W RT_BIT(6)
178#define AHCI_CMDHDR_A RT_BIT(5)
179#define AHCI_CMDHDR_CFL_MASK 0x1f
180
181#define AHCI_CMDHDR_PRDT_OFFSET 0x80
182#define AHCI_CMDHDR_ACMD_OFFSET 0x40
183
184/* Defines for the command FIS. */
185/* Defines that are used in the first double word. */
186#define AHCI_CMDFIS_TYPE 0 /* The first byte. */
187# define AHCI_CMDFIS_TYPE_H2D 0x27 /* Register - Host to Device FIS. */
188# define AHCI_CMDFIS_TYPE_H2D_SIZE 20 /* Five double words. */
189# define AHCI_CMDFIS_TYPE_D2H 0x34 /* Register - Device to Host FIS. */
190# define AHCI_CMDFIS_TYPE_D2H_SIZE 20 /* Five double words. */
191# define AHCI_CMDFIS_TYPE_SETDEVBITS 0xa1 /* Set Device Bits - Device to Host FIS. */
192# define AHCI_CMDFIS_TYPE_SETDEVBITS_SIZE 8 /* Two double words. */
193# define AHCI_CMDFIS_TYPE_DMAACTD2H 0x39 /* DMA Activate - Device to Host FIS. */
194# define AHCI_CMDFIS_TYPE_DMAACTD2H_SIZE 4 /* One double word. */
195# define AHCI_CMDFIS_TYPE_DMASETUP 0x41 /* DMA Setup - Bidirectional FIS. */
196# define AHCI_CMDFIS_TYPE_DMASETUP_SIZE 28 /* Seven double words. */
197# define AHCI_CMDFIS_TYPE_PIOSETUP 0x5f /* PIO Setup - Device to Host FIS. */
198# define AHCI_CMDFIS_TYPE_PIOSETUP_SIZE 20 /* Five double words. */
199# define AHCI_CMDFIS_TYPE_DATA 0x46 /* Data - Bidirectional FIS. */
200
201#define AHCI_CMDFIS_BITS 1 /* Interrupt and Update bit. */
202#define AHCI_CMDFIS_C RT_BIT(7) /* Host to device. */
203#define AHCI_CMDFIS_I RT_BIT(6) /* Device to Host. */
204#define AHCI_CMDFIS_D RT_BIT(5)
205
206#define AHCI_CMDFIS_CMD 2
207#define AHCI_CMDFIS_FET 3
208
209#define AHCI_CMDFIS_SECTN 4
210#define AHCI_CMDFIS_CYLL 5
211#define AHCI_CMDFIS_CYLH 6
212#define AHCI_CMDFIS_HEAD 7
213
214#define AHCI_CMDFIS_SECTNEXP 8
215#define AHCI_CMDFIS_CYLLEXP 9
216#define AHCI_CMDFIS_CYLHEXP 10
217#define AHCI_CMDFIS_FETEXP 11
218
219#define AHCI_CMDFIS_SECTC 12
220#define AHCI_CMDFIS_SECTCEXP 13
221#define AHCI_CMDFIS_CTL 15
222# define AHCI_CMDFIS_CTL_SRST RT_BIT(2) /* Reset device. */
223# define AHCI_CMDFIS_CTL_NIEN RT_BIT(1) /* Assert or clear interrupt. */
224
225/* For D2H FIS */
226#define AHCI_CMDFIS_STS 2
227#define AHCI_CMDFIS_ERR 3
228
229/** Pointer to a task state. */
230typedef struct AHCIREQ *PAHCIREQ;
231
232/**
233 * Data processing callback
234 *
235 * @returns VBox status code.
236 * @param pAhciReq The task state.
237 * @param ppvProc Where to store the pointer to the buffer holding the processed data on success.
238 * Must be freed with RTMemFree().
239 * @param pcbProc Where to store the size of the buffer on success.
240 */
241typedef DECLCALLBACK(int) FNAHCIPOSTPROCESS(PAHCIREQ pAhciReq, void **ppvProc, size_t *pcbProc);
242/** Pointer to a FNAHCIPOSTPROCESS() function. */
243typedef FNAHCIPOSTPROCESS *PFNAHCIPOSTPROCESS;
244
245/**
246 * Transfer type.
247 */
248typedef enum AHCITXDIR
249{
250 /** Invalid */
251 AHCITXDIR_INVALID = 0,
252 /** None */
253 AHCITXDIR_NONE,
254 /** Read */
255 AHCITXDIR_READ,
256 /** Write */
257 AHCITXDIR_WRITE,
258 /** Flush */
259 AHCITXDIR_FLUSH,
260 /** Trim */
261 AHCITXDIR_TRIM
262} AHCITXDIR;
263
264/**
265 * Task state.
266 */
267typedef enum AHCITXSTATE
268{
269 /** Invalid. */
270 AHCITXSTATE_INVALID = 0,
271 /** Task is not active. */
272 AHCITXSTATE_FREE,
273 /** Task is active */
274 AHCITXSTATE_ACTIVE,
275 /** Task was canceled but the request didn't completed yet. */
276 AHCITXSTATE_CANCELED,
277 /** 32bit hack. */
278 AHCITXSTATE_32BIT_HACK = 0x7fffffff
279} AHCITXSTATE, *PAHCITXSTATE;
280AssertCompileSize(AHCITXSTATE, sizeof(uint32_t));
281
282/** Task encountered a buffer overflow. */
283#define AHCI_REQ_OVERFLOW RT_BIT_32(0)
284/** Request is a PIO data command, if this flag is not set it either is
285 * a command which does not transfer data or a DMA command based on the transfer size. */
286#define AHCI_REQ_PIO_DATA RT_BIT_32(1)
287/** The request has the SACT register set. */
288#define AHCI_REQ_CLEAR_SACT RT_BIT_32(2)
289/** Flag whether the request is queued. */
290#define AHCI_REQ_IS_QUEUED RT_BIT_32(3)
291/** Flag whether the request is stored on the stack. */
292#define AHCI_REQ_IS_ON_STACK RT_BIT_32(4)
293
294/**
295 * A task state.
296 */
297typedef struct AHCIREQ
298{
299 /** List node for the free list if the request is not in use. */
300 RTLISTNODE NodeList;
301 /** Task state. */
302 volatile AHCITXSTATE enmTxState;
303 /** Start timestamp of the request. */
304 uint64_t tsStart;
305 /** Tag of the task. */
306 uint32_t uTag;
307 /** The command header for this task. */
308 CmdHdr cmdHdr;
309 /** The command Fis for this task. */
310 uint8_t cmdFis[AHCI_CMDFIS_TYPE_H2D_SIZE];
311 /** The ATAPI command data. */
312 uint8_t aATAPICmd[ATAPI_PACKET_SIZE];
313 /** Size of one sector for the ATAPI transfer. */
314 size_t cbATAPISector;
315 /** Physical address of the command header. - GC */
316 RTGCPHYS GCPhysCmdHdrAddr;
317 /** Physical address if the PRDT */
318 RTGCPHYS GCPhysPrdtl;
319 /** Number of entries in the PRDTL. */
320 unsigned cPrdtlEntries;
321 /** Data direction. */
322 AHCITXDIR enmTxDir;
323 /** Start offset. */
324 uint64_t uOffset;
325 /** Number of bytes to transfer. */
326 uint32_t cbTransfer;
327 /** ATA error register */
328 uint8_t uATARegError;
329 /** ATA status register */
330 uint8_t uATARegStatus;
331 /** Flags for this task. */
332 uint32_t fFlags;
333 /** Additional memory allocation for this task. */
334 void *pvAlloc;
335 /** Siize of the allocation. */
336 size_t cbAlloc;
337 /** Number of times we had too much memory allocated for the request. */
338 unsigned cAllocTooMuch;
339 /** Data dependent on the transfer direction. */
340 union
341 {
342 /** Data for an I/O request. */
343 struct
344 {
345 /** Data segment. */
346 RTSGSEG DataSeg;
347 /** Post processing callback.
348 * If this is set we will use a buffer for the data
349 * and the callback returns a buffer with the final data. */
350 PFNAHCIPOSTPROCESS pfnPostProcess;
351 } Io;
352 /** Data for a trim request. */
353 struct
354 {
355 /** Pointer to the array of ranges to trim. */
356 PRTRANGE paRanges;
357 /** Number of entries in the array. */
358 unsigned cRanges;
359 } Trim;
360 } u;
361} AHCIREQ;
362
363/**
364 * Notifier queue item.
365 */
366typedef struct DEVPORTNOTIFIERQUEUEITEM
367{
368 /** The core part owned by the queue manager. */
369 PDMQUEUEITEMCORE Core;
370 /** The port to process. */
371 uint8_t iPort;
372} DEVPORTNOTIFIERQUEUEITEM, *PDEVPORTNOTIFIERQUEUEITEM;
373
374
375/**
376 * @implements PDMIBASE
377 * @implements PDMIBLOCKPORT
378 * @implements PDMIBLOCKASYNCPORT
379 * @implements PDMIMOUNTNOTIFY
380 */
381typedef struct AHCIPort
382{
383 /** Pointer to the device instance - HC ptr */
384 PPDMDEVINSR3 pDevInsR3;
385 /** Pointer to the device instance - R0 ptr */
386 PPDMDEVINSR0 pDevInsR0;
387 /** Pointer to the device instance - RC ptr. */
388 PPDMDEVINSRC pDevInsRC;
389
390#if HC_ARCH_BITS == 64
391 uint32_t Alignment0;
392#endif
393
394 /** Pointer to the parent AHCI structure - R3 ptr. */
395 R3PTRTYPE(struct AHCI *) pAhciR3;
396 /** Pointer to the parent AHCI structure - R0 ptr. */
397 R0PTRTYPE(struct AHCI *) pAhciR0;
398 /** Pointer to the parent AHCI structure - RC ptr. */
399 RCPTRTYPE(struct AHCI *) pAhciRC;
400
401 /** Command List Base Address. */
402 uint32_t regCLB;
403 /** Command List Base Address upper bits. */
404 uint32_t regCLBU;
405 /** FIS Base Address. */
406 uint32_t regFB;
407 /** FIS Base Address upper bits. */
408 uint32_t regFBU;
409 /** Interrupt Status. */
410 volatile uint32_t regIS;
411 /** Interrupt Enable. */
412 uint32_t regIE;
413 /** Command. */
414 uint32_t regCMD;
415 /** Task File Data. */
416 uint32_t regTFD;
417 /** Signature */
418 uint32_t regSIG;
419 /** Serial ATA Status. */
420 uint32_t regSSTS;
421 /** Serial ATA Control. */
422 uint32_t regSCTL;
423 /** Serial ATA Error. */
424 uint32_t regSERR;
425 /** Serial ATA Active. */
426 volatile uint32_t regSACT;
427 /** Command Issue. */
428 uint32_t regCI;
429
430 /** Current number of active tasks. */
431 volatile uint32_t cTasksActive;
432 /** Command List Base Address */
433 volatile RTGCPHYS GCPhysAddrClb;
434 /** FIS Base Address */
435 volatile RTGCPHYS GCPhysAddrFb;
436
437 /** Device is powered on. */
438 bool fPoweredOn;
439 /** Device has spun up. */
440 bool fSpunUp;
441 /** First D2H FIS was send. */
442 bool fFirstD2HFisSend;
443 /** Mark the drive as having a non-rotational medium (i.e. as a SSD). */
444 bool fNonRotational;
445 /** Attached device is a CD/DVD drive. */
446 bool fATAPI;
447 /** Passthrough SCSI commands. */
448 bool fATAPIPassthrough;
449 /** Flag whether this port is in a reset state. */
450 volatile bool fPortReset;
451 /** If we use the new async interface. */
452 bool fAsyncInterface;
453 /** Flag if we are in a device reset. */
454 bool fResetDevice;
455 /** Flag whether this port is hot plug capable. */
456 bool fHotpluggable;
457 /** Flag whether the port is in redo task mode. */
458 volatile bool fRedo;
459 /** Flag whether the worker thread is sleeping. */
460 volatile bool fWrkThreadSleeping;
461
462 bool afAlignment[3];
463
464 /** Number of total sectors. */
465 uint64_t cTotalSectors;
466 /** Size of one sector. */
467 uint32_t cbSector;
468 /** Currently configured number of sectors in a multi-sector transfer. */
469 uint32_t cMultSectors;
470 /** Currently active transfer mode (MDMA/UDMA) and speed. */
471 uint8_t uATATransferMode;
472 /** ATAPI sense data. */
473 uint8_t abATAPISense[ATAPI_SENSE_SIZE];
474 /** HACK: Countdown till we report a newly unmounted drive as mounted. */
475 uint8_t cNotifiedMediaChange;
476 /** Exponent of logical sectors in a physical sector, number of logical sectors is 2^exp. */
477 uint8_t cLogSectorsPerPhysicalExp;
478 /** The same for GET_EVENT_STATUS for mechanism */
479 volatile uint32_t MediaEventStatus;
480 /** Media type if known. */
481 volatile uint32_t MediaTrackType;
482 /** The LUN. */
483 RTUINT iLUN;
484
485 /** Bitmap for finished tasks (R3 -> Guest). */
486 volatile uint32_t u32TasksFinished;
487 /** Bitmap for finished queued tasks (R3 -> Guest). */
488 volatile uint32_t u32QueuedTasksFinished;
489 /** Bitmap for new queued tasks (Guest -> R3). */
490 volatile uint32_t u32TasksNew;
491 /** Bitmap of tasks which must be redone because of a non fatal error. */
492 volatile uint32_t u32TasksRedo;
493
494 /** Current command slot processed.
495 * Accessed by the guest by reading the CMD register.
496 * Holds the command slot of the command processed at the moment. */
497 volatile uint32_t u32CurrentCommandSlot;
498
499#if HC_ARCH_BITS == 64
500 uint32_t u32Alignment2;
501#endif
502
503 /** Device specific settings (R3 only stuff). */
504 /** Pointer to the attached driver's base interface. */
505 R3PTRTYPE(PPDMIBASE) pDrvBase;
506 /** Pointer to the attached driver's block interface. */
507 R3PTRTYPE(PPDMIBLOCK) pDrvBlock;
508 /** Pointer to the attached driver's async block interface. */
509 R3PTRTYPE(PPDMIBLOCKASYNC) pDrvBlockAsync;
510 /** Pointer to the attached driver's block bios interface. */
511 R3PTRTYPE(PPDMIBLOCKBIOS) pDrvBlockBios;
512 /** Pointer to the attached driver's mount interface. */
513 R3PTRTYPE(PPDMIMOUNT) pDrvMount;
514 /** The base interface. */
515 PDMIBASE IBase;
516 /** The block port interface. */
517 PDMIBLOCKPORT IPort;
518 /** The optional block async port interface. */
519 PDMIBLOCKASYNCPORT IPortAsync;
520 /** The mount notify interface. */
521 PDMIMOUNTNOTIFY IMountNotify;
522 /** Physical geometry of this image. */
523 PDMMEDIAGEOMETRY PCHSGeometry;
524 /** The status LED state for this drive. */
525 PDMLED Led;
526
527 uint32_t u32Alignment3;
528
529 /** Async IO Thread. */
530 R3PTRTYPE(PPDMTHREAD) pAsyncIOThread;
531 /** Array of active tasks indexed by the tag. */
532 R3PTRTYPE(volatile PAHCIREQ) aActiveTasks[AHCI_NR_COMMAND_SLOTS];
533 /** First task throwing an error. */
534 R3PTRTYPE(volatile PAHCIREQ) pTaskErr;
535 /** The current tracklist of the loaded medium if passthrough is used. */
536 R3PTRTYPE(PTRACKLIST) pTrackList;
537
538 /** The event semaphore the processing thread waits on. */
539 SUPSEMEVENT hEvtProcess;
540
541 /** Release statistics: number of DMA commands. */
542 STAMCOUNTER StatDMA;
543 /** Release statistics: number of bytes written. */
544 STAMCOUNTER StatBytesWritten;
545 /** Release statistics: number of bytes read. */
546 STAMCOUNTER StatBytesRead;
547 /** Release statistics: Number of I/O requests processed per second. */
548 STAMCOUNTER StatIORequestsPerSecond;
549#ifdef VBOX_WITH_STATISTICS
550 /** Statistics: Time to complete one request. */
551 STAMPROFILE StatProfileProcessTime;
552 /** Statistics: Amount of time to read/write data. */
553 STAMPROFILE StatProfileReadWrite;
554#endif /* VBOX_WITH_STATISTICS */
555
556 /** The serial numnber to use for IDENTIFY DEVICE commands. */
557 char szSerialNumber[AHCI_SERIAL_NUMBER_LENGTH+1]; /** < one extra byte for termination */
558 /** The firmware revision to use for IDENTIFY DEVICE commands. */
559 char szFirmwareRevision[AHCI_FIRMWARE_REVISION_LENGTH+1]; /** < one extra byte for termination */
560 /** The model number to use for IDENTIFY DEVICE commands. */
561 char szModelNumber[AHCI_MODEL_NUMBER_LENGTH+1]; /** < one extra byte for termination */
562 /** The vendor identification string for SCSI INQUIRY commands. */
563 char szInquiryVendorId[AHCI_ATAPI_INQUIRY_VENDOR_ID_LENGTH+1];
564 /** The product identification string for SCSI INQUIRY commands. */
565 char szInquiryProductId[AHCI_ATAPI_INQUIRY_PRODUCT_ID_LENGTH+1];
566 /** The revision string for SCSI INQUIRY commands. */
567 char szInquiryRevision[AHCI_ATAPI_INQUIRY_REVISION_LENGTH+1];
568 /** Error counter */
569 uint32_t cErrors;
570
571 uint32_t u32Alignment5;
572
573 /** Critical section protecting the global free list. */
574 RTCRITSECT CritSectReqsFree;
575 /** Head of the global free request list. */
576 R3PTRTYPE(PRTLISTANCHOR) pListReqsFree;
577
578 /** Align to a multiple of 8. */
579#if HC_ARCH_BITS == 32
580 uint32_t u32Alignment6;
581#endif
582
583} AHCIPort;
584/** Pointer to the state of an AHCI port. */
585typedef AHCIPort *PAHCIPort;
586
587AssertCompileMemberAlignment(AHCIPort, StatDMA, 8);
588AssertCompileSizeAlignment(AHCIPort, 8);
589
590/**
591 * Main AHCI device state.
592 *
593 * @implements PDMILEDPORTS
594 */
595typedef struct AHCI
596{
597 /** The PCI device structure. */
598 PCIDEVICE dev;
599 /** Pointer to the device instance - R3 ptr */
600 PPDMDEVINSR3 pDevInsR3;
601 /** Pointer to the device instance - R0 ptr */
602 PPDMDEVINSR0 pDevInsR0;
603 /** Pointer to the device instance - RC ptr. */
604 PPDMDEVINSRC pDevInsRC;
605
606#if HC_ARCH_BITS == 64
607 uint32_t Alignment0;
608#endif
609
610 /** Status LUN: The base interface. */
611 PDMIBASE IBase;
612 /** Status LUN: Leds interface. */
613 PDMILEDPORTS ILeds;
614 /** Status LUN: Partner of ILeds. */
615 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
616 /** Status LUN: Media Notifys. */
617 R3PTRTYPE(PPDMIMEDIANOTIFY) pMediaNotify;
618
619#if HC_ARCH_BITS == 32
620 uint32_t Alignment1;
621#endif
622
623 /** Base address of the MMIO region. */
624 RTGCPHYS MMIOBase;
625 /** Base address of the I/O port region for Idx/Data. */
626 RTIOPORT IOPortBase;
627
628 /** Global Host Control register of the HBA */
629
630 /** HBA Capabilities - Readonly */
631 uint32_t regHbaCap;
632 /** HBA Control */
633 uint32_t regHbaCtrl;
634 /** Interrupt Status */
635 uint32_t regHbaIs;
636 /** Ports Implemented - Readonly */
637 uint32_t regHbaPi;
638 /** AHCI Version - Readonly */
639 uint32_t regHbaVs;
640 /** Command completion coalescing control */
641 uint32_t regHbaCccCtl;
642 /** Command completion coalescing ports */
643 uint32_t regHbaCccPorts;
644
645 /** Index register for BIOS access. */
646 uint32_t regIdx;
647
648#if HC_ARCH_BITS == 64
649 uint32_t Alignment3;
650#endif
651
652 /** Countdown timer for command completion coalescing - R3 ptr */
653 PTMTIMERR3 pHbaCccTimerR3;
654 /** Countdown timer for command completion coalescing - R0 ptr */
655 PTMTIMERR0 pHbaCccTimerR0;
656 /** Countdown timer for command completion coalescing - RC ptr */
657 PTMTIMERRC pHbaCccTimerRC;
658
659#if HC_ARCH_BITS == 64
660 uint32_t Alignment4;
661#endif
662
663 /** Queue to send tasks to R3. - HC ptr */
664 R3PTRTYPE(PPDMQUEUE) pNotifierQueueR3;
665 /** Queue to send tasks to R3. - HC ptr */
666 R0PTRTYPE(PPDMQUEUE) pNotifierQueueR0;
667 /** Queue to send tasks to R3. - RC ptr */
668 RCPTRTYPE(PPDMQUEUE) pNotifierQueueRC;
669
670#if HC_ARCH_BITS == 64
671 uint32_t Alignment5;
672#endif
673
674
675 /** Which port number is used to mark an CCC interrupt */
676 uint8_t uCccPortNr;
677
678#if HC_ARCH_BITS == 64
679 uint32_t Alignment6;
680#endif
681
682 /** Timeout value */
683 uint64_t uCccTimeout;
684 /** Number of completions used to assert an interrupt */
685 uint32_t uCccNr;
686 /** Current number of completed commands */
687 uint32_t uCccCurrentNr;
688
689 /** Register structure per port */
690 AHCIPort ahciPort[AHCI_MAX_NR_PORTS_IMPL];
691
692 /** The critical section. */
693 PDMCRITSECT lock;
694
695 /** Bitmask of ports which asserted an interrupt. */
696 volatile uint32_t u32PortsInterrupted;
697 /** Number of I/O threads currently active - used for async controller reset handling. */
698 volatile uint32_t cThreadsActive;
699 /** Device is in a reset state. */
700 bool fReset;
701 /** Supports 64bit addressing */
702 bool f64BitAddr;
703 /** GC enabled. */
704 bool fGCEnabled;
705 /** R0 enabled. */
706 bool fR0Enabled;
707 /** If the new async interface is used if available. */
708 bool fUseAsyncInterfaceIfAvailable;
709 /** Indicates that PDMDevHlpAsyncNotificationCompleted should be called when
710 * a port is entering the idle state. */
711 bool volatile fSignalIdle;
712 /** Flag whether the controller has BIOS access enabled. */
713 bool fBootable;
714 /** Flag whether the legacy port reset method should be used to make it work with saved states. */
715 bool fLegacyPortResetMethod;
716
717 /** Number of usable ports on this controller. */
718 uint32_t cPortsImpl;
719 /** Number of usable command slots for each port. */
720 uint32_t cCmdSlotsAvail;
721
722 /** Flag whether we have written the first 4bytes in an 8byte MMIO write successfully. */
723 volatile bool f8ByteMMIO4BytesWrittenSuccessfully;
724
725#if HC_ARCH_BITS == 64
726 uint32_t Alignment7;
727#endif
728
729 /** The support driver session handle. */
730 R3R0PTRTYPE(PSUPDRVSESSION) pSupDrvSession;
731} AHCI;
732/** Pointer to the state of an AHCI device. */
733typedef AHCI *PAHCI;
734
735AssertCompileMemberAlignment(AHCI, ahciPort, 8);
736
737/**
738 * Scatter gather list entry.
739 */
740typedef struct
741{
742 /** Data Base Address. */
743 uint32_t u32DBA;
744 /** Data Base Address - Upper 32-bits. */
745 uint32_t u32DBAUp;
746 /** Reserved */
747 uint32_t u32Reserved;
748 /** Description information. */
749 uint32_t u32DescInf;
750} SGLEntry;
751AssertCompileSize(SGLEntry, 16);
752
753/** Defines for a scatter gather list entry. */
754#define SGLENTRY_DBA_READONLY ~(RT_BIT(0))
755#define SGLENTRY_DESCINF_I RT_BIT(31)
756#define SGLENTRY_DESCINF_DBC 0x3fffff
757#define SGLENTRY_DESCINF_READONLY 0x803fffff
758
759/* Defines for the global host control registers for the HBA. */
760
761#define AHCI_HBA_GLOBAL_SIZE 0x100
762
763/* Defines for the HBA Capabilities - Readonly */
764#define AHCI_HBA_CAP_S64A RT_BIT(31)
765#define AHCI_HBA_CAP_SNCQ RT_BIT(30)
766#define AHCI_HBA_CAP_SIS RT_BIT(28)
767#define AHCI_HBA_CAP_SSS RT_BIT(27)
768#define AHCI_HBA_CAP_SALP RT_BIT(26)
769#define AHCI_HBA_CAP_SAL RT_BIT(25)
770#define AHCI_HBA_CAP_SCLO RT_BIT(24)
771#define AHCI_HBA_CAP_ISS (RT_BIT(23) | RT_BIT(22) | RT_BIT(21) | RT_BIT(20))
772# define AHCI_HBA_CAP_ISS_SHIFT(x) (((x) << 20) & AHCI_HBA_CAP_ISS)
773# define AHCI_HBA_CAP_ISS_GEN1 RT_BIT(0)
774# define AHCI_HBA_CAP_ISS_GEN2 RT_BIT(1)
775#define AHCI_HBA_CAP_SNZO RT_BIT(19)
776#define AHCI_HBA_CAP_SAM RT_BIT(18)
777#define AHCI_HBA_CAP_SPM RT_BIT(17)
778#define AHCI_HBA_CAP_PMD RT_BIT(15)
779#define AHCI_HBA_CAP_SSC RT_BIT(14)
780#define AHCI_HBA_CAP_PSC RT_BIT(13)
781#define AHCI_HBA_CAP_NCS (RT_BIT(12) | RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
782#define AHCI_HBA_CAP_NCS_SET(x) (((x-1) << 8) & AHCI_HBA_CAP_NCS) /* 0's based */
783#define AHCI_HBA_CAP_CCCS RT_BIT(7)
784#define AHCI_HBA_CAP_NP (RT_BIT(4) | RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
785#define AHCI_HBA_CAP_NP_SET(x) ((x-1) & AHCI_HBA_CAP_NP) /* 0's based */
786
787/* Defines for the HBA Control register - Read/Write */
788#define AHCI_HBA_CTRL_AE RT_BIT(31)
789#define AHCI_HBA_CTRL_IE RT_BIT(1)
790#define AHCI_HBA_CTRL_HR RT_BIT(0)
791#define AHCI_HBA_CTRL_RW_MASK (RT_BIT(0) | RT_BIT(1)) /* Mask for the used bits */
792
793/* Defines for the HBA Version register - Readonly (We support AHCI 1.0) */
794#define AHCI_HBA_VS_MJR (1 << 16)
795#define AHCI_HBA_VS_MNR 0x100
796
797/* Defines for the command completion coalescing control register */
798#define AHCI_HBA_CCC_CTL_TV 0xffff0000
799#define AHCI_HBA_CCC_CTL_TV_SET(x) (x << 16)
800#define AHCI_HBA_CCC_CTL_TV_GET(x) ((x & AHCI_HBA_CCC_CTL_TV) >> 16)
801
802#define AHCI_HBA_CCC_CTL_CC 0xff00
803#define AHCI_HBA_CCC_CTL_CC_SET(x) (x << 8)
804#define AHCI_HBA_CCC_CTL_CC_GET(x) ((x & AHCI_HBA_CCC_CTL_CC) >> 8)
805
806#define AHCI_HBA_CCC_CTL_INT 0xf8
807#define AHCI_HBA_CCC_CTL_INT_SET(x) (x << 3)
808#define AHCI_HBA_CCC_CTL_INT_GET(x) ((x & AHCI_HBA_CCC_CTL_INT) >> 3)
809
810#define AHCI_HBA_CCC_CTL_EN RT_BIT(0)
811
812/* Defines for the port registers. */
813
814#define AHCI_PORT_REGISTER_SIZE 0x80
815
816#define AHCI_PORT_CLB_RESERVED 0xfffffc00 /* For masking out the reserved bits. */
817
818#define AHCI_PORT_FB_RESERVED 0xffffff00 /* For masking out the reserved bits. */
819
820#define AHCI_PORT_IS_CPDS RT_BIT(31)
821#define AHCI_PORT_IS_TFES RT_BIT(30)
822#define AHCI_PORT_IS_HBFS RT_BIT(29)
823#define AHCI_PORT_IS_HBDS RT_BIT(28)
824#define AHCI_PORT_IS_IFS RT_BIT(27)
825#define AHCI_PORT_IS_INFS RT_BIT(26)
826#define AHCI_PORT_IS_OFS RT_BIT(24)
827#define AHCI_PORT_IS_IPMS RT_BIT(23)
828#define AHCI_PORT_IS_PRCS RT_BIT(22)
829#define AHCI_PORT_IS_DIS RT_BIT(7)
830#define AHCI_PORT_IS_PCS RT_BIT(6)
831#define AHCI_PORT_IS_DPS RT_BIT(5)
832#define AHCI_PORT_IS_UFS RT_BIT(4)
833#define AHCI_PORT_IS_SDBS RT_BIT(3)
834#define AHCI_PORT_IS_DSS RT_BIT(2)
835#define AHCI_PORT_IS_PSS RT_BIT(1)
836#define AHCI_PORT_IS_DHRS RT_BIT(0)
837#define AHCI_PORT_IS_READONLY 0xfd8000af /* Readonly mask including reserved bits. */
838
839#define AHCI_PORT_IE_CPDE RT_BIT(31)
840#define AHCI_PORT_IE_TFEE RT_BIT(30)
841#define AHCI_PORT_IE_HBFE RT_BIT(29)
842#define AHCI_PORT_IE_HBDE RT_BIT(28)
843#define AHCI_PORT_IE_IFE RT_BIT(27)
844#define AHCI_PORT_IE_INFE RT_BIT(26)
845#define AHCI_PORT_IE_OFE RT_BIT(24)
846#define AHCI_PORT_IE_IPME RT_BIT(23)
847#define AHCI_PORT_IE_PRCE RT_BIT(22)
848#define AHCI_PORT_IE_DIE RT_BIT(7) /* Not supported for now, readonly. */
849#define AHCI_PORT_IE_PCE RT_BIT(6)
850#define AHCI_PORT_IE_DPE RT_BIT(5)
851#define AHCI_PORT_IE_UFE RT_BIT(4)
852#define AHCI_PORT_IE_SDBE RT_BIT(3)
853#define AHCI_PORT_IE_DSE RT_BIT(2)
854#define AHCI_PORT_IE_PSE RT_BIT(1)
855#define AHCI_PORT_IE_DHRE RT_BIT(0)
856#define AHCI_PORT_IE_READONLY (0xfdc000ff) /* Readonly mask including reserved bits. */
857
858#define AHCI_PORT_CMD_ICC (RT_BIT(28) | RT_BIT(29) | RT_BIT(30) | RT_BIT(31))
859#define AHCI_PORT_CMD_ICC_SHIFT(x) ((x) << 28)
860# define AHCI_PORT_CMD_ICC_IDLE 0x0
861# define AHCI_PORT_CMD_ICC_ACTIVE 0x1
862# define AHCI_PORT_CMD_ICC_PARTIAL 0x2
863# define AHCI_PORT_CMD_ICC_SLUMBER 0x6
864#define AHCI_PORT_CMD_ASP RT_BIT(27) /* Not supported - Readonly */
865#define AHCI_PORT_CMD_ALPE RT_BIT(26) /* Not supported - Readonly */
866#define AHCI_PORT_CMD_DLAE RT_BIT(25)
867#define AHCI_PORT_CMD_ATAPI RT_BIT(24)
868#define AHCI_PORT_CMD_CPD RT_BIT(20)
869#define AHCI_PORT_CMD_ISP RT_BIT(19) /* Readonly */
870#define AHCI_PORT_CMD_HPCP RT_BIT(18)
871#define AHCI_PORT_CMD_PMA RT_BIT(17) /* Not supported - Readonly */
872#define AHCI_PORT_CMD_CPS RT_BIT(16)
873#define AHCI_PORT_CMD_CR RT_BIT(15) /* Readonly */
874#define AHCI_PORT_CMD_FR RT_BIT(14) /* Readonly */
875#define AHCI_PORT_CMD_ISS RT_BIT(13) /* Readonly */
876#define AHCI_PORT_CMD_CCS (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11) | RT_BIT(12))
877#define AHCI_PORT_CMD_CCS_SHIFT(x) (x << 8) /* Readonly */
878#define AHCI_PORT_CMD_FRE RT_BIT(4)
879#define AHCI_PORT_CMD_CLO RT_BIT(3)
880#define AHCI_PORT_CMD_POD RT_BIT(2)
881#define AHCI_PORT_CMD_SUD RT_BIT(1)
882#define AHCI_PORT_CMD_ST RT_BIT(0)
883#define AHCI_PORT_CMD_READONLY (0xff02001f & ~(AHCI_PORT_CMD_ASP | AHCI_PORT_CMD_ALPE | AHCI_PORT_CMD_PMA))
884
885#define AHCI_PORT_SCTL_IPM (RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
886#define AHCI_PORT_SCTL_IPM_GET(x) ((x & AHCI_PORT_SCTL_IPM) >> 8)
887#define AHCI_PORT_SCTL_SPD (RT_BIT(7) | RT_BIT(6) | RT_BIT(5) | RT_BIT(4))
888#define AHCI_PORT_SCTL_SPD_GET(x) ((x & AHCI_PORT_SCTL_SPD) >> 4)
889#define AHCI_PORT_SCTL_DET (RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
890#define AHCI_PORT_SCTL_DET_GET(x) (x & AHCI_PORT_SCTL_DET)
891#define AHCI_PORT_SCTL_DET_NINIT 0
892#define AHCI_PORT_SCTL_DET_INIT 1
893#define AHCI_PORT_SCTL_DET_OFFLINE 4
894#define AHCI_PORT_SCTL_READONLY 0xfff
895
896#define AHCI_PORT_SSTS_IPM (RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
897#define AHCI_PORT_SSTS_IPM_GET(x) ((x & AHCI_PORT_SCTL_IPM) >> 8)
898#define AHCI_PORT_SSTS_SPD (RT_BIT(7) | RT_BIT(6) | RT_BIT(5) | RT_BIT(4))
899#define AHCI_PORT_SSTS_SPD_GET(x) ((x & AHCI_PORT_SCTL_SPD) >> 4)
900#define AHCI_PORT_SSTS_DET (RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
901#define AHCI_PORT_SSTS_DET_GET(x) (x & AHCI_PORT_SCTL_DET)
902
903#define AHCI_PORT_TFD_BSY RT_BIT(7)
904#define AHCI_PORT_TFD_DRQ RT_BIT(3)
905#define AHCI_PORT_TFD_ERR RT_BIT(0)
906
907#define AHCI_PORT_SERR_X RT_BIT(26)
908#define AHCI_PORT_SERR_W RT_BIT(18)
909#define AHCI_PORT_SERR_N RT_BIT(16)
910
911/* Signatures for attached storage devices. */
912#define AHCI_PORT_SIG_DISK 0x00000101
913#define AHCI_PORT_SIG_ATAPI 0xeb140101
914
915/*
916 * The AHCI spec defines an area of memory where the HBA posts received FIS's from the device.
917 * regFB points to the base of this area.
918 * Every FIS type has an offset where it is posted in this area.
919 */
920#define AHCI_RECFIS_DSFIS_OFFSET 0x00 /* DMA Setup FIS */
921#define AHCI_RECFIS_PSFIS_OFFSET 0x20 /* PIO Setup FIS */
922#define AHCI_RECFIS_RFIS_OFFSET 0x40 /* D2H Register FIS */
923#define AHCI_RECFIS_SDBFIS_OFFSET 0x58 /* Set Device Bits FIS */
924#define AHCI_RECFIS_UFIS_OFFSET 0x60 /* Unknown FIS type */
925
926/** Mask to get the LBA value from a LBA range. */
927#define AHCI_RANGE_LBA_MASK UINT64_C(0xffffffffffff)
928/** Mas to get the length value from a LBA range. */
929#define AHCI_RANGE_LENGTH_MASK UINT64_C(0xffff000000000000)
930/** Returns the length of the range in sectors. */
931#define AHCI_RANGE_LENGTH_GET(val) (((val) & AHCI_RANGE_LENGTH_MASK) >> 48)
932
933/**
934 * AHCI register operator.
935 */
936typedef struct ahci_opreg
937{
938 const char *pszName;
939 int (*pfnRead )(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value);
940 int (*pfnWrite)(PAHCI ahci, uint32_t iReg, uint32_t u32Value);
941} AHCIOPREG;
942
943/**
944 * AHCI port register operator.
945 */
946typedef struct pAhciPort_opreg
947{
948 const char *pszName;
949 int (*pfnRead )(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value);
950 int (*pfnWrite)(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value);
951} AHCIPORTOPREG;
952
953#ifndef VBOX_DEVICE_STRUCT_TESTCASE
954RT_C_DECLS_BEGIN
955static void ahciHBAReset(PAHCI pThis);
956#ifdef IN_RING3
957static int ahciPostFisIntoMemory(PAHCIPort pAhciPort, unsigned uFisType, uint8_t *cmdFis);
958static void ahciPostFirstD2HFisIntoMemory(PAHCIPort pAhciPort);
959static size_t ahciCopyToPrdtl(PPDMDEVINS pDevIns, PAHCIREQ pAhciReq,
960 void *pvBuf, size_t cbBuf);
961static size_t ahciCopyFromPrdtl(PPDMDEVINS pDevIns, PAHCIREQ pAhciReq,
962 void *pvBuf, size_t cbBuf);
963static bool ahciCancelActiveTasks(PAHCIPort pAhciPort, PAHCIREQ pAhciReqExcept);
964static void ahciReqMemFree(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, bool fForceFree);
965static void ahciR3PortCachedReqsFree(PAHCIPort pAhciPort);
966#endif
967RT_C_DECLS_END
968
969#define PCIDEV_2_PAHCI(pPciDev) ( (PAHCI)(pPciDev) )
970#define PDMIMOUNT_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCIPort, IMount)) )
971#define PDMIMOUNTNOTIFY_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCIPort, IMountNotify)) )
972#define PDMIBASE_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCIPort, IBase)) )
973#define PDMIBLOCKPORT_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCIPort, IPort)) )
974#define PDMIBASE_2_PAHCI(pInterface) ( (PAHCI)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCI, IBase)) )
975#define PDMILEDPORTS_2_PAHCI(pInterface) ( (PAHCI)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCI, ILeds)) )
976
977#define AHCI_RTGCPHYS_FROM_U32(Hi, Lo) ( (RTGCPHYS)RT_MAKE_U64(Lo, Hi) )
978
979#ifdef IN_RING3
980
981# ifdef LOG_USE_C99
982# define ahciLog(a) \
983 Log(("R3 P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
984# else
985# define ahciLog(a) \
986 do { Log(("R3 P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
987# endif
988
989#elif IN_RING0
990
991# ifdef LOG_USE_C99
992# define ahciLog(a) \
993 Log(("R0 P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
994# else
995# define ahciLog(a) \
996 do { Log(("R0 P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
997# endif
998
999#elif IN_RC
1000
1001# ifdef LOG_USE_C99
1002# define ahciLog(a) \
1003 Log(("GC P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
1004# else
1005# define ahciLog(a) \
1006 do { Log(("GC P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
1007# endif
1008
1009#endif
1010
1011/**
1012 * Update PCI IRQ levels
1013 */
1014static void ahciHbaClearInterrupt(PAHCI pAhci)
1015{
1016 Log(("%s: Clearing interrupt\n", __FUNCTION__));
1017 PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 0);
1018}
1019
1020/**
1021 * Updates the IRQ level and sets port bit in the global interrupt status register of the HBA.
1022 */
1023static int ahciHbaSetInterrupt(PAHCI pAhci, uint8_t iPort, int rcBusy)
1024{
1025 Log(("P%u: %s: Setting interrupt\n", iPort, __FUNCTION__));
1026
1027 int rc = PDMCritSectEnter(&pAhci->lock, rcBusy);
1028 if (rc != VINF_SUCCESS)
1029 return rc;
1030
1031 if (pAhci->regHbaCtrl & AHCI_HBA_CTRL_IE)
1032 {
1033 if ((pAhci->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN) && (pAhci->regHbaCccPorts & (1 << iPort)))
1034 {
1035 pAhci->uCccCurrentNr++;
1036 if (pAhci->uCccCurrentNr >= pAhci->uCccNr)
1037 {
1038 /* Reset command completion coalescing state. */
1039 TMTimerSetMillies(pAhci->CTX_SUFF(pHbaCccTimer), pAhci->uCccTimeout);
1040 pAhci->uCccCurrentNr = 0;
1041
1042 pAhci->u32PortsInterrupted |= (1 << pAhci->uCccPortNr);
1043 if (!(pAhci->u32PortsInterrupted & ~(1 << pAhci->uCccPortNr)))
1044 {
1045 Log(("P%u: %s: Fire interrupt\n", iPort, __FUNCTION__));
1046 PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 1);
1047 }
1048 }
1049 }
1050 else
1051 {
1052 /* If only the bit of the actual port is set assert an interrupt
1053 * because the interrupt status register was already read by the guest
1054 * and we need to send a new notification.
1055 * Otherwise an interrupt is still pending.
1056 */
1057 ASMAtomicOrU32((volatile uint32_t *)&pAhci->u32PortsInterrupted, (1 << iPort));
1058 if (!(pAhci->u32PortsInterrupted & ~(1 << iPort)))
1059 {
1060 Log(("P%u: %s: Fire interrupt\n", iPort, __FUNCTION__));
1061 PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 1);
1062 }
1063 }
1064 }
1065
1066 PDMCritSectLeave(&pAhci->lock);
1067 return VINF_SUCCESS;
1068}
1069
1070#ifdef IN_RING3
1071/*
1072 * Assert irq when an CCC timeout occurs
1073 */
1074static DECLCALLBACK(void) ahciCccTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1075{
1076 PAHCI pAhci = (PAHCI)pvUser;
1077
1078 int rc = ahciHbaSetInterrupt(pAhci, pAhci->uCccPortNr, VERR_IGNORED);
1079 AssertRC(rc);
1080}
1081
1082/**
1083 * Finishes the port reset of the given port.
1084 *
1085 * @returns nothing.
1086 * @param pAhciPort The port to finish the reset on.
1087 */
1088static void ahciPortResetFinish(PAHCIPort pAhciPort)
1089{
1090 /* Cancel all tasks first. */
1091 bool fAllTasksCanceled = ahciCancelActiveTasks(pAhciPort, NULL);
1092 Assert(fAllTasksCanceled);
1093
1094 /* Signature for SATA device. */
1095 if (pAhciPort->fATAPI)
1096 pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
1097 else
1098 pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
1099
1100 /* We received a COMINIT from the device. Tell the guest. */
1101 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_PCS);
1102 pAhciPort->regSERR |= AHCI_PORT_SERR_X;
1103 pAhciPort->regTFD |= ATA_STAT_BUSY;
1104
1105 if ((pAhciPort->regCMD & AHCI_PORT_CMD_FRE) && (!pAhciPort->fFirstD2HFisSend))
1106 {
1107 ahciPostFirstD2HFisIntoMemory(pAhciPort);
1108 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_DHRS);
1109
1110 if (pAhciPort->regIE & AHCI_PORT_IE_DHRE)
1111 {
1112 int rc = ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
1113 AssertRC(rc);
1114 }
1115 }
1116
1117 pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
1118 (0x03 << 0); /* Device detected and communication established. */
1119
1120 /*
1121 * Use the maximum allowed speed.
1122 * (Not that it changes anything really)
1123 */
1124 switch (AHCI_PORT_SCTL_SPD_GET(pAhciPort->regSCTL))
1125 {
1126 case 0x01:
1127 pAhciPort->regSSTS |= (0x01 << 4); /* Generation 1 (1.5GBps) speed. */
1128 break;
1129 case 0x02:
1130 case 0x00:
1131 default:
1132 pAhciPort->regSSTS |= (0x02 << 4); /* Generation 2 (3.0GBps) speed. */
1133 break;
1134 }
1135
1136 ASMAtomicXchgBool(&pAhciPort->fPortReset, false);
1137}
1138#endif
1139
1140/**
1141 * Kicks the I/O thread from RC or R0.
1142 *
1143 * @returns nothing.
1144 * @param pAhci The AHCI controller instance.
1145 * @param pAhciPort The port to kick.
1146 */
1147static void ahciIoThreadKick(PAHCI pAhci, PAHCIPort pAhciPort)
1148{
1149#ifdef IN_RC
1150 PDEVPORTNOTIFIERQUEUEITEM pItem = (PDEVPORTNOTIFIERQUEUEITEM)PDMQueueAlloc(pAhci->CTX_SUFF(pNotifierQueue));
1151 AssertMsg(VALID_PTR(pItem), ("Allocating item for queue failed\n"));
1152
1153 if (pItem)
1154 {
1155 pItem->iPort = pAhciPort->iLUN;
1156 PDMQueueInsert(pAhci->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
1157 }
1158#else
1159 LogFlowFunc(("Signal event semaphore\n"));
1160 int rc = SUPSemEventSignal(pAhci->pSupDrvSession, pAhciPort->hEvtProcess);
1161 AssertRC(rc);
1162#endif
1163}
1164
1165static int PortCmdIssue_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1166{
1167 uint32_t uCIValue;
1168
1169 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1170
1171 /* Update the CI register first. */
1172 uCIValue = ASMAtomicXchgU32(&pAhciPort->u32TasksFinished, 0);
1173 pAhciPort->regCI &= ~uCIValue;
1174
1175 if ( (pAhciPort->regCMD & AHCI_PORT_CMD_CR)
1176 && u32Value > 0)
1177 {
1178 /*
1179 * Clear all tasks which are already marked as busy. The guest
1180 * shouldn't write already busy tasks actually.
1181 */
1182 u32Value &= ~pAhciPort->regCI;
1183
1184 ASMAtomicOrU32(&pAhciPort->u32TasksNew, u32Value);
1185
1186 /* Send a notification to R3 if u32TasksNew was 0 before our write. */
1187 if (ASMAtomicReadBool(&pAhciPort->fWrkThreadSleeping))
1188 ahciIoThreadKick(ahci, pAhciPort);
1189 }
1190
1191 pAhciPort->regCI |= u32Value;
1192
1193 return VINF_SUCCESS;
1194}
1195
1196static int PortCmdIssue_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1197{
1198 uint32_t uCIValue = 0;
1199
1200 uCIValue = ASMAtomicXchgU32(&pAhciPort->u32TasksFinished, 0);
1201
1202 ahciLog(("%s: read regCI=%#010x uCIValue=%#010x\n", __FUNCTION__, pAhciPort->regCI, uCIValue));
1203
1204 pAhciPort->regCI &= ~uCIValue;
1205
1206 *pu32Value = pAhciPort->regCI;
1207
1208 return VINF_SUCCESS;
1209}
1210
1211static int PortSActive_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1212{
1213 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1214
1215 pAhciPort->regSACT |= u32Value;
1216
1217 return VINF_SUCCESS;
1218}
1219
1220static int PortSActive_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1221{
1222 uint32_t u32TasksFinished = ASMAtomicXchgU32(&pAhciPort->u32QueuedTasksFinished, 0);
1223
1224 pAhciPort->regSACT &= ~u32TasksFinished;
1225
1226 ahciLog(("%s: read regSACT=%#010x regCI=%#010x u32TasksFinished=%#010x\n",
1227 __FUNCTION__, pAhciPort->regSACT, pAhciPort->regCI, u32TasksFinished));
1228
1229 *pu32Value = pAhciPort->regSACT;
1230
1231 return VINF_SUCCESS;
1232}
1233
1234static int PortSError_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1235{
1236 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1237
1238 if ( (u32Value & AHCI_PORT_SERR_X)
1239 && (pAhciPort->regSERR & AHCI_PORT_SERR_X))
1240 {
1241 ASMAtomicAndU32(&pAhciPort->regIS, ~AHCI_PORT_IS_PCS);
1242 pAhciPort->regTFD |= ATA_STAT_ERR;
1243 pAhciPort->regTFD &= ~(ATA_STAT_DRQ | ATA_STAT_BUSY);
1244 }
1245
1246 if ( (u32Value & AHCI_PORT_SERR_N)
1247 && (pAhciPort->regSERR & AHCI_PORT_SERR_N))
1248 ASMAtomicAndU32(&pAhciPort->regIS, ~AHCI_PORT_IS_PRCS);
1249
1250 pAhciPort->regSERR &= ~u32Value;
1251
1252 return VINF_SUCCESS;
1253}
1254
1255static int PortSError_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1256{
1257 ahciLog(("%s: read regSERR=%#010x\n", __FUNCTION__, pAhciPort->regSERR));
1258 *pu32Value = pAhciPort->regSERR;
1259 return VINF_SUCCESS;
1260}
1261
1262static int PortSControl_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1263{
1264 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1265 ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
1266 AHCI_PORT_SCTL_IPM_GET(u32Value), AHCI_PORT_SCTL_SPD_GET(u32Value), AHCI_PORT_SCTL_DET_GET(u32Value)));
1267
1268#ifndef IN_RING3
1269 return VINF_IOM_R3_MMIO_WRITE;
1270#else
1271 if ((u32Value & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_INIT)
1272 {
1273 if (!ASMAtomicXchgBool(&pAhciPort->fPortReset, true))
1274 LogRel(("AHCI#%u: Port %d reset\n", ahci->CTX_SUFF(pDevIns)->iInstance,
1275 pAhciPort->iLUN));
1276
1277 pAhciPort->regSSTS = 0;
1278 pAhciPort->regSIG = ~0;
1279 pAhciPort->regTFD = 0x7f;
1280 pAhciPort->fFirstD2HFisSend = false;
1281 pAhciPort->regSCTL = u32Value;
1282 }
1283 else if ( (u32Value & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_NINIT
1284 && (pAhciPort->regSCTL & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_INIT
1285 && pAhciPort->pDrvBase)
1286 {
1287 /* Do the port reset here, so the guest sees the new status immediately. */
1288 if (ahci->fLegacyPortResetMethod)
1289 {
1290 ahciPortResetFinish(pAhciPort);
1291 pAhciPort->regSCTL = u32Value; /* Update after finishing the reset, so the I/O thread doesn't get a chance to do the reset. */
1292 }
1293 else
1294 {
1295 pAhciPort->regSSTS = 0x1; /* Indicate device presence detected but communication not established. */
1296 pAhciPort->regSCTL = u32Value; /* Update before kicking the I/O thread. */
1297
1298 /* Kick the thread to finish the reset. */
1299 ahciIoThreadKick(ahci, pAhciPort);
1300 }
1301 }
1302 else /* Just update the value if there is no device attached. */
1303 pAhciPort->regSCTL = u32Value;
1304
1305 return VINF_SUCCESS;
1306#endif
1307}
1308
1309static int PortSControl_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1310{
1311 ahciLog(("%s: read regSCTL=%#010x\n", __FUNCTION__, pAhciPort->regSCTL));
1312 ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
1313 AHCI_PORT_SCTL_IPM_GET(pAhciPort->regSCTL), AHCI_PORT_SCTL_SPD_GET(pAhciPort->regSCTL),
1314 AHCI_PORT_SCTL_DET_GET(pAhciPort->regSCTL)));
1315
1316 *pu32Value = pAhciPort->regSCTL;
1317 return VINF_SUCCESS;
1318}
1319
1320static int PortSStatus_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1321{
1322 ahciLog(("%s: read regSSTS=%#010x\n", __FUNCTION__, pAhciPort->regSSTS));
1323 ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
1324 AHCI_PORT_SSTS_IPM_GET(pAhciPort->regSSTS), AHCI_PORT_SSTS_SPD_GET(pAhciPort->regSSTS),
1325 AHCI_PORT_SSTS_DET_GET(pAhciPort->regSSTS)));
1326
1327 *pu32Value = pAhciPort->regSSTS;
1328 return VINF_SUCCESS;
1329}
1330
1331static int PortSignature_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1332{
1333 ahciLog(("%s: read regSIG=%#010x\n", __FUNCTION__, pAhciPort->regSIG));
1334 *pu32Value = pAhciPort->regSIG;
1335 return VINF_SUCCESS;
1336}
1337
1338static int PortTaskFileData_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1339{
1340 ahciLog(("%s: read regTFD=%#010x\n", __FUNCTION__, pAhciPort->regTFD));
1341 ahciLog(("%s: ERR=%x BSY=%d DRQ=%d ERR=%d\n", __FUNCTION__,
1342 (pAhciPort->regTFD >> 8), (pAhciPort->regTFD & AHCI_PORT_TFD_BSY) >> 7,
1343 (pAhciPort->regTFD & AHCI_PORT_TFD_DRQ) >> 3, (pAhciPort->regTFD & AHCI_PORT_TFD_ERR)));
1344 *pu32Value = pAhciPort->regTFD;
1345 return VINF_SUCCESS;
1346}
1347
1348/**
1349 * Read from the port command register.
1350 */
1351static int PortCmd_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1352{
1353 ahciLog(("%s: read regCMD=%#010x\n", __FUNCTION__, pAhciPort->regCMD | AHCI_PORT_CMD_CCS_SHIFT(pAhciPort->u32CurrentCommandSlot)));
1354 ahciLog(("%s: ICC=%d ASP=%d ALPE=%d DLAE=%d ATAPI=%d CPD=%d ISP=%d HPCP=%d PMA=%d CPS=%d CR=%d FR=%d ISS=%d CCS=%d FRE=%d CLO=%d POD=%d SUD=%d ST=%d\n",
1355 __FUNCTION__, (pAhciPort->regCMD & AHCI_PORT_CMD_ICC) >> 28, (pAhciPort->regCMD & AHCI_PORT_CMD_ASP) >> 27,
1356 (pAhciPort->regCMD & AHCI_PORT_CMD_ALPE) >> 26, (pAhciPort->regCMD & AHCI_PORT_CMD_DLAE) >> 25,
1357 (pAhciPort->regCMD & AHCI_PORT_CMD_ATAPI) >> 24, (pAhciPort->regCMD & AHCI_PORT_CMD_CPD) >> 20,
1358 (pAhciPort->regCMD & AHCI_PORT_CMD_ISP) >> 19, (pAhciPort->regCMD & AHCI_PORT_CMD_HPCP) >> 18,
1359 (pAhciPort->regCMD & AHCI_PORT_CMD_PMA) >> 17, (pAhciPort->regCMD & AHCI_PORT_CMD_CPS) >> 16,
1360 (pAhciPort->regCMD & AHCI_PORT_CMD_CR) >> 15, (pAhciPort->regCMD & AHCI_PORT_CMD_FR) >> 14,
1361 (pAhciPort->regCMD & AHCI_PORT_CMD_ISS) >> 13, pAhciPort->u32CurrentCommandSlot,
1362 (pAhciPort->regCMD & AHCI_PORT_CMD_FRE) >> 4, (pAhciPort->regCMD & AHCI_PORT_CMD_CLO) >> 3,
1363 (pAhciPort->regCMD & AHCI_PORT_CMD_POD) >> 2, (pAhciPort->regCMD & AHCI_PORT_CMD_SUD) >> 1,
1364 (pAhciPort->regCMD & AHCI_PORT_CMD_ST)));
1365 *pu32Value = pAhciPort->regCMD | AHCI_PORT_CMD_CCS_SHIFT(pAhciPort->u32CurrentCommandSlot);
1366 return VINF_SUCCESS;
1367}
1368
1369/**
1370 * Write to the port command register.
1371 * This is the register where all the data transfer is started
1372 */
1373static int PortCmd_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1374{
1375 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1376 ahciLog(("%s: ICC=%d ASP=%d ALPE=%d DLAE=%d ATAPI=%d CPD=%d ISP=%d HPCP=%d PMA=%d CPS=%d CR=%d FR=%d ISS=%d CCS=%d FRE=%d CLO=%d POD=%d SUD=%d ST=%d\n",
1377 __FUNCTION__, (u32Value & AHCI_PORT_CMD_ICC) >> 28, (u32Value & AHCI_PORT_CMD_ASP) >> 27,
1378 (u32Value & AHCI_PORT_CMD_ALPE) >> 26, (u32Value & AHCI_PORT_CMD_DLAE) >> 25,
1379 (u32Value & AHCI_PORT_CMD_ATAPI) >> 24, (u32Value & AHCI_PORT_CMD_CPD) >> 20,
1380 (u32Value & AHCI_PORT_CMD_ISP) >> 19, (u32Value & AHCI_PORT_CMD_HPCP) >> 18,
1381 (u32Value & AHCI_PORT_CMD_PMA) >> 17, (u32Value & AHCI_PORT_CMD_CPS) >> 16,
1382 (u32Value & AHCI_PORT_CMD_CR) >> 15, (u32Value & AHCI_PORT_CMD_FR) >> 14,
1383 (u32Value & AHCI_PORT_CMD_ISS) >> 13, (u32Value & AHCI_PORT_CMD_CCS) >> 8,
1384 (u32Value & AHCI_PORT_CMD_FRE) >> 4, (u32Value & AHCI_PORT_CMD_CLO) >> 3,
1385 (u32Value & AHCI_PORT_CMD_POD) >> 2, (u32Value & AHCI_PORT_CMD_SUD) >> 1,
1386 (u32Value & AHCI_PORT_CMD_ST)));
1387
1388 /* The PxCMD.CCS bits are R/O and maintained separately. */
1389 u32Value &= ~AHCI_PORT_CMD_CCS;
1390
1391 if (pAhciPort->fPoweredOn && pAhciPort->fSpunUp)
1392 {
1393 if (u32Value & AHCI_PORT_CMD_CLO)
1394 {
1395 ahciLog(("%s: Command list override requested\n", __FUNCTION__));
1396 u32Value &= ~(AHCI_PORT_TFD_BSY | AHCI_PORT_TFD_DRQ);
1397 /* Clear the CLO bit. */
1398 u32Value &= ~(AHCI_PORT_CMD_CLO);
1399 }
1400
1401 if (u32Value & AHCI_PORT_CMD_ST)
1402 {
1403 /*
1404 * Set engine state to running if there is a device attached and
1405 * IS.PCS is clear.
1406 */
1407 if ( pAhciPort->pDrvBase
1408 && !(pAhciPort->regIS & AHCI_PORT_IS_PCS))
1409 {
1410 ahciLog(("%s: Engine starts\n", __FUNCTION__));
1411 u32Value |= AHCI_PORT_CMD_CR;
1412
1413 /* If there is something in CI, kick the I/O thread. */
1414 if ( pAhciPort->regCI > 0
1415 && ASMAtomicReadBool(&pAhciPort->fWrkThreadSleeping))
1416 {
1417 ASMAtomicOrU32(&pAhciPort->u32TasksNew, pAhciPort->regCI);
1418#ifdef IN_RC
1419 PDEVPORTNOTIFIERQUEUEITEM pItem = (PDEVPORTNOTIFIERQUEUEITEM)PDMQueueAlloc(ahci->CTX_SUFF(pNotifierQueue));
1420 AssertMsg(VALID_PTR(pItem), ("Allocating item for queue failed\n"));
1421
1422 pItem->iPort = pAhciPort->iLUN;
1423 PDMQueueInsert(ahci->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
1424#else
1425 LogFlowFunc(("Signal event semaphore\n"));
1426 int rc = SUPSemEventSignal(ahci->pSupDrvSession, pAhciPort->hEvtProcess);
1427 AssertRC(rc);
1428#endif
1429 }
1430 }
1431 else
1432 u32Value &= ~AHCI_PORT_CMD_CR;
1433 }
1434 else
1435 {
1436 ahciLog(("%s: Engine stops\n", __FUNCTION__));
1437 /* Clear command issue register. */
1438 pAhciPort->regCI = 0;
1439 pAhciPort->regSACT = 0;
1440 /* Clear current command slot. */
1441 pAhciPort->u32CurrentCommandSlot = 0;
1442 u32Value &= ~AHCI_PORT_CMD_CR;
1443 }
1444 }
1445 else if (pAhciPort->pDrvBase)
1446 {
1447 if ((u32Value & AHCI_PORT_CMD_POD) && (pAhciPort->regCMD & AHCI_PORT_CMD_CPS) && !pAhciPort->fPoweredOn)
1448 {
1449 ahciLog(("%s: Power on the device\n", __FUNCTION__));
1450 pAhciPort->fPoweredOn = true;
1451
1452 /*
1453 * Set states in the Port Signature and SStatus registers.
1454 */
1455 if (pAhciPort->fATAPI)
1456 pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
1457 else
1458 pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
1459 pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
1460 (0x02 << 4) | /* Generation 2 (3.0GBps) speed. */
1461 (0x03 << 0); /* Device detected and communication established. */
1462
1463 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
1464 {
1465#ifndef IN_RING3
1466 return VINF_IOM_R3_MMIO_WRITE;
1467#else
1468 ahciPostFirstD2HFisIntoMemory(pAhciPort);
1469 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_DHRS);
1470
1471 if (pAhciPort->regIE & AHCI_PORT_IE_DHRE)
1472 {
1473 int rc = ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
1474 AssertRC(rc);
1475 }
1476#endif
1477 }
1478 }
1479
1480 if ((u32Value & AHCI_PORT_CMD_SUD) && pAhciPort->fPoweredOn && !pAhciPort->fSpunUp)
1481 {
1482 ahciLog(("%s: Spin up the device\n", __FUNCTION__));
1483 pAhciPort->fSpunUp = true;
1484 }
1485 }
1486
1487 if (u32Value & AHCI_PORT_CMD_FRE)
1488 {
1489 ahciLog(("%s: FIS receive enabled\n", __FUNCTION__));
1490
1491 u32Value |= AHCI_PORT_CMD_FR;
1492
1493 /* Send the first D2H FIS only if it wasn't already send. */
1494 if ( !pAhciPort->fFirstD2HFisSend
1495 && pAhciPort->pDrvBase)
1496 {
1497#ifndef IN_RING3
1498 return VINF_IOM_R3_MMIO_WRITE;
1499#else
1500 ahciPostFirstD2HFisIntoMemory(pAhciPort);
1501 pAhciPort->fFirstD2HFisSend = true;
1502#endif
1503 }
1504 }
1505 else if (!(u32Value & AHCI_PORT_CMD_FRE))
1506 {
1507 ahciLog(("%s: FIS receive disabled\n", __FUNCTION__));
1508 u32Value &= ~AHCI_PORT_CMD_FR;
1509 }
1510
1511 pAhciPort->regCMD = u32Value;
1512
1513 return VINF_SUCCESS;
1514}
1515
1516/**
1517 * Read from the port interrupt enable register.
1518 */
1519static int PortIntrEnable_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1520{
1521 ahciLog(("%s: read regIE=%#010x\n", __FUNCTION__, pAhciPort->regIE));
1522 ahciLog(("%s: CPDE=%d TFEE=%d HBFE=%d HBDE=%d IFE=%d INFE=%d OFE=%d IPME=%d PRCE=%d DIE=%d PCE=%d DPE=%d UFE=%d SDBE=%d DSE=%d PSE=%d DHRE=%d\n",
1523 __FUNCTION__, (pAhciPort->regIE & AHCI_PORT_IE_CPDE) >> 31, (pAhciPort->regIE & AHCI_PORT_IE_TFEE) >> 30,
1524 (pAhciPort->regIE & AHCI_PORT_IE_HBFE) >> 29, (pAhciPort->regIE & AHCI_PORT_IE_HBDE) >> 28,
1525 (pAhciPort->regIE & AHCI_PORT_IE_IFE) >> 27, (pAhciPort->regIE & AHCI_PORT_IE_INFE) >> 26,
1526 (pAhciPort->regIE & AHCI_PORT_IE_OFE) >> 24, (pAhciPort->regIE & AHCI_PORT_IE_IPME) >> 23,
1527 (pAhciPort->regIE & AHCI_PORT_IE_PRCE) >> 22, (pAhciPort->regIE & AHCI_PORT_IE_DIE) >> 7,
1528 (pAhciPort->regIE & AHCI_PORT_IE_PCE) >> 6, (pAhciPort->regIE & AHCI_PORT_IE_DPE) >> 5,
1529 (pAhciPort->regIE & AHCI_PORT_IE_UFE) >> 4, (pAhciPort->regIE & AHCI_PORT_IE_SDBE) >> 3,
1530 (pAhciPort->regIE & AHCI_PORT_IE_DSE) >> 2, (pAhciPort->regIE & AHCI_PORT_IE_PSE) >> 1,
1531 (pAhciPort->regIE & AHCI_PORT_IE_DHRE)));
1532 *pu32Value = pAhciPort->regIE;
1533 return VINF_SUCCESS;
1534}
1535
1536/**
1537 * Write to the port interrupt enable register.
1538 */
1539static int PortIntrEnable_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1540{
1541 int rc = VINF_SUCCESS;
1542 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1543 ahciLog(("%s: CPDE=%d TFEE=%d HBFE=%d HBDE=%d IFE=%d INFE=%d OFE=%d IPME=%d PRCE=%d DIE=%d PCE=%d DPE=%d UFE=%d SDBE=%d DSE=%d PSE=%d DHRE=%d\n",
1544 __FUNCTION__, (u32Value & AHCI_PORT_IE_CPDE) >> 31, (u32Value & AHCI_PORT_IE_TFEE) >> 30,
1545 (u32Value & AHCI_PORT_IE_HBFE) >> 29, (u32Value & AHCI_PORT_IE_HBDE) >> 28,
1546 (u32Value & AHCI_PORT_IE_IFE) >> 27, (u32Value & AHCI_PORT_IE_INFE) >> 26,
1547 (u32Value & AHCI_PORT_IE_OFE) >> 24, (u32Value & AHCI_PORT_IE_IPME) >> 23,
1548 (u32Value & AHCI_PORT_IE_PRCE) >> 22, (u32Value & AHCI_PORT_IE_DIE) >> 7,
1549 (u32Value & AHCI_PORT_IE_PCE) >> 6, (u32Value & AHCI_PORT_IE_DPE) >> 5,
1550 (u32Value & AHCI_PORT_IE_UFE) >> 4, (u32Value & AHCI_PORT_IE_SDBE) >> 3,
1551 (u32Value & AHCI_PORT_IE_DSE) >> 2, (u32Value & AHCI_PORT_IE_PSE) >> 1,
1552 (u32Value & AHCI_PORT_IE_DHRE)));
1553
1554 u32Value &= AHCI_PORT_IE_READONLY;
1555
1556 /* Check if some a interrupt status bit changed*/
1557 uint32_t u32IntrStatus = ASMAtomicReadU32(&pAhciPort->regIS);
1558
1559 if (u32Value & u32IntrStatus)
1560 rc = ahciHbaSetInterrupt(ahci, pAhciPort->iLUN, VINF_IOM_R3_MMIO_WRITE);
1561
1562 if (rc == VINF_SUCCESS)
1563 pAhciPort->regIE = u32Value;
1564
1565 return rc;
1566}
1567
1568/**
1569 * Read from the port interrupt status register.
1570 */
1571static int PortIntrSts_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1572{
1573 ahciLog(("%s: read regIS=%#010x\n", __FUNCTION__, pAhciPort->regIS));
1574 ahciLog(("%s: CPDS=%d TFES=%d HBFS=%d HBDS=%d IFS=%d INFS=%d OFS=%d IPMS=%d PRCS=%d DIS=%d PCS=%d DPS=%d UFS=%d SDBS=%d DSS=%d PSS=%d DHRS=%d\n",
1575 __FUNCTION__, (pAhciPort->regIS & AHCI_PORT_IS_CPDS) >> 31, (pAhciPort->regIS & AHCI_PORT_IS_TFES) >> 30,
1576 (pAhciPort->regIS & AHCI_PORT_IS_HBFS) >> 29, (pAhciPort->regIS & AHCI_PORT_IS_HBDS) >> 28,
1577 (pAhciPort->regIS & AHCI_PORT_IS_IFS) >> 27, (pAhciPort->regIS & AHCI_PORT_IS_INFS) >> 26,
1578 (pAhciPort->regIS & AHCI_PORT_IS_OFS) >> 24, (pAhciPort->regIS & AHCI_PORT_IS_IPMS) >> 23,
1579 (pAhciPort->regIS & AHCI_PORT_IS_PRCS) >> 22, (pAhciPort->regIS & AHCI_PORT_IS_DIS) >> 7,
1580 (pAhciPort->regIS & AHCI_PORT_IS_PCS) >> 6, (pAhciPort->regIS & AHCI_PORT_IS_DPS) >> 5,
1581 (pAhciPort->regIS & AHCI_PORT_IS_UFS) >> 4, (pAhciPort->regIS & AHCI_PORT_IS_SDBS) >> 3,
1582 (pAhciPort->regIS & AHCI_PORT_IS_DSS) >> 2, (pAhciPort->regIS & AHCI_PORT_IS_PSS) >> 1,
1583 (pAhciPort->regIS & AHCI_PORT_IS_DHRS)));
1584 *pu32Value = pAhciPort->regIS;
1585 return VINF_SUCCESS;
1586}
1587
1588/**
1589 * Write to the port interrupt status register.
1590 */
1591static int PortIntrSts_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1592{
1593 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1594 ASMAtomicAndU32(&pAhciPort->regIS, ~(u32Value & AHCI_PORT_IS_READONLY));
1595
1596 return VINF_SUCCESS;
1597}
1598
1599/**
1600 * Read from the port FIS base address upper 32bit register.
1601 */
1602static int PortFisAddrUp_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1603{
1604 ahciLog(("%s: read regFBU=%#010x\n", __FUNCTION__, pAhciPort->regFBU));
1605 *pu32Value = pAhciPort->regFBU;
1606 return VINF_SUCCESS;
1607}
1608
1609/**
1610 * Write to the port FIS base address upper 32bit register.
1611 */
1612static int PortFisAddrUp_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1613{
1614 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1615
1616 pAhciPort->regFBU = u32Value;
1617 pAhciPort->GCPhysAddrFb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regFBU, pAhciPort->regFB);
1618
1619 return VINF_SUCCESS;
1620}
1621
1622/**
1623 * Read from the port FIS base address register.
1624 */
1625static int PortFisAddr_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1626{
1627 ahciLog(("%s: read regFB=%#010x\n", __FUNCTION__, pAhciPort->regFB));
1628 *pu32Value = pAhciPort->regFB;
1629 return VINF_SUCCESS;
1630}
1631
1632/**
1633 * Write to the port FIS base address register.
1634 */
1635static int PortFisAddr_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1636{
1637 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1638
1639 Assert(!(u32Value & ~AHCI_PORT_FB_RESERVED));
1640
1641 pAhciPort->regFB = (u32Value & AHCI_PORT_FB_RESERVED);
1642 pAhciPort->GCPhysAddrFb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regFBU, pAhciPort->regFB);
1643
1644 return VINF_SUCCESS;
1645}
1646
1647/**
1648 * Write to the port command list base address upper 32bit register.
1649 */
1650static int PortCmdLstAddrUp_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1651{
1652 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1653
1654 pAhciPort->regCLBU = u32Value;
1655 pAhciPort->GCPhysAddrClb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regCLBU, pAhciPort->regCLB);
1656
1657 return VINF_SUCCESS;
1658}
1659
1660/**
1661 * Read from the port command list base address upper 32bit register.
1662 */
1663static int PortCmdLstAddrUp_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1664{
1665 ahciLog(("%s: read regCLBU=%#010x\n", __FUNCTION__, pAhciPort->regCLBU));
1666 *pu32Value = pAhciPort->regCLBU;
1667 return VINF_SUCCESS;
1668}
1669
1670/**
1671 * Read from the port command list base address register.
1672 */
1673static int PortCmdLstAddr_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1674{
1675 ahciLog(("%s: read regCLB=%#010x\n", __FUNCTION__, pAhciPort->regCLB));
1676 *pu32Value = pAhciPort->regCLB;
1677 return VINF_SUCCESS;
1678}
1679
1680/**
1681 * Write to the port command list base address register.
1682 */
1683static int PortCmdLstAddr_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1684{
1685 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1686
1687 Assert(!(u32Value & ~AHCI_PORT_CLB_RESERVED));
1688
1689 pAhciPort->regCLB = (u32Value & AHCI_PORT_CLB_RESERVED);
1690 pAhciPort->GCPhysAddrClb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regCLBU, pAhciPort->regCLB);
1691
1692 return VINF_SUCCESS;
1693}
1694
1695/**
1696 * Read from the global Version register.
1697 */
1698static int HbaVersion_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1699{
1700 Log(("%s: read regHbaVs=%#010x\n", __FUNCTION__, ahci->regHbaVs));
1701 *pu32Value = ahci->regHbaVs;
1702 return VINF_SUCCESS;
1703}
1704
1705/**
1706 * Read from the global Ports implemented register.
1707 */
1708static int HbaPortsImplemented_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1709{
1710 Log(("%s: read regHbaPi=%#010x\n", __FUNCTION__, ahci->regHbaPi));
1711 *pu32Value = ahci->regHbaPi;
1712 return VINF_SUCCESS;
1713}
1714
1715/**
1716 * Write to the global interrupt status register.
1717 */
1718static int HbaInterruptStatus_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)
1719{
1720 int rc;
1721 Log(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1722
1723 rc = PDMCritSectEnter(&ahci->lock, VINF_IOM_R3_MMIO_WRITE);
1724 if (rc != VINF_SUCCESS)
1725 return rc;
1726
1727 ahci->regHbaIs &= ~(u32Value);
1728
1729 /*
1730 * Update interrupt status register and check for ports who
1731 * set the interrupt inbetween.
1732 */
1733 bool fClear = true;
1734 ahci->regHbaIs |= ASMAtomicXchgU32(&ahci->u32PortsInterrupted, 0);
1735 if (!ahci->regHbaIs)
1736 {
1737 unsigned i = 0;
1738
1739 /* Check if the cleared ports have a interrupt status bit set. */
1740 while ((u32Value > 0) && (i < AHCI_MAX_NR_PORTS_IMPL))
1741 {
1742 if (u32Value & 0x01)
1743 {
1744 PAHCIPort pAhciPort = &ahci->ahciPort[i];
1745
1746 if (pAhciPort->regIE & pAhciPort->regIS)
1747 {
1748 Log(("%s: Interrupt status of port %u set -> Set interrupt again\n", __FUNCTION__, i));
1749 ASMAtomicOrU32(&ahci->u32PortsInterrupted, 1 << i);
1750 fClear = false;
1751 break;
1752 }
1753 }
1754 u32Value >>= 1;
1755 i++;
1756 }
1757 }
1758 else
1759 fClear = false;
1760
1761 if (fClear)
1762 ahciHbaClearInterrupt(ahci);
1763 else
1764 {
1765 Log(("%s: Not clearing interrupt: u32PortsInterrupted=%#010x\n", __FUNCTION__, ahci->u32PortsInterrupted));
1766 /*
1767 * We need to set the interrupt again because the I/O APIC does not set it again even if the
1768 * line is still high.
1769 * We need to clear it first because the PCI bus only calls the interrupt controller if the state changes.
1770 */
1771 PDMDevHlpPCISetIrq(ahci->CTX_SUFF(pDevIns), 0, 0);
1772 PDMDevHlpPCISetIrq(ahci->CTX_SUFF(pDevIns), 0, 1);
1773 }
1774
1775 PDMCritSectLeave(&ahci->lock);
1776 return VINF_SUCCESS;
1777}
1778
1779/**
1780 * Read from the global interrupt status register.
1781 */
1782static int HbaInterruptStatus_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1783{
1784 uint32_t u32PortsInterrupted;
1785 int rc;
1786
1787 rc = PDMCritSectEnter(&ahci->lock, VINF_IOM_R3_MMIO_READ);
1788 if (rc != VINF_SUCCESS)
1789 return rc;
1790
1791 u32PortsInterrupted = ASMAtomicXchgU32(&ahci->u32PortsInterrupted, 0);
1792
1793 PDMCritSectLeave(&ahci->lock);
1794 Log(("%s: read regHbaIs=%#010x u32PortsInterrupted=%#010x\n", __FUNCTION__, ahci->regHbaIs, u32PortsInterrupted));
1795
1796 ahci->regHbaIs |= u32PortsInterrupted;
1797
1798#ifdef LOG_ENABLED
1799 Log(("%s:", __FUNCTION__));
1800 unsigned i;
1801 for (i = 0; i < ahci->cPortsImpl; i++)
1802 {
1803 if ((ahci->regHbaIs >> i) & 0x01)
1804 Log((" P%d", i));
1805 }
1806 Log(("\n"));
1807#endif
1808
1809 *pu32Value = ahci->regHbaIs;
1810
1811 return VINF_SUCCESS;
1812}
1813
1814/**
1815 * Write to the global control register.
1816 */
1817static int HbaControl_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)
1818{
1819 Log(("%s: write u32Value=%#010x\n"
1820 "%s: AE=%d IE=%d HR=%d\n",
1821 __FUNCTION__, u32Value,
1822 __FUNCTION__, (u32Value & AHCI_HBA_CTRL_AE) >> 31, (u32Value & AHCI_HBA_CTRL_IE) >> 1,
1823 (u32Value & AHCI_HBA_CTRL_HR)));
1824
1825#ifndef IN_RING3
1826 return VINF_IOM_R3_MMIO_WRITE;
1827#else
1828 /*
1829 * Increase the active thread counter because we might set the host controller
1830 * reset bit.
1831 */
1832 ASMAtomicIncU32(&ahci->cThreadsActive);
1833 ASMAtomicWriteU32(&ahci->regHbaCtrl, (u32Value & AHCI_HBA_CTRL_RW_MASK) | AHCI_HBA_CTRL_AE);
1834
1835 /*
1836 * Do the HBA reset if requested and there is no other active thread at the moment,
1837 * the work is deferred to the last active thread otherwise.
1838 */
1839 uint32_t cThreadsActive = ASMAtomicDecU32(&ahci->cThreadsActive);
1840 if ( (u32Value & AHCI_HBA_CTRL_HR)
1841 && !cThreadsActive)
1842 ahciHBAReset(ahci);
1843
1844 return VINF_SUCCESS;
1845#endif
1846}
1847
1848/**
1849 * Read the global control register.
1850 */
1851static int HbaControl_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1852{
1853 Log(("%s: read regHbaCtrl=%#010x\n"
1854 "%s: AE=%d IE=%d HR=%d\n",
1855 __FUNCTION__, ahci->regHbaCtrl,
1856 __FUNCTION__, (ahci->regHbaCtrl & AHCI_HBA_CTRL_AE) >> 31, (ahci->regHbaCtrl & AHCI_HBA_CTRL_IE) >> 1,
1857 (ahci->regHbaCtrl & AHCI_HBA_CTRL_HR)));
1858 *pu32Value = ahci->regHbaCtrl;
1859 return VINF_SUCCESS;
1860}
1861
1862/**
1863 * Read the global capabilities register.
1864 */
1865static int HbaCapabilities_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1866{
1867 Log(("%s: read regHbaCap=%#010x\n"
1868 "%s: S64A=%d SNCQ=%d SIS=%d SSS=%d SALP=%d SAL=%d SCLO=%d ISS=%d SNZO=%d SAM=%d SPM=%d PMD=%d SSC=%d PSC=%d NCS=%d NP=%d\n",
1869 __FUNCTION__, ahci->regHbaCap,
1870 __FUNCTION__, (ahci->regHbaCap & AHCI_HBA_CAP_S64A) >> 31, (ahci->regHbaCap & AHCI_HBA_CAP_SNCQ) >> 30,
1871 (ahci->regHbaCap & AHCI_HBA_CAP_SIS) >> 28, (ahci->regHbaCap & AHCI_HBA_CAP_SSS) >> 27,
1872 (ahci->regHbaCap & AHCI_HBA_CAP_SALP) >> 26, (ahci->regHbaCap & AHCI_HBA_CAP_SAL) >> 25,
1873 (ahci->regHbaCap & AHCI_HBA_CAP_SCLO) >> 24, (ahci->regHbaCap & AHCI_HBA_CAP_ISS) >> 20,
1874 (ahci->regHbaCap & AHCI_HBA_CAP_SNZO) >> 19, (ahci->regHbaCap & AHCI_HBA_CAP_SAM) >> 18,
1875 (ahci->regHbaCap & AHCI_HBA_CAP_SPM) >> 17, (ahci->regHbaCap & AHCI_HBA_CAP_PMD) >> 15,
1876 (ahci->regHbaCap & AHCI_HBA_CAP_SSC) >> 14, (ahci->regHbaCap & AHCI_HBA_CAP_PSC) >> 13,
1877 (ahci->regHbaCap & AHCI_HBA_CAP_NCS) >> 8, (ahci->regHbaCap & AHCI_HBA_CAP_NP)));
1878 *pu32Value = ahci->regHbaCap;
1879 return VINF_SUCCESS;
1880}
1881
1882/**
1883 * Write to the global command completion coalescing control register.
1884 */
1885static int HbaCccCtl_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)
1886{
1887 Log(("%s: write u32Value=%#010x\n"
1888 "%s: TV=%d CC=%d INT=%d EN=%d\n",
1889 __FUNCTION__, u32Value,
1890 __FUNCTION__, AHCI_HBA_CCC_CTL_TV_GET(u32Value), AHCI_HBA_CCC_CTL_CC_GET(u32Value),
1891 AHCI_HBA_CCC_CTL_INT_GET(u32Value), (u32Value & AHCI_HBA_CCC_CTL_EN)));
1892
1893 ahci->regHbaCccCtl = u32Value;
1894 ahci->uCccTimeout = AHCI_HBA_CCC_CTL_TV_GET(u32Value);
1895 ahci->uCccPortNr = AHCI_HBA_CCC_CTL_INT_GET(u32Value);
1896 ahci->uCccNr = AHCI_HBA_CCC_CTL_CC_GET(u32Value);
1897
1898 if (u32Value & AHCI_HBA_CCC_CTL_EN)
1899 {
1900 /* Arm the timer */
1901 TMTimerSetMillies(ahci->CTX_SUFF(pHbaCccTimer), ahci->uCccTimeout);
1902 }
1903 else
1904 {
1905 TMTimerStop(ahci->CTX_SUFF(pHbaCccTimer));
1906 }
1907
1908 return VINF_SUCCESS;
1909}
1910
1911/**
1912 * Read the global command completion coalescing control register.
1913 */
1914static int HbaCccCtl_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1915{
1916 Log(("%s: read regHbaCccCtl=%#010x\n"
1917 "%s: TV=%d CC=%d INT=%d EN=%d\n",
1918 __FUNCTION__, ahci->regHbaCccCtl,
1919 __FUNCTION__, AHCI_HBA_CCC_CTL_TV_GET(ahci->regHbaCccCtl), AHCI_HBA_CCC_CTL_CC_GET(ahci->regHbaCccCtl),
1920 AHCI_HBA_CCC_CTL_INT_GET(ahci->regHbaCccCtl), (ahci->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN)));
1921 *pu32Value = ahci->regHbaCccCtl;
1922 return VINF_SUCCESS;
1923}
1924
1925/**
1926 * Write to the global command completion coalescing ports register.
1927 */
1928static int HbaCccPorts_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)
1929{
1930 Log(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
1931
1932 ahci->regHbaCccPorts = u32Value;
1933
1934 return VINF_SUCCESS;
1935}
1936
1937/**
1938 * Read the global command completion coalescing ports register.
1939 */
1940static int HbaCccPorts_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1941{
1942 Log(("%s: read regHbaCccPorts=%#010x\n", __FUNCTION__, ahci->regHbaCccPorts));
1943
1944#ifdef LOG_ENABLED
1945 Log(("%s:", __FUNCTION__));
1946 unsigned i;
1947 for (i = 0; i < ahci->cPortsImpl; i++)
1948 {
1949 if ((ahci->regHbaCccPorts >> i) & 0x01)
1950 Log((" P%d", i));
1951 }
1952 Log(("\n"));
1953#endif
1954
1955 *pu32Value = ahci->regHbaCccPorts;
1956 return VINF_SUCCESS;
1957}
1958
1959/**
1960 * Invalid write to global register
1961 */
1962static int HbaInvalid_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)
1963{
1964 Log(("%s: Write denied!!! iReg=%u u32Value=%#010x\n", __FUNCTION__, iReg, u32Value));
1965 return VINF_SUCCESS;
1966}
1967
1968/**
1969 * Invalid Port write.
1970 */
1971static int PortInvalid_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
1972{
1973 ahciLog(("%s: Write denied!!! iReg=%u u32Value=%#010x\n", __FUNCTION__, iReg, u32Value));
1974 return VINF_SUCCESS;
1975}
1976
1977/**
1978 * Invalid Port read.
1979 */
1980static int PortInvalid_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
1981{
1982 ahciLog(("%s: Read denied!!! iReg=%u\n", __FUNCTION__, iReg));
1983 return VINF_SUCCESS;
1984}
1985
1986/**
1987 * Register descriptor table for global HBA registers
1988 */
1989static const AHCIOPREG g_aOpRegs[] =
1990{
1991 {"HbaCapabilites", HbaCapabilities_r, HbaInvalid_w}, /* Readonly */
1992 {"HbaControl" , HbaControl_r, HbaControl_w},
1993 {"HbaInterruptStatus", HbaInterruptStatus_r, HbaInterruptStatus_w},
1994 {"HbaPortsImplemented", HbaPortsImplemented_r, HbaInvalid_w}, /* Readonly */
1995 {"HbaVersion", HbaVersion_r, HbaInvalid_w}, /* ReadOnly */
1996 {"HbaCccCtl", HbaCccCtl_r, HbaCccCtl_w},
1997 {"HbaCccPorts", HbaCccPorts_r, HbaCccPorts_w},
1998};
1999
2000/**
2001 * Register descriptor table for port registers
2002 */
2003static const AHCIPORTOPREG g_aPortOpRegs[] =
2004{
2005 {"PortCmdLstAddr", PortCmdLstAddr_r, PortCmdLstAddr_w},
2006 {"PortCmdLstAddrUp", PortCmdLstAddrUp_r, PortCmdLstAddrUp_w},
2007 {"PortFisAddr", PortFisAddr_r, PortFisAddr_w},
2008 {"PortFisAddrUp", PortFisAddrUp_r, PortFisAddrUp_w},
2009 {"PortIntrSts", PortIntrSts_r, PortIntrSts_w},
2010 {"PortIntrEnable", PortIntrEnable_r, PortIntrEnable_w},
2011 {"PortCmd", PortCmd_r, PortCmd_w},
2012 {"PortReserved1", PortInvalid_r, PortInvalid_w}, /* Not used. */
2013 {"PortTaskFileData", PortTaskFileData_r, PortInvalid_w}, /* Readonly */
2014 {"PortSignature", PortSignature_r, PortInvalid_w}, /* Readonly */
2015 {"PortSStatus", PortSStatus_r, PortInvalid_w}, /* Readonly */
2016 {"PortSControl", PortSControl_r, PortSControl_w},
2017 {"PortSError", PortSError_r, PortSError_w},
2018 {"PortSActive", PortSActive_r, PortSActive_w},
2019 {"PortCmdIssue", PortCmdIssue_r, PortCmdIssue_w},
2020 {"PortReserved2", PortInvalid_r, PortInvalid_w}, /* Not used. */
2021};
2022
2023#ifdef IN_RING3
2024/**
2025 * Reset initiated by system software for one port.
2026 *
2027 * @param pAhciPort The port to reset.
2028 */
2029static void ahciPortSwReset(PAHCIPort pAhciPort)
2030{
2031 bool fAllTasksCanceled;
2032
2033 /* Cancel all tasks first. */
2034 fAllTasksCanceled = ahciCancelActiveTasks(pAhciPort, NULL);
2035 Assert(fAllTasksCanceled);
2036
2037 Assert(pAhciPort->cTasksActive == 0);
2038
2039 pAhciPort->regIS = 0;
2040 pAhciPort->regIE = 0;
2041 pAhciPort->regCMD = AHCI_PORT_CMD_CPD | /* Cold presence detection */
2042 AHCI_PORT_CMD_SUD | /* Device has spun up. */
2043 AHCI_PORT_CMD_POD; /* Port is powered on. */
2044
2045 /* Hotplugging supported?. */
2046 if (pAhciPort->fHotpluggable)
2047 pAhciPort->regCMD |= AHCI_PORT_CMD_HPCP;
2048
2049 pAhciPort->regTFD = (1 << 8) | ATA_STAT_SEEK | ATA_STAT_WRERR;
2050 pAhciPort->regSIG = ~0;
2051 pAhciPort->regSSTS = 0;
2052 pAhciPort->regSCTL = 0;
2053 pAhciPort->regSERR = 0;
2054 pAhciPort->regSACT = 0;
2055 pAhciPort->regCI = 0;
2056
2057 pAhciPort->fResetDevice = false;
2058 pAhciPort->fPoweredOn = true;
2059 pAhciPort->fSpunUp = true;
2060 pAhciPort->cMultSectors = ATA_MAX_MULT_SECTORS;
2061 pAhciPort->uATATransferMode = ATA_MODE_UDMA | 6;
2062
2063 pAhciPort->u32TasksNew = 0;
2064 pAhciPort->u32TasksRedo = 0;
2065 pAhciPort->u32TasksFinished = 0;
2066 pAhciPort->u32QueuedTasksFinished = 0;
2067 pAhciPort->u32CurrentCommandSlot = 0;
2068
2069 ASMAtomicWriteU32(&pAhciPort->MediaEventStatus, ATA_EVENT_STATUS_UNCHANGED);
2070 ASMAtomicWriteU32(&pAhciPort->MediaTrackType, ATA_MEDIA_TYPE_UNKNOWN);
2071
2072 if (pAhciPort->pDrvBase)
2073 {
2074 pAhciPort->regCMD |= AHCI_PORT_CMD_CPS; /* Indicate that there is a device on that port */
2075
2076 if (pAhciPort->fPoweredOn)
2077 {
2078 /*
2079 * Set states in the Port Signature and SStatus registers.
2080 */
2081 if (pAhciPort->fATAPI)
2082 pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
2083 else
2084 pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
2085 pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
2086 (0x02 << 4) | /* Generation 2 (3.0GBps) speed. */
2087 (0x03 << 0); /* Device detected and communication established. */
2088 }
2089 }
2090}
2091
2092/**
2093 * Hardware reset used for machine power on and reset.
2094 *
2095 * @param pAhciport The port to reset.
2096 */
2097static void ahciPortHwReset(PAHCIPort pAhciPort)
2098{
2099 /* Reset the address registers. */
2100 pAhciPort->regCLB = 0;
2101 pAhciPort->regCLBU = 0;
2102 pAhciPort->regFB = 0;
2103 pAhciPort->regFBU = 0;
2104
2105 /* Reset calculated addresses. */
2106 pAhciPort->GCPhysAddrClb = 0;
2107 pAhciPort->GCPhysAddrFb = 0;
2108}
2109
2110/**
2111 * Create implemented ports bitmap.
2112 *
2113 * @returns 32bit bitmask with a bit set for every implemented port.
2114 * @param cPorts Number of ports.
2115 */
2116static uint32_t ahciGetPortsImplemented(unsigned cPorts)
2117{
2118 uint32_t uPortsImplemented = 0;
2119
2120 for (unsigned i = 0; i < cPorts; i++)
2121 uPortsImplemented |= (1 << i);
2122
2123 return uPortsImplemented;
2124}
2125
2126/**
2127 * Reset the entire HBA.
2128 *
2129 * @param pThis The HBA state.
2130 */
2131static void ahciHBAReset(PAHCI pThis)
2132{
2133 unsigned i;
2134 int rc = VINF_SUCCESS;
2135
2136 LogRel(("AHCI#%u: Reset the HBA\n", pThis->CTX_SUFF(pDevIns)->iInstance));
2137
2138 /* Stop the CCC timer. */
2139 if (pThis->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN)
2140 {
2141 rc = TMTimerStop(pThis->CTX_SUFF(pHbaCccTimer));
2142 if (RT_FAILURE(rc))
2143 AssertMsgFailed(("%s: Failed to stop timer!\n", __FUNCTION__));
2144 }
2145
2146 /* Reset every port */
2147 for (i = 0; i < pThis->cPortsImpl; i++)
2148 {
2149 PAHCIPort pAhciPort = &pThis->ahciPort[i];
2150
2151 pAhciPort->iLUN = i;
2152 ahciPortSwReset(pAhciPort);
2153 }
2154
2155 /* Init Global registers */
2156 pThis->regHbaCap = AHCI_HBA_CAP_ISS_SHIFT(AHCI_HBA_CAP_ISS_GEN2) |
2157 AHCI_HBA_CAP_S64A | /* 64bit addressing supported */
2158 AHCI_HBA_CAP_SAM | /* AHCI mode only */
2159 AHCI_HBA_CAP_SNCQ | /* Support native command queuing */
2160 AHCI_HBA_CAP_SSS | /* Staggered spin up */
2161 AHCI_HBA_CAP_CCCS | /* Support command completion coalescing */
2162 AHCI_HBA_CAP_NCS_SET(pThis->cCmdSlotsAvail) | /* Number of command slots we support */
2163 AHCI_HBA_CAP_NP_SET(pThis->cPortsImpl); /* Number of supported ports */
2164 pThis->regHbaCtrl = AHCI_HBA_CTRL_AE;
2165 pThis->regHbaPi = ahciGetPortsImplemented(pThis->cPortsImpl);
2166 pThis->regHbaVs = AHCI_HBA_VS_MJR | AHCI_HBA_VS_MNR;
2167 pThis->regHbaCccCtl = 0;
2168 pThis->regHbaCccPorts = 0;
2169 pThis->uCccTimeout = 0;
2170 pThis->uCccPortNr = 0;
2171 pThis->uCccNr = 0;
2172
2173 /* Clear pending interrupts. */
2174 pThis->regHbaIs = 0;
2175 pThis->u32PortsInterrupted = 0;
2176 ahciHbaClearInterrupt(pThis);
2177
2178 pThis->f64BitAddr = false;
2179 pThis->u32PortsInterrupted = 0;
2180 pThis->f8ByteMMIO4BytesWrittenSuccessfully = false;
2181 /* Clear the HBA Reset bit */
2182 pThis->regHbaCtrl &= ~AHCI_HBA_CTRL_HR;
2183}
2184#endif
2185
2186/**
2187 * Reads from a AHCI controller register.
2188 *
2189 * @returns VBox status code.
2190 *
2191 * @param pAhci The AHCI instance.
2192 * @param uReg The register to write.
2193 * @param pv Where to store the result.
2194 * @param cb Number of bytes read.
2195 */
2196static int ahciRegisterRead(PAHCI pAhci, uint32_t uReg, void *pv, unsigned cb)
2197{
2198 int rc = VINF_SUCCESS;
2199 uint32_t iReg;
2200
2201 /*
2202 * If the access offset is smaller than AHCI_HBA_GLOBAL_SIZE the guest accesses the global registers.
2203 * Otherwise it accesses the registers of a port.
2204 */
2205 if (uReg < AHCI_HBA_GLOBAL_SIZE)
2206 {
2207 iReg = uReg >> 2;
2208 Log3(("%s: Trying to read from global register %u\n", __FUNCTION__, iReg));
2209 if (iReg < RT_ELEMENTS(g_aOpRegs))
2210 {
2211 const AHCIOPREG *pReg = &g_aOpRegs[iReg];
2212 rc = pReg->pfnRead(pAhci, iReg, (uint32_t *)pv);
2213 }
2214 else
2215 {
2216 Log3(("%s: Trying to read global register %u/%u!!!\n", __FUNCTION__, iReg, RT_ELEMENTS(g_aOpRegs)));
2217 *(uint32_t *)pv = 0;
2218 }
2219 }
2220 else
2221 {
2222 uint32_t iRegOffset;
2223 uint32_t iPort;
2224
2225 /* Calculate accessed port. */
2226 uReg -= AHCI_HBA_GLOBAL_SIZE;
2227 iPort = uReg / AHCI_PORT_REGISTER_SIZE;
2228 iRegOffset = (uReg % AHCI_PORT_REGISTER_SIZE);
2229 iReg = iRegOffset >> 2;
2230
2231 Log3(("%s: Trying to read from port %u and register %u\n", __FUNCTION__, iPort, iReg));
2232
2233 if (RT_LIKELY( iPort < pAhci->cPortsImpl
2234 && iReg < RT_ELEMENTS(g_aPortOpRegs)))
2235 {
2236 const AHCIPORTOPREG *pPortReg = &g_aPortOpRegs[iReg];
2237 rc = pPortReg->pfnRead(pAhci, &pAhci->ahciPort[iPort], iReg, (uint32_t *)pv);
2238 }
2239 else
2240 {
2241 Log3(("%s: Trying to read port %u register %u/%u!!!\n", __FUNCTION__, iPort, iReg, RT_ELEMENTS(g_aPortOpRegs)));
2242 rc = VINF_IOM_MMIO_UNUSED_00;
2243 }
2244
2245 /*
2246 * Windows Vista tries to read one byte from some registers instead of four.
2247 * Correct the value according to the read size.
2248 */
2249 if (RT_SUCCESS(rc) && cb != sizeof(uint32_t))
2250 {
2251 switch (cb)
2252 {
2253 case 1:
2254 {
2255 uint8_t uNewValue;
2256 uint8_t *p = (uint8_t *)pv;
2257
2258 iRegOffset &= 3;
2259 Log3(("%s: iRegOffset=%u\n", __FUNCTION__, iRegOffset));
2260 uNewValue = p[iRegOffset];
2261 /* Clear old value */
2262 *(uint32_t *)pv = 0;
2263 *(uint8_t *)pv = uNewValue;
2264 break;
2265 }
2266 default:
2267 AssertMsgFailed(("%s: unsupported access width cb=%d iPort=%x iRegOffset=%x iReg=%x!!!\n",
2268 __FUNCTION__, cb, iPort, iRegOffset, iReg));
2269 }
2270 }
2271 }
2272
2273 return rc;
2274}
2275
2276/**
2277 * Writes a value to one of the AHCI controller registers.
2278 *
2279 * @returns VBox status code.
2280 *
2281 * @param pAhci The AHCI instance.
2282 * @param offReg The offset of the register to write to.
2283 * @param u32Value The value to write.
2284 */
2285static int ahciRegisterWrite(PAHCI pAhci, uint32_t offReg, uint32_t u32Value)
2286{
2287 int rc;
2288 uint32_t iReg;
2289
2290 /*
2291 * If the access offset is smaller than 100h the guest accesses the global registers.
2292 * Otherwise it accesses the registers of a port.
2293 */
2294 if (offReg < AHCI_HBA_GLOBAL_SIZE)
2295 {
2296 Log3(("Write global HBA register\n"));
2297 iReg = offReg >> 2;
2298 if (iReg < RT_ELEMENTS(g_aOpRegs))
2299 {
2300 const AHCIOPREG *pReg = &g_aOpRegs[iReg];
2301 rc = pReg->pfnWrite(pAhci, iReg, u32Value);
2302 }
2303 else
2304 {
2305 Log3(("%s: Trying to write global register %u/%u!!!\n", __FUNCTION__, iReg, RT_ELEMENTS(g_aOpRegs)));
2306 rc = VINF_SUCCESS;
2307 }
2308 }
2309 else
2310 {
2311 uint32_t iPort;
2312 Log3(("Write Port register\n"));
2313 /* Calculate accessed port. */
2314 offReg -= AHCI_HBA_GLOBAL_SIZE;
2315 iPort = offReg / AHCI_PORT_REGISTER_SIZE;
2316 iReg = (offReg % AHCI_PORT_REGISTER_SIZE) >> 2;
2317 Log3(("%s: Trying to write to port %u and register %u\n", __FUNCTION__, iPort, iReg));
2318 if (RT_LIKELY( iPort < pAhci->cPortsImpl
2319 && iReg < RT_ELEMENTS(g_aPortOpRegs)))
2320 {
2321 const AHCIPORTOPREG *pPortReg = &g_aPortOpRegs[iReg];
2322 rc = pPortReg->pfnWrite(pAhci, &pAhci->ahciPort[iPort], iReg, u32Value);
2323 }
2324 else
2325 {
2326 Log3(("%s: Trying to write port %u register %u/%u!!!\n", __FUNCTION__, iPort, iReg, RT_ELEMENTS(g_aPortOpRegs)));
2327 rc = VINF_SUCCESS;
2328 }
2329 }
2330
2331 return rc;
2332}
2333
2334/**
2335 * Memory mapped I/O Handler for read operations.
2336 *
2337 * @returns VBox status code.
2338 *
2339 * @param pDevIns The device instance.
2340 * @param pvUser User argument.
2341 * @param GCPhysAddr Physical address (in GC) where the read starts.
2342 * @param pv Where to store the result.
2343 * @param cb Number of bytes read.
2344 */
2345PDMBOTHCBDECL(int) ahciMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2346{
2347 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2348 Log2(("#%d ahciMMIORead: pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp\n",
2349 pDevIns->iInstance, pv, cb, pv, cb, GCPhysAddr));
2350
2351 int rc = ahciRegisterRead(pAhci, GCPhysAddr - pAhci->MMIOBase, pv, cb);
2352
2353 Log2(("#%d ahciMMIORead: return pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp rc=%Rrc\n",
2354 pDevIns->iInstance, pv, cb, pv, cb, GCPhysAddr, rc));
2355 return rc;
2356}
2357
2358
2359/**
2360 * Memory mapped I/O Handler for write operations.
2361 *
2362 * @returns VBox status code.
2363 *
2364 * @param pDevIns The device instance.
2365 * @param pvUser User argument.
2366 * @param GCPhysAddr Physical address (in GC) where the read starts.
2367 * @param pv Where to fetch the result.
2368 * @param cb Number of bytes to write.
2369 */
2370PDMBOTHCBDECL(int) ahciMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
2371{
2372 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2373 Assert(cb == 4 || cb == 8);
2374 Assert(!(GCPhysAddr & (cb - 1)));
2375
2376 /* Break up 64 bits writes into two dword writes. */
2377 /** @todo Eliminate this code once the IOM/EM starts taking care of these
2378 * situations. */
2379 if (cb == 8)
2380 {
2381 /*
2382 * Only write the first 4 bytes if they weren't already.
2383 * It is possible that the last write to the register caused a world
2384 * switch and we entered this function again.
2385 * Writing the first 4 bytes again could cause indeterminate behavior
2386 * which can cause errors in the guest.
2387 */
2388 int rc = VINF_SUCCESS;
2389 if (!pAhci->f8ByteMMIO4BytesWrittenSuccessfully)
2390 {
2391 rc = ahciMMIOWrite(pDevIns, pvUser, GCPhysAddr, pv, 4);
2392 if (rc != VINF_SUCCESS)
2393 return rc;
2394
2395 pAhci->f8ByteMMIO4BytesWrittenSuccessfully = true;
2396 }
2397
2398 rc = ahciMMIOWrite(pDevIns, pvUser, GCPhysAddr + 4, (uint8_t *)pv + 4, 4);
2399 /*
2400 * Reset flag again so that the first 4 bytes are written again on the next
2401 * 8byte MMIO access.
2402 */
2403 if (rc == VINF_SUCCESS)
2404 pAhci->f8ByteMMIO4BytesWrittenSuccessfully = false;
2405
2406 return rc;
2407 }
2408
2409 /* Do the access. */
2410 Log2(("#%d ahciMMIOWrite: pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp\n", pDevIns->iInstance, pv, cb, pv, cb, GCPhysAddr));
2411 return ahciRegisterWrite(pAhci, GCPhysAddr - pAhci->MMIOBase, *(uint32_t const *)pv);
2412}
2413
2414PDMBOTHCBDECL(int) ahciLegacyFakeWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2415{
2416 AssertMsgFailed(("Should not happen\n"));
2417 return VINF_SUCCESS;
2418}
2419
2420PDMBOTHCBDECL(int) ahciLegacyFakeRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
2421{
2422 AssertMsgFailed(("Should not happen\n"));
2423 return VINF_SUCCESS;
2424}
2425
2426/**
2427 * I/O port handler for writes to the index/data register pair.
2428 *
2429 * @returns VBox status code.
2430 *
2431 * @param pDevIns The device instance.
2432 * @param pvUser User argument.
2433 * @param Port Port address where the write starts.
2434 * @param pv Where to fetch the result.
2435 * @param cb Number of bytes to write.
2436 */
2437PDMBOTHCBDECL(int) ahciIdxDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2438{
2439 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2440 int rc = VINF_SUCCESS;
2441
2442 if (Port - pAhci->IOPortBase >= 8)
2443 {
2444 unsigned iReg = (Port - pAhci->IOPortBase - 8) / 4;
2445
2446 Assert(cb == 4);
2447
2448 if (iReg == 0)
2449 {
2450 /* Write the index register. */
2451 pAhci->regIdx = u32;
2452 }
2453 else
2454 {
2455 /** @todo range check? */
2456 Assert(iReg == 1);
2457 rc = ahciRegisterWrite(pAhci, pAhci->regIdx, u32);
2458 if (rc == VINF_IOM_R3_MMIO_WRITE)
2459 rc = VINF_IOM_R3_IOPORT_WRITE;
2460 }
2461 }
2462 /* else: ignore */
2463
2464 Log2(("#%d ahciIdxDataWrite: pu32=%p:{%.*Rhxs} cb=%d Port=%#x rc=%Rrc\n",
2465 pDevIns->iInstance, &u32, cb, &u32, cb, Port, rc));
2466 return rc;
2467}
2468
2469/**
2470 * I/O port handler for reads from the index/data register pair.
2471 *
2472 * @returns VBox status code.
2473 *
2474 * @param pDevIns The device instance.
2475 * @param pvUser User argument.
2476 * @param Port Port address where the read starts.
2477 * @param pv Where to fetch the result.
2478 * @param cb Number of bytes to write.
2479 */
2480PDMBOTHCBDECL(int) ahciIdxDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
2481{
2482 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
2483 int rc = VINF_SUCCESS;
2484
2485 if (Port - pAhci->IOPortBase >= 8)
2486 {
2487 unsigned iReg = (Port - pAhci->IOPortBase - 8) / 4;
2488
2489 Assert(cb == 4);
2490
2491 if (iReg == 0)
2492 {
2493 /* Read the index register. */
2494 *pu32 = pAhci->regIdx;
2495 }
2496 else
2497 {
2498 Assert(iReg == 1);
2499 /** @todo range check? */
2500 rc = ahciRegisterRead(pAhci, pAhci->regIdx, pu32, cb);
2501 if (rc == VINF_IOM_R3_MMIO_READ)
2502 rc = VINF_IOM_R3_IOPORT_READ;
2503 else if (rc == VINF_IOM_MMIO_UNUSED_00)
2504 rc = VERR_IOM_IOPORT_UNUSED;
2505 }
2506 }
2507 else
2508 *pu32 = UINT32_C(0xffffffff);
2509
2510 Log2(("#%d ahciIdxDataRead: pu32=%p:{%.*Rhxs} cb=%d Port=%#x rc=%Rrc\n",
2511 pDevIns->iInstance, pu32, cb, pu32, cb, Port, rc));
2512 return rc;
2513}
2514
2515#ifdef IN_RING3
2516
2517static DECLCALLBACK(int) ahciR3MMIOMap(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
2518{
2519 PAHCI pThis = PCIDEV_2_PAHCI(pPciDev);
2520 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2521 int rc = VINF_SUCCESS;
2522
2523 Log2(("%s: registering MMIO area at GCPhysAddr=%RGp cb=%u\n", __FUNCTION__, GCPhysAddress, cb));
2524
2525 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
2526 Assert(cb >= 4352);
2527
2528 /* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
2529 /** @todo change this to IOMMMIO_FLAGS_WRITE_ONLY_DWORD once EM/IOM starts
2530 * handling 2nd DWORD failures on split accesses correctly. */
2531 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
2532 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD_QWORD,
2533 ahciMMIOWrite, ahciMMIORead, "AHCI");
2534 if (RT_FAILURE(rc))
2535 return rc;
2536
2537 if (pThis->fR0Enabled)
2538 {
2539 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/, "ahciMMIOWrite", "ahciMMIORead");
2540 if (RT_FAILURE(rc))
2541 return rc;
2542 }
2543
2544 if (pThis->fGCEnabled)
2545 {
2546 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/, "ahciMMIOWrite", "ahciMMIORead");
2547 if (RT_FAILURE(rc))
2548 return rc;
2549 }
2550
2551 pThis->MMIOBase = GCPhysAddress;
2552 return rc;
2553}
2554
2555/**
2556 * Map the legacy I/O port ranges to make Solaris work with the controller.
2557 */
2558static DECLCALLBACK(int) ahciR3LegacyFakeIORangeMap(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
2559{
2560 PAHCI pThis = PCIDEV_2_PAHCI(pPciDev);
2561 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2562 int rc = VINF_SUCCESS;
2563
2564 Log2(("%s: registering fake I/O area at GCPhysAddr=%RGp cb=%u\n", __FUNCTION__, GCPhysAddress, cb));
2565
2566 Assert(enmType == PCI_ADDRESS_SPACE_IO);
2567
2568 /* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
2569 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, NULL,
2570 ahciLegacyFakeWrite, ahciLegacyFakeRead, NULL, NULL, "AHCI Fake");
2571 if (RT_FAILURE(rc))
2572 return rc;
2573
2574 if (pThis->fR0Enabled)
2575 {
2576 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
2577 "ahciLegacyFakeWrite", "ahciLegacyFakeRead", NULL, NULL, "AHCI Fake");
2578 if (RT_FAILURE(rc))
2579 return rc;
2580 }
2581
2582 if (pThis->fGCEnabled)
2583 {
2584 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
2585 "ahciLegacyFakeWrite", "ahciLegacyFakeRead", NULL, NULL, "AHCI Fake");
2586 if (RT_FAILURE(rc))
2587 return rc;
2588 }
2589
2590 return rc;
2591}
2592
2593/**
2594 * Map the BMDMA I/O port range (used for the Index/Data pair register access)
2595 */
2596static DECLCALLBACK(int) ahciR3IdxDataIORangeMap(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
2597{
2598 PAHCI pThis = PCIDEV_2_PAHCI(pPciDev);
2599 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2600 int rc = VINF_SUCCESS;
2601
2602 Log2(("%s: registering fake I/O area at GCPhysAddr=%RGp cb=%u\n", __FUNCTION__, GCPhysAddress, cb));
2603
2604 Assert(enmType == PCI_ADDRESS_SPACE_IO);
2605
2606 /* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
2607 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, NULL,
2608 ahciIdxDataWrite, ahciIdxDataRead, NULL, NULL, "AHCI IDX/DATA");
2609 if (RT_FAILURE(rc))
2610 return rc;
2611
2612 if (pThis->fR0Enabled)
2613 {
2614 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
2615 "ahciIdxDataWrite", "ahciIdxDataRead", NULL, NULL, "AHCI IDX/DATA");
2616 if (RT_FAILURE(rc))
2617 return rc;
2618 }
2619
2620 if (pThis->fGCEnabled)
2621 {
2622 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
2623 "ahciIdxDataWrite", "ahciIdxDataRead", NULL, NULL, "AHCI IDX/DATA");
2624 if (RT_FAILURE(rc))
2625 return rc;
2626 }
2627
2628 pThis->IOPortBase = (RTIOPORT)GCPhysAddress;
2629 return rc;
2630}
2631
2632/* -=-=-=-=-=- PAHCI::ILeds -=-=-=-=-=- */
2633
2634/**
2635 * Gets the pointer to the status LED of a unit.
2636 *
2637 * @returns VBox status code.
2638 * @param pInterface Pointer to the interface structure containing the called function pointer.
2639 * @param iLUN The unit which status LED we desire.
2640 * @param ppLed Where to store the LED pointer.
2641 */
2642static DECLCALLBACK(int) ahciR3Status_QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
2643{
2644 PAHCI pAhci = PDMILEDPORTS_2_PAHCI(pInterface);
2645 if (iLUN < AHCI_MAX_NR_PORTS_IMPL)
2646 {
2647 *ppLed = &pAhci->ahciPort[iLUN].Led;
2648 Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
2649 return VINF_SUCCESS;
2650 }
2651 return VERR_PDM_LUN_NOT_FOUND;
2652}
2653
2654/**
2655 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2656 */
2657static DECLCALLBACK(void *) ahciR3Status_QueryInterface(PPDMIBASE pInterface, const char *pszIID)
2658{
2659 PAHCI pThis = PDMIBASE_2_PAHCI(pInterface);
2660 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
2661 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
2662 return NULL;
2663}
2664
2665/**
2666 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2667 */
2668static DECLCALLBACK(void *) ahciR3PortQueryInterface(PPDMIBASE pInterface, const char *pszIID)
2669{
2670 PAHCIPort pAhciPort = PDMIBASE_2_PAHCIPORT(pInterface);
2671 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pAhciPort->IBase);
2672 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBLOCKPORT, &pAhciPort->IPort);
2673 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBLOCKASYNCPORT, &pAhciPort->IPortAsync);
2674 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMOUNTNOTIFY, &pAhciPort->IMountNotify);
2675 return NULL;
2676}
2677
2678/**
2679 * @interface_method_impl{PDMIBLOCKPORT,pfnQueryDeviceLocation}
2680 */
2681static DECLCALLBACK(int) ahciR3PortQueryDeviceLocation(PPDMIBLOCKPORT pInterface, const char **ppcszController,
2682 uint32_t *piInstance, uint32_t *piLUN)
2683{
2684 PAHCIPort pAhciPort = PDMIBLOCKPORT_2_PAHCIPORT(pInterface);
2685 PPDMDEVINS pDevIns = pAhciPort->CTX_SUFF(pDevIns);
2686
2687 AssertPtrReturn(ppcszController, VERR_INVALID_POINTER);
2688 AssertPtrReturn(piInstance, VERR_INVALID_POINTER);
2689 AssertPtrReturn(piLUN, VERR_INVALID_POINTER);
2690
2691 *ppcszController = pDevIns->pReg->szName;
2692 *piInstance = pDevIns->iInstance;
2693 *piLUN = pAhciPort->iLUN;
2694
2695 return VINF_SUCCESS;
2696}
2697
2698#ifdef LOG_ENABLED
2699
2700/**
2701 * Dump info about the FIS
2702 *
2703 * @returns nothing
2704 * @param pAhciPort The port the command FIS was read from.
2705 * @param cmdFis The FIS to print info from.
2706 */
2707static void ahciDumpFisInfo(PAHCIPort pAhciPort, uint8_t *cmdFis)
2708{
2709 ahciLog(("%s: *** Begin FIS info dump. ***\n", __FUNCTION__));
2710 /* Print FIS type. */
2711 switch (cmdFis[AHCI_CMDFIS_TYPE])
2712 {
2713 case AHCI_CMDFIS_TYPE_H2D:
2714 {
2715 ahciLog(("%s: Command Fis type: H2D\n", __FUNCTION__));
2716 ahciLog(("%s: Command Fis size: %d bytes\n", __FUNCTION__, AHCI_CMDFIS_TYPE_H2D_SIZE));
2717 if (cmdFis[AHCI_CMDFIS_BITS] & AHCI_CMDFIS_C)
2718 ahciLog(("%s: Command register update\n", __FUNCTION__));
2719 else
2720 ahciLog(("%s: Control register update\n", __FUNCTION__));
2721 ahciLog(("%s: CMD=%#04x \"%s\"\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CMD], ATACmdText(cmdFis[AHCI_CMDFIS_CMD])));
2722 ahciLog(("%s: FEAT=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_FET]));
2723 ahciLog(("%s: SECTN=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTN]));
2724 ahciLog(("%s: CYLL=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLL]));
2725 ahciLog(("%s: CYLH=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLH]));
2726 ahciLog(("%s: HEAD=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_HEAD]));
2727
2728 ahciLog(("%s: SECTNEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTNEXP]));
2729 ahciLog(("%s: CYLLEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLLEXP]));
2730 ahciLog(("%s: CYLHEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLHEXP]));
2731 ahciLog(("%s: FETEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_FETEXP]));
2732
2733 ahciLog(("%s: SECTC=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTC]));
2734 ahciLog(("%s: SECTCEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTCEXP]));
2735 ahciLog(("%s: CTL=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CTL]));
2736 if (cmdFis[AHCI_CMDFIS_CTL] & AHCI_CMDFIS_CTL_SRST)
2737 ahciLog(("%s: Reset bit is set\n", __FUNCTION__));
2738 break;
2739 }
2740 case AHCI_CMDFIS_TYPE_D2H:
2741 {
2742 ahciLog(("%s: Command Fis type D2H\n", __FUNCTION__));
2743 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_D2H_SIZE));
2744 break;
2745 }
2746 case AHCI_CMDFIS_TYPE_SETDEVBITS:
2747 {
2748 ahciLog(("%s: Command Fis type Set Device Bits\n", __FUNCTION__));
2749 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_SETDEVBITS_SIZE));
2750 break;
2751 }
2752 case AHCI_CMDFIS_TYPE_DMAACTD2H:
2753 {
2754 ahciLog(("%s: Command Fis type DMA Activate H2D\n", __FUNCTION__));
2755 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_DMAACTD2H_SIZE));
2756 break;
2757 }
2758 case AHCI_CMDFIS_TYPE_DMASETUP:
2759 {
2760 ahciLog(("%s: Command Fis type DMA Setup\n", __FUNCTION__));
2761 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_DMASETUP_SIZE));
2762 break;
2763 }
2764 case AHCI_CMDFIS_TYPE_PIOSETUP:
2765 {
2766 ahciLog(("%s: Command Fis type PIO Setup\n", __FUNCTION__));
2767 ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_PIOSETUP_SIZE));
2768 break;
2769 }
2770 case AHCI_CMDFIS_TYPE_DATA:
2771 {
2772 ahciLog(("%s: Command Fis type Data\n", __FUNCTION__));
2773 break;
2774 }
2775 default:
2776 ahciLog(("%s: ERROR Unknown command FIS type\n", __FUNCTION__));
2777 break;
2778 }
2779 ahciLog(("%s: *** End FIS info dump. ***\n", __FUNCTION__));
2780}
2781
2782/**
2783 * Dump info about the command header
2784 *
2785 * @returns nothing
2786 * @param pAhciPort Pointer to the port the command header was read from.
2787 * @param pCmdHdr The command header to print info from.
2788 */
2789static void ahciDumpCmdHdrInfo(PAHCIPort pAhciPort, CmdHdr *pCmdHdr)
2790{
2791 ahciLog(("%s: *** Begin command header info dump. ***\n", __FUNCTION__));
2792 ahciLog(("%s: Number of Scatter/Gatther List entries: %u\n", __FUNCTION__, AHCI_CMDHDR_PRDTL_ENTRIES(pCmdHdr->u32DescInf)));
2793 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_C)
2794 ahciLog(("%s: Clear busy upon R_OK\n", __FUNCTION__));
2795 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_B)
2796 ahciLog(("%s: BIST Fis\n", __FUNCTION__));
2797 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_R)
2798 ahciLog(("%s: Device Reset Fis\n", __FUNCTION__));
2799 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_P)
2800 ahciLog(("%s: Command prefetchable\n", __FUNCTION__));
2801 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_W)
2802 ahciLog(("%s: Device write\n", __FUNCTION__));
2803 else
2804 ahciLog(("%s: Device read\n", __FUNCTION__));
2805 if (pCmdHdr->u32DescInf & AHCI_CMDHDR_A)
2806 ahciLog(("%s: ATAPI command\n", __FUNCTION__));
2807 else
2808 ahciLog(("%s: ATA command\n", __FUNCTION__));
2809
2810 ahciLog(("%s: Command FIS length %u DW\n", __FUNCTION__, (pCmdHdr->u32DescInf & AHCI_CMDHDR_CFL_MASK)));
2811 ahciLog(("%s: *** End command header info dump. ***\n", __FUNCTION__));
2812}
2813
2814#endif /* LOG_ENABLED */
2815
2816/**
2817 * Post the first D2H FIS from the device into guest memory.
2818 *
2819 * @returns nothing
2820 * @param pAhciPort Pointer to the port which "receives" the FIS.
2821 */
2822static void ahciPostFirstD2HFisIntoMemory(PAHCIPort pAhciPort)
2823{
2824 uint8_t d2hFis[AHCI_CMDFIS_TYPE_D2H_SIZE];
2825
2826 pAhciPort->fFirstD2HFisSend = true;
2827
2828 ahciLog(("%s: Sending First D2H FIS from FIFO\n", __FUNCTION__));
2829 memset(&d2hFis[0], 0, sizeof(d2hFis));
2830 d2hFis[AHCI_CMDFIS_TYPE] = AHCI_CMDFIS_TYPE_D2H;
2831 d2hFis[AHCI_CMDFIS_ERR] = 0x01;
2832
2833 d2hFis[AHCI_CMDFIS_STS] = 0x00;
2834
2835 /* Set the signature based on the device type. */
2836 if (pAhciPort->fATAPI)
2837 {
2838 d2hFis[AHCI_CMDFIS_CYLL] = 0x14;
2839 d2hFis[AHCI_CMDFIS_CYLH] = 0xeb;
2840 }
2841 else
2842 {
2843 d2hFis[AHCI_CMDFIS_CYLL] = 0x00;
2844 d2hFis[AHCI_CMDFIS_CYLH] = 0x00;
2845 }
2846
2847 d2hFis[AHCI_CMDFIS_HEAD] = 0x00;
2848 d2hFis[AHCI_CMDFIS_SECTN] = 0x01;
2849 d2hFis[AHCI_CMDFIS_SECTC] = 0x01;
2850
2851 pAhciPort->regTFD = (1 << 8) | ATA_STAT_SEEK | ATA_STAT_WRERR;
2852 if (!pAhciPort->fATAPI)
2853 pAhciPort->regTFD |= ATA_STAT_READY;
2854
2855 ahciPostFisIntoMemory(pAhciPort, AHCI_CMDFIS_TYPE_D2H, d2hFis);
2856}
2857
2858/**
2859 * Post the FIS in the memory area allocated by the guest and set interrupt if necessary.
2860 *
2861 * @returns VBox status code
2862 * @param pAhciPort The port which "receives" the FIS.
2863 * @param uFisType The type of the FIS.
2864 * @param pCmdFis Pointer to the FIS which is to be posted into memory.
2865 */
2866static int ahciPostFisIntoMemory(PAHCIPort pAhciPort, unsigned uFisType, uint8_t *pCmdFis)
2867{
2868 int rc = VINF_SUCCESS;
2869 RTGCPHYS GCPhysAddrRecFis = pAhciPort->GCPhysAddrFb;
2870 unsigned cbFis = 0;
2871
2872 ahciLog(("%s: pAhciPort=%p uFisType=%u pCmdFis=%p\n", __FUNCTION__, pAhciPort, uFisType, pCmdFis));
2873
2874 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
2875 {
2876 AssertMsg(GCPhysAddrRecFis, ("%s: GCPhysAddrRecFis is 0\n", __FUNCTION__));
2877
2878 /* Determine the offset and size of the FIS based on uFisType. */
2879 switch (uFisType)
2880 {
2881 case AHCI_CMDFIS_TYPE_D2H:
2882 {
2883 GCPhysAddrRecFis += AHCI_RECFIS_RFIS_OFFSET;
2884 cbFis = AHCI_CMDFIS_TYPE_D2H_SIZE;
2885 break;
2886 }
2887 case AHCI_CMDFIS_TYPE_SETDEVBITS:
2888 {
2889 GCPhysAddrRecFis += AHCI_RECFIS_SDBFIS_OFFSET;
2890 cbFis = AHCI_CMDFIS_TYPE_SETDEVBITS_SIZE;
2891 break;
2892 }
2893 case AHCI_CMDFIS_TYPE_DMASETUP:
2894 {
2895 GCPhysAddrRecFis += AHCI_RECFIS_DSFIS_OFFSET;
2896 cbFis = AHCI_CMDFIS_TYPE_DMASETUP_SIZE;
2897 break;
2898 }
2899 case AHCI_CMDFIS_TYPE_PIOSETUP:
2900 {
2901 GCPhysAddrRecFis += AHCI_RECFIS_PSFIS_OFFSET;
2902 cbFis = AHCI_CMDFIS_TYPE_PIOSETUP_SIZE;
2903 break;
2904 }
2905 default:
2906 /*
2907 * We should post the unknown FIS into memory too but this never happens because
2908 * we know which FIS types we generate. ;)
2909 */
2910 AssertMsgFailed(("%s: Unknown FIS type!\n", __FUNCTION__));
2911 }
2912
2913 /* Post the FIS into memory. */
2914 ahciLog(("%s: PDMDevHlpPCIPhysWrite GCPhysAddrRecFis=%RGp cbFis=%u\n", __FUNCTION__, GCPhysAddrRecFis, cbFis));
2915 PDMDevHlpPCIPhysWrite(pAhciPort->CTX_SUFF(pDevIns), GCPhysAddrRecFis, pCmdFis, cbFis);
2916 }
2917
2918 return rc;
2919}
2920
2921DECLINLINE(void) ataH2BE_U16(uint8_t *pbBuf, uint16_t val)
2922{
2923 pbBuf[0] = val >> 8;
2924 pbBuf[1] = val;
2925}
2926
2927
2928DECLINLINE(void) ataH2BE_U24(uint8_t *pbBuf, uint32_t val)
2929{
2930 pbBuf[0] = val >> 16;
2931 pbBuf[1] = val >> 8;
2932 pbBuf[2] = val;
2933}
2934
2935
2936DECLINLINE(void) ataH2BE_U32(uint8_t *pbBuf, uint32_t val)
2937{
2938 pbBuf[0] = val >> 24;
2939 pbBuf[1] = val >> 16;
2940 pbBuf[2] = val >> 8;
2941 pbBuf[3] = val;
2942}
2943
2944
2945DECLINLINE(uint16_t) ataBE2H_U16(const uint8_t *pbBuf)
2946{
2947 return (pbBuf[0] << 8) | pbBuf[1];
2948}
2949
2950
2951DECLINLINE(uint32_t) ataBE2H_U24(const uint8_t *pbBuf)
2952{
2953 return (pbBuf[0] << 16) | (pbBuf[1] << 8) | pbBuf[2];
2954}
2955
2956
2957DECLINLINE(uint32_t) ataBE2H_U32(const uint8_t *pbBuf)
2958{
2959 return (pbBuf[0] << 24) | (pbBuf[1] << 16) | (pbBuf[2] << 8) | pbBuf[3];
2960}
2961
2962
2963DECLINLINE(void) ataLBA2MSF(uint8_t *pbBuf, uint32_t iATAPILBA)
2964{
2965 iATAPILBA += 150;
2966 pbBuf[0] = (iATAPILBA / 75) / 60;
2967 pbBuf[1] = (iATAPILBA / 75) % 60;
2968 pbBuf[2] = iATAPILBA % 75;
2969}
2970
2971
2972DECLINLINE(uint32_t) ataMSF2LBA(const uint8_t *pbBuf)
2973{
2974 return (pbBuf[0] * 60 + pbBuf[1]) * 75 + pbBuf[2];
2975}
2976
2977static void atapiCmdOK(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
2978{
2979 pAhciReq->uATARegError = 0;
2980 pAhciReq->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
2981 pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] = (pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] & ~7)
2982 | ((pAhciReq->enmTxDir != AHCITXDIR_WRITE) ? ATAPI_INT_REASON_IO : 0)
2983 | (!pAhciReq->cbTransfer ? ATAPI_INT_REASON_CD : 0);
2984 memset(pAhciPort->abATAPISense, '\0', sizeof(pAhciPort->abATAPISense));
2985 pAhciPort->abATAPISense[0] = 0x70;
2986 pAhciPort->abATAPISense[7] = 10;
2987}
2988
2989static void atapiCmdError(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, const uint8_t *pabATAPISense, size_t cbATAPISense)
2990{
2991 Log(("%s: sense=%#x (%s) asc=%#x ascq=%#x (%s)\n", __FUNCTION__, pabATAPISense[2] & 0x0f, SCSISenseText(pabATAPISense[2] & 0x0f),
2992 pabATAPISense[12], pabATAPISense[13], SCSISenseExtText(pabATAPISense[12], pabATAPISense[13])));
2993 pAhciReq->uATARegError = pabATAPISense[2] << 4;
2994 pAhciReq->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
2995 pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] = (pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] & ~7) |
2996 ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
2997 memset(pAhciPort->abATAPISense, '\0', sizeof(pAhciPort->abATAPISense));
2998 memcpy(pAhciPort->abATAPISense, pabATAPISense, RT_MIN(cbATAPISense, sizeof(pAhciPort->abATAPISense)));
2999}
3000
3001/** @todo deprecated function - doesn't provide enough info. Replace by direct
3002 * calls to atapiCmdError() with full data. */
3003static void atapiCmdErrorSimple(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, uint8_t uATAPISenseKey, uint8_t uATAPIASC)
3004{
3005 uint8_t abATAPISense[ATAPI_SENSE_SIZE];
3006 memset(abATAPISense, '\0', sizeof(abATAPISense));
3007 abATAPISense[0] = 0x70 | (1 << 7);
3008 abATAPISense[2] = uATAPISenseKey & 0x0f;
3009 abATAPISense[7] = 10;
3010 abATAPISense[12] = uATAPIASC;
3011 atapiCmdError(pAhciPort, pAhciReq, abATAPISense, sizeof(abATAPISense));
3012}
3013
3014static void ataSCSIPadStr(uint8_t *pbDst, const char *pbSrc, uint32_t cbSize)
3015{
3016 for (uint32_t i = 0; i < cbSize; i++)
3017 {
3018 if (*pbSrc)
3019 pbDst[i] = *pbSrc++;
3020 else
3021 pbDst[i] = ' ';
3022 }
3023}
3024
3025static void ataPadString(uint8_t *pbDst, const char *pbSrc, uint32_t cbSize)
3026{
3027 for (uint32_t i = 0; i < cbSize; i++)
3028 {
3029 if (*pbSrc)
3030 pbDst[i ^ 1] = *pbSrc++;
3031 else
3032 pbDst[i ^ 1] = ' ';
3033 }
3034}
3035
3036static uint32_t ataChecksum(void* ptr, size_t count)
3037{
3038 uint8_t u8Sum = 0xa5, *p = (uint8_t*)ptr;
3039 size_t i;
3040
3041 for (i = 0; i < count; i++)
3042 {
3043 u8Sum += *p++;
3044 }
3045
3046 return (uint8_t)-(int32_t)u8Sum;
3047}
3048
3049static int ahciIdentifySS(PAHCIPort pAhciPort, void *pvBuf)
3050{
3051 uint16_t *p;
3052 int rc = VINF_SUCCESS;
3053
3054 p = (uint16_t *)pvBuf;
3055 memset(p, 0, 512);
3056 p[0] = RT_H2LE_U16(0x0040);
3057 p[1] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383));
3058 p[3] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cHeads);
3059 /* Block size; obsolete, but required for the BIOS. */
3060 p[5] = RT_H2LE_U16(512);
3061 p[6] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cSectors);
3062 ataPadString((uint8_t *)(p + 10), pAhciPort->szSerialNumber, AHCI_SERIAL_NUMBER_LENGTH); /* serial number */
3063 p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
3064 p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
3065 p[22] = RT_H2LE_U16(0); /* ECC bytes per sector */
3066 ataPadString((uint8_t *)(p + 23), pAhciPort->szFirmwareRevision, AHCI_FIRMWARE_REVISION_LENGTH); /* firmware version */
3067 ataPadString((uint8_t *)(p + 27), pAhciPort->szModelNumber, AHCI_MODEL_NUMBER_LENGTH); /* model */
3068#if ATA_MAX_MULT_SECTORS > 1
3069 p[47] = RT_H2LE_U16(0x8000 | ATA_MAX_MULT_SECTORS);
3070#endif
3071 p[48] = RT_H2LE_U16(1); /* dword I/O, used by the BIOS */
3072 p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
3073 p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
3074 p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
3075 p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
3076 p[53] = RT_H2LE_U16(1 | 1 << 1 | 1 << 2); /* words 54-58,64-70,88 valid */
3077 p[54] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383));
3078 p[55] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cHeads);
3079 p[56] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cSectors);
3080 p[57] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors);
3081 p[58] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors >> 16);
3082 if (pAhciPort->cMultSectors)
3083 p[59] = RT_H2LE_U16(0x100 | pAhciPort->cMultSectors);
3084 if (pAhciPort->cTotalSectors <= (1 << 28) - 1)
3085 {
3086 p[60] = RT_H2LE_U16(pAhciPort->cTotalSectors);
3087 p[61] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 16);
3088 }
3089 else
3090 {
3091 /* Report maximum number of sectors possible with LBA28 */
3092 p[60] = RT_H2LE_U16(((1 << 28) - 1) & 0xffff);
3093 p[61] = RT_H2LE_U16(((1 << 28) - 1) >> 16);
3094 }
3095 p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* MDMA modes supported / mode enabled */
3096 p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
3097 p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
3098 p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
3099 p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
3100 p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
3101 if ( pAhciPort->pDrvBlock->pfnDiscard
3102 || ( pAhciPort->fAsyncInterface
3103 && pAhciPort->pDrvBlockAsync->pfnStartDiscard)
3104 || pAhciPort->cbSector != 512
3105 || pAhciPort->fNonRotational)
3106 {
3107 p[80] = RT_H2LE_U16(0x1f0); /* support everything up to ATA/ATAPI-8 ACS */
3108 p[81] = RT_H2LE_U16(0x28); /* conforms to ATA/ATAPI-8 ACS */
3109 }
3110 else
3111 {
3112 p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
3113 p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
3114 }
3115 p[82] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* supports power management, write cache and look-ahead */
3116 p[83] = RT_H2LE_U16(1 << 14 | 1 << 10 | 1 << 12 | 1 << 13); /* supports LBA48, FLUSH CACHE and FLUSH CACHE EXT */
3117 p[84] = RT_H2LE_U16(1 << 14);
3118 p[85] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* enabled power management, write cache and look-ahead */
3119 p[86] = RT_H2LE_U16(1 << 10 | 1 << 12 | 1 << 13); /* enabled LBA48, FLUSH CACHE and FLUSH CACHE EXT */
3120 p[87] = RT_H2LE_U16(1 << 14);
3121 p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* UDMA modes supported / mode enabled */
3122 p[93] = RT_H2LE_U16(0x00);
3123 p[100] = RT_H2LE_U16(pAhciPort->cTotalSectors);
3124 p[101] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 16);
3125 p[102] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 32);
3126 p[103] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 48);
3127
3128 /* valid information, more than one logical sector per physical sector, 2^cLogSectorsPerPhysicalExp logical sectors per physical sector */
3129 if (pAhciPort->cLogSectorsPerPhysicalExp)
3130 p[106] = RT_H2LE_U16(RT_BIT(14) | RT_BIT(13) | pAhciPort->cLogSectorsPerPhysicalExp);
3131
3132 if (pAhciPort->cbSector != 512)
3133 {
3134 uint32_t cSectorSizeInWords = pAhciPort->cbSector / sizeof(uint16_t);
3135 /* Enable reporting of logical sector size. */
3136 p[106] |= RT_H2LE_U16(RT_BIT(12) | RT_BIT(14));
3137 p[117] = RT_H2LE_U16(cSectorSizeInWords);
3138 p[118] = RT_H2LE_U16(cSectorSizeInWords >> 16);
3139 }
3140
3141 if (pAhciPort->fNonRotational)
3142 p[217] = RT_H2LE_U16(1); /* Non-rotational medium */
3143
3144 if ( pAhciPort->pDrvBlock->pfnDiscard
3145 || ( pAhciPort->fAsyncInterface
3146 && pAhciPort->pDrvBlockAsync->pfnStartDiscard)) /** @todo: Set bit 14 in word 69 too? (Deterministic read after TRIM). */
3147 p[169] = RT_H2LE_U16(1); /* DATA SET MANAGEMENT command supported. */
3148
3149 /* The following are SATA specific */
3150 p[75] = RT_H2LE_U16(pAhciPort->CTX_SUFF(pAhci)->cCmdSlotsAvail-1); /* Number of commands we support, 0's based */
3151 p[76] = RT_H2LE_U16((1 << 8) | (1 << 2)); /* Native command queuing and Serial ATA Gen2 (3.0 Gbps) speed supported */
3152
3153 uint32_t uCsum = ataChecksum(p, 510);
3154 p[255] = RT_H2LE_U16(0xa5 | (uCsum << 8)); /* Integrity word */
3155
3156 return VINF_SUCCESS;
3157}
3158
3159typedef int (*PAtapiFunc)(PAHCIREQ, PAHCIPort, size_t, size_t *);
3160
3161static int atapiGetConfigurationSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
3162static int atapiGetEventStatusNotificationSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
3163static int atapiIdentifySS(PAHCIREQ, PAHCIPort, size_t, size_t *);
3164static int atapiInquirySS(PAHCIREQ, PAHCIPort, size_t, size_t *);
3165static int atapiMechanismStatusSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
3166static int atapiModeSenseErrorRecoverySS(PAHCIREQ, PAHCIPort, size_t, size_t *);
3167static int atapiModeSenseCDStatusSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
3168static int atapiReadCapacitySS(PAHCIREQ, PAHCIPort, size_t, size_t *);
3169static int atapiReadDiscInformationSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
3170static int atapiReadTOCNormalSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
3171static int atapiReadTOCMultiSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
3172static int atapiReadTOCRawSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
3173static int atapiReadTrackInformationSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
3174static int atapiRequestSenseSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
3175static int atapiPassthroughSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
3176static int atapiReadDVDStructureSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
3177
3178/**
3179 * Source/sink function indexes for g_apfnAtapiFuncs.
3180 */
3181typedef enum ATAPIFN
3182{
3183 ATAFN_SS_NULL = 0,
3184 ATAFN_SS_ATAPI_GET_CONFIGURATION,
3185 ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION,
3186 ATAFN_SS_ATAPI_IDENTIFY,
3187 ATAFN_SS_ATAPI_INQUIRY,
3188 ATAFN_SS_ATAPI_MECHANISM_STATUS,
3189 ATAFN_SS_ATAPI_MODE_SENSE_ERROR_RECOVERY,
3190 ATAFN_SS_ATAPI_MODE_SENSE_CD_STATUS,
3191 ATAFN_SS_ATAPI_READ_CAPACITY,
3192 ATAFN_SS_ATAPI_READ_DISC_INFORMATION,
3193 ATAFN_SS_ATAPI_READ_TOC_NORMAL,
3194 ATAFN_SS_ATAPI_READ_TOC_MULTI,
3195 ATAFN_SS_ATAPI_READ_TOC_RAW,
3196 ATAFN_SS_ATAPI_READ_TRACK_INFORMATION,
3197 ATAFN_SS_ATAPI_REQUEST_SENSE,
3198 ATAFN_SS_ATAPI_PASSTHROUGH,
3199 ATAFN_SS_ATAPI_READ_DVD_STRUCTURE,
3200 ATAFN_SS_MAX
3201} ATAPIFN;
3202
3203/**
3204 * Array of source/sink functions, the index is ATAFNSS.
3205 * Make sure ATAFNSS and this array match!
3206 */
3207static const PAtapiFunc g_apfnAtapiFuncs[ATAFN_SS_MAX] =
3208{
3209 NULL,
3210 atapiGetConfigurationSS,
3211 atapiGetEventStatusNotificationSS,
3212 atapiIdentifySS,
3213 atapiInquirySS,
3214 atapiMechanismStatusSS,
3215 atapiModeSenseErrorRecoverySS,
3216 atapiModeSenseCDStatusSS,
3217 atapiReadCapacitySS,
3218 atapiReadDiscInformationSS,
3219 atapiReadTOCNormalSS,
3220 atapiReadTOCMultiSS,
3221 atapiReadTOCRawSS,
3222 atapiReadTrackInformationSS,
3223 atapiRequestSenseSS,
3224 atapiPassthroughSS,
3225 atapiReadDVDStructureSS
3226};
3227
3228static int atapiIdentifySS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
3229{
3230 uint16_t p[256];
3231
3232 memset(p, 0, 512);
3233 /* Removable CDROM, 50us response, 12 byte packets */
3234 p[0] = RT_H2LE_U16(2 << 14 | 5 << 8 | 1 << 7 | 2 << 5 | 0 << 0);
3235 ataPadString((uint8_t *)(p + 10), pAhciPort->szSerialNumber, AHCI_SERIAL_NUMBER_LENGTH); /* serial number */
3236 p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
3237 p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
3238 ataPadString((uint8_t *)(p + 23), pAhciPort->szFirmwareRevision, AHCI_FIRMWARE_REVISION_LENGTH); /* firmware version */
3239 ataPadString((uint8_t *)(p + 27), pAhciPort->szModelNumber, AHCI_MODEL_NUMBER_LENGTH); /* model */
3240 p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
3241 p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
3242 p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
3243 p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
3244 p[53] = RT_H2LE_U16(1 << 1 | 1 << 2); /* words 64-70,88 are valid */
3245 p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* MDMA modes supported / mode enabled */
3246 p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
3247 p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
3248 p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
3249 p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
3250 p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
3251 p[73] = RT_H2LE_U16(0x003e); /* ATAPI CDROM major */
3252 p[74] = RT_H2LE_U16(9); /* ATAPI CDROM minor */
3253 p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
3254 p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
3255 p[82] = RT_H2LE_U16(1 << 4 | 1 << 9); /* supports packet command set and DEVICE RESET */
3256 p[83] = RT_H2LE_U16(1 << 14);
3257 p[84] = RT_H2LE_U16(1 << 14);
3258 p[85] = RT_H2LE_U16(1 << 4 | 1 << 9); /* enabled packet command set and DEVICE RESET */
3259 p[86] = RT_H2LE_U16(0);
3260 p[87] = RT_H2LE_U16(1 << 14);
3261 p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* UDMA modes supported / mode enabled */
3262 p[93] = RT_H2LE_U16((1 | 1 << 1) << ((pAhciPort->iLUN & 1) == 0 ? 0 : 8) | 1 << 13 | 1 << 14);
3263
3264 /* The following are SATA specific */
3265 p[75] = RT_H2LE_U16(31); /* We support 32 commands */
3266 p[76] = RT_H2LE_U16((1 << 8) | (1 << 2)); /* Native command queuing and Serial ATA Gen2 (3.0 Gbps) speed supported */
3267
3268 /* Copy the buffer in to the scatter gather list. */
3269 *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&p[0],
3270 RT_MIN(cbData, sizeof(p)));
3271
3272 atapiCmdOK(pAhciPort, pAhciReq);
3273 return VINF_SUCCESS;
3274}
3275
3276static int atapiReadCapacitySS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
3277{
3278 uint8_t aBuf[8];
3279
3280 ataH2BE_U32(aBuf, pAhciPort->cTotalSectors - 1);
3281 ataH2BE_U32(aBuf + 4, 2048);
3282
3283 /* Copy the buffer in to the scatter gather list. */
3284 *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
3285 RT_MIN(cbData, sizeof(aBuf)));
3286
3287 atapiCmdOK(pAhciPort, pAhciReq);
3288 return VINF_SUCCESS;
3289}
3290
3291
3292static int atapiReadDiscInformationSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
3293{
3294 uint8_t aBuf[34];
3295
3296 memset(aBuf, '\0', 34);
3297 ataH2BE_U16(aBuf, 32);
3298 aBuf[2] = (0 << 4) | (3 << 2) | (2 << 0); /* not erasable, complete session, complete disc */
3299 aBuf[3] = 1; /* number of first track */
3300 aBuf[4] = 1; /* number of sessions (LSB) */
3301 aBuf[5] = 1; /* first track number in last session (LSB) */
3302 aBuf[6] = 1; /* last track number in last session (LSB) */
3303 aBuf[7] = (0 << 7) | (0 << 6) | (1 << 5) | (0 << 2) | (0 << 0); /* disc id not valid, disc bar code not valid, unrestricted use, not dirty, not RW medium */
3304 aBuf[8] = 0; /* disc type = CD-ROM */
3305 aBuf[9] = 0; /* number of sessions (MSB) */
3306 aBuf[10] = 0; /* number of sessions (MSB) */
3307 aBuf[11] = 0; /* number of sessions (MSB) */
3308 ataH2BE_U32(aBuf + 16, 0x00ffffff); /* last session lead-in start time is not available */
3309 ataH2BE_U32(aBuf + 20, 0x00ffffff); /* last possible start time for lead-out is not available */
3310
3311 /* Copy the buffer in to the scatter gather list. */
3312 *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
3313 RT_MIN(cbData, sizeof(aBuf)));
3314
3315 atapiCmdOK(pAhciPort, pAhciReq);
3316 return VINF_SUCCESS;
3317}
3318
3319
3320static int atapiReadTrackInformationSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
3321{
3322 uint8_t aBuf[36];
3323
3324 /* Accept address/number type of 1 only, and only track 1 exists. */
3325 if ((pAhciReq->aATAPICmd[1] & 0x03) != 1 || ataBE2H_U32(&pAhciReq->aATAPICmd[2]) != 1)
3326 {
3327 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3328 return VINF_SUCCESS;
3329 }
3330 memset(aBuf, '\0', 36);
3331 ataH2BE_U16(aBuf, 34);
3332 aBuf[2] = 1; /* track number (LSB) */
3333 aBuf[3] = 1; /* session number (LSB) */
3334 aBuf[5] = (0 << 5) | (0 << 4) | (4 << 0); /* not damaged, primary copy, data track */
3335 aBuf[6] = (0 << 7) | (0 << 6) | (0 << 5) | (0 << 6) | (1 << 0); /* not reserved track, not blank, not packet writing, not fixed packet, data mode 1 */
3336 aBuf[7] = (0 << 1) | (0 << 0); /* last recorded address not valid, next recordable address not valid */
3337 ataH2BE_U32(aBuf + 8, 0); /* track start address is 0 */
3338 ataH2BE_U32(aBuf + 24, pAhciPort->cTotalSectors); /* track size */
3339 aBuf[32] = 0; /* track number (MSB) */
3340 aBuf[33] = 0; /* session number (MSB) */
3341
3342 /* Copy the buffer in to the scatter gather list. */
3343 *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
3344 RT_MIN(cbData, sizeof(aBuf)));
3345
3346 atapiCmdOK(pAhciPort, pAhciReq);
3347 return VINF_SUCCESS;
3348}
3349
3350static size_t atapiGetConfigurationFillFeatureListProfiles(PAHCIPort pAhciPort, uint8_t *pbBuf, size_t cbBuf)
3351{
3352 if (cbBuf < 3*4)
3353 return 0;
3354
3355 ataH2BE_U16(pbBuf, 0x0); /* feature 0: list of profiles supported */
3356 pbBuf[2] = (0 << 2) | (1 << 1) | (1 << 0); /* version 0, persistent, current */
3357 pbBuf[3] = 8; /* additional bytes for profiles */
3358 /* The MMC-3 spec says that DVD-ROM read capability should be reported
3359 * before CD-ROM read capability. */
3360 ataH2BE_U16(pbBuf + 4, 0x10); /* profile: read-only DVD */
3361 pbBuf[6] = (0 << 0); /* NOT current profile */
3362 ataH2BE_U16(pbBuf + 8, 0x08); /* profile: read only CD */
3363 pbBuf[10] = (1 << 0); /* current profile */
3364
3365 return 3*4; /* Header + 2 profiles entries */
3366}
3367
3368static size_t atapiGetConfigurationFillFeatureCore(PAHCIPort pAhciPort, uint8_t *pbBuf, size_t cbBuf)
3369{
3370 if (cbBuf < 12)
3371 return 0;
3372
3373 ataH2BE_U16(pbBuf, 0x1); /* feature 0001h: Core Feature */
3374 pbBuf[2] = (0x2 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
3375 pbBuf[3] = 8; /* Additional length */
3376 ataH2BE_U16(pbBuf + 4, 0x00000002); /* Physical interface ATAPI. */
3377 pbBuf[8] = RT_BIT(0); /* DBE */
3378 /* Rest is reserved. */
3379
3380 return 12;
3381}
3382
3383static size_t atapiGetConfigurationFillFeatureMorphing(PAHCIPort pAhciPort, uint8_t *pbBuf, size_t cbBuf)
3384{
3385 if (cbBuf < 8)
3386 return 0;
3387
3388 ataH2BE_U16(pbBuf, 0x2); /* feature 0002h: Morphing Feature */
3389 pbBuf[2] = (0x1 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
3390 pbBuf[3] = 4; /* Additional length */
3391 pbBuf[4] = RT_BIT(1) | 0x0; /* OCEvent | !ASYNC */
3392 /* Rest is reserved. */
3393
3394 return 8;
3395}
3396
3397static size_t atapiGetConfigurationFillFeatureRemovableMedium(PAHCIPort pAhciPort, uint8_t *pbBuf, size_t cbBuf)
3398{
3399 if (cbBuf < 8)
3400 return 0;
3401
3402 ataH2BE_U16(pbBuf, 0x3); /* feature 0003h: Removable Medium Feature */
3403 pbBuf[2] = (0x2 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
3404 pbBuf[3] = 4; /* Additional length */
3405 /* Tray type loading | Load | Eject | !Pvnt Jmpr | !DBML | Lock */
3406 pbBuf[4] = (0x2 << 5) | RT_BIT(4) | RT_BIT(3) | (0x0 << 2) | (0x0 << 1) | RT_BIT(0);
3407 /* Rest is reserved. */
3408
3409 return 8;
3410}
3411
3412static size_t atapiGetConfigurationFillFeatureRandomReadable(PAHCIPort pAhciPort, uint8_t *pbBuf, size_t cbBuf)
3413{
3414 if (cbBuf < 12)
3415 return 0;
3416
3417 ataH2BE_U16(pbBuf, 0x10); /* feature 0010h: Random Readable Feature */
3418 pbBuf[2] = (0x0 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
3419 pbBuf[3] = 8; /* Additional length */
3420 ataH2BE_U32(pbBuf + 4, 2048); /* Logical block size. */
3421 ataH2BE_U16(pbBuf + 8, 0x10); /* Blocking (0x10 for DVD, CD is not defined). */
3422 pbBuf[10] = 0; /* PP not present */
3423 /* Rest is reserved. */
3424
3425 return 12;
3426}
3427
3428static size_t atapiGetConfigurationFillFeatureCDRead(PAHCIPort pAhciPort, uint8_t *pbBuf, size_t cbBuf)
3429{
3430 if (cbBuf < 8)
3431 return 0;
3432
3433 ataH2BE_U16(pbBuf, 0x1e); /* feature 001Eh: CD Read Feature */
3434 pbBuf[2] = (0x2 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
3435 pbBuf[3] = 0; /* Additional length */
3436 pbBuf[4] = (0x0 << 7) | (0x0 << 1) | 0x0; /* !DAP | !C2-Flags | !CD-Text. */
3437 /* Rest is reserved. */
3438
3439 return 8;
3440}
3441
3442static size_t atapiGetConfigurationFillFeaturePowerManagement(PAHCIPort pAhciPort, uint8_t *pbBuf, size_t cbBuf)
3443{
3444 if (cbBuf < 4)
3445 return 0;
3446
3447 ataH2BE_U16(pbBuf, 0x100); /* feature 0100h: Power Management Feature */
3448 pbBuf[2] = (0x0 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
3449 pbBuf[3] = 0; /* Additional length */
3450
3451 return 4;
3452}
3453
3454static size_t atapiGetConfigurationFillFeatureTimeout(PAHCIPort pAhciPort, uint8_t *pbBuf, size_t cbBuf)
3455{
3456 if (cbBuf < 8)
3457 return 0;
3458
3459 ataH2BE_U16(pbBuf, 0x105); /* feature 0105h: Timeout Feature */
3460 pbBuf[2] = (0x0 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
3461 pbBuf[3] = 4; /* Additional length */
3462 pbBuf[4] = 0x0; /* !Group3 */
3463
3464 return 8;
3465}
3466
3467static int atapiGetConfigurationSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
3468{
3469 uint8_t aBuf[80];
3470 uint8_t *pbBuf = &aBuf[0];
3471 size_t cbBuf = sizeof(aBuf);
3472 size_t cbCopied = 0;
3473
3474 /* Accept valid request types only, and only starting feature 0. */
3475 if ((pAhciReq->aATAPICmd[1] & 0x03) == 3 || ataBE2H_U16(&pAhciReq->aATAPICmd[2]) != 0)
3476 {
3477 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3478 return VINF_SUCCESS;
3479 }
3480 /** @todo implement switching between CD-ROM and DVD-ROM profile (the only
3481 * way to differentiate them right now is based on the image size). */
3482 if (pAhciPort->cTotalSectors)
3483 ataH2BE_U16(pbBuf + 6, 0x08); /* current profile: read-only CD */
3484 else
3485 ataH2BE_U16(pbBuf + 6, 0x00); /* current profile: none -> no media */
3486 cbBuf -= 8;
3487 pbBuf += 8;
3488
3489 cbCopied = atapiGetConfigurationFillFeatureListProfiles(pAhciPort, pbBuf, cbBuf);
3490 cbBuf -= cbCopied;
3491 pbBuf += cbCopied;
3492
3493 cbCopied = atapiGetConfigurationFillFeatureCore(pAhciPort, pbBuf, cbBuf);
3494 cbBuf -= cbCopied;
3495 pbBuf += cbCopied;
3496
3497 cbCopied = atapiGetConfigurationFillFeatureMorphing(pAhciPort, pbBuf, cbBuf);
3498 cbBuf -= cbCopied;
3499 pbBuf += cbCopied;
3500
3501 cbCopied = atapiGetConfigurationFillFeatureRemovableMedium(pAhciPort, pbBuf, cbBuf);
3502 cbBuf -= cbCopied;
3503 pbBuf += cbCopied;
3504
3505 cbCopied = atapiGetConfigurationFillFeatureRandomReadable(pAhciPort, pbBuf, cbBuf);
3506 cbBuf -= cbCopied;
3507 pbBuf += cbCopied;
3508
3509 cbCopied = atapiGetConfigurationFillFeatureCDRead(pAhciPort, pbBuf, cbBuf);
3510 cbBuf -= cbCopied;
3511 pbBuf += cbCopied;
3512
3513 cbCopied = atapiGetConfigurationFillFeaturePowerManagement(pAhciPort, pbBuf, cbBuf);
3514 cbBuf -= cbCopied;
3515 pbBuf += cbCopied;
3516
3517 cbCopied = atapiGetConfigurationFillFeatureTimeout(pAhciPort, pbBuf, cbBuf);
3518 cbBuf -= cbCopied;
3519 pbBuf += cbCopied;
3520
3521 /* Set data length now. */
3522 ataH2BE_U32(&aBuf[0], sizeof(aBuf) - cbBuf);
3523
3524 /* Copy the buffer in to the scatter gather list. */
3525 *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
3526 RT_MIN(cbData, sizeof(aBuf)));
3527
3528 atapiCmdOK(pAhciPort, pAhciReq);
3529 return VINF_SUCCESS;
3530}
3531
3532
3533static int atapiGetEventStatusNotificationSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
3534{
3535 uint8_t abBuf[8];
3536
3537 Assert(pAhciReq->enmTxDir == AHCITXDIR_READ);
3538 Assert(pAhciReq->cbTransfer <= 8);
3539
3540 if (!(pAhciReq->aATAPICmd[1] & 1))
3541 {
3542 /* no asynchronous operation supported */
3543 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3544 return VINF_SUCCESS;
3545 }
3546
3547 uint32_t OldStatus, NewStatus;
3548 do
3549 {
3550 OldStatus = ASMAtomicReadU32(&pAhciPort->MediaEventStatus);
3551 NewStatus = ATA_EVENT_STATUS_UNCHANGED;
3552 switch (OldStatus)
3553 {
3554 case ATA_EVENT_STATUS_MEDIA_NEW:
3555 /* mount */
3556 ataH2BE_U16(abBuf + 0, 6);
3557 abBuf[2] = 0x04; /* media */
3558 abBuf[3] = 0x5e; /* supported = busy|media|external|power|operational */
3559 abBuf[4] = 0x02; /* new medium */
3560 abBuf[5] = 0x02; /* medium present / door closed */
3561 abBuf[6] = 0x00;
3562 abBuf[7] = 0x00;
3563 break;
3564
3565 case ATA_EVENT_STATUS_MEDIA_CHANGED:
3566 case ATA_EVENT_STATUS_MEDIA_REMOVED:
3567 /* umount */
3568 ataH2BE_U16(abBuf + 0, 6);
3569 abBuf[2] = 0x04; /* media */
3570 abBuf[3] = 0x5e; /* supported = busy|media|external|power|operational */
3571 abBuf[4] = 0x03; /* media removal */
3572 abBuf[5] = 0x00; /* medium absent / door closed */
3573 abBuf[6] = 0x00;
3574 abBuf[7] = 0x00;
3575 if (OldStatus == ATA_EVENT_STATUS_MEDIA_CHANGED)
3576 NewStatus = ATA_EVENT_STATUS_MEDIA_NEW;
3577 break;
3578
3579 case ATA_EVENT_STATUS_MEDIA_EJECT_REQUESTED: /* currently unused */
3580 ataH2BE_U16(abBuf + 0, 6);
3581 abBuf[2] = 0x04; /* media */
3582 abBuf[3] = 0x5e; /* supported = busy|media|external|power|operational */
3583 abBuf[4] = 0x01; /* eject requested (eject button pressed) */
3584 abBuf[5] = 0x02; /* medium present / door closed */
3585 abBuf[6] = 0x00;
3586 abBuf[7] = 0x00;
3587 break;
3588
3589 case ATA_EVENT_STATUS_UNCHANGED:
3590 default:
3591 ataH2BE_U16(abBuf + 0, 6);
3592 abBuf[2] = 0x01; /* operational change request / notification */
3593 abBuf[3] = 0x5e; /* supported = busy|media|external|power|operational */
3594 abBuf[4] = 0x00;
3595 abBuf[5] = 0x00;
3596 abBuf[6] = 0x00;
3597 abBuf[7] = 0x00;
3598 break;
3599 }
3600 } while (!ASMAtomicCmpXchgU32(&pAhciPort->MediaEventStatus, NewStatus, OldStatus));
3601
3602 *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&abBuf[0],
3603 RT_MIN(cbData, sizeof(abBuf)));
3604
3605 atapiCmdOK(pAhciPort, pAhciReq);
3606 return VINF_SUCCESS;
3607}
3608
3609
3610static int atapiInquirySS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
3611{
3612 uint8_t aBuf[36];
3613
3614 aBuf[0] = 0x05; /* CD-ROM */
3615 aBuf[1] = 0x80; /* removable */
3616 aBuf[2] = 0x00; /* ISO */
3617 aBuf[3] = 0x21; /* ATAPI-2 (XXX: put ATAPI-4 ?) */
3618 aBuf[4] = 31; /* additional length */
3619 aBuf[5] = 0; /* reserved */
3620 aBuf[6] = 0; /* reserved */
3621 aBuf[7] = 0; /* reserved */
3622 ataSCSIPadStr(aBuf + 8, pAhciPort->szInquiryVendorId, 8);
3623 ataSCSIPadStr(aBuf + 16, pAhciPort->szInquiryProductId, 16);
3624 ataSCSIPadStr(aBuf + 32, pAhciPort->szInquiryRevision, 4);
3625
3626 /* Copy the buffer in to the scatter gather list. */
3627 *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
3628 RT_MIN(cbData, sizeof(aBuf)));
3629
3630 atapiCmdOK(pAhciPort, pAhciReq);
3631 return VINF_SUCCESS;
3632}
3633
3634
3635static int atapiModeSenseErrorRecoverySS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
3636{
3637 uint8_t aBuf[16];
3638
3639 ataH2BE_U16(&aBuf[0], 16 + 6);
3640 aBuf[2] = 0x70;
3641 aBuf[3] = 0;
3642 aBuf[4] = 0;
3643 aBuf[5] = 0;
3644 aBuf[6] = 0;
3645 aBuf[7] = 0;
3646
3647 aBuf[8] = 0x01;
3648 aBuf[9] = 0x06;
3649 aBuf[10] = 0x00;
3650 aBuf[11] = 0x05;
3651 aBuf[12] = 0x00;
3652 aBuf[13] = 0x00;
3653 aBuf[14] = 0x00;
3654 aBuf[15] = 0x00;
3655
3656 /* Copy the buffer in to the scatter gather list. */
3657 *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
3658 RT_MIN(cbData, sizeof(aBuf)));
3659
3660 atapiCmdOK(pAhciPort, pAhciReq);
3661 return VINF_SUCCESS;
3662}
3663
3664
3665static int atapiModeSenseCDStatusSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
3666{
3667 uint8_t aBuf[40];
3668
3669 ataH2BE_U16(&aBuf[0], 38);
3670 aBuf[2] = 0x70;
3671 aBuf[3] = 0;
3672 aBuf[4] = 0;
3673 aBuf[5] = 0;
3674 aBuf[6] = 0;
3675 aBuf[7] = 0;
3676
3677 aBuf[8] = 0x2a;
3678 aBuf[9] = 30; /* page length */
3679 aBuf[10] = 0x08; /* DVD-ROM read support */
3680 aBuf[11] = 0x00; /* no write support */
3681 /* The following claims we support audio play. This is obviously false,
3682 * but the Linux generic CDROM support makes many features depend on this
3683 * capability. If it's not set, this causes many things to be disabled. */
3684 aBuf[12] = 0x71; /* multisession support, mode 2 form 1/2 support, audio play */
3685 aBuf[13] = 0x00; /* no subchannel reads supported */
3686 aBuf[14] = (1 << 0) | (1 << 3) | (1 << 5); /* lock supported, eject supported, tray type loading mechanism */
3687 if (pAhciPort->pDrvMount->pfnIsLocked(pAhciPort->pDrvMount))
3688 aBuf[14] |= 1 << 1; /* report lock state */
3689 aBuf[15] = 0; /* no subchannel reads supported, no separate audio volume control, no changer etc. */
3690 ataH2BE_U16(&aBuf[16], 5632); /* (obsolete) claim 32x speed support */
3691 ataH2BE_U16(&aBuf[18], 2); /* number of audio volume levels */
3692 ataH2BE_U16(&aBuf[20], 128); /* buffer size supported in Kbyte - We don't have a buffer because we write directly into guest memory.
3693 Just write the value DevATA is using. */
3694 ataH2BE_U16(&aBuf[22], 5632); /* (obsolete) current read speed 32x */
3695 aBuf[24] = 0; /* reserved */
3696 aBuf[25] = 0; /* reserved for digital audio (see idx 15) */
3697 ataH2BE_U16(&aBuf[26], 0); /* (obsolete) maximum write speed */
3698 ataH2BE_U16(&aBuf[28], 0); /* (obsolete) current write speed */
3699 ataH2BE_U16(&aBuf[30], 0); /* copy management revision supported 0=no CSS */
3700 aBuf[32] = 0; /* reserved */
3701 aBuf[33] = 0; /* reserved */
3702 aBuf[34] = 0; /* reserved */
3703 aBuf[35] = 1; /* rotation control CAV */
3704 ataH2BE_U16(&aBuf[36], 0); /* current write speed */
3705 ataH2BE_U16(&aBuf[38], 0); /* number of write speed performance descriptors */
3706
3707 /* Copy the buffer in to the scatter gather list. */
3708 *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
3709 RT_MIN(cbData, sizeof(aBuf)));
3710
3711 atapiCmdOK(pAhciPort, pAhciReq);
3712 return VINF_SUCCESS;
3713}
3714
3715
3716static int atapiRequestSenseSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
3717{
3718 /* Copy the buffer in to the scatter gather list. */
3719 *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq,
3720 pAhciPort->abATAPISense, RT_MIN(cbData, sizeof(pAhciPort->abATAPISense)));
3721
3722 atapiCmdOK(pAhciPort, pAhciReq);
3723 return VINF_SUCCESS;
3724}
3725
3726
3727static int atapiMechanismStatusSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
3728{
3729 uint8_t aBuf[8];
3730
3731 ataH2BE_U16(&aBuf[0], 0);
3732 /* no current LBA */
3733 aBuf[2] = 0;
3734 aBuf[3] = 0;
3735 aBuf[4] = 0;
3736 aBuf[5] = 1;
3737 ataH2BE_U16(aBuf + 6, 0);
3738
3739 /* Copy the buffer in to the scatter gather list. */
3740 *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
3741 RT_MIN(cbData, sizeof(aBuf)));
3742
3743 atapiCmdOK(pAhciPort, pAhciReq);
3744 return VINF_SUCCESS;
3745}
3746
3747
3748static int atapiReadTOCNormalSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
3749{
3750 uint8_t aBuf[20], *q, iStartTrack;
3751 bool fMSF;
3752 uint32_t cbSize;
3753
3754 fMSF = (pAhciReq->aATAPICmd[1] >> 1) & 1;
3755 iStartTrack = pAhciReq->aATAPICmd[6];
3756 if (iStartTrack > 1 && iStartTrack != 0xaa)
3757 {
3758 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3759 return VINF_SUCCESS;
3760 }
3761 q = aBuf + 2;
3762 *q++ = 1; /* first session */
3763 *q++ = 1; /* last session */
3764 if (iStartTrack <= 1)
3765 {
3766 *q++ = 0; /* reserved */
3767 *q++ = 0x14; /* ADR, control */
3768 *q++ = 1; /* track number */
3769 *q++ = 0; /* reserved */
3770 if (fMSF)
3771 {
3772 *q++ = 0; /* reserved */
3773 ataLBA2MSF(q, 0);
3774 q += 3;
3775 }
3776 else
3777 {
3778 /* sector 0 */
3779 ataH2BE_U32(q, 0);
3780 q += 4;
3781 }
3782 }
3783 /* lead out track */
3784 *q++ = 0; /* reserved */
3785 *q++ = 0x14; /* ADR, control */
3786 *q++ = 0xaa; /* track number */
3787 *q++ = 0; /* reserved */
3788 if (fMSF)
3789 {
3790 *q++ = 0; /* reserved */
3791 ataLBA2MSF(q, pAhciPort->cTotalSectors);
3792 q += 3;
3793 }
3794 else
3795 {
3796 ataH2BE_U32(q, pAhciPort->cTotalSectors);
3797 q += 4;
3798 }
3799 cbSize = q - aBuf;
3800 ataH2BE_U16(aBuf, cbSize - 2);
3801
3802 /* Copy the buffer in to the scatter gather list. */
3803 *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
3804 RT_MIN(cbData, cbSize));
3805
3806 atapiCmdOK(pAhciPort, pAhciReq);
3807 return VINF_SUCCESS;
3808}
3809
3810
3811static int atapiReadTOCMultiSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
3812{
3813 uint8_t aBuf[12];
3814 bool fMSF;
3815
3816 fMSF = (pAhciReq->aATAPICmd[1] >> 1) & 1;
3817 /* multi session: only a single session defined */
3818/** @todo double-check this stuff against what a real drive says for a CD-ROM (not a CD-R) with only a single data session. Maybe solve the problem with "cdrdao read-toc" not being able to figure out whether numbers are in BCD or hex. */
3819 memset(aBuf, 0, 12);
3820 aBuf[1] = 0x0a;
3821 aBuf[2] = 0x01;
3822 aBuf[3] = 0x01;
3823 aBuf[5] = 0x14; /* ADR, control */
3824 aBuf[6] = 1; /* first track in last complete session */
3825 if (fMSF)
3826 {
3827 aBuf[8] = 0; /* reserved */
3828 ataLBA2MSF(&aBuf[9], 0);
3829 }
3830 else
3831 {
3832 /* sector 0 */
3833 ataH2BE_U32(aBuf + 8, 0);
3834 }
3835
3836 /* Copy the buffer in to the scatter gather list. */
3837 *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
3838 RT_MIN(cbData, sizeof(aBuf)));
3839
3840 atapiCmdOK(pAhciPort, pAhciReq);
3841 return VINF_SUCCESS;
3842}
3843
3844
3845static int atapiReadTOCRawSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
3846{
3847 uint8_t aBuf[50]; /* Counted a maximum of 45 bytes but better be on the safe side. */
3848 uint8_t *q, iStartTrack;
3849 bool fMSF;
3850 uint32_t cbSize;
3851
3852 fMSF = (pAhciReq->aATAPICmd[1] >> 1) & 1;
3853 iStartTrack = pAhciReq->aATAPICmd[6];
3854
3855 q = aBuf + 2;
3856 *q++ = 1; /* first session */
3857 *q++ = 1; /* last session */
3858
3859 *q++ = 1; /* session number */
3860 *q++ = 0x14; /* data track */
3861 *q++ = 0; /* track number */
3862 *q++ = 0xa0; /* first track in program area */
3863 *q++ = 0; /* min */
3864 *q++ = 0; /* sec */
3865 *q++ = 0; /* frame */
3866 *q++ = 0;
3867 *q++ = 1; /* first track */
3868 *q++ = 0x00; /* disk type CD-DA or CD data */
3869 *q++ = 0;
3870
3871 *q++ = 1; /* session number */
3872 *q++ = 0x14; /* data track */
3873 *q++ = 0; /* track number */
3874 *q++ = 0xa1; /* last track in program area */
3875 *q++ = 0; /* min */
3876 *q++ = 0; /* sec */
3877 *q++ = 0; /* frame */
3878 *q++ = 0;
3879 *q++ = 1; /* last track */
3880 *q++ = 0;
3881 *q++ = 0;
3882
3883 *q++ = 1; /* session number */
3884 *q++ = 0x14; /* data track */
3885 *q++ = 0; /* track number */
3886 *q++ = 0xa2; /* lead-out */
3887 *q++ = 0; /* min */
3888 *q++ = 0; /* sec */
3889 *q++ = 0; /* frame */
3890 if (fMSF)
3891 {
3892 *q++ = 0; /* reserved */
3893 ataLBA2MSF(q, pAhciPort->cTotalSectors);
3894 q += 3;
3895 }
3896 else
3897 {
3898 ataH2BE_U32(q, pAhciPort->cTotalSectors);
3899 q += 4;
3900 }
3901
3902 *q++ = 1; /* session number */
3903 *q++ = 0x14; /* ADR, control */
3904 *q++ = 0; /* track number */
3905 *q++ = 1; /* point */
3906 *q++ = 0; /* min */
3907 *q++ = 0; /* sec */
3908 *q++ = 0; /* frame */
3909 if (fMSF)
3910 {
3911 *q++ = 0; /* reserved */
3912 ataLBA2MSF(q, 0);
3913 q += 3;
3914 }
3915 else
3916 {
3917 /* sector 0 */
3918 ataH2BE_U32(q, 0);
3919 q += 4;
3920 }
3921
3922 cbSize = q - aBuf;
3923 ataH2BE_U16(aBuf, cbSize - 2);
3924
3925 /* Copy the buffer in to the scatter gather list. */
3926 *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
3927 RT_MIN(cbData, cbSize));
3928
3929 atapiCmdOK(pAhciPort, pAhciReq);
3930 return VINF_SUCCESS;
3931}
3932
3933/**
3934 * Sets the given media track type.
3935 */
3936static uint32_t ahciMediumTypeSet(PAHCIPort pAhciPort, uint32_t MediaTrackType)
3937{
3938 return ASMAtomicXchgU32(&pAhciPort->MediaTrackType, MediaTrackType);
3939}
3940
3941static int atapiPassthroughSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
3942{
3943 int rc = VINF_SUCCESS;
3944 uint8_t abATAPISense[ATAPI_SENSE_SIZE];
3945 uint32_t cbTransfer;
3946 void *pvBuf = NULL;
3947
3948 cbTransfer = pAhciReq->cbTransfer;
3949
3950 if (cbTransfer)
3951 {
3952 pvBuf = (uint8_t *)RTMemAlloc(cbTransfer);
3953 if (!pvBuf)
3954 return VERR_NO_MEMORY;
3955
3956 if (pAhciReq->enmTxDir == AHCITXDIR_WRITE)
3957 {
3958 ahciCopyFromPrdtl(pAhciPort->pDevInsR3, pAhciReq, pvBuf, cbTransfer);
3959 if (pAhciReq->fFlags & AHCI_REQ_OVERFLOW)
3960 return VINF_SUCCESS;
3961 }
3962 }
3963
3964 /* Simple heuristics: if there is at least one sector of data
3965 * to transfer, it's worth updating the LEDs. */
3966 if (cbTransfer >= 2048)
3967 {
3968 if (pAhciReq->enmTxDir != AHCITXDIR_WRITE)
3969 pAhciPort->Led.Asserted.s.fReading = pAhciPort->Led.Actual.s.fReading = 1;
3970 else
3971 pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 1;
3972 }
3973
3974 if (cbTransfer > SCSI_MAX_BUFFER_SIZE)
3975 {
3976 /* Linux accepts commands with up to 100KB of data, but expects
3977 * us to handle commands with up to 128KB of data. The usual
3978 * imbalance of powers. */
3979 uint8_t aATAPICmd[ATAPI_PACKET_SIZE];
3980 uint32_t iATAPILBA, cSectors, cReqSectors, cbCurrTX;
3981 uint8_t *pbBuf = (uint8_t *)pvBuf;
3982
3983 switch (pAhciReq->aATAPICmd[0])
3984 {
3985 case SCSI_READ_10:
3986 case SCSI_WRITE_10:
3987 case SCSI_WRITE_AND_VERIFY_10:
3988 iATAPILBA = ataBE2H_U32(pAhciReq->aATAPICmd + 2);
3989 cSectors = ataBE2H_U16(pAhciReq->aATAPICmd + 7);
3990 break;
3991 case SCSI_READ_12:
3992 case SCSI_WRITE_12:
3993 iATAPILBA = ataBE2H_U32(pAhciReq->aATAPICmd + 2);
3994 cSectors = ataBE2H_U32(pAhciReq->aATAPICmd + 6);
3995 break;
3996 case SCSI_READ_CD:
3997 iATAPILBA = ataBE2H_U32(pAhciReq->aATAPICmd + 2);
3998 cSectors = ataBE2H_U24(pAhciReq->aATAPICmd + 6);
3999 break;
4000 case SCSI_READ_CD_MSF:
4001 iATAPILBA = ataMSF2LBA(pAhciReq->aATAPICmd + 3);
4002 cSectors = ataMSF2LBA(pAhciReq->aATAPICmd + 6) - iATAPILBA;
4003 break;
4004 default:
4005 AssertMsgFailed(("Don't know how to split command %#04x\n", pAhciReq->aATAPICmd[0]));
4006 if (pAhciPort->cErrors++ < MAX_LOG_REL_ERRORS)
4007 LogRel(("AHCI: LUN#%d: CD-ROM passthrough split error\n", pAhciPort->iLUN));
4008 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
4009 RTMemFree(pvBuf);
4010 return VINF_SUCCESS;
4011 }
4012 memcpy(aATAPICmd, pAhciReq->aATAPICmd, ATAPI_PACKET_SIZE);
4013 cReqSectors = 0;
4014 for (uint32_t i = cSectors; i > 0; i -= cReqSectors)
4015 {
4016 if (i * pAhciReq->cbATAPISector > SCSI_MAX_BUFFER_SIZE)
4017 cReqSectors = SCSI_MAX_BUFFER_SIZE / pAhciReq->cbATAPISector;
4018 else
4019 cReqSectors = i;
4020 cbCurrTX = pAhciReq->cbATAPISector * cReqSectors;
4021 switch (pAhciReq->aATAPICmd[0])
4022 {
4023 case SCSI_READ_10:
4024 case SCSI_WRITE_10:
4025 case SCSI_WRITE_AND_VERIFY_10:
4026 ataH2BE_U32(aATAPICmd + 2, iATAPILBA);
4027 ataH2BE_U16(aATAPICmd + 7, cReqSectors);
4028 break;
4029 case SCSI_READ_12:
4030 case SCSI_WRITE_12:
4031 ataH2BE_U32(aATAPICmd + 2, iATAPILBA);
4032 ataH2BE_U32(aATAPICmd + 6, cReqSectors);
4033 break;
4034 case SCSI_READ_CD:
4035 ataH2BE_U32(aATAPICmd + 2, iATAPILBA);
4036 ataH2BE_U24(aATAPICmd + 6, cReqSectors);
4037 break;
4038 case SCSI_READ_CD_MSF:
4039 ataLBA2MSF(aATAPICmd + 3, iATAPILBA);
4040 ataLBA2MSF(aATAPICmd + 6, iATAPILBA + cReqSectors);
4041 break;
4042 }
4043 rc = pAhciPort->pDrvBlock->pfnSendCmd(pAhciPort->pDrvBlock,
4044 aATAPICmd,
4045 pAhciReq->enmTxDir == AHCITXDIR_READ
4046 ? PDMBLOCKTXDIR_FROM_DEVICE
4047 : PDMBLOCKTXDIR_TO_DEVICE,
4048 pbBuf,
4049 &cbCurrTX,
4050 abATAPISense,
4051 sizeof(abATAPISense),
4052 30000 /**< @todo timeout */);
4053 if (rc != VINF_SUCCESS)
4054 break;
4055 iATAPILBA += cReqSectors;
4056 pbBuf += pAhciReq->cbATAPISector * cReqSectors;
4057 }
4058 }
4059 else
4060 {
4061 PDMBLOCKTXDIR enmBlockTxDir = PDMBLOCKTXDIR_NONE;
4062
4063 if (pAhciReq->enmTxDir == AHCITXDIR_READ)
4064 enmBlockTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
4065 else if (pAhciReq->enmTxDir == AHCITXDIR_WRITE)
4066 enmBlockTxDir = PDMBLOCKTXDIR_TO_DEVICE;
4067 else if (pAhciReq->enmTxDir == AHCITXDIR_NONE)
4068 enmBlockTxDir = PDMBLOCKTXDIR_NONE;
4069 else
4070 AssertMsgFailed(("Invalid transfer direction %d\n", pAhciReq->enmTxDir));
4071
4072 rc = pAhciPort->pDrvBlock->pfnSendCmd(pAhciPort->pDrvBlock,
4073 pAhciReq->aATAPICmd,
4074 enmBlockTxDir,
4075 pvBuf,
4076 &cbTransfer,
4077 abATAPISense,
4078 sizeof(abATAPISense),
4079 30000 /**< @todo timeout */);
4080 }
4081
4082 /* Update the LEDs and the read/write statistics. */
4083 if (cbTransfer >= 2048)
4084 {
4085 if (pAhciReq->enmTxDir != AHCITXDIR_WRITE)
4086 {
4087 pAhciPort->Led.Actual.s.fReading = 0;
4088 STAM_REL_COUNTER_ADD(&pAhciPort->StatBytesRead, cbTransfer);
4089 }
4090 else
4091 {
4092 pAhciPort->Led.Actual.s.fWriting = 0;
4093 STAM_REL_COUNTER_ADD(&pAhciPort->StatBytesWritten, cbTransfer);
4094 }
4095 }
4096
4097 if (RT_SUCCESS(rc))
4098 {
4099 /* Do post processing for certain commands. */
4100 switch (pAhciReq->aATAPICmd[0])
4101 {
4102 case SCSI_SEND_CUE_SHEET:
4103 case SCSI_READ_TOC_PMA_ATIP:
4104 {
4105 if (!pAhciPort->pTrackList)
4106 rc = ATAPIPassthroughTrackListCreateEmpty(&pAhciPort->pTrackList);
4107
4108 if (RT_SUCCESS(rc))
4109 rc = ATAPIPassthroughTrackListUpdate(pAhciPort->pTrackList, pAhciReq->aATAPICmd, pvBuf);
4110
4111 if ( RT_FAILURE(rc)
4112 && pAhciPort->cErrors++ < MAX_LOG_REL_ERRORS)
4113 LogRel(("AHCI: Error (%Rrc) while updating the tracklist during %s, burning the disc might fail\n",
4114 rc, pAhciReq->aATAPICmd[0] == SCSI_SEND_CUE_SHEET ? "SEND CUE SHEET" : "READ TOC/PMA/ATIP"));
4115 break;
4116 }
4117 case SCSI_SYNCHRONIZE_CACHE:
4118 {
4119 if (pAhciPort->pTrackList)
4120 ATAPIPassthroughTrackListClear(pAhciPort->pTrackList);
4121 break;
4122 }
4123 }
4124
4125 if (pAhciReq->enmTxDir == AHCITXDIR_READ)
4126 {
4127 Assert(cbTransfer <= pAhciReq->cbTransfer);
4128
4129 if (pAhciReq->aATAPICmd[0] == SCSI_INQUIRY)
4130 {
4131 /* Make sure that the real drive cannot be identified.
4132 * Motivation: changing the VM configuration should be as
4133 * invisible as possible to the guest. */
4134 if (cbTransfer >= 8 + 8)
4135 ataSCSIPadStr((uint8_t *)pvBuf + 8, "VBOX", 8);
4136 if (cbTransfer >= 16 + 16)
4137 ataSCSIPadStr((uint8_t *)pvBuf + 16, "CD-ROM", 16);
4138 if (cbTransfer >= 32 + 4)
4139 ataSCSIPadStr((uint8_t *)pvBuf + 32, "1.0", 4);
4140 }
4141
4142 if (cbTransfer)
4143 {
4144 Log3(("ATAPI PT data read (%d): %.*Rhxs\n", cbTransfer, cbTransfer, (uint8_t *)pvBuf));
4145
4146 /* Reply with the same amount of data as the real drive. */
4147 *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, pvBuf,
4148 cbTransfer);
4149 }
4150 else
4151 *pcbData = 0;
4152 }
4153 else
4154 *pcbData = cbTransfer;
4155 atapiCmdOK(pAhciPort, pAhciReq);
4156 }
4157 else
4158 {
4159 if (pAhciPort->cErrors < MAX_LOG_REL_ERRORS)
4160 {
4161 uint8_t u8Cmd = pAhciReq->aATAPICmd[0];
4162 do
4163 {
4164 /* don't log superfluous errors */
4165 if ( rc == VERR_DEV_IO_ERROR
4166 && ( u8Cmd == SCSI_TEST_UNIT_READY
4167 || u8Cmd == SCSI_READ_CAPACITY
4168 || u8Cmd == SCSI_READ_DVD_STRUCTURE
4169 || u8Cmd == SCSI_READ_TOC_PMA_ATIP))
4170 break;
4171 pAhciPort->cErrors++;
4172 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough cmd=%#04x sense=%d ASC=%#02x ASCQ=%#02x %Rrc\n",
4173 pAhciPort->iLUN, u8Cmd, abATAPISense[2] & 0x0f, abATAPISense[12], abATAPISense[13], rc));
4174 } while (0);
4175 }
4176 atapiCmdError(pAhciPort, pAhciReq, abATAPISense, sizeof(abATAPISense));
4177 }
4178
4179 if (pvBuf)
4180 RTMemFree(pvBuf);
4181
4182 return VINF_SUCCESS;
4183}
4184
4185/** @todo: Revise ASAP. */
4186/* Keep in sync with DevATA.cpp! */
4187static int atapiReadDVDStructureSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
4188{
4189 uint8_t aBuf[25]; /* Counted a maximum of 20 bytes but better be on the safe side. */
4190 uint8_t *buf = aBuf;
4191 int media = pAhciReq->aATAPICmd[1];
4192 int format = pAhciReq->aATAPICmd[7];
4193
4194 uint16_t max_len = RT_MIN(ataBE2H_U16(&pAhciReq->aATAPICmd[8]), sizeof(aBuf));
4195
4196 memset(buf, 0, max_len);
4197
4198 switch (format) {
4199 case 0x00:
4200 case 0x01:
4201 case 0x02:
4202 case 0x03:
4203 case 0x04:
4204 case 0x05:
4205 case 0x06:
4206 case 0x07:
4207 case 0x08:
4208 case 0x09:
4209 case 0x0a:
4210 case 0x0b:
4211 case 0x0c:
4212 case 0x0d:
4213 case 0x0e:
4214 case 0x0f:
4215 case 0x10:
4216 case 0x11:
4217 case 0x30:
4218 case 0x31:
4219 case 0xff:
4220 if (media == 0)
4221 {
4222 int uASC = SCSI_ASC_NONE;
4223
4224 switch (format)
4225 {
4226 case 0x0: /* Physical format information */
4227 {
4228 int layer = pAhciReq->aATAPICmd[6];
4229 uint64_t total_sectors;
4230
4231 if (layer != 0)
4232 {
4233 uASC = -SCSI_ASC_INV_FIELD_IN_CMD_PACKET;
4234 break;
4235 }
4236
4237 total_sectors = pAhciPort->cTotalSectors;
4238 total_sectors >>= 2;
4239 if (total_sectors == 0)
4240 {
4241 uASC = -SCSI_ASC_MEDIUM_NOT_PRESENT;
4242 break;
4243 }
4244
4245 buf[4] = 1; /* DVD-ROM, part version 1 */
4246 buf[5] = 0xf; /* 120mm disc, minimum rate unspecified */
4247 buf[6] = 1; /* one layer, read-only (per MMC-2 spec) */
4248 buf[7] = 0; /* default densities */
4249
4250 /* FIXME: 0x30000 per spec? */
4251 ataH2BE_U32(buf + 8, 0); /* start sector */
4252 ataH2BE_U32(buf + 12, total_sectors - 1); /* end sector */
4253 ataH2BE_U32(buf + 16, total_sectors - 1); /* l0 end sector */
4254
4255 /* Size of buffer, not including 2 byte size field */
4256 ataH2BE_U32(&buf[0], 2048 + 2);
4257
4258 /* 2k data + 4 byte header */
4259 uASC = (2048 + 4);
4260 break;
4261 }
4262 case 0x01: /* DVD copyright information */
4263 buf[4] = 0; /* no copyright data */
4264 buf[5] = 0; /* no region restrictions */
4265
4266 /* Size of buffer, not including 2 byte size field */
4267 ataH2BE_U16(buf, 4 + 2);
4268
4269 /* 4 byte header + 4 byte data */
4270 uASC = (4 + 4);
4271 break;
4272
4273 case 0x03: /* BCA information - invalid field for no BCA info */
4274 uASC = -SCSI_ASC_INV_FIELD_IN_CMD_PACKET;
4275 break;
4276
4277 case 0x04: /* DVD disc manufacturing information */
4278 /* Size of buffer, not including 2 byte size field */
4279 ataH2BE_U16(buf, 2048 + 2);
4280
4281 /* 2k data + 4 byte header */
4282 uASC = (2048 + 4);
4283 break;
4284 case 0xff:
4285 /*
4286 * This lists all the command capabilities above. Add new ones
4287 * in order and update the length and buffer return values.
4288 */
4289
4290 buf[4] = 0x00; /* Physical format */
4291 buf[5] = 0x40; /* Not writable, is readable */
4292 ataH2BE_U16((buf + 6), 2048 + 4);
4293
4294 buf[8] = 0x01; /* Copyright info */
4295 buf[9] = 0x40; /* Not writable, is readable */
4296 ataH2BE_U16((buf + 10), 4 + 4);
4297
4298 buf[12] = 0x03; /* BCA info */
4299 buf[13] = 0x40; /* Not writable, is readable */
4300 ataH2BE_U16((buf + 14), 188 + 4);
4301
4302 buf[16] = 0x04; /* Manufacturing info */
4303 buf[17] = 0x40; /* Not writable, is readable */
4304 ataH2BE_U16((buf + 18), 2048 + 4);
4305
4306 /* Size of buffer, not including 2 byte size field */
4307 ataH2BE_U16(buf, 16 + 2);
4308
4309 /* data written + 4 byte header */
4310 uASC = (16 + 4);
4311 break;
4312 default: /* TODO: formats beyond DVD-ROM requires */
4313 uASC = -SCSI_ASC_INV_FIELD_IN_CMD_PACKET;
4314 }
4315
4316 if (uASC < 0)
4317 {
4318 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, -uASC);
4319 return false;
4320 }
4321 break;
4322 }
4323 /* TODO: BD support, fall through for now */
4324
4325 /* Generic disk structures */
4326 case 0x80: /* TODO: AACS volume identifier */
4327 case 0x81: /* TODO: AACS media serial number */
4328 case 0x82: /* TODO: AACS media identifier */
4329 case 0x83: /* TODO: AACS media key block */
4330 case 0x90: /* TODO: List of recognized format layers */
4331 case 0xc0: /* TODO: Write protection status */
4332 default:
4333 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST,
4334 SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
4335 return false;
4336 }
4337
4338 /* Copy the buffer into the scatter gather list. */
4339 *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
4340 RT_MIN(cbData, max_len));
4341
4342 atapiCmdOK(pAhciPort, pAhciReq);
4343 return false;
4344}
4345
4346static int atapiDoTransfer(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, size_t cbMax, ATAPIFN iSourceSink)
4347{
4348 size_t cbTransfered = 0;
4349 int rcSourceSink;
4350
4351 rcSourceSink = g_apfnAtapiFuncs[iSourceSink](pAhciReq, pAhciPort, cbMax,
4352 &cbTransfered);
4353
4354 pAhciReq->cmdHdr.u32PRDBC = cbTransfered;
4355 pAhciReq->cbTransfer = cbTransfered;
4356
4357 LogFlow(("cbTransfered=%d\n", cbTransfered));
4358
4359 /* Write updated command header into memory of the guest. */
4360 PDMDevHlpPCIPhysWrite(pAhciPort->CTX_SUFF(pDevIns), pAhciReq->GCPhysCmdHdrAddr, &pAhciReq->cmdHdr, sizeof(CmdHdr));
4361
4362 return rcSourceSink;
4363}
4364
4365static DECLCALLBACK(int) atapiReadSectors2352PostProcess(PAHCIREQ pAhciReq, void **ppvProc, size_t *pcbProc)
4366{
4367 uint8_t *pbBuf = NULL;
4368 uint32_t cSectors = pAhciReq->cbTransfer / 2048;
4369 uint32_t iATAPILBA = pAhciReq->uOffset / 2048;
4370 uint8_t *pbBufDst;
4371 uint8_t *pbBufSrc = (uint8_t *)pAhciReq->u.Io.DataSeg.pvSeg;
4372 size_t cbAlloc = pAhciReq->cbTransfer + cSectors * (1 + 11 + 3 + 1 + 288); /* Per sector data like ECC. */
4373
4374 pbBuf = (uint8_t *)RTMemAlloc(cbAlloc);
4375 if (RT_UNLIKELY(!pbBuf))
4376 return VERR_NO_MEMORY;
4377
4378 pbBufDst = pbBuf;
4379
4380 for (uint32_t i = iATAPILBA; i < iATAPILBA + cSectors; i++)
4381 {
4382 /* sync bytes */
4383 *pbBufDst++ = 0x00;
4384 memset(pbBufDst, 0xff, 11);
4385 pbBufDst += 11;
4386 /* MSF */
4387 ataLBA2MSF(pbBufDst, i);
4388 pbBufDst += 3;
4389 *pbBufDst++ = 0x01; /* mode 1 data */
4390 /* data */
4391 memcpy(pbBufDst, pbBufSrc, 2048);
4392 pbBufDst += 2048;
4393 pbBufSrc += 2048;
4394 /* ECC */
4395 memset(pbBufDst, 0, 288);
4396 pbBufDst += 288;
4397 }
4398
4399 *ppvProc = pbBuf;
4400 *pcbProc = cbAlloc;
4401
4402 return VINF_SUCCESS;
4403}
4404
4405static int atapiReadSectors(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, uint32_t iATAPILBA, uint32_t cSectors, uint32_t cbSector)
4406{
4407 Log(("%s: %d sectors at LBA %d\n", __FUNCTION__, cSectors, iATAPILBA));
4408
4409 switch (cbSector)
4410 {
4411 case 2048:
4412 pAhciReq->uOffset = (uint64_t)iATAPILBA * cbSector;
4413 pAhciReq->cbTransfer = cSectors * cbSector;
4414 break;
4415 case 2352:
4416 {
4417 pAhciReq->u.Io.pfnPostProcess = atapiReadSectors2352PostProcess;
4418 pAhciReq->uOffset = (uint64_t)iATAPILBA * 2048;
4419 pAhciReq->cbTransfer = cSectors * 2048;
4420 break;
4421 }
4422 default:
4423 AssertMsgFailed(("Unsupported sectors size\n"));
4424 break;
4425 }
4426
4427 return VINF_SUCCESS;
4428}
4429
4430static AHCITXDIR atapiParseCmdVirtualATAPI(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
4431{
4432 AHCITXDIR enmTxDir = AHCITXDIR_NONE;
4433 const uint8_t *pbPacket;
4434 uint32_t cbMax;
4435
4436 pbPacket = pAhciReq->aATAPICmd;
4437
4438 ahciLog(("%s: ATAPI CMD=%#04x \"%s\"\n", __FUNCTION__, pbPacket[0], SCSICmdText(pbPacket[0])));
4439
4440 switch (pbPacket[0])
4441 {
4442 case SCSI_TEST_UNIT_READY:
4443 if (pAhciPort->cNotifiedMediaChange > 0)
4444 {
4445 if (pAhciPort->cNotifiedMediaChange-- > 2)
4446 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
4447 else
4448 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
4449 }
4450 else if (pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
4451 atapiCmdOK(pAhciPort, pAhciReq);
4452 else
4453 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
4454 break;
4455 case SCSI_GET_EVENT_STATUS_NOTIFICATION:
4456 cbMax = ataBE2H_U16(pbPacket + 7);
4457 atapiDoTransfer(pAhciPort, pAhciReq, cbMax, ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION);
4458 break;
4459 case SCSI_MODE_SENSE_10:
4460 {
4461 uint8_t uPageControl, uPageCode;
4462 cbMax = ataBE2H_U16(pbPacket + 7);
4463 uPageControl = pbPacket[2] >> 6;
4464 uPageCode = pbPacket[2] & 0x3f;
4465 switch (uPageControl)
4466 {
4467 case SCSI_PAGECONTROL_CURRENT:
4468 switch (uPageCode)
4469 {
4470 case SCSI_MODEPAGE_ERROR_RECOVERY:
4471 atapiDoTransfer(pAhciPort, pAhciReq, cbMax, ATAFN_SS_ATAPI_MODE_SENSE_ERROR_RECOVERY);
4472 break;
4473 case SCSI_MODEPAGE_CD_STATUS:
4474 atapiDoTransfer(pAhciPort, pAhciReq, cbMax, ATAFN_SS_ATAPI_MODE_SENSE_CD_STATUS);
4475 break;
4476 default:
4477 goto error_cmd;
4478 }
4479 break;
4480 case SCSI_PAGECONTROL_CHANGEABLE:
4481 goto error_cmd;
4482 case SCSI_PAGECONTROL_DEFAULT:
4483 goto error_cmd;
4484 default:
4485 case SCSI_PAGECONTROL_SAVED:
4486 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_SAVING_PARAMETERS_NOT_SUPPORTED);
4487 break;
4488 }
4489 break;
4490 }
4491 case SCSI_REQUEST_SENSE:
4492 cbMax = pbPacket[4];
4493 atapiDoTransfer(pAhciPort, pAhciReq, cbMax, ATAFN_SS_ATAPI_REQUEST_SENSE);
4494 break;
4495 case SCSI_PREVENT_ALLOW_MEDIUM_REMOVAL:
4496 if (pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
4497 {
4498 if (pbPacket[4] & 1)
4499 pAhciPort->pDrvMount->pfnLock(pAhciPort->pDrvMount);
4500 else
4501 pAhciPort->pDrvMount->pfnUnlock(pAhciPort->pDrvMount);
4502 atapiCmdOK(pAhciPort, pAhciReq);
4503 }
4504 else
4505 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
4506 break;
4507 case SCSI_READ_10:
4508 case SCSI_READ_12:
4509 {
4510 uint32_t cSectors, iATAPILBA;
4511
4512 if (pAhciPort->cNotifiedMediaChange > 0)
4513 {
4514 pAhciPort->cNotifiedMediaChange-- ;
4515 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
4516 break;
4517 }
4518 if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
4519 {
4520 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
4521 break;
4522 }
4523 if (pbPacket[0] == SCSI_READ_10)
4524 cSectors = ataBE2H_U16(pbPacket + 7);
4525 else
4526 cSectors = ataBE2H_U32(pbPacket + 6);
4527 iATAPILBA = ataBE2H_U32(pbPacket + 2);
4528 if (cSectors == 0)
4529 {
4530 atapiCmdOK(pAhciPort, pAhciReq);
4531 break;
4532 }
4533 if ((uint64_t)iATAPILBA + cSectors > pAhciPort->cTotalSectors)
4534 {
4535 /* Rate limited logging, one log line per second. For
4536 * guests that insist on reading from places outside the
4537 * valid area this often generates too many release log
4538 * entries otherwise. */
4539 static uint64_t s_uLastLogTS = 0;
4540 if (RTTimeMilliTS() >= s_uLastLogTS + 1000)
4541 {
4542 LogRel(("AHCI ATAPI: LUN#%d: CD-ROM block number %Ld invalid (READ)\n", pAhciPort->iLUN, (uint64_t)iATAPILBA + cSectors));
4543 s_uLastLogTS = RTTimeMilliTS();
4544 }
4545 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
4546 break;
4547 }
4548 atapiReadSectors(pAhciPort, pAhciReq, iATAPILBA, cSectors, 2048);
4549 enmTxDir = AHCITXDIR_READ;
4550 break;
4551 }
4552 case SCSI_READ_CD:
4553 {
4554 uint32_t cSectors, iATAPILBA;
4555
4556 if (pAhciPort->cNotifiedMediaChange > 0)
4557 {
4558 pAhciPort->cNotifiedMediaChange-- ;
4559 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
4560 break;
4561 }
4562 else if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
4563 {
4564 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
4565 break;
4566 }
4567 cSectors = (pbPacket[6] << 16) | (pbPacket[7] << 8) | pbPacket[8];
4568 iATAPILBA = ataBE2H_U32(pbPacket + 2);
4569 if (cSectors == 0)
4570 {
4571 atapiCmdOK(pAhciPort, pAhciReq);
4572 break;
4573 }
4574 if ((uint64_t)iATAPILBA + cSectors > pAhciPort->cTotalSectors)
4575 {
4576 /* Rate limited logging, one log line per second. For
4577 * guests that insist on reading from places outside the
4578 * valid area this often generates too many release log
4579 * entries otherwise. */
4580 static uint64_t s_uLastLogTS = 0;
4581 if (RTTimeMilliTS() >= s_uLastLogTS + 1000)
4582 {
4583 LogRel(("AHCI ATA: LUN#%d: CD-ROM block number %Ld invalid (READ CD)\n", pAhciPort->iLUN, (uint64_t)iATAPILBA + cSectors));
4584 s_uLastLogTS = RTTimeMilliTS();
4585 }
4586 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
4587 break;
4588 }
4589 switch (pbPacket[9] & 0xf8)
4590 {
4591 case 0x00:
4592 /* nothing */
4593 atapiCmdOK(pAhciPort, pAhciReq);
4594 break;
4595 case 0x10:
4596 /* normal read */
4597 atapiReadSectors(pAhciPort, pAhciReq, iATAPILBA, cSectors, 2048);
4598 enmTxDir = AHCITXDIR_READ;
4599 break;
4600 case 0xf8:
4601 /* read all data */
4602 atapiReadSectors(pAhciPort, pAhciReq, iATAPILBA, cSectors, 2352);
4603 enmTxDir = AHCITXDIR_READ;
4604 break;
4605 default:
4606 LogRel(("AHCI ATAPI: LUN#%d: CD-ROM sector format not supported\n", pAhciPort->iLUN));
4607 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
4608 break;
4609 }
4610 break;
4611 }
4612 case SCSI_SEEK_10:
4613 {
4614 uint32_t iATAPILBA;
4615 if (pAhciPort->cNotifiedMediaChange > 0)
4616 {
4617 pAhciPort->cNotifiedMediaChange-- ;
4618 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
4619 break;
4620 }
4621 else if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
4622 {
4623 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
4624 break;
4625 }
4626 iATAPILBA = ataBE2H_U32(pbPacket + 2);
4627 if (iATAPILBA > pAhciPort->cTotalSectors)
4628 {
4629 /* Rate limited logging, one log line per second. For
4630 * guests that insist on seeking to places outside the
4631 * valid area this often generates too many release log
4632 * entries otherwise. */
4633 static uint64_t s_uLastLogTS = 0;
4634 if (RTTimeMilliTS() >= s_uLastLogTS + 1000)
4635 {
4636 LogRel(("AHCI ATAPI: LUN#%d: CD-ROM block number %Ld invalid (SEEK)\n", pAhciPort->iLUN, (uint64_t)iATAPILBA));
4637 s_uLastLogTS = RTTimeMilliTS();
4638 }
4639 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
4640 break;
4641 }
4642 atapiCmdOK(pAhciPort, pAhciReq);
4643 pAhciReq->uATARegStatus |= ATA_STAT_SEEK; /* Linux expects this. */
4644 break;
4645 }
4646 case SCSI_START_STOP_UNIT:
4647 {
4648 int rc = VINF_SUCCESS;
4649 switch (pbPacket[4] & 3)
4650 {
4651 case 0: /* 00 - Stop motor */
4652 case 1: /* 01 - Start motor */
4653 break;
4654 case 2: /* 10 - Eject media */
4655 {
4656 /* This must be done from EMT. */
4657 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
4658 PPDMDEVINS pDevIns = pAhci->CTX_SUFF(pDevIns);
4659
4660 /*
4661 * Free the I/O memory of all cached tasks of this port
4662 * because the driver providing I/O memory allocation interface
4663 * is about to be destroyed.
4664 */
4665 ahciR3PortCachedReqsFree(pAhciPort);
4666
4667 /*
4668 * Also make sure that the current request has no memory allocated
4669 * from the driver below us. We don't require it here anyway.
4670 */
4671 ahciReqMemFree(pAhciPort, pAhciReq, true /* fForceFree */);
4672
4673 rc = VMR3ReqPriorityCallWait(PDMDevHlpGetVM(pDevIns), VMCPUID_ANY,
4674 (PFNRT)pAhciPort->pDrvMount->pfnUnmount, 3,
4675 pAhciPort->pDrvMount, false/*=fForce*/, true/*=fEject*/);
4676 Assert(RT_SUCCESS(rc) || rc == VERR_PDM_MEDIA_LOCKED || rc == VERR_PDM_MEDIA_NOT_MOUNTED);
4677 if (RT_SUCCESS(rc) && pAhci->pMediaNotify)
4678 {
4679 rc = VMR3ReqCallNoWait(PDMDevHlpGetVM(pDevIns), VMCPUID_ANY,
4680 (PFNRT)pAhci->pMediaNotify->pfnEjected, 2,
4681 pAhci->pMediaNotify, pAhciPort->iLUN);
4682 AssertRC(rc);
4683 }
4684 break;
4685 }
4686 case 3: /* 11 - Load media */
4687 /** @todo rc = s->pDrvMount->pfnLoadMedia(s->pDrvMount) */
4688 break;
4689 }
4690 if (RT_SUCCESS(rc))
4691 atapiCmdOK(pAhciPort, pAhciReq);
4692 else
4693 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIA_LOAD_OR_EJECT_FAILED);
4694 break;
4695 }
4696 case SCSI_MECHANISM_STATUS:
4697 {
4698 cbMax = ataBE2H_U16(pbPacket + 8);
4699 atapiDoTransfer(pAhciPort, pAhciReq, cbMax, ATAFN_SS_ATAPI_MECHANISM_STATUS);
4700 break;
4701 }
4702 case SCSI_READ_TOC_PMA_ATIP:
4703 {
4704 uint8_t format;
4705
4706 if (pAhciPort->cNotifiedMediaChange > 0)
4707 {
4708 pAhciPort->cNotifiedMediaChange-- ;
4709 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
4710 break;
4711 }
4712 else if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
4713 {
4714 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
4715 break;
4716 }
4717 cbMax = ataBE2H_U16(pbPacket + 7);
4718 /* SCSI MMC-3 spec says format is at offset 2 (lower 4 bits),
4719 * but Linux kernel uses offset 9 (topmost 2 bits). Hope that
4720 * the other field is clear... */
4721 format = (pbPacket[2] & 0xf) | (pbPacket[9] >> 6);
4722 switch (format)
4723 {
4724 case 0:
4725 atapiDoTransfer(pAhciPort, pAhciReq, cbMax, ATAFN_SS_ATAPI_READ_TOC_NORMAL);
4726 break;
4727 case 1:
4728 atapiDoTransfer(pAhciPort, pAhciReq, cbMax, ATAFN_SS_ATAPI_READ_TOC_MULTI);
4729 break;
4730 case 2:
4731 atapiDoTransfer(pAhciPort, pAhciReq, cbMax, ATAFN_SS_ATAPI_READ_TOC_RAW);
4732 break;
4733 default:
4734 error_cmd:
4735 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
4736 break;
4737 }
4738 break;
4739 }
4740 case SCSI_READ_CAPACITY:
4741 if (pAhciPort->cNotifiedMediaChange > 0)
4742 {
4743 pAhciPort->cNotifiedMediaChange-- ;
4744 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
4745 break;
4746 }
4747 else if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
4748 {
4749 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
4750 break;
4751 }
4752 atapiDoTransfer(pAhciPort, pAhciReq, 8 /* cbMax */, ATAFN_SS_ATAPI_READ_CAPACITY);
4753 break;
4754 case SCSI_READ_DISC_INFORMATION:
4755 if (pAhciPort->cNotifiedMediaChange > 0)
4756 {
4757 pAhciPort->cNotifiedMediaChange-- ;
4758 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
4759 break;
4760 }
4761 else if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
4762 {
4763 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
4764 break;
4765 }
4766 cbMax = ataBE2H_U16(pbPacket + 7);
4767 atapiDoTransfer(pAhciPort, pAhciReq, cbMax, ATAFN_SS_ATAPI_READ_DISC_INFORMATION);
4768 break;
4769 case SCSI_READ_TRACK_INFORMATION:
4770 if (pAhciPort->cNotifiedMediaChange > 0)
4771 {
4772 pAhciPort->cNotifiedMediaChange-- ;
4773 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
4774 break;
4775 }
4776 else if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
4777 {
4778 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
4779 break;
4780 }
4781 cbMax = ataBE2H_U16(pbPacket + 7);
4782 atapiDoTransfer(pAhciPort, pAhciReq, cbMax, ATAFN_SS_ATAPI_READ_TRACK_INFORMATION);
4783 break;
4784 case SCSI_GET_CONFIGURATION:
4785 /* No media change stuff here, it can confuse Linux guests. */
4786 cbMax = ataBE2H_U16(pbPacket + 7);
4787 atapiDoTransfer(pAhciPort, pAhciReq, cbMax, ATAFN_SS_ATAPI_GET_CONFIGURATION);
4788 break;
4789 case SCSI_INQUIRY:
4790 cbMax = pbPacket[4];
4791 atapiDoTransfer(pAhciPort, pAhciReq, cbMax, ATAFN_SS_ATAPI_INQUIRY);
4792 break;
4793 case SCSI_READ_DVD_STRUCTURE:
4794 cbMax = ataBE2H_U16(pbPacket + 8);
4795 atapiDoTransfer(pAhciPort, pAhciReq, cbMax, ATAFN_SS_ATAPI_READ_DVD_STRUCTURE);
4796 break;
4797 default:
4798 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
4799 break;
4800 }
4801
4802 return enmTxDir;
4803}
4804
4805/*
4806 * Parse ATAPI commands, passing them directly to the CD/DVD drive.
4807 */
4808static AHCITXDIR atapiParseCmdPassthrough(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
4809{
4810 const uint8_t *pbPacket;
4811 uint32_t cSectors, iATAPILBA;
4812 uint32_t cbTransfer = 0;
4813 AHCITXDIR enmTxDir = AHCITXDIR_NONE;
4814
4815 pbPacket = pAhciReq->aATAPICmd;
4816 switch (pbPacket[0])
4817 {
4818 case SCSI_BLANK:
4819 goto sendcmd;
4820 case SCSI_CLOSE_TRACK_SESSION:
4821 goto sendcmd;
4822 case SCSI_ERASE_10:
4823 iATAPILBA = ataBE2H_U32(pbPacket + 2);
4824 cbTransfer = ataBE2H_U16(pbPacket + 7);
4825 Log2(("ATAPI PT: lba %d\n", iATAPILBA));
4826 enmTxDir = AHCITXDIR_WRITE;
4827 goto sendcmd;
4828 case SCSI_FORMAT_UNIT:
4829 cbTransfer = pAhciReq->cmdFis[AHCI_CMDFIS_CYLL] | (pAhciReq->cmdFis[AHCI_CMDFIS_CYLH] << 8); /* use ATAPI transfer length */
4830 enmTxDir = AHCITXDIR_WRITE;
4831 goto sendcmd;
4832 case SCSI_GET_CONFIGURATION:
4833 cbTransfer = ataBE2H_U16(pbPacket + 7);
4834 enmTxDir = AHCITXDIR_READ;
4835 goto sendcmd;
4836 case SCSI_GET_EVENT_STATUS_NOTIFICATION:
4837 cbTransfer = ataBE2H_U16(pbPacket + 7);
4838 if (ASMAtomicReadU32(&pAhciPort->MediaEventStatus) != ATA_EVENT_STATUS_UNCHANGED)
4839 {
4840 pAhciReq->cbTransfer = RT_MIN(cbTransfer, 8);
4841 atapiDoTransfer(pAhciPort, pAhciReq, pAhciReq->cbTransfer, ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION);
4842 break;
4843 }
4844 enmTxDir = AHCITXDIR_READ;
4845 goto sendcmd;
4846 case SCSI_GET_PERFORMANCE:
4847 cbTransfer = pAhciReq->cmdFis[AHCI_CMDFIS_CYLL] | (pAhciReq->cmdFis[AHCI_CMDFIS_CYLH] << 8); /* use ATAPI transfer length */
4848 enmTxDir = AHCITXDIR_READ;
4849 goto sendcmd;
4850 case SCSI_INQUIRY:
4851 cbTransfer = ataBE2H_U16(pbPacket + 3);
4852 enmTxDir = AHCITXDIR_READ;
4853 goto sendcmd;
4854 case SCSI_LOAD_UNLOAD_MEDIUM:
4855 goto sendcmd;
4856 case SCSI_MECHANISM_STATUS:
4857 cbTransfer = ataBE2H_U16(pbPacket + 8);
4858 enmTxDir = AHCITXDIR_READ;
4859 goto sendcmd;
4860 case SCSI_MODE_SELECT_10:
4861 cbTransfer = ataBE2H_U16(pbPacket + 7);
4862 enmTxDir = AHCITXDIR_WRITE;
4863 goto sendcmd;
4864 case SCSI_MODE_SENSE_10:
4865 cbTransfer = ataBE2H_U16(pbPacket + 7);
4866 enmTxDir = AHCITXDIR_READ;
4867 goto sendcmd;
4868 case SCSI_PAUSE_RESUME:
4869 goto sendcmd;
4870 case SCSI_PLAY_AUDIO_10:
4871 goto sendcmd;
4872 case SCSI_PLAY_AUDIO_12:
4873 goto sendcmd;
4874 case SCSI_PLAY_AUDIO_MSF:
4875 goto sendcmd;
4876 case SCSI_PREVENT_ALLOW_MEDIUM_REMOVAL:
4877 /** @todo do not forget to unlock when a VM is shut down */
4878 goto sendcmd;
4879 case SCSI_READ_10:
4880 iATAPILBA = ataBE2H_U32(pbPacket + 2);
4881 cSectors = ataBE2H_U16(pbPacket + 7);
4882 Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
4883 pAhciReq->cbATAPISector = 2048; /**< @todo this size is not always correct */
4884 cbTransfer = cSectors * pAhciReq->cbATAPISector;
4885 enmTxDir = AHCITXDIR_READ;
4886 goto sendcmd;
4887 case SCSI_READ_12:
4888 iATAPILBA = ataBE2H_U32(pbPacket + 2);
4889 cSectors = ataBE2H_U32(pbPacket + 6);
4890 Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
4891 pAhciReq->cbATAPISector = 2048; /**< @todo this size is not always correct */
4892 cbTransfer = cSectors * pAhciReq->cbATAPISector;
4893 enmTxDir = AHCITXDIR_READ;
4894 goto sendcmd;
4895 case SCSI_READ_BUFFER:
4896 cbTransfer = ataBE2H_U24(pbPacket + 6);
4897 enmTxDir = AHCITXDIR_READ;
4898 goto sendcmd;
4899 case SCSI_READ_BUFFER_CAPACITY:
4900 cbTransfer = ataBE2H_U16(pbPacket + 7);
4901 enmTxDir = AHCITXDIR_READ;
4902 goto sendcmd;
4903 case SCSI_READ_CAPACITY:
4904 cbTransfer = 8;
4905 enmTxDir = AHCITXDIR_READ;
4906 goto sendcmd;
4907 case SCSI_READ_CD:
4908 case SCSI_READ_CD_MSF:
4909 {
4910 /* Get sector size based on the expected sector type field. */
4911 switch ((pbPacket[1] >> 2) & 0x7)
4912 {
4913 case 0x0: /* All types. */
4914 {
4915 uint32_t iLbaStart;
4916
4917 if (pbPacket[0] == SCSI_READ_CD)
4918 iLbaStart = ataBE2H_U32(&pbPacket[2]);
4919 else
4920 iLbaStart = ataMSF2LBA(&pbPacket[3]);
4921
4922 if (pAhciPort->pTrackList)
4923 pAhciReq->cbATAPISector = ATAPIPassthroughTrackListGetSectorSizeFromLba(pAhciPort->pTrackList, iLbaStart);
4924 else
4925 pAhciReq->cbATAPISector = 2048; /* Might be incorrect if we couldn't determine the type. */
4926 break;
4927 }
4928 case 0x1: /* CD-DA */
4929 pAhciReq->cbATAPISector = 2352;
4930 break;
4931 case 0x2: /* Mode 1 */
4932 pAhciReq->cbATAPISector = 2048;
4933 break;
4934 case 0x3: /* Mode 2 formless */
4935 pAhciReq->cbATAPISector = 2336;
4936 break;
4937 case 0x4: /* Mode 2 form 1 */
4938 pAhciReq->cbATAPISector = 2048;
4939 break;
4940 case 0x5: /* Mode 2 form 2 */
4941 pAhciReq->cbATAPISector = 2324;
4942 break;
4943 default: /* Reserved */
4944 AssertMsgFailed(("Unknown sector type\n"));
4945 pAhciReq->cbATAPISector = 0; /** @todo we should probably fail the command here already. */
4946 }
4947
4948 if (pbPacket[0] == SCSI_READ_CD)
4949 cbTransfer = ataBE2H_U24(pbPacket + 6) * pAhciReq->cbATAPISector;
4950 else /* SCSI_READ_MSF */
4951 {
4952 cSectors = ataMSF2LBA(pbPacket + 6) - ataMSF2LBA(pbPacket + 3);
4953 if (cSectors > 32)
4954 cSectors = 32; /* Limit transfer size to 64~74K. Safety first. In any case this can only harm software doing CDDA extraction. */
4955 cbTransfer = cSectors * pAhciReq->cbATAPISector;
4956 }
4957 enmTxDir = AHCITXDIR_READ;
4958 goto sendcmd;
4959 }
4960 case SCSI_READ_DISC_INFORMATION:
4961 cbTransfer = ataBE2H_U16(pbPacket + 7);
4962 enmTxDir = AHCITXDIR_READ;
4963 goto sendcmd;
4964 case SCSI_READ_DVD_STRUCTURE:
4965 cbTransfer = ataBE2H_U16(pbPacket + 8);
4966 enmTxDir = AHCITXDIR_READ;
4967 goto sendcmd;
4968 case SCSI_READ_FORMAT_CAPACITIES:
4969 cbTransfer = ataBE2H_U16(pbPacket + 7);
4970 enmTxDir = AHCITXDIR_READ;
4971 goto sendcmd;
4972 case SCSI_READ_SUBCHANNEL:
4973 cbTransfer = ataBE2H_U16(pbPacket + 7);
4974 enmTxDir = AHCITXDIR_READ;
4975 goto sendcmd;
4976 case SCSI_READ_TOC_PMA_ATIP:
4977 cbTransfer = ataBE2H_U16(pbPacket + 7);
4978 enmTxDir = AHCITXDIR_READ;
4979 goto sendcmd;
4980 case SCSI_READ_TRACK_INFORMATION:
4981 cbTransfer = ataBE2H_U16(pbPacket + 7);
4982 enmTxDir = AHCITXDIR_READ;
4983 goto sendcmd;
4984 case SCSI_REPAIR_TRACK:
4985 goto sendcmd;
4986 case SCSI_REPORT_KEY:
4987 cbTransfer = ataBE2H_U16(pbPacket + 8);
4988 enmTxDir = AHCITXDIR_READ;
4989 goto sendcmd;
4990 case SCSI_REQUEST_SENSE:
4991 cbTransfer = pbPacket[4];
4992 if ((pAhciPort->abATAPISense[2] & 0x0f) != SCSI_SENSE_NONE)
4993 {
4994 pAhciReq->cbTransfer = cbTransfer;
4995 pAhciReq->enmTxDir = AHCITXDIR_READ;
4996 atapiDoTransfer(pAhciPort, pAhciReq, cbTransfer, ATAFN_SS_ATAPI_REQUEST_SENSE);
4997 break;
4998 }
4999 enmTxDir = AHCITXDIR_READ;
5000 goto sendcmd;
5001 case SCSI_RESERVE_TRACK:
5002 goto sendcmd;
5003 case SCSI_SCAN:
5004 goto sendcmd;
5005 case SCSI_SEEK_10:
5006 goto sendcmd;
5007 case SCSI_SEND_CUE_SHEET:
5008 cbTransfer = ataBE2H_U24(pbPacket + 6);
5009 enmTxDir = AHCITXDIR_WRITE;
5010 goto sendcmd;
5011 case SCSI_SEND_DVD_STRUCTURE:
5012 cbTransfer = ataBE2H_U16(pbPacket + 8);
5013 enmTxDir = AHCITXDIR_WRITE;
5014 goto sendcmd;
5015 case SCSI_SEND_EVENT:
5016 cbTransfer = ataBE2H_U16(pbPacket + 8);
5017 enmTxDir = AHCITXDIR_WRITE;
5018 goto sendcmd;
5019 case SCSI_SEND_KEY:
5020 cbTransfer = ataBE2H_U16(pbPacket + 8);
5021 enmTxDir = AHCITXDIR_WRITE;
5022 goto sendcmd;
5023 case SCSI_SEND_OPC_INFORMATION:
5024 cbTransfer = ataBE2H_U16(pbPacket + 7);
5025 enmTxDir = AHCITXDIR_WRITE;
5026 goto sendcmd;
5027 case SCSI_SET_CD_SPEED:
5028 goto sendcmd;
5029 case SCSI_SET_READ_AHEAD:
5030 goto sendcmd;
5031 case SCSI_SET_STREAMING:
5032 cbTransfer = ataBE2H_U16(pbPacket + 9);
5033 enmTxDir = AHCITXDIR_WRITE;
5034 goto sendcmd;
5035 case SCSI_START_STOP_UNIT:
5036 goto sendcmd;
5037 case SCSI_STOP_PLAY_SCAN:
5038 goto sendcmd;
5039 case SCSI_SYNCHRONIZE_CACHE:
5040 goto sendcmd;
5041 case SCSI_TEST_UNIT_READY:
5042 goto sendcmd;
5043 case SCSI_VERIFY_10:
5044 goto sendcmd;
5045 case SCSI_WRITE_10:
5046 case SCSI_WRITE_AND_VERIFY_10:
5047 iATAPILBA = ataBE2H_U32(pbPacket + 2);
5048 cSectors = ataBE2H_U16(pbPacket + 7);
5049 Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
5050 if (pAhciPort->pTrackList)
5051 pAhciReq->cbATAPISector = ATAPIPassthroughTrackListGetSectorSizeFromLba(pAhciPort->pTrackList, iATAPILBA);
5052 else
5053 pAhciReq->cbATAPISector = 2048;
5054 cbTransfer = cSectors * pAhciReq->cbATAPISector;
5055 enmTxDir = AHCITXDIR_WRITE;
5056 goto sendcmd;
5057 case SCSI_WRITE_12:
5058 iATAPILBA = ataBE2H_U32(pbPacket + 2);
5059 cSectors = ataBE2H_U32(pbPacket + 6);
5060 Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
5061 if (pAhciPort->pTrackList)
5062 pAhciReq->cbATAPISector = ATAPIPassthroughTrackListGetSectorSizeFromLba(pAhciPort->pTrackList, iATAPILBA);
5063 else
5064 pAhciReq->cbATAPISector = 2048;
5065 cbTransfer = cSectors * pAhciReq->cbATAPISector;
5066 enmTxDir = AHCITXDIR_WRITE;
5067 goto sendcmd;
5068 case SCSI_WRITE_BUFFER:
5069 switch (pbPacket[1] & 0x1f)
5070 {
5071 case 0x04: /* download microcode */
5072 case 0x05: /* download microcode and save */
5073 case 0x06: /* download microcode with offsets */
5074 case 0x07: /* download microcode with offsets and save */
5075 case 0x0e: /* download microcode with offsets and defer activation */
5076 case 0x0f: /* activate deferred microcode */
5077 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough command attempted to update firmware, blocked\n", pAhciPort->iLUN));
5078 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
5079 break;
5080 default:
5081 cbTransfer = ataBE2H_U16(pbPacket + 6);
5082 enmTxDir = AHCITXDIR_WRITE;
5083 goto sendcmd;
5084 }
5085 break;
5086 case SCSI_REPORT_LUNS: /* Not part of MMC-3, but used by Windows. */
5087 cbTransfer = ataBE2H_U32(pbPacket + 6);
5088 enmTxDir = AHCITXDIR_READ;
5089 goto sendcmd;
5090 case SCSI_REZERO_UNIT:
5091 /* Obsolete command used by cdrecord. What else would one expect?
5092 * This command is not sent to the drive, it is handled internally,
5093 * as the Linux kernel doesn't like it (message "scsi: unknown
5094 * opcode 0x01" in syslog) and replies with a sense code of 0,
5095 * which sends cdrecord to an endless loop. */
5096 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
5097 break;
5098 default:
5099 LogRel(("AHCI: LUN#%d: passthrough unimplemented for command %#x\n", pAhciPort->iLUN, pbPacket[0]));
5100 atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
5101 break;
5102 sendcmd:
5103 /* Send a command to the drive, passing data in/out as required. */
5104 Log2(("ATAPI PT: max size %d\n", cbTransfer));
5105 if (cbTransfer == 0)
5106 enmTxDir = AHCITXDIR_NONE;
5107 pAhciReq->enmTxDir = enmTxDir;
5108 pAhciReq->cbTransfer = cbTransfer;
5109 atapiDoTransfer(pAhciPort, pAhciReq, cbTransfer, ATAFN_SS_ATAPI_PASSTHROUGH);
5110 }
5111
5112 return AHCITXDIR_NONE;
5113}
5114
5115static AHCITXDIR atapiParseCmd(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
5116{
5117 AHCITXDIR enmTxDir = AHCITXDIR_NONE;
5118 const uint8_t *pbPacket;
5119
5120 pbPacket = pAhciReq->aATAPICmd;
5121 Log(("%s: LUN#%d CMD=%#04x \"%s\"\n", __FUNCTION__, pAhciPort->iLUN, pbPacket[0], SCSICmdText(pbPacket[0])));
5122 Log2(("%s: limit=%#x packet: %.*Rhxs\n", __FUNCTION__, pAhciReq->cmdFis[AHCI_CMDFIS_CYLL] | (pAhciReq->cmdFis[AHCI_CMDFIS_CYLH] << 8), ATAPI_PACKET_SIZE, pbPacket));
5123
5124 if (pAhciPort->fATAPIPassthrough)
5125 enmTxDir = atapiParseCmdPassthrough(pAhciPort, pAhciReq);
5126 else
5127 enmTxDir = atapiParseCmdVirtualATAPI(pAhciPort, pAhciReq);
5128
5129 return enmTxDir;
5130}
5131
5132/**
5133 * Reset all values after a reset of the attached storage device.
5134 *
5135 * @returns nothing
5136 * @param pAhciPort The port the device is attached to.
5137 * @param pAhciReq The state to get the tag number from.
5138 */
5139static void ahciFinishStorageDeviceReset(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
5140{
5141 int rc;
5142
5143 /* Send a status good D2H FIS. */
5144 ASMAtomicWriteU32(&pAhciPort->MediaEventStatus, ATA_EVENT_STATUS_UNCHANGED);
5145 pAhciPort->fResetDevice = false;
5146 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
5147 ahciPostFirstD2HFisIntoMemory(pAhciPort);
5148
5149 /* As this is the first D2H FIS after the reset update the signature in the SIG register of the port. */
5150 if (pAhciPort->fATAPI)
5151 pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
5152 else
5153 pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
5154 ASMAtomicOrU32(&pAhciPort->u32TasksFinished, (1 << pAhciReq->uTag));
5155
5156 rc = ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
5157 AssertRC(rc);
5158}
5159
5160/**
5161 * Initiates a device reset caused by ATA_DEVICE_RESET (ATAPI only).
5162 *
5163 * @returns nothing.
5164 * @param pAhciPort The device to reset.
5165 * @param pAhciReq The task state.
5166 */
5167static void ahciDeviceReset(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
5168{
5169 ASMAtomicWriteBool(&pAhciPort->fResetDevice, true);
5170
5171 /*
5172 * Because this ATAPI only and ATAPI can't have
5173 * more than one command active at a time the task counter should be 0
5174 * and it is possible to finish the reset now.
5175 */
5176 Assert(ASMAtomicReadU32(&pAhciPort->cTasksActive) == 0);
5177 ahciFinishStorageDeviceReset(pAhciPort, pAhciReq);
5178}
5179
5180/**
5181 * Create a PIO setup FIS and post it into the memory area of the guest.
5182 *
5183 * @returns nothing.
5184 * @param pAhciPort The port of the SATA controller.
5185 * @param pAhciReq The state of the task.
5186 * @param pCmdFis Pointer to the command FIS from the guest.
5187 * @param fInterrupt If an interrupt should be send to the guest.
5188 */
5189static void ahciSendPioSetupFis(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, uint8_t *pCmdFis,
5190 bool fInterrupt)
5191{
5192 uint8_t abPioSetupFis[20];
5193 bool fAssertIntr = false;
5194 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
5195
5196 ahciLog(("%s: building PIO setup Fis\n", __FUNCTION__));
5197
5198 AssertMsg( pAhciReq->cbTransfer > 0
5199 && pAhciReq->cbTransfer <= 65534,
5200 ("Can't send PIO setup FIS for requests with 0 bytes to transfer or greater than 65534\n"));
5201
5202 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
5203 {
5204 memset(&abPioSetupFis[0], 0, sizeof(abPioSetupFis));
5205 abPioSetupFis[AHCI_CMDFIS_TYPE] = AHCI_CMDFIS_TYPE_PIOSETUP;
5206 abPioSetupFis[AHCI_CMDFIS_BITS] = (fInterrupt ? AHCI_CMDFIS_I : 0);
5207 if (pAhciReq->enmTxDir == AHCITXDIR_READ)
5208 abPioSetupFis[AHCI_CMDFIS_BITS] |= AHCI_CMDFIS_D;
5209 abPioSetupFis[AHCI_CMDFIS_STS] = pAhciReq->uATARegStatus;
5210 abPioSetupFis[AHCI_CMDFIS_ERR] = pAhciReq->uATARegError;
5211 abPioSetupFis[AHCI_CMDFIS_SECTN] = pCmdFis[AHCI_CMDFIS_SECTN];
5212 abPioSetupFis[AHCI_CMDFIS_CYLL] = pCmdFis[AHCI_CMDFIS_CYLL];
5213 abPioSetupFis[AHCI_CMDFIS_CYLH] = pCmdFis[AHCI_CMDFIS_CYLH];
5214 abPioSetupFis[AHCI_CMDFIS_HEAD] = pCmdFis[AHCI_CMDFIS_HEAD];
5215 abPioSetupFis[AHCI_CMDFIS_SECTNEXP] = pCmdFis[AHCI_CMDFIS_SECTNEXP];
5216 abPioSetupFis[AHCI_CMDFIS_CYLLEXP] = pCmdFis[AHCI_CMDFIS_CYLLEXP];
5217 abPioSetupFis[AHCI_CMDFIS_CYLHEXP] = pCmdFis[AHCI_CMDFIS_CYLHEXP];
5218 abPioSetupFis[AHCI_CMDFIS_SECTC] = pCmdFis[AHCI_CMDFIS_SECTC];
5219 abPioSetupFis[AHCI_CMDFIS_SECTCEXP] = pCmdFis[AHCI_CMDFIS_SECTCEXP];
5220
5221 /* Set transfer count. */
5222 abPioSetupFis[16] = (pAhciReq->cbTransfer >> 8) & 0xff;
5223 abPioSetupFis[17] = pAhciReq->cbTransfer & 0xff;
5224
5225 /* Update registers. */
5226 pAhciPort->regTFD = (pAhciReq->uATARegError << 8) | pAhciReq->uATARegStatus;
5227
5228 ahciPostFisIntoMemory(pAhciPort, AHCI_CMDFIS_TYPE_PIOSETUP, abPioSetupFis);
5229
5230 if (fInterrupt)
5231 {
5232 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_PSS);
5233 /* Check if we should assert an interrupt */
5234 if (pAhciPort->regIE & AHCI_PORT_IE_PSE)
5235 fAssertIntr = true;
5236 }
5237
5238 if (fAssertIntr)
5239 {
5240 int rc = ahciHbaSetInterrupt(pAhci, pAhciPort->iLUN, VERR_IGNORED);
5241 AssertRC(rc);
5242 }
5243 }
5244}
5245
5246/**
5247 * Build a D2H FIS and post into the memory area of the guest.
5248 *
5249 * @returns Nothing
5250 * @param pAhciPort The port of the SATA controller.
5251 * @param pAhciReq The state of the task.
5252 * @param pCmdFis Pointer to the command FIS from the guest.
5253 * @param fInterrupt If an interrupt should be send to the guest.
5254 */
5255static void ahciSendD2HFis(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, uint8_t *pCmdFis, bool fInterrupt)
5256{
5257 uint8_t d2hFis[20];
5258 bool fAssertIntr = false;
5259 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
5260
5261 ahciLog(("%s: building D2H Fis\n", __FUNCTION__));
5262
5263 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
5264 {
5265 memset(&d2hFis[0], 0, sizeof(d2hFis));
5266 d2hFis[AHCI_CMDFIS_TYPE] = AHCI_CMDFIS_TYPE_D2H;
5267 d2hFis[AHCI_CMDFIS_BITS] = (fInterrupt ? AHCI_CMDFIS_I : 0);
5268 d2hFis[AHCI_CMDFIS_STS] = pAhciReq->uATARegStatus;
5269 d2hFis[AHCI_CMDFIS_ERR] = pAhciReq->uATARegError;
5270 d2hFis[AHCI_CMDFIS_SECTN] = pCmdFis[AHCI_CMDFIS_SECTN];
5271 d2hFis[AHCI_CMDFIS_CYLL] = pCmdFis[AHCI_CMDFIS_CYLL];
5272 d2hFis[AHCI_CMDFIS_CYLH] = pCmdFis[AHCI_CMDFIS_CYLH];
5273 d2hFis[AHCI_CMDFIS_HEAD] = pCmdFis[AHCI_CMDFIS_HEAD];
5274 d2hFis[AHCI_CMDFIS_SECTNEXP] = pCmdFis[AHCI_CMDFIS_SECTNEXP];
5275 d2hFis[AHCI_CMDFIS_CYLLEXP] = pCmdFis[AHCI_CMDFIS_CYLLEXP];
5276 d2hFis[AHCI_CMDFIS_CYLHEXP] = pCmdFis[AHCI_CMDFIS_CYLHEXP];
5277 d2hFis[AHCI_CMDFIS_SECTC] = pCmdFis[AHCI_CMDFIS_SECTC];
5278 d2hFis[AHCI_CMDFIS_SECTCEXP] = pCmdFis[AHCI_CMDFIS_SECTCEXP];
5279
5280 /* Update registers. */
5281 pAhciPort->regTFD = (pAhciReq->uATARegError << 8) | pAhciReq->uATARegStatus;
5282
5283 ahciPostFisIntoMemory(pAhciPort, AHCI_CMDFIS_TYPE_D2H, d2hFis);
5284
5285 if (pAhciReq->uATARegStatus & ATA_STAT_ERR)
5286 {
5287 /* Error bit is set. */
5288 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_TFES);
5289 if (pAhciPort->regIE & AHCI_PORT_IE_TFEE)
5290 fAssertIntr = true;
5291 /*
5292 * Don't mark the command slot as completed because the guest
5293 * needs it to identify the failed command.
5294 */
5295 }
5296 else if (fInterrupt)
5297 {
5298 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_DHRS);
5299 /* Check if we should assert an interrupt */
5300 if (pAhciPort->regIE & AHCI_PORT_IE_DHRE)
5301 fAssertIntr = true;
5302
5303 /* Mark command as completed. */
5304 ASMAtomicOrU32(&pAhciPort->u32TasksFinished, (1 << pAhciReq->uTag));
5305 }
5306
5307 if (fAssertIntr)
5308 {
5309 int rc = ahciHbaSetInterrupt(pAhci, pAhciPort->iLUN, VERR_IGNORED);
5310 AssertRC(rc);
5311 }
5312 }
5313}
5314
5315/**
5316 * Build a SDB Fis and post it into the memory area of the guest.
5317 *
5318 * @returns Nothing
5319 * @param pAhciPort The port for which the SDB Fis is send.
5320 * @param uFinishedTasks Bitmask of finished tasks.
5321 * @param fInterrupt If an interrupt should be asserted.
5322 */
5323static void ahciSendSDBFis(PAHCIPort pAhciPort, uint32_t uFinishedTasks, bool fInterrupt)
5324{
5325 uint32_t sdbFis[2];
5326 bool fAssertIntr = false;
5327 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
5328 PAHCIREQ pTaskErr = ASMAtomicReadPtrT(&pAhciPort->pTaskErr, PAHCIREQ);
5329
5330 ahciLog(("%s: Building SDB FIS\n", __FUNCTION__));
5331
5332 if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
5333 {
5334 memset(&sdbFis[0], 0, sizeof(sdbFis));
5335 sdbFis[0] = AHCI_CMDFIS_TYPE_SETDEVBITS;
5336 sdbFis[0] |= (fInterrupt ? (1 << 14) : 0);
5337 if (RT_UNLIKELY(pTaskErr))
5338 {
5339 sdbFis[0] = pTaskErr->uATARegError;
5340 sdbFis[0] |= (pTaskErr->uATARegStatus & 0x77) << 16; /* Some bits are marked as reserved and thus are masked out. */
5341
5342 /* Update registers. */
5343 pAhciPort->regTFD = (pTaskErr->uATARegError << 8) | pTaskErr->uATARegStatus;
5344 }
5345 else
5346 {
5347 sdbFis[0] = 0;
5348 sdbFis[0] |= (ATA_STAT_READY | ATA_STAT_SEEK) << 16;
5349 pAhciPort->regTFD = ATA_STAT_READY | ATA_STAT_SEEK;
5350 }
5351
5352 sdbFis[1] = pAhciPort->u32QueuedTasksFinished | uFinishedTasks;
5353
5354 ahciPostFisIntoMemory(pAhciPort, AHCI_CMDFIS_TYPE_SETDEVBITS, (uint8_t *)sdbFis);
5355
5356 if (RT_UNLIKELY(pTaskErr))
5357 {
5358 /* Error bit is set. */
5359 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_TFES);
5360 if (pAhciPort->regIE & AHCI_PORT_IE_TFEE)
5361 fAssertIntr = true;
5362 }
5363
5364 if (fInterrupt)
5365 {
5366 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_SDBS);
5367 /* Check if we should assert an interrupt */
5368 if (pAhciPort->regIE & AHCI_PORT_IE_SDBE)
5369 fAssertIntr = true;
5370 }
5371
5372 ASMAtomicOrU32(&pAhciPort->u32QueuedTasksFinished, uFinishedTasks);
5373
5374 if (fAssertIntr)
5375 {
5376 int rc = ahciHbaSetInterrupt(pAhci, pAhciPort->iLUN, VERR_IGNORED);
5377 AssertRC(rc);
5378 }
5379 }
5380}
5381
5382static uint32_t ahciGetNSectors(uint8_t *pCmdFis, bool fLBA48)
5383{
5384 /* 0 means either 256 (LBA28) or 65536 (LBA48) sectors. */
5385 if (fLBA48)
5386 {
5387 if (!pCmdFis[AHCI_CMDFIS_SECTC] && !pCmdFis[AHCI_CMDFIS_SECTCEXP])
5388 return 65536;
5389 else
5390 return pCmdFis[AHCI_CMDFIS_SECTCEXP] << 8 | pCmdFis[AHCI_CMDFIS_SECTC];
5391 }
5392 else
5393 {
5394 if (!pCmdFis[AHCI_CMDFIS_SECTC])
5395 return 256;
5396 else
5397 return pCmdFis[AHCI_CMDFIS_SECTC];
5398 }
5399}
5400
5401static uint64_t ahciGetSector(PAHCIPort pAhciPort, uint8_t *pCmdFis, bool fLBA48)
5402{
5403 uint64_t iLBA;
5404 if (pCmdFis[AHCI_CMDFIS_HEAD] & 0x40)
5405 {
5406 /* any LBA variant */
5407 if (fLBA48)
5408 {
5409 /* LBA48 */
5410 iLBA = ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLHEXP] << 40) |
5411 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLLEXP] << 32) |
5412 ((uint64_t)pCmdFis[AHCI_CMDFIS_SECTNEXP] << 24) |
5413 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLH] << 16) |
5414 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLL] << 8) |
5415 pCmdFis[AHCI_CMDFIS_SECTN];
5416 }
5417 else
5418 {
5419 /* LBA */
5420 iLBA = ((pCmdFis[AHCI_CMDFIS_HEAD] & 0x0f) << 24) | (pCmdFis[AHCI_CMDFIS_CYLH] << 16) |
5421 (pCmdFis[AHCI_CMDFIS_CYLL] << 8) | pCmdFis[AHCI_CMDFIS_SECTN];
5422 }
5423 }
5424 else
5425 {
5426 /* CHS */
5427 iLBA = ((pCmdFis[AHCI_CMDFIS_CYLH] << 8) | pCmdFis[AHCI_CMDFIS_CYLL]) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors +
5428 (pCmdFis[AHCI_CMDFIS_HEAD] & 0x0f) * pAhciPort->PCHSGeometry.cSectors +
5429 (pCmdFis[AHCI_CMDFIS_SECTN] - 1);
5430 }
5431 return iLBA;
5432}
5433
5434static uint64_t ahciGetSectorQueued(uint8_t *pCmdFis)
5435{
5436 uint64_t uLBA;
5437
5438 uLBA = ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLHEXP] << 40) |
5439 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLLEXP] << 32) |
5440 ((uint64_t)pCmdFis[AHCI_CMDFIS_SECTNEXP] << 24) |
5441 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLH] << 16) |
5442 ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLL] << 8) |
5443 pCmdFis[AHCI_CMDFIS_SECTN];
5444
5445 return uLBA;
5446}
5447
5448DECLINLINE(uint32_t) ahciGetNSectorsQueued(uint8_t *pCmdFis)
5449{
5450 if (!pCmdFis[AHCI_CMDFIS_FETEXP] && !pCmdFis[AHCI_CMDFIS_FET])
5451 return 65536;
5452 else
5453 return pCmdFis[AHCI_CMDFIS_FETEXP] << 8 | pCmdFis[AHCI_CMDFIS_FET];
5454}
5455
5456DECLINLINE(uint8_t) ahciGetTagQueued(uint8_t *pCmdFis)
5457{
5458 return pCmdFis[AHCI_CMDFIS_SECTC] >> 3;
5459}
5460
5461/**
5462 * Allocates memory for the given request using already allocated memory if possible.
5463 *
5464 * @returns Pointer to the memory or NULL on failure
5465 * @param pAhciPort The AHCI port.
5466 * @param pAhciReq The request to allocate memory for.
5467 * @param cb The amount of memory to allocate.
5468 */
5469static void *ahciReqMemAlloc(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, size_t cb)
5470{
5471 if (pAhciReq->cbAlloc > cb)
5472 {
5473 pAhciReq->cAllocTooMuch++;
5474 }
5475 else if (pAhciReq->cbAlloc < cb)
5476 {
5477 if (pAhciReq->cbAlloc)
5478 pAhciPort->pDrvBlock->pfnIoBufFree(pAhciPort->pDrvBlock, pAhciReq->pvAlloc, pAhciReq->cbAlloc);
5479
5480 pAhciReq->pvAlloc = NULL;
5481 pAhciReq->cbAlloc = RT_ALIGN_Z(cb, _4K);
5482 int rc = pAhciPort->pDrvBlock->pfnIoBufAlloc(pAhciPort->pDrvBlock, pAhciReq->cbAlloc, &pAhciReq->pvAlloc);
5483 if (RT_FAILURE(rc))
5484 pAhciReq->pvAlloc = NULL;
5485
5486 pAhciReq->cAllocTooMuch = 0;
5487 if (RT_UNLIKELY(!pAhciReq->pvAlloc))
5488 pAhciReq->cbAlloc = 0;
5489 }
5490
5491 return pAhciReq->pvAlloc;
5492}
5493
5494/**
5495 * Frees memory allocated for the given request.
5496 *
5497 * @returns nothing.
5498 * @param pAhciPort The AHCI port.
5499 * @param pAhciReq The request.
5500 * @param fForceFree Flag whether to force a free
5501 */
5502static void ahciReqMemFree(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, bool fForceFree)
5503{
5504 if ( pAhciReq->cAllocTooMuch >= AHCI_MAX_ALLOC_TOO_MUCH
5505 || fForceFree)
5506 {
5507 if (pAhciReq->cbAlloc)
5508 {
5509 pAhciPort->pDrvBlock->pfnIoBufFree(pAhciPort->pDrvBlock, pAhciReq->pvAlloc, pAhciReq->cbAlloc);
5510 pAhciReq->cbAlloc = 0;
5511 pAhciReq->cAllocTooMuch = 0;
5512 }
5513 }
5514}
5515
5516/**
5517 * Copies a data buffer into the S/G buffer set up by the guest.
5518 *
5519 * @returns Amount of bytes copied to the PRDTL.
5520 * @param pDevIns Pointer to the device instance data.
5521 * @param pAhciReq AHCI request structure.
5522 * @param pvBuf The buffer to copy from.
5523 * @param cbBuf The size of the buffer.
5524 */
5525static size_t ahciCopyToPrdtl(PPDMDEVINS pDevIns, PAHCIREQ pAhciReq,
5526 void *pvBuf, size_t cbBuf)
5527{
5528 uint8_t *pbBuf = (uint8_t *)pvBuf;
5529 SGLEntry aPrdtlEntries[32];
5530 RTGCPHYS GCPhysPrdtl = pAhciReq->GCPhysPrdtl;
5531 unsigned cPrdtlEntries = pAhciReq->cPrdtlEntries;
5532 size_t cbCopied = 0;
5533
5534 AssertMsgReturn(cPrdtlEntries > 0, ("Copying 0 bytes is not possible\n"), 0);
5535
5536 do
5537 {
5538 uint32_t cPrdtlEntriesRead = cPrdtlEntries < RT_ELEMENTS(aPrdtlEntries)
5539 ? cPrdtlEntries
5540 : RT_ELEMENTS(aPrdtlEntries);
5541
5542 PDMDevHlpPhysRead(pDevIns, GCPhysPrdtl, &aPrdtlEntries[0], cPrdtlEntriesRead * sizeof(SGLEntry));
5543
5544 for (uint32_t i = 0; (i < cPrdtlEntriesRead) && cbBuf; i++)
5545 {
5546 RTGCPHYS GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(aPrdtlEntries[i].u32DBAUp, aPrdtlEntries[i].u32DBA);
5547 uint32_t cbThisCopy = (aPrdtlEntries[i].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
5548
5549 cbThisCopy = RT_MIN(cbThisCopy, cbBuf);
5550
5551 /* Copy into SG entry. */
5552 PDMDevHlpPCIPhysWrite(pDevIns, GCPhysAddrDataBase, pbBuf, cbThisCopy);
5553
5554 pbBuf += cbThisCopy;
5555 cbBuf -= cbThisCopy;
5556 cbCopied += cbThisCopy;
5557 }
5558
5559 GCPhysPrdtl += cPrdtlEntriesRead * sizeof(SGLEntry);
5560 cPrdtlEntries -= cPrdtlEntriesRead;
5561 } while (cPrdtlEntries && cbBuf);
5562
5563 if (cbCopied < cbBuf)
5564 pAhciReq->fFlags |= AHCI_REQ_OVERFLOW;
5565
5566 return cbCopied;
5567}
5568
5569/**
5570 * Copies the S/G buffer into a data buffer.
5571 *
5572 * @returns Amount of bytes copied to the PRDTL.
5573 * @param pDevIns Pointer to the device instance data.
5574 * @param pAhciReq AHCI request structure.
5575 * @param pvBuf The buffer to copy to.
5576 * @param cbBuf The size of the buffer.
5577 */
5578static size_t ahciCopyFromPrdtl(PPDMDEVINS pDevIns, PAHCIREQ pAhciReq,
5579 void *pvBuf, size_t cbBuf)
5580{
5581 uint8_t *pbBuf = (uint8_t *)pvBuf;
5582 SGLEntry aPrdtlEntries[32];
5583 RTGCPHYS GCPhysPrdtl = pAhciReq->GCPhysPrdtl;
5584 unsigned cPrdtlEntries = pAhciReq->cPrdtlEntries;
5585 size_t cbCopied = 0;
5586
5587 AssertMsgReturn(cPrdtlEntries > 0, ("Copying 0 bytes is not possible\n"), 0);
5588
5589 do
5590 {
5591 uint32_t cPrdtlEntriesRead = (cPrdtlEntries < RT_ELEMENTS(aPrdtlEntries))
5592 ? cPrdtlEntries
5593 : RT_ELEMENTS(aPrdtlEntries);
5594
5595 PDMDevHlpPhysRead(pDevIns, GCPhysPrdtl, &aPrdtlEntries[0], cPrdtlEntriesRead * sizeof(SGLEntry));
5596
5597 for (uint32_t i = 0; (i < cPrdtlEntriesRead) && cbBuf; i++)
5598 {
5599 RTGCPHYS GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(aPrdtlEntries[i].u32DBAUp, aPrdtlEntries[i].u32DBA);
5600 uint32_t cbThisCopy = (aPrdtlEntries[i].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
5601
5602 cbThisCopy = RT_MIN(cbThisCopy, cbBuf);
5603
5604 /* Copy into buffer. */
5605 PDMDevHlpPhysRead(pDevIns, GCPhysAddrDataBase, pbBuf, cbThisCopy);
5606
5607 pbBuf += cbThisCopy;
5608 cbBuf -= cbThisCopy;
5609 cbCopied += cbThisCopy;
5610 }
5611
5612 GCPhysPrdtl += cPrdtlEntriesRead * sizeof(SGLEntry);
5613 cPrdtlEntries -= cPrdtlEntriesRead;
5614 } while (cPrdtlEntries && cbBuf);
5615
5616 if (cbCopied < cbBuf)
5617 pAhciReq->fFlags |= AHCI_REQ_OVERFLOW;
5618
5619 return cbCopied;
5620}
5621
5622/**
5623 * Allocate I/O memory and copies the guest buffer for writes.
5624 *
5625 * @returns VBox status code.
5626 * @param pAhciPort The AHCI port.
5627 * @param pAhciReq The request state.
5628 * @param cbTransfer Amount of bytes to allocate.
5629 */
5630static int ahciIoBufAllocate(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, size_t cbTransfer)
5631{
5632 AssertMsg( pAhciReq->enmTxDir == AHCITXDIR_READ
5633 || pAhciReq->enmTxDir == AHCITXDIR_WRITE,
5634 ("Allocating I/O memory for a non I/O request is not allowed\n"));
5635
5636 pAhciReq->u.Io.DataSeg.pvSeg = ahciReqMemAlloc(pAhciPort, pAhciReq, cbTransfer);
5637 if (!pAhciReq->u.Io.DataSeg.pvSeg)
5638 return VERR_NO_MEMORY;
5639
5640 pAhciReq->u.Io.DataSeg.cbSeg = cbTransfer;
5641 if (pAhciReq->enmTxDir == AHCITXDIR_WRITE)
5642 {
5643 ahciCopyFromPrdtl(pAhciPort->pDevInsR3, pAhciReq,
5644 pAhciReq->u.Io.DataSeg.pvSeg,
5645 cbTransfer);
5646 }
5647 return VINF_SUCCESS;
5648}
5649
5650/**
5651 * Frees the I/O memory of the given request and updates the guest buffer if necessary.
5652 *
5653 * @returns nothing.
5654 * @param pAhciPort The AHCI port.
5655 * @param pAhciReq The request state.
5656 * @param fCopyToGuest Flag whether to update the guest buffer if necessary.
5657 * Nothing is copied if false even if the request was a read.
5658 */
5659static void ahciIoBufFree(PAHCIPort pAhciPort, PAHCIREQ pAhciReq,
5660 bool fCopyToGuest)
5661{
5662 AssertMsg( pAhciReq->enmTxDir == AHCITXDIR_READ
5663 || pAhciReq->enmTxDir == AHCITXDIR_WRITE,
5664 ("Freeing I/O memory for a non I/O request is not allowed\n"));
5665
5666 if ( pAhciReq->enmTxDir == AHCITXDIR_READ
5667 && fCopyToGuest)
5668 {
5669 if (pAhciReq->u.Io.pfnPostProcess)
5670 {
5671 void *pv = NULL;
5672 size_t cb = 0;
5673 int rc = pAhciReq->u.Io.pfnPostProcess(pAhciReq, &pv, &cb);
5674
5675 if (RT_SUCCESS(rc))
5676 {
5677 pAhciReq->cbTransfer = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, pv, cb);
5678 RTMemFree(pv);
5679 }
5680 }
5681 else
5682 ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq,
5683 pAhciReq->u.Io.DataSeg.pvSeg,
5684 pAhciReq->u.Io.DataSeg.cbSeg);
5685 }
5686
5687 ahciReqMemFree(pAhciPort, pAhciReq, false /* fForceFree */);
5688 pAhciReq->u.Io.DataSeg.pvSeg = NULL;
5689 pAhciReq->u.Io.DataSeg.cbSeg = 0;
5690}
5691
5692
5693/**
5694 * Free all cached tasks on the given port.
5695 *
5696 * @returns nothing.
5697 * @param pAhciPort The AHCI port.
5698 */
5699static void ahciR3PortCachedReqsFree(PAHCIPort pAhciPort)
5700{
5701 if (pAhciPort->pListReqsFree)
5702 {
5703 PAHCIREQ pReq = NULL;
5704 PAHCIREQ pReqNext = NULL;
5705
5706 RTCritSectEnter(&pAhciPort->CritSectReqsFree);
5707 RTListForEachSafe(pAhciPort->pListReqsFree, pReq, pReqNext, AHCIREQ, NodeList)
5708 {
5709 RTListNodeRemove(&pReq->NodeList);
5710 ahciReqMemFree(pAhciPort, pReq, true /* fForceFree */);
5711 RTMemFree(pReq);
5712 }
5713 RTCritSectLeave(&pAhciPort->CritSectReqsFree);
5714 }
5715}
5716
5717/**
5718 * Cancels all active tasks on the port.
5719 *
5720 * @returns Whether all active tasks were canceled.
5721 * @param pAhciPort The ahci port.
5722 * @param pAhciReqExcept The given request is excepted from the cancelling
5723 * (used for error page reading).
5724 */
5725static bool ahciCancelActiveTasks(PAHCIPort pAhciPort, PAHCIREQ pAhciReqExcept)
5726{
5727 for (unsigned i = 0; i < RT_ELEMENTS(pAhciPort->aActiveTasks); i++)
5728 {
5729 PAHCIREQ pAhciReq = ASMAtomicReadPtrT(&pAhciPort->aActiveTasks[i], PAHCIREQ);
5730 if (pAhciReq != pAhciReqExcept)
5731 {
5732 pAhciReq = (PAHCIREQ)ASMAtomicXchgPtr((void * volatile *)&pAhciPort->aActiveTasks[i], NULL);
5733
5734 if (VALID_PTR(pAhciReq))
5735 {
5736 bool fXchg = ASMAtomicCmpXchgU32((volatile uint32_t *)&pAhciReq->enmTxState, AHCITXSTATE_CANCELED, AHCITXSTATE_ACTIVE);
5737 if (fXchg)
5738 {
5739 /* Task is active and was canceled. */
5740 AssertReleaseMsg(ASMAtomicReadU32(&pAhciPort->cTasksActive) > 0,
5741 ("Task was canceled but none is active\n"));
5742 ASMAtomicDecU32(&pAhciPort->cTasksActive);
5743
5744 /*
5745 * Clear the pointer in the cached array. The controller will allocate a
5746 * a new task structure for this tag.
5747 */
5748 ASMAtomicWriteNullPtr(&pAhciPort->aActiveTasks[i]);
5749 LogRel(("AHCI#%uP%u: Cancelled task %u\n", pAhciPort->CTX_SUFF(pDevIns)->iInstance,
5750 pAhciPort->iLUN, pAhciReq->uTag));
5751 }
5752 else
5753 AssertMsg(pAhciReq->enmTxState == AHCITXSTATE_FREE,
5754 ("Invalid task state, must be free!\n"));
5755 }
5756 }
5757 }
5758
5759 return true; /* always true for now because tasks don't use guest memory as the buffer which makes canceling a task impossible. */
5760}
5761
5762/* -=-=-=-=- IBlockAsyncPort -=-=-=-=- */
5763
5764/** Makes a PAHCIPort out of a PPDMIBLOCKASYNCPORT. */
5765#define PDMIBLOCKASYNCPORT_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)pInterface - RT_OFFSETOF(AHCIPort, IPortAsync)) )
5766
5767static void ahciWarningDiskFull(PPDMDEVINS pDevIns)
5768{
5769 int rc;
5770 LogRel(("AHCI: Host disk full\n"));
5771 rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevAHCI_DISKFULL",
5772 N_("Host system reported disk full. VM execution is suspended. You can resume after freeing some space"));
5773 AssertRC(rc);
5774}
5775
5776static void ahciWarningFileTooBig(PPDMDEVINS pDevIns)
5777{
5778 int rc;
5779 LogRel(("AHCI: File too big\n"));
5780 rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevAHCI_FILETOOBIG",
5781 N_("Host system reported that the file size limit of the host file system has been exceeded. VM execution is suspended. You need to move your virtual hard disk to a filesystem which allows bigger files"));
5782 AssertRC(rc);
5783}
5784
5785static void ahciWarningISCSI(PPDMDEVINS pDevIns)
5786{
5787 int rc;
5788 LogRel(("AHCI: iSCSI target unavailable\n"));
5789 rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevAHCI_ISCSIDOWN",
5790 N_("The iSCSI target has stopped responding. VM execution is suspended. You can resume when it is available again"));
5791 AssertRC(rc);
5792}
5793
5794bool ahciIsRedoSetWarning(PAHCIPort pAhciPort, int rc)
5795{
5796 if (rc == VERR_DISK_FULL)
5797 {
5798 if (ASMAtomicCmpXchgBool(&pAhciPort->fRedo, true, false))
5799 ahciWarningDiskFull(pAhciPort->CTX_SUFF(pDevIns));
5800 return true;
5801 }
5802 if (rc == VERR_FILE_TOO_BIG)
5803 {
5804 if (ASMAtomicCmpXchgBool(&pAhciPort->fRedo, true, false))
5805 ahciWarningFileTooBig(pAhciPort->CTX_SUFF(pDevIns));
5806 return true;
5807 }
5808 if (rc == VERR_BROKEN_PIPE || rc == VERR_NET_CONNECTION_REFUSED)
5809 {
5810 /* iSCSI connection abort (first error) or failure to reestablish
5811 * connection (second error). Pause VM. On resume we'll retry. */
5812 if (ASMAtomicCmpXchgBool(&pAhciPort->fRedo, true, false))
5813 ahciWarningISCSI(pAhciPort->CTX_SUFF(pDevIns));
5814 return true;
5815 }
5816 if (rc == VERR_VD_DEK_MISSING)
5817 {
5818 /* Error message already set. */
5819 ASMAtomicCmpXchgBool(&pAhciPort->fRedo, true, false);
5820 return true;
5821 }
5822
5823 return false;
5824}
5825
5826/**
5827 * Creates the array of ranges to trim.
5828 *
5829 * @returns VBox status code.
5830 * @param pAhciPort AHCI port state.
5831 * @param pAhciReq The request handling the TRIM request.
5832 */
5833static int ahciTrimRangesCreate(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
5834{
5835 SGLEntry aPrdtlEntries[32];
5836 uint64_t aRanges[64];
5837 unsigned cRangesMax;
5838 unsigned cRanges = 0;
5839 uint32_t cPrdtlEntries = pAhciReq->cPrdtlEntries;
5840 RTGCPHYS GCPhysPrdtl = pAhciReq->GCPhysPrdtl;
5841 PPDMDEVINS pDevIns = pAhciPort->CTX_SUFF(pDevIns);
5842 int rc = VINF_SUCCESS;
5843
5844 LogFlowFunc(("pAhciPort=%#p pAhciReq=%#p\n", pAhciPort, pAhciReq));
5845
5846 AssertMsgReturn(pAhciReq->enmTxDir == AHCITXDIR_TRIM, ("This is not a trim request\n"), VERR_INVALID_PARAMETER);
5847
5848 /* The data buffer contains LBA range entries. Each range is 8 bytes big. */
5849 if (!pAhciReq->cmdFis[AHCI_CMDFIS_SECTC] && !pAhciReq->cmdFis[AHCI_CMDFIS_SECTCEXP])
5850 cRangesMax = 65536 * 512 / 8;
5851 else
5852 cRangesMax = pAhciReq->cmdFis[AHCI_CMDFIS_SECTC] * 512 / 8;
5853
5854 if (!cPrdtlEntries)
5855 {
5856 pAhciReq->fFlags |= AHCI_REQ_OVERFLOW;
5857 return VINF_SUCCESS;
5858 }
5859
5860 do
5861 {
5862 uint32_t cPrdtlEntriesRead = (cPrdtlEntries < RT_ELEMENTS(aPrdtlEntries))
5863 ? cPrdtlEntries
5864 : RT_ELEMENTS(aPrdtlEntries);
5865
5866 PDMDevHlpPhysRead(pDevIns, GCPhysPrdtl, &aPrdtlEntries[0], cPrdtlEntriesRead * sizeof(SGLEntry));
5867
5868 for (uint32_t i = 0; i < cPrdtlEntriesRead; i++)
5869 {
5870 RTGCPHYS GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(aPrdtlEntries[i].u32DBAUp, aPrdtlEntries[i].u32DBA);
5871 uint32_t cbThisCopy = (aPrdtlEntries[i].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
5872
5873 cbThisCopy = RT_MIN(cbThisCopy, sizeof(aRanges));
5874
5875 /* Copy into buffer. */
5876 PDMDevHlpPhysRead(pDevIns, GCPhysAddrDataBase, aRanges, cbThisCopy);
5877
5878 for (unsigned idxRange = 0; idxRange < RT_ELEMENTS(aRanges); idxRange++)
5879 {
5880 aRanges[idxRange] = RT_H2LE_U64(aRanges[idxRange]);
5881 if (AHCI_RANGE_LENGTH_GET(aRanges[idxRange]) != 0)
5882 cRanges++;
5883 else
5884 break;
5885 }
5886 }
5887
5888 GCPhysPrdtl += cPrdtlEntriesRead * sizeof(SGLEntry);
5889 cPrdtlEntries -= cPrdtlEntriesRead;
5890 } while (cPrdtlEntries);
5891
5892 if (RT_UNLIKELY(!cRanges))
5893 {
5894 return VERR_BUFFER_OVERFLOW;
5895 }
5896
5897 pAhciReq->u.Trim.cRanges = cRanges;
5898 pAhciReq->u.Trim.paRanges = (PRTRANGE)RTMemAllocZ(sizeof(RTRANGE) * cRanges);
5899 if (pAhciReq->u.Trim.paRanges)
5900 {
5901 uint32_t idxRange = 0;
5902
5903 cPrdtlEntries = pAhciReq->cPrdtlEntries;
5904 GCPhysPrdtl = pAhciReq->GCPhysPrdtl;
5905
5906 /* Convert the ranges from the guest to our format. */
5907 do
5908 {
5909 uint32_t cPrdtlEntriesRead = (cPrdtlEntries < RT_ELEMENTS(aPrdtlEntries))
5910 ? cPrdtlEntries
5911 : RT_ELEMENTS(aPrdtlEntries);
5912
5913 PDMDevHlpPhysRead(pDevIns, GCPhysPrdtl, &aPrdtlEntries[0], cPrdtlEntriesRead * sizeof(SGLEntry));
5914
5915 for (uint32_t i = 0; i < cPrdtlEntriesRead; i++)
5916 {
5917 RTGCPHYS GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(aPrdtlEntries[i].u32DBAUp, aPrdtlEntries[i].u32DBA);
5918 uint32_t cbThisCopy = (aPrdtlEntries[i].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
5919
5920 cbThisCopy = RT_MIN(cbThisCopy, sizeof(aRanges));
5921
5922 /* Copy into buffer. */
5923 PDMDevHlpPhysRead(pDevIns, GCPhysAddrDataBase, aRanges, cbThisCopy);
5924
5925 for (unsigned idxRangeSrc = 0; idxRangeSrc < RT_ELEMENTS(aRanges); idxRangeSrc++)
5926 {
5927 aRanges[idxRangeSrc] = RT_H2LE_U64(aRanges[idxRangeSrc]);
5928 if (AHCI_RANGE_LENGTH_GET(aRanges[idxRangeSrc]) != 0)
5929 {
5930 pAhciReq->u.Trim.paRanges[idxRange].offStart = (aRanges[idxRangeSrc] & AHCI_RANGE_LBA_MASK) * pAhciPort->cbSector;
5931 pAhciReq->u.Trim.paRanges[idxRange].cbRange = AHCI_RANGE_LENGTH_GET(aRanges[idxRangeSrc]) * pAhciPort->cbSector;
5932 idxRange++;
5933 }
5934 else
5935 break;
5936 }
5937 }
5938
5939 GCPhysPrdtl += cPrdtlEntriesRead * sizeof(SGLEntry);
5940 cPrdtlEntries -= cPrdtlEntriesRead;
5941 } while (idxRange < cRanges);
5942 }
5943 else
5944 rc = VERR_NO_MEMORY;
5945
5946 LogFlowFunc(("returns rc=%Rrc\n", rc));
5947 return rc;
5948}
5949
5950/**
5951 * Destroy the trim range list.
5952 *
5953 * @returns nothing.
5954 * @param pAhciReq The task state.
5955 */
5956static void ahciTrimRangesDestroy(PAHCIREQ pAhciReq)
5957{
5958 AssertReturnVoid(pAhciReq->enmTxDir == AHCITXDIR_TRIM);
5959 RTMemFree(pAhciReq->u.Trim.paRanges);
5960}
5961
5962/**
5963 * Allocates a new AHCI request.
5964 *
5965 * @returns A new AHCI request structure or NULL if out of memory.
5966 * @param pAhciPort The AHCI port.
5967 */
5968static PAHCIREQ ahciR3ReqAlloc(PAHCIPort pAhciPort)
5969{
5970 PAHCIREQ pAhciReq = NULL;
5971
5972 /* Check the global free list first. */
5973 RTCritSectEnter(&pAhciPort->CritSectReqsFree);
5974 pAhciReq = RTListGetFirst(pAhciPort->pListReqsFree, AHCIREQ, NodeList);
5975 if (pAhciReq)
5976 {
5977 AssertMsg(pAhciReq->enmTxState == AHCITXSTATE_FREE, ("Should be free!\n"));
5978 RTListNodeRemove(&pAhciReq->NodeList);
5979 }
5980 RTCritSectLeave(&pAhciPort->CritSectReqsFree);
5981
5982 if (!pAhciReq)
5983 pAhciReq = (PAHCIREQ)RTMemAllocZ(sizeof(AHCIREQ));
5984
5985 pAhciReq->enmTxState = AHCITXSTATE_ACTIVE;
5986 return pAhciReq;
5987}
5988
5989/**
5990 * Frees a given AHCI request structure.
5991 *
5992 * @returns nothing.
5993 * @param pAhciPort The AHCI port.
5994 */
5995static void ahciR3ReqFree(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
5996{
5997 AssertMsg(pAhciReq->enmTxState != AHCITXSTATE_FREE, ("Double free!\n"));
5998 pAhciReq->enmTxState = AHCITXSTATE_FREE;
5999
6000 RTCritSectEnter(&pAhciPort->CritSectReqsFree);
6001 RTListAppend(pAhciPort->pListReqsFree, &pAhciReq->NodeList);
6002 RTCritSectLeave(&pAhciPort->CritSectReqsFree);
6003}
6004
6005/**
6006 * Complete a data transfer task by freeing all occupied resources
6007 * and notifying the guest.
6008 *
6009 * @returns Flag whether the given request was canceled inbetween;
6010 *
6011 * @param pAhciPort Pointer to the port where to request completed.
6012 * @param pAhciReq Pointer to the task which finished.
6013 * @param rcReq IPRT status code of the completed request.
6014 */
6015static bool ahciTransferComplete(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, int rcReq)
6016{
6017 bool fRedo = false;
6018 bool fCanceled = false;
6019 uint64_t tsNow = RTTimeMilliTS();
6020 AHCITXSTATE enmTxState = AHCITXSTATE_INVALID;
6021
6022 LogFlowFunc(("pAhciPort=%p pAhciReq=%p rcReq=%d\n",
6023 pAhciPort, pAhciReq, rcReq));
6024
6025 enmTxState = (AHCITXSTATE)ASMAtomicReadU32((volatile uint32_t *)&pAhciReq->enmTxState);
6026 VBOXDD_AHCI_REQ_COMPLETED(pAhciReq, rcReq, enmTxState, pAhciReq->uOffset, pAhciReq->cbTransfer);
6027 VBOXDD_AHCI_REQ_COMPLETED_TIMESTAMP(pAhciReq, tsNow);
6028
6029 /*
6030 * Clear the request structure from the active request list first so it doesn't get cancelled
6031 * while we complete it. If the request is not in the active list anymore it was already canceled
6032 * and we have to make sure to not copy anything to guest memory because the guest might use it
6033 * for other things already.
6034 */
6035 bool fPortReset = ASMAtomicReadBool(&pAhciPort->fPortReset);
6036 bool fXchg = ASMAtomicCmpXchgPtr(&pAhciPort->aActiveTasks[pAhciReq->uTag], NULL, pAhciReq);
6037 bool fReqErrSaved = false;
6038
6039 /*
6040 * Leave a release log entry if the request was active for more than 25 seconds
6041 * (30 seconds is the timeout of the guest).
6042 */
6043 if (tsNow - pAhciReq->tsStart >= 25 * 1000)
6044 {
6045 const char *pcszReq = NULL;
6046
6047 switch (pAhciReq->enmTxDir)
6048 {
6049 case AHCITXDIR_READ:
6050 pcszReq = "Read";
6051 break;
6052 case AHCITXDIR_WRITE:
6053 pcszReq = "Write";
6054 break;
6055 case AHCITXDIR_FLUSH:
6056 pcszReq = "Flush";
6057 break;
6058 case AHCITXDIR_TRIM:
6059 pcszReq = "Trim";
6060 break;
6061 default:
6062 pcszReq = "<Invalid>";
6063 }
6064
6065 LogRel(("AHCI#%uP%u: %s request was active for %llu seconds\n",
6066 pAhciPort->CTX_SUFF(pDevIns)->iInstance, pAhciPort->iLUN, pcszReq, (tsNow - pAhciReq->tsStart) / 1000));
6067 }
6068
6069 if (fXchg && !fPortReset)
6070 {
6071 if (pAhciReq->enmTxDir == AHCITXDIR_READ)
6072 {
6073 ahciIoBufFree(pAhciPort, pAhciReq, true /* fCopyToGuest */);
6074 STAM_REL_COUNTER_ADD(&pAhciPort->StatBytesRead, pAhciReq->cbTransfer);
6075 pAhciPort->Led.Actual.s.fReading = 0;
6076 }
6077 else if (pAhciReq->enmTxDir == AHCITXDIR_WRITE)
6078 {
6079 ahciIoBufFree(pAhciPort, pAhciReq, false /* fCopyToGuest */);
6080 STAM_REL_COUNTER_ADD(&pAhciPort->StatBytesWritten, pAhciReq->cbTransfer);
6081 pAhciPort->Led.Actual.s.fWriting = 0;
6082 }
6083 else if (pAhciReq->enmTxDir == AHCITXDIR_TRIM)
6084 {
6085 ahciTrimRangesDestroy(pAhciReq);
6086 pAhciPort->Led.Actual.s.fWriting = 0;
6087 }
6088
6089 if (RT_FAILURE(rcReq))
6090 {
6091 /* Log the error. */
6092 if (pAhciPort->cErrors++ < MAX_LOG_REL_ERRORS)
6093 {
6094 if (pAhciReq->enmTxDir == AHCITXDIR_FLUSH)
6095 LogRel(("AHCI#%uP%u: Flush returned rc=%Rrc\n",
6096 pAhciPort->CTX_SUFF(pDevIns)->iInstance, pAhciPort->iLUN, rcReq));
6097 else if (pAhciReq->enmTxDir == AHCITXDIR_TRIM)
6098 LogRel(("AHCI#%uP%u: Trim returned rc=%Rrc\n",
6099 pAhciPort->CTX_SUFF(pDevIns)->iInstance, pAhciPort->iLUN, rcReq));
6100 else
6101 LogRel(("AHCI#%uP%u: %s at offset %llu (%u bytes left) returned rc=%Rrc\n",
6102 pAhciPort->CTX_SUFF(pDevIns)->iInstance, pAhciPort->iLUN,
6103 pAhciReq->enmTxDir == AHCITXDIR_READ
6104 ? "Read"
6105 : "Write",
6106 pAhciReq->uOffset,
6107 pAhciReq->cbTransfer, rcReq));
6108 }
6109
6110 fRedo = ahciIsRedoSetWarning(pAhciPort, rcReq);
6111 if (!fRedo)
6112 {
6113 pAhciReq->cmdHdr.u32PRDBC = 0;
6114 pAhciReq->uATARegError = ID_ERR;
6115 pAhciReq->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
6116 fReqErrSaved = ASMAtomicCmpXchgPtr(&pAhciPort->pTaskErr, pAhciReq, NULL);
6117 }
6118 else
6119 ASMAtomicOrU32(&pAhciPort->u32TasksRedo, RT_BIT_32(pAhciReq->uTag));
6120 }
6121 else
6122 {
6123 pAhciReq->cmdHdr.u32PRDBC = pAhciReq->cbTransfer;
6124
6125 /* Status will be set already for non I/O requests. */
6126 if (pAhciReq->enmTxDir != AHCITXDIR_NONE)
6127 {
6128 pAhciReq->uATARegError = 0;
6129 pAhciReq->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
6130 }
6131
6132 /* Write updated command header into memory of the guest. */
6133 PDMDevHlpPCIPhysWrite(pAhciPort->CTX_SUFF(pDevIns), pAhciReq->GCPhysCmdHdrAddr, &pAhciReq->cmdHdr, sizeof(CmdHdr));
6134
6135 if (pAhciReq->fFlags & AHCI_REQ_OVERFLOW)
6136 {
6137 /*
6138 * The guest tried to transfer more data than there is space in the buffer.
6139 * Terminate task and set the overflow bit.
6140 */
6141 /* Notify the guest. */
6142 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_OFS);
6143 if (pAhciPort->regIE & AHCI_PORT_IE_OFE)
6144 ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
6145 }
6146 }
6147
6148 if (!fRedo)
6149 {
6150
6151 /* Post a PIO setup FIS first if this is a PIO command which transfers data. */
6152 if (pAhciReq->fFlags & AHCI_REQ_PIO_DATA)
6153 ahciSendPioSetupFis(pAhciPort, pAhciReq, pAhciReq->cmdFis, false /* fInterrupt */);
6154
6155 if (pAhciReq->fFlags & AHCI_REQ_CLEAR_SACT)
6156 {
6157 if (RT_SUCCESS(rcReq) && !ASMAtomicReadPtrT(&pAhciPort->pTaskErr, PAHCIREQ))
6158 ASMAtomicOrU32(&pAhciPort->u32QueuedTasksFinished, RT_BIT_32(pAhciReq->uTag));
6159 }
6160
6161 if (pAhciReq->fFlags & AHCI_REQ_IS_QUEUED)
6162 {
6163 /*
6164 * Always raise an interrupt after task completion; delaying
6165 * this (interrupt coalescing) increases latency and has a significant
6166 * impact on performance (see @bugref{5071})
6167 */
6168 ahciSendSDBFis(pAhciPort, 0, true);
6169 }
6170 else
6171 ahciSendD2HFis(pAhciPort, pAhciReq, pAhciReq->cmdFis, true);
6172 }
6173 }
6174 else
6175 {
6176 /*
6177 * Task was canceled, do the cleanup but DO NOT access the guest memory!
6178 * The guest might use it for other things now because it doesn't know about that task anymore.
6179 */
6180 AssertMsg(pAhciReq->enmTxState == AHCITXSTATE_CANCELED || fPortReset,
6181 ("Task is not active but wasn't canceled and no port reset is active!\n"));
6182
6183 fCanceled = true;
6184
6185 if (pAhciReq->enmTxDir == AHCITXDIR_TRIM)
6186 ahciTrimRangesDestroy(pAhciReq);
6187 else if (pAhciReq->enmTxDir != AHCITXDIR_FLUSH)
6188 ahciIoBufFree(pAhciPort, pAhciReq, false /* fCopyToGuest */);
6189
6190 /* Leave a log message about the canceled request. */
6191 if (pAhciPort->cErrors++ < MAX_LOG_REL_ERRORS)
6192 {
6193 if (pAhciReq->enmTxDir == AHCITXDIR_FLUSH)
6194 LogRel(("AHCI#%uP%u: Canceled flush returned rc=%Rrc\n",
6195 pAhciPort->CTX_SUFF(pDevIns)->iInstance, pAhciPort->iLUN, rcReq));
6196 else if (pAhciReq->enmTxDir == AHCITXDIR_TRIM)
6197 LogRel(("AHCI#%uP%u: Canceled trim returned rc=%Rrc\n",
6198 pAhciPort->CTX_SUFF(pDevIns)->iInstance,pAhciPort->iLUN, rcReq));
6199 else
6200 LogRel(("AHCI#%uP%u: Canceled %s at offset %llu (%u bytes left) returned rc=%Rrc\n",
6201 pAhciPort->CTX_SUFF(pDevIns)->iInstance, pAhciPort->iLUN,
6202 pAhciReq->enmTxDir == AHCITXDIR_READ
6203 ? "read"
6204 : "write",
6205 pAhciReq->uOffset,
6206 pAhciReq->cbTransfer, rcReq));
6207 }
6208 }
6209
6210 /*
6211 * Decrement the active task counter as the last step or we might run into a
6212 * hang during power off otherwise (see @bugref{7859}).
6213 * Before it could happen that we signal PDM that we are done while we still have to
6214 * copy the data to the guest but EMT might be busy destroying the driver chains
6215 * below us while we have to delegate copying data to EMT instead of doing it
6216 * on this thread.
6217 */
6218 if (fXchg)
6219 {
6220 AssertReleaseMsg(ASMAtomicReadU32(&pAhciPort->cTasksActive) > 0,
6221 ("Inconsistent request counter\n"));
6222 ASMAtomicDecU32(&pAhciPort->cTasksActive);
6223 }
6224
6225 if (pAhciPort->cTasksActive == 0 && pAhciPort->pAhciR3->fSignalIdle)
6226 PDMDevHlpAsyncNotificationCompleted(pAhciPort->pDevInsR3);
6227
6228 /* Don't free the request yet when it is saved for the error log page. */
6229 if ( pAhciReq
6230 && !(pAhciReq->fFlags & AHCI_REQ_IS_ON_STACK)
6231 && !fReqErrSaved)
6232 ahciR3ReqFree(pAhciPort, pAhciReq);
6233 return fCanceled;
6234}
6235
6236/**
6237 * Notification callback for a completed transfer.
6238 *
6239 * @returns VBox status code.
6240 * @param pInterface Pointer to the interface.
6241 * @param pvUser User data.
6242 * @param rcReq IPRT Status code of the completed request.
6243 */
6244static DECLCALLBACK(int) ahciR3TransferCompleteNotify(PPDMIBLOCKASYNCPORT pInterface, void *pvUser, int rcReq)
6245{
6246 PAHCIPort pAhciPort = PDMIBLOCKASYNCPORT_2_PAHCIPORT(pInterface);
6247 PAHCIREQ pAhciReq = (PAHCIREQ)pvUser;
6248
6249 ahciLog(("%s: pInterface=%p pvUser=%p uTag=%u\n",
6250 __FUNCTION__, pInterface, pvUser, pAhciReq->uTag));
6251
6252 ahciTransferComplete(pAhciPort, pAhciReq, rcReq);
6253
6254 return VINF_SUCCESS;
6255}
6256
6257/**
6258 * Process an non read/write ATA command.
6259 *
6260 * @returns The direction of the data transfer
6261 * @param pCmdHdr Pointer to the command header.
6262 */
6263static AHCITXDIR ahciProcessCmd(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, uint8_t *pCmdFis)
6264{
6265 AHCITXDIR enmTxDir = AHCITXDIR_NONE;
6266 bool fLBA48 = false;
6267 CmdHdr *pCmdHdr = &pAhciReq->cmdHdr;
6268
6269 AssertMsg(pCmdFis[AHCI_CMDFIS_TYPE] == AHCI_CMDFIS_TYPE_H2D, ("FIS is not a host to device Fis!!\n"));
6270
6271 pAhciReq->cbTransfer = 0;
6272
6273 switch (pCmdFis[AHCI_CMDFIS_CMD])
6274 {
6275 case ATA_IDENTIFY_DEVICE:
6276 {
6277 if (pAhciPort->pDrvBlock && !pAhciPort->fATAPI)
6278 {
6279 uint16_t u16Temp[256];
6280 size_t cbCopied;
6281
6282 /* Fill the buffer. */
6283 ahciIdentifySS(pAhciPort, u16Temp);
6284
6285 /* Copy the buffer. */
6286 cbCopied = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq,
6287 &u16Temp[0], sizeof(u16Temp));
6288
6289 pAhciReq->fFlags |= AHCI_REQ_PIO_DATA;
6290 pAhciReq->cbTransfer = cbCopied;
6291 }
6292 else
6293 {
6294 pAhciReq->uATARegError = ABRT_ERR;
6295 pAhciReq->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK | ATA_STAT_ERR;
6296 }
6297 break;
6298 }
6299 case ATA_READ_NATIVE_MAX_ADDRESS_EXT:
6300 case ATA_READ_NATIVE_MAX_ADDRESS:
6301 break;
6302 case ATA_SET_FEATURES:
6303 {
6304 switch (pCmdFis[AHCI_CMDFIS_FET])
6305 {
6306 case 0x02: /* write cache enable */
6307 case 0xaa: /* read look-ahead enable */
6308 case 0x55: /* read look-ahead disable */
6309 case 0xcc: /* reverting to power-on defaults enable */
6310 case 0x66: /* reverting to power-on defaults disable */
6311 pAhciReq->uATARegError = 0;
6312 pAhciReq->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
6313 break;
6314 case 0x82: /* write cache disable */
6315 enmTxDir = AHCITXDIR_FLUSH;
6316 break;
6317 case 0x03:
6318 {
6319 /* set transfer mode */
6320 Log2(("%s: transfer mode %#04x\n", __FUNCTION__, pCmdFis[AHCI_CMDFIS_SECTC]));
6321 switch (pCmdFis[AHCI_CMDFIS_SECTC] & 0xf8)
6322 {
6323 case 0x00: /* PIO default */
6324 case 0x08: /* PIO mode */
6325 break;
6326 case ATA_MODE_MDMA: /* MDMA mode */
6327 pAhciPort->uATATransferMode = (pCmdFis[AHCI_CMDFIS_SECTC] & 0xf8) | RT_MIN(pCmdFis[AHCI_CMDFIS_SECTC] & 0x07, ATA_MDMA_MODE_MAX);
6328 break;
6329 case ATA_MODE_UDMA: /* UDMA mode */
6330 pAhciPort->uATATransferMode = (pCmdFis[AHCI_CMDFIS_SECTC] & 0xf8) | RT_MIN(pCmdFis[AHCI_CMDFIS_SECTC] & 0x07, ATA_UDMA_MODE_MAX);
6331 break;
6332 }
6333 break;
6334 }
6335 default:
6336 pAhciReq->uATARegError = ABRT_ERR;
6337 pAhciReq->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
6338 }
6339 break;
6340 }
6341 case ATA_DEVICE_RESET:
6342 {
6343 if (!pAhciPort->fATAPI)
6344 {
6345 pAhciReq->uATARegError = ABRT_ERR;
6346 pAhciReq->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
6347 }
6348 else
6349 {
6350 /* Reset the device. */
6351 ahciDeviceReset(pAhciPort, pAhciReq);
6352 }
6353 break;
6354 }
6355 case ATA_FLUSH_CACHE_EXT:
6356 case ATA_FLUSH_CACHE:
6357 enmTxDir = AHCITXDIR_FLUSH;
6358 break;
6359 case ATA_PACKET:
6360 if (!pAhciPort->fATAPI)
6361 {
6362 pAhciReq->uATARegError = ABRT_ERR;
6363 pAhciReq->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
6364 }
6365 else
6366 enmTxDir = atapiParseCmd(pAhciPort, pAhciReq);
6367 break;
6368 case ATA_IDENTIFY_PACKET_DEVICE:
6369 if (!pAhciPort->fATAPI)
6370 {
6371 pAhciReq->uATARegError = ABRT_ERR;
6372 pAhciReq->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
6373 }
6374 else
6375 {
6376 atapiDoTransfer(pAhciPort, pAhciReq, 512, ATAFN_SS_ATAPI_IDENTIFY);
6377
6378 pAhciReq->fFlags |= AHCI_REQ_PIO_DATA;
6379 pAhciReq->uATARegError = 0;
6380 pAhciReq->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
6381 }
6382 break;
6383 case ATA_SET_MULTIPLE_MODE:
6384 if ( pCmdFis[AHCI_CMDFIS_SECTC] != 0
6385 && ( pCmdFis[AHCI_CMDFIS_SECTC] > ATA_MAX_MULT_SECTORS
6386 || (pCmdFis[AHCI_CMDFIS_SECTC] & (pCmdFis[AHCI_CMDFIS_SECTC] - 1)) != 0))
6387 {
6388 pAhciReq->uATARegError = ABRT_ERR;
6389 pAhciReq->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
6390 }
6391 else
6392 {
6393 Log2(("%s: set multi sector count to %d\n", __FUNCTION__, pCmdFis[AHCI_CMDFIS_SECTC]));
6394 pAhciPort->cMultSectors = pCmdFis[AHCI_CMDFIS_SECTC];
6395 pAhciReq->uATARegError = 0;
6396 pAhciReq->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
6397 }
6398 break;
6399 case ATA_STANDBY_IMMEDIATE:
6400 break; /* Do nothing. */
6401 case ATA_CHECK_POWER_MODE:
6402 pAhciReq->cmdFis[AHCI_CMDFIS_SECTC] = 0xff; /* drive active or idle */
6403 /* fall through */
6404 case ATA_INITIALIZE_DEVICE_PARAMETERS:
6405 case ATA_IDLE_IMMEDIATE:
6406 case ATA_RECALIBRATE:
6407 case ATA_NOP:
6408 case ATA_READ_VERIFY_SECTORS_EXT:
6409 case ATA_READ_VERIFY_SECTORS:
6410 case ATA_READ_VERIFY_SECTORS_WITHOUT_RETRIES:
6411 case ATA_SLEEP:
6412 pAhciReq->uATARegError = 0;
6413 pAhciReq->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
6414 break;
6415 case ATA_READ_DMA_EXT:
6416 fLBA48 = true;
6417 case ATA_READ_DMA:
6418 {
6419 pAhciReq->cbTransfer = ahciGetNSectors(pCmdFis, fLBA48) * pAhciPort->cbSector;
6420 pAhciReq->uOffset = ahciGetSector(pAhciPort, pCmdFis, fLBA48) * pAhciPort->cbSector;
6421 enmTxDir = AHCITXDIR_READ;
6422 break;
6423 }
6424 case ATA_WRITE_DMA_EXT:
6425 fLBA48 = true;
6426 case ATA_WRITE_DMA:
6427 {
6428 pAhciReq->cbTransfer = ahciGetNSectors(pCmdFis, fLBA48) * pAhciPort->cbSector;
6429 pAhciReq->uOffset = ahciGetSector(pAhciPort, pCmdFis, fLBA48) * pAhciPort->cbSector;
6430 enmTxDir = AHCITXDIR_WRITE;
6431 break;
6432 }
6433 case ATA_READ_FPDMA_QUEUED:
6434 {
6435 pAhciReq->cbTransfer = ahciGetNSectorsQueued(pCmdFis) * pAhciPort->cbSector;
6436 pAhciReq->uOffset = ahciGetSectorQueued(pCmdFis) * pAhciPort->cbSector;
6437 pAhciReq->fFlags |= AHCI_REQ_IS_QUEUED;
6438 enmTxDir = AHCITXDIR_READ;
6439 break;
6440 }
6441 case ATA_WRITE_FPDMA_QUEUED:
6442 {
6443 pAhciReq->cbTransfer = ahciGetNSectorsQueued(pCmdFis) * pAhciPort->cbSector;
6444 pAhciReq->uOffset = ahciGetSectorQueued(pCmdFis) * pAhciPort->cbSector;
6445 pAhciReq->fFlags |= AHCI_REQ_IS_QUEUED;
6446 enmTxDir = AHCITXDIR_WRITE;
6447 break;
6448 }
6449 case ATA_READ_LOG_EXT:
6450 {
6451 size_t cbLogRead = ((pCmdFis[AHCI_CMDFIS_SECTCEXP] << 8) | pCmdFis[AHCI_CMDFIS_SECTC]) * 512;
6452 unsigned offLogRead = ((pCmdFis[AHCI_CMDFIS_CYLLEXP] << 8) | pCmdFis[AHCI_CMDFIS_CYLL]) * 512;
6453 unsigned iPage = pCmdFis[AHCI_CMDFIS_SECTN];
6454 size_t cbCopied;
6455
6456 LogFlow(("Trying to read %zu bytes starting at offset %u from page %u\n", cbLogRead, offLogRead, iPage));
6457
6458 uint8_t aBuf[512];
6459
6460 memset(aBuf, 0, sizeof(aBuf));
6461
6462 if (offLogRead + cbLogRead <= sizeof(aBuf))
6463 {
6464 switch (iPage)
6465 {
6466 case 0x10:
6467 {
6468 LogFlow(("Reading error page\n"));
6469 PAHCIREQ pTaskErr = ASMAtomicXchgPtrT(&pAhciPort->pTaskErr, NULL, PAHCIREQ);
6470 if (pTaskErr)
6471 {
6472 aBuf[0] = (pTaskErr->fFlags & AHCI_REQ_IS_QUEUED) ? pTaskErr->uTag : (1 << 7);
6473 aBuf[2] = pTaskErr->uATARegStatus;
6474 aBuf[3] = pTaskErr->uATARegError;
6475 aBuf[4] = pTaskErr->cmdFis[AHCI_CMDFIS_SECTN];
6476 aBuf[5] = pTaskErr->cmdFis[AHCI_CMDFIS_CYLL];
6477 aBuf[6] = pTaskErr->cmdFis[AHCI_CMDFIS_CYLH];
6478 aBuf[7] = pTaskErr->cmdFis[AHCI_CMDFIS_HEAD];
6479 aBuf[8] = pTaskErr->cmdFis[AHCI_CMDFIS_SECTNEXP];
6480 aBuf[9] = pTaskErr->cmdFis[AHCI_CMDFIS_CYLLEXP];
6481 aBuf[10] = pTaskErr->cmdFis[AHCI_CMDFIS_CYLHEXP];
6482 aBuf[12] = pTaskErr->cmdFis[AHCI_CMDFIS_SECTC];
6483 aBuf[13] = pTaskErr->cmdFis[AHCI_CMDFIS_SECTCEXP];
6484
6485 /* Calculate checksum */
6486 uint8_t uChkSum = 0;
6487 for (unsigned i = 0; i < RT_ELEMENTS(aBuf)-1; i++)
6488 uChkSum += aBuf[i];
6489
6490 aBuf[511] = (uint8_t)-(int8_t)uChkSum;
6491
6492 if (pTaskErr->enmTxDir == AHCITXDIR_TRIM)
6493 ahciTrimRangesDestroy(pTaskErr);
6494 else if (pTaskErr->enmTxDir != AHCITXDIR_FLUSH)
6495 ahciReqMemFree(pAhciPort, pTaskErr, true /* fForceFree */);
6496
6497 /* Finally free the error task state structure because it is completely unused now. */
6498 RTMemFree(pTaskErr);
6499 }
6500
6501 /*
6502 * Reading this log page results in an abort of all outstanding commands
6503 * and clearing the SActive register and TaskFile register.
6504 *
6505 * See SATA2 1.2 spec chapter 4.2.3.4
6506 */
6507 bool fAbortedAll = ahciCancelActiveTasks(pAhciPort, pAhciReq);
6508 Assert(fAbortedAll);
6509 ahciSendSDBFis(pAhciPort, 0xffffffff, true);
6510
6511 break;
6512 }
6513 }
6514
6515 /* Copy the buffer. */
6516 cbCopied = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq,
6517 &aBuf[offLogRead], cbLogRead);
6518
6519 pAhciReq->fFlags |= AHCI_REQ_PIO_DATA;
6520 pAhciReq->cbTransfer = cbCopied;
6521 }
6522
6523 break;
6524 }
6525 case ATA_DATA_SET_MANAGEMENT:
6526 {
6527 if ( ( !pAhciPort->fAsyncInterface
6528 && pAhciPort->pDrvBlock->pfnDiscard)
6529 || ( pAhciPort->fAsyncInterface
6530 && pAhciPort->pDrvBlockAsync->pfnStartDiscard))
6531 {
6532 /* Check that the trim bit is set and all other bits are 0. */
6533 if ( !(pAhciReq->cmdFis[AHCI_CMDFIS_FET] & UINT16_C(0x01))
6534 || (pAhciReq->cmdFis[AHCI_CMDFIS_FET] & ~UINT16_C(0x1)))
6535 {
6536 pAhciReq->uATARegError = ABRT_ERR;
6537 pAhciReq->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
6538 }
6539 else
6540 enmTxDir = AHCITXDIR_TRIM;
6541 break;
6542 }
6543 /* else: fall through and report error to the guest. */
6544 }
6545 /* All not implemented commands go below. */
6546 case ATA_SECURITY_FREEZE_LOCK:
6547 case ATA_SMART:
6548 case ATA_NV_CACHE:
6549 case ATA_IDLE:
6550 case ATA_TRUSTED_RECEIVE_DMA: /* Windows 8+ */
6551 pAhciReq->uATARegError = ABRT_ERR;
6552 pAhciReq->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
6553 break;
6554 default: /* For debugging purposes. */
6555 AssertMsgFailed(("Unknown command issued (%#x)\n", pCmdFis[AHCI_CMDFIS_CMD]));
6556 pAhciReq->uATARegError = ABRT_ERR;
6557 pAhciReq->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
6558 }
6559
6560 return enmTxDir;
6561}
6562
6563/**
6564 * Retrieve a command FIS from guest memory.
6565 *
6566 * @returns whether the H2D FIS was successfully read from the guest memory.
6567 * @param pAhciReq The state of the actual task.
6568 */
6569static bool ahciPortTaskGetCommandFis(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
6570{
6571 RTGCPHYS GCPhysAddrCmdTbl;
6572
6573 AssertMsgReturn(pAhciPort->GCPhysAddrClb && pAhciPort->GCPhysAddrFb,
6574 ("%s: GCPhysAddrClb and/or GCPhysAddrFb are 0\n", __FUNCTION__),
6575 false);
6576
6577 /*
6578 * First we are reading the command header pointed to by regCLB.
6579 * From this we get the address of the command table which we are reading too.
6580 * We can process the Command FIS afterwards.
6581 */
6582 pAhciReq->GCPhysCmdHdrAddr = pAhciPort->GCPhysAddrClb + pAhciReq->uTag * sizeof(CmdHdr);
6583 LogFlow(("%s: PDMDevHlpPhysRead GCPhysAddrCmdLst=%RGp cbCmdHdr=%u\n", __FUNCTION__,
6584 pAhciReq->GCPhysCmdHdrAddr, sizeof(CmdHdr)));
6585 PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), pAhciReq->GCPhysCmdHdrAddr, &pAhciReq->cmdHdr, sizeof(CmdHdr));
6586
6587#ifdef LOG_ENABLED
6588 /* Print some infos about the command header. */
6589 ahciDumpCmdHdrInfo(pAhciPort, &pAhciReq->cmdHdr);
6590#endif
6591
6592 GCPhysAddrCmdTbl = AHCI_RTGCPHYS_FROM_U32(pAhciReq->cmdHdr.u32CmdTblAddrUp, pAhciReq->cmdHdr.u32CmdTblAddr);
6593
6594 AssertMsgReturn((pAhciReq->cmdHdr.u32DescInf & AHCI_CMDHDR_CFL_MASK) * sizeof(uint32_t) == AHCI_CMDFIS_TYPE_H2D_SIZE,
6595 ("This is not a command FIS!!\n"),
6596 false);
6597
6598 /* Read the command Fis. */
6599 LogFlow(("%s: PDMDevHlpPhysRead GCPhysAddrCmdTbl=%RGp cbCmdFis=%u\n", __FUNCTION__, GCPhysAddrCmdTbl, AHCI_CMDFIS_TYPE_H2D_SIZE));
6600 PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), GCPhysAddrCmdTbl, &pAhciReq->cmdFis[0], AHCI_CMDFIS_TYPE_H2D_SIZE);
6601
6602 AssertMsgReturn(pAhciReq->cmdFis[AHCI_CMDFIS_TYPE] == AHCI_CMDFIS_TYPE_H2D,
6603 ("This is not a command FIS\n"),
6604 false);
6605
6606 /* Set transfer direction. */
6607 pAhciReq->enmTxDir = (pAhciReq->cmdHdr.u32DescInf & AHCI_CMDHDR_W) ? AHCITXDIR_WRITE : AHCITXDIR_READ;
6608
6609 /* If this is an ATAPI command read the atapi command. */
6610 if (pAhciReq->cmdHdr.u32DescInf & AHCI_CMDHDR_A)
6611 {
6612 GCPhysAddrCmdTbl += AHCI_CMDHDR_ACMD_OFFSET;
6613 PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), GCPhysAddrCmdTbl, &pAhciReq->aATAPICmd[0], ATAPI_PACKET_SIZE);
6614 }
6615
6616 /* We "received" the FIS. Clear the BSY bit in regTFD. */
6617 if ((pAhciReq->cmdHdr.u32DescInf & AHCI_CMDHDR_C) && (pAhciReq->fFlags & AHCI_REQ_CLEAR_SACT))
6618 {
6619 /*
6620 * We need to send a FIS which clears the busy bit if this is a queued command so that the guest can queue other commands.
6621 * but this FIS does not assert an interrupt
6622 */
6623 ahciSendD2HFis(pAhciPort, pAhciReq, pAhciReq->cmdFis, false);
6624 pAhciPort->regTFD &= ~AHCI_PORT_TFD_BSY;
6625 }
6626
6627 pAhciReq->GCPhysPrdtl = AHCI_RTGCPHYS_FROM_U32(pAhciReq->cmdHdr.u32CmdTblAddrUp, pAhciReq->cmdHdr.u32CmdTblAddr) + AHCI_CMDHDR_PRDT_OFFSET;
6628 pAhciReq->cPrdtlEntries = AHCI_CMDHDR_PRDTL_ENTRIES(pAhciReq->cmdHdr.u32DescInf);
6629
6630#ifdef LOG_ENABLED
6631 /* Print some infos about the FIS. */
6632 ahciDumpFisInfo(pAhciPort, &pAhciReq->cmdFis[0]);
6633
6634 /* Print the PRDT */
6635 ahciLog(("PRDT address %RGp number of entries %u\n", pAhciReq->GCPhysPrdtl, pAhciReq->cPrdtlEntries));
6636 RTGCPHYS GCPhysPrdtl = pAhciReq->GCPhysPrdtl;
6637
6638 for (unsigned i = 0; i < pAhciReq->cPrdtlEntries; i++)
6639 {
6640 SGLEntry SGEntry;
6641
6642 ahciLog(("Entry %u at address %RGp\n", i, GCPhysPrdtl));
6643 PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), GCPhysPrdtl, &SGEntry, sizeof(SGLEntry));
6644
6645 RTGCPHYS GCPhysDataAddr = AHCI_RTGCPHYS_FROM_U32(SGEntry.u32DBAUp, SGEntry.u32DBA);
6646 ahciLog(("GCPhysAddr=%RGp Size=%u\n", GCPhysDataAddr, SGEntry.u32DescInf & SGLENTRY_DESCINF_DBC));
6647
6648 GCPhysPrdtl += sizeof(SGLEntry);
6649 }
6650#endif
6651
6652 return true;
6653}
6654
6655/**
6656 * Submits a given request for execution.
6657 *
6658 * @returns Flag whether the request was canceled inbetween.
6659 * @param pAhciPort The port the request is for.
6660 * @param pAhciReq The request to submit.
6661 * @param enmTxDir The request type.
6662 */
6663static bool ahciR3ReqSubmit(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, AHCITXDIR enmTxDir)
6664{
6665 int rc = VINF_SUCCESS;
6666 bool fReqCanceled = false;
6667
6668 if (pAhciPort->fAsyncInterface)
6669 {
6670 VBOXDD_AHCI_REQ_SUBMIT(pAhciReq, pAhciReq->enmTxDir, pAhciReq->uOffset, pAhciReq->cbTransfer);
6671 VBOXDD_AHCI_REQ_SUBMIT_TIMESTAMP(pAhciReq, pAhciReq->tsStart);
6672 if (enmTxDir == AHCITXDIR_FLUSH)
6673 {
6674 rc = pAhciPort->pDrvBlockAsync->pfnStartFlush(pAhciPort->pDrvBlockAsync,
6675 pAhciReq);
6676 }
6677 else if (enmTxDir == AHCITXDIR_TRIM)
6678 {
6679 rc = ahciTrimRangesCreate(pAhciPort, pAhciReq);
6680 if (RT_SUCCESS(rc))
6681 {
6682 pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 1;
6683 rc = pAhciPort->pDrvBlockAsync->pfnStartDiscard(pAhciPort->pDrvBlockAsync, pAhciReq->u.Trim.paRanges,
6684 pAhciReq->u.Trim.cRanges, pAhciReq);
6685 }
6686 }
6687 else if (enmTxDir == AHCITXDIR_READ)
6688 {
6689 pAhciPort->Led.Asserted.s.fReading = pAhciPort->Led.Actual.s.fReading = 1;
6690 rc = pAhciPort->pDrvBlockAsync->pfnStartRead(pAhciPort->pDrvBlockAsync, pAhciReq->uOffset,
6691 &pAhciReq->u.Io.DataSeg, 1,
6692 pAhciReq->cbTransfer,
6693 pAhciReq);
6694 }
6695 else
6696 {
6697 pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 1;
6698 rc = pAhciPort->pDrvBlockAsync->pfnStartWrite(pAhciPort->pDrvBlockAsync, pAhciReq->uOffset,
6699 &pAhciReq->u.Io.DataSeg, 1,
6700 pAhciReq->cbTransfer,
6701 pAhciReq);
6702 }
6703 if (rc == VINF_VD_ASYNC_IO_FINISHED)
6704 fReqCanceled = ahciTransferComplete(pAhciPort, pAhciReq, VINF_SUCCESS);
6705 else if (RT_FAILURE(rc) && rc != VERR_VD_ASYNC_IO_IN_PROGRESS)
6706 fReqCanceled = ahciTransferComplete(pAhciPort, pAhciReq, rc);
6707 }
6708 else
6709 {
6710 if (enmTxDir == AHCITXDIR_FLUSH)
6711 rc = pAhciPort->pDrvBlock->pfnFlush(pAhciPort->pDrvBlock);
6712 else if (enmTxDir == AHCITXDIR_TRIM)
6713 {
6714 rc = ahciTrimRangesCreate(pAhciPort, pAhciReq);
6715 if (RT_SUCCESS(rc))
6716 {
6717 pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 1;
6718 rc = pAhciPort->pDrvBlock->pfnDiscard(pAhciPort->pDrvBlock, pAhciReq->u.Trim.paRanges,
6719 pAhciReq->u.Trim.cRanges);
6720 pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 0;
6721 }
6722 }
6723 else if (enmTxDir == AHCITXDIR_READ)
6724 {
6725 pAhciPort->Led.Asserted.s.fReading = pAhciPort->Led.Actual.s.fReading = 1;
6726 rc = pAhciPort->pDrvBlock->pfnRead(pAhciPort->pDrvBlock, pAhciReq->uOffset,
6727 pAhciReq->u.Io.DataSeg.pvSeg,
6728 pAhciReq->cbTransfer);
6729 pAhciPort->Led.Asserted.s.fReading = pAhciPort->Led.Actual.s.fReading = 0;
6730 }
6731 else
6732 {
6733 pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 1;
6734 rc = pAhciPort->pDrvBlock->pfnWrite(pAhciPort->pDrvBlock, pAhciReq->uOffset,
6735 pAhciReq->u.Io.DataSeg.pvSeg,
6736 pAhciReq->cbTransfer);
6737 pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 0;
6738 }
6739 fReqCanceled = ahciTransferComplete(pAhciPort, pAhciReq, rc);
6740 }
6741
6742 return fReqCanceled;
6743}
6744
6745/**
6746 * Prepares the command for execution coping it from guest memory and doing a few
6747 * validation checks on it.
6748 *
6749 * @returns Whether the command was successfully fetched from guest memory and
6750 * can be continued.
6751 * @param pAhciPort The AHCI port the request is for.
6752 * @param pAhciReq Request structure to copy the command to.
6753 */
6754static bool ahciR3CmdPrepare(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
6755{
6756 pAhciReq->tsStart = RTTimeMilliTS();
6757 pAhciReq->uATARegStatus = 0;
6758 pAhciReq->uATARegError = 0;
6759
6760 /* Set current command slot */
6761 ASMAtomicWriteU32(&pAhciPort->u32CurrentCommandSlot, pAhciReq->uTag);
6762 ASMAtomicWritePtr(&pAhciPort->aActiveTasks[pAhciReq->uTag], pAhciReq);
6763
6764 bool fContinue = ahciPortTaskGetCommandFis(pAhciPort, pAhciReq);
6765 if (fContinue)
6766 {
6767 /* Mark the task as processed by the HBA if this is a queued task so that it doesn't occur in the CI register anymore. */
6768 if (pAhciPort->regSACT & RT_BIT_32(pAhciReq->uTag))
6769 {
6770 pAhciReq->fFlags |= AHCI_REQ_CLEAR_SACT;
6771 ASMAtomicOrU32(&pAhciPort->u32TasksFinished, RT_BIT_32(pAhciReq->uTag));
6772 }
6773
6774 if (pAhciReq->cmdFis[AHCI_CMDFIS_BITS] & AHCI_CMDFIS_C)
6775 {
6776 /*
6777 * It is possible that the request counter can get one higher than the maximum because
6778 * the request counter is decremented after the guest was notified about the completed
6779 * request (see @bugref{7859}). If the completing thread is preempted in between the
6780 * guest might already issue another request before the request counter is decremented
6781 * which would trigger the following assertion incorrectly in the past.
6782 */
6783 AssertLogRelMsg(ASMAtomicReadU32(&pAhciPort->cTasksActive) <= AHCI_NR_COMMAND_SLOTS,
6784 ("AHCI#%uP%u: There are more than %u (+1) requests active",
6785 pAhciPort->CTX_SUFF(pDevIns)->iInstance, pAhciPort->iLUN,
6786 AHCI_NR_COMMAND_SLOTS));
6787 ASMAtomicIncU32(&pAhciPort->cTasksActive);
6788 }
6789 else
6790 {
6791 /* If the reset bit is set put the device into reset state. */
6792 if (pAhciReq->cmdFis[AHCI_CMDFIS_CTL] & AHCI_CMDFIS_CTL_SRST)
6793 {
6794 ahciLog(("%s: Setting device into reset state\n", __FUNCTION__));
6795 pAhciPort->fResetDevice = true;
6796 ahciSendD2HFis(pAhciPort, pAhciReq, pAhciReq->cmdFis, true);
6797 }
6798 else if (pAhciPort->fResetDevice) /* The bit is not set and we are in a reset state. */
6799 ahciFinishStorageDeviceReset(pAhciPort, pAhciReq);
6800 else /* We are not in a reset state update the control registers. */
6801 AssertMsgFailed(("%s: Update the control register\n", __FUNCTION__));
6802
6803 fContinue = false;
6804 }
6805 }
6806 else
6807 {
6808 /*
6809 * Couldn't find anything in either the AHCI or SATA spec which
6810 * indicates what should be done if the FIS is not read successfully.
6811 * The closest thing is in the state machine, stating that the device
6812 * should go into idle state again (SATA spec 1.0 chapter 8.7.1).
6813 * Do the same here and ignore any corrupt FIS types, after all
6814 * the guest messed up everything and this behavior is undefined.
6815 */
6816 fContinue = false;
6817 }
6818
6819 return fContinue;
6820}
6821
6822/**
6823 * Transmit queue consumer
6824 * Queue a new async task.
6825 *
6826 * @returns Success indicator.
6827 * If false the item will not be removed and the flushing will stop.
6828 * @param pDevIns The device instance.
6829 * @param pItem The item to consume. Upon return this item will be freed.
6830 */
6831static DECLCALLBACK(bool) ahciNotifyQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
6832{
6833 PDEVPORTNOTIFIERQUEUEITEM pNotifierItem = (PDEVPORTNOTIFIERQUEUEITEM)pItem;
6834 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
6835 PAHCIPort pAhciPort = &pThis->ahciPort[pNotifierItem->iPort];
6836 int rc = VINF_SUCCESS;
6837
6838 ahciLog(("%s: Got notification from GC\n", __FUNCTION__));
6839 /* Notify the async IO thread. */
6840 rc = SUPSemEventSignal(pThis->pSupDrvSession, pAhciPort->hEvtProcess);
6841 AssertRC(rc);
6842
6843 return true;
6844}
6845
6846/* The async IO thread for one port. */
6847static DECLCALLBACK(int) ahciAsyncIOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
6848{
6849 PAHCIPort pAhciPort = (PAHCIPort)pThread->pvUser;
6850 PAHCI pAhci = pAhciPort->CTX_SUFF(pAhci);
6851 int rc = VINF_SUCCESS;
6852 uint64_t u64StartTime = 0;
6853 uint64_t u64StopTime = 0;
6854 uint32_t uIORequestsProcessed = 0;
6855 uint32_t uIOsPerSec = 0;
6856 uint32_t fTasksToProcess = 0;
6857
6858 ahciLog(("%s: Port %d entering async IO loop.\n", __FUNCTION__, pAhciPort->iLUN));
6859
6860 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
6861 return VINF_SUCCESS;
6862
6863 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
6864 {
6865 unsigned idx = 0;
6866 uint32_t u32Tasks = 0;
6867 uint32_t u32RegHbaCtrl = 0;
6868
6869 ASMAtomicWriteBool(&pAhciPort->fWrkThreadSleeping, true);
6870 u32Tasks = ASMAtomicXchgU32(&pAhciPort->u32TasksNew, 0);
6871 if (!u32Tasks)
6872 {
6873 Assert(ASMAtomicReadBool(&pAhciPort->fWrkThreadSleeping));
6874 rc = SUPSemEventWaitNoResume(pAhci->pSupDrvSession, pAhciPort->hEvtProcess, RT_INDEFINITE_WAIT);
6875 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
6876 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
6877 break;
6878 LogFlowFunc(("Woken up with rc=%Rrc\n", rc));
6879 u32Tasks = ASMAtomicXchgU32(&pAhciPort->u32TasksNew, 0);
6880 }
6881
6882 ASMAtomicWriteBool(&pAhciPort->fWrkThreadSleeping, false);
6883 ASMAtomicIncU32(&pAhci->cThreadsActive);
6884
6885 /* Check whether the thread should be suspended. */
6886 if (pAhci->fSignalIdle)
6887 {
6888 if (!ASMAtomicDecU32(&pAhci->cThreadsActive))
6889 PDMDevHlpAsyncNotificationCompleted(pAhciPort->pDevInsR3);
6890 continue;
6891 }
6892
6893 /*
6894 * Check whether the global host controller bit is set and go to sleep immediately again
6895 * if it is set.
6896 */
6897 u32RegHbaCtrl = ASMAtomicReadU32(&pAhci->regHbaCtrl);
6898 if ( u32RegHbaCtrl & AHCI_HBA_CTRL_HR
6899 && !ASMAtomicDecU32(&pAhci->cThreadsActive))
6900 {
6901 ahciHBAReset(pAhci);
6902 if (pAhci->fSignalIdle)
6903 PDMDevHlpAsyncNotificationCompleted(pAhciPort->pDevInsR3);
6904 continue;
6905 }
6906
6907 idx = ASMBitFirstSetU32(u32Tasks);
6908 while ( idx
6909 && !pAhciPort->fPortReset)
6910 {
6911 bool fReqCanceled = false;
6912 AHCITXDIR enmTxDir;
6913 PAHCIREQ pAhciReq;
6914
6915 /* Decrement to get the slot number. */
6916 idx--;
6917 ahciLog(("%s: Processing command at slot %d\n", __FUNCTION__, idx));
6918
6919 /* Check whether the request is already active and ignore. */
6920 if (ASMAtomicReadPtr((void * volatile *)&pAhciPort->aActiveTasks[idx]))
6921 {
6922 ahciLog(("%s: Ignoring command at slot %d because it is already active\n", __FUNCTION__, idx));
6923 continue;
6924 }
6925
6926 pAhciReq = ahciR3ReqAlloc(pAhciPort);
6927 if (RT_LIKELY(pAhciReq))
6928 {
6929 pAhciReq->uTag = idx;
6930 pAhciReq->fFlags = 0;
6931
6932 bool fContinue = ahciR3CmdPrepare(pAhciPort, pAhciReq);
6933 if (fContinue)
6934 {
6935 enmTxDir = ahciProcessCmd(pAhciPort, pAhciReq, pAhciReq->cmdFis);
6936 pAhciReq->enmTxDir = enmTxDir;
6937
6938 if (enmTxDir != AHCITXDIR_NONE)
6939 {
6940 if ( enmTxDir != AHCITXDIR_FLUSH
6941 && enmTxDir != AHCITXDIR_TRIM)
6942 {
6943 STAM_REL_COUNTER_INC(&pAhciPort->StatDMA);
6944
6945 rc = ahciIoBufAllocate(pAhciPort, pAhciReq, pAhciReq->cbTransfer);
6946 if (RT_FAILURE(rc))
6947 {
6948 /* In case we can't allocate enough memory fail the request with an overflow error. */
6949 AssertMsgFailed(("%s: Failed to process command %Rrc\n", __FUNCTION__, rc));
6950 pAhciReq->fFlags |= AHCI_REQ_OVERFLOW;
6951 }
6952 }
6953
6954 if (!(pAhciReq->fFlags & AHCI_REQ_OVERFLOW))
6955 fReqCanceled = ahciR3ReqSubmit(pAhciPort, pAhciReq, enmTxDir);
6956 else /* Overflow is handled in completion routine. */
6957 fReqCanceled = ahciTransferComplete(pAhciPort, pAhciReq, VINF_SUCCESS);
6958 }
6959 else
6960 fReqCanceled = ahciTransferComplete(pAhciPort, pAhciReq, VINF_SUCCESS);
6961 } /* Command */
6962 else
6963 {
6964 ASMAtomicWriteNullPtr(&pAhciPort->aActiveTasks[pAhciReq->uTag]);
6965 ahciR3ReqFree(pAhciPort, pAhciReq);
6966 }
6967 }
6968 else /* !Request allocated, use on stack variant to signal the error. */
6969 {
6970 AHCIREQ Req;
6971 Req.uTag = idx;
6972 Req.fFlags = AHCI_REQ_IS_ON_STACK;
6973
6974 bool fContinue = ahciR3CmdPrepare(pAhciPort, &Req);
6975 if (fContinue)
6976 fReqCanceled = ahciTransferComplete(pAhciPort, &Req, VERR_NO_MEMORY);
6977 }
6978
6979 /*
6980 * Don't process other requests if the last one was canceled,
6981 * the others are not valid anymore.
6982 */
6983 if (fReqCanceled)
6984 break;
6985
6986 u32Tasks &= ~RT_BIT_32(idx); /* Clear task bit. */
6987 idx = ASMBitFirstSetU32(u32Tasks);
6988 } /* while tasks available */
6989
6990 /* Check whether a port reset was active. */
6991 if ( ASMAtomicReadBool(&pAhciPort->fPortReset)
6992 && (pAhciPort->regSCTL & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_NINIT)
6993 ahciPortResetFinish(pAhciPort);
6994
6995 /*
6996 * Check whether a host controller reset is pending and execute the reset
6997 * if this is the last active thread.
6998 */
6999 u32RegHbaCtrl = ASMAtomicReadU32(&pAhci->regHbaCtrl);
7000 uint32_t cThreadsActive = ASMAtomicDecU32(&pAhci->cThreadsActive);
7001 if ( (u32RegHbaCtrl & AHCI_HBA_CTRL_HR)
7002 && !cThreadsActive)
7003 ahciHBAReset(pAhci);
7004
7005 if (!cThreadsActive && pAhci->fSignalIdle)
7006 PDMDevHlpAsyncNotificationCompleted(pAhciPort->pDevInsR3);
7007 } /* While running */
7008
7009 ahciLog(("%s: Port %d async IO thread exiting\n", __FUNCTION__, pAhciPort->iLUN));
7010 return VINF_SUCCESS;
7011}
7012
7013/**
7014 * Unblock the async I/O thread so it can respond to a state change.
7015 *
7016 * @returns VBox status code.
7017 * @param pDevIns The device instance.
7018 * @param pThread The send thread.
7019 */
7020static DECLCALLBACK(int) ahciAsyncIOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
7021{
7022 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
7023 PAHCIPort pAhciPort = (PAHCIPort)pThread->pvUser;
7024 return SUPSemEventSignal(pThis->pSupDrvSession, pAhciPort->hEvtProcess);
7025}
7026
7027/* -=-=-=-=- DBGF -=-=-=-=- */
7028
7029/**
7030 * AHCI status info callback.
7031 *
7032 * @param pDevIns The device instance.
7033 * @param pHlp The output helpers.
7034 * @param pszArgs The arguments.
7035 */
7036static DECLCALLBACK(void) ahciR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
7037{
7038 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
7039
7040 /*
7041 * Show info.
7042 */
7043 pHlp->pfnPrintf(pHlp,
7044 "%s#%d: mmio=%RGp ports=%u GC=%RTbool R0=%RTbool\n",
7045 pDevIns->pReg->szName,
7046 pDevIns->iInstance,
7047 pThis->MMIOBase,
7048 pThis->cPortsImpl,
7049 pThis->fGCEnabled ? true : false,
7050 pThis->fR0Enabled ? true : false);
7051
7052 /*
7053 * Show global registers.
7054 */
7055 pHlp->pfnPrintf(pHlp, "HbaCap=%#x\n", pThis->regHbaCap);
7056 pHlp->pfnPrintf(pHlp, "HbaCtrl=%#x\n", pThis->regHbaCtrl);
7057 pHlp->pfnPrintf(pHlp, "HbaIs=%#x\n", pThis->regHbaIs);
7058 pHlp->pfnPrintf(pHlp, "HbaPi=%#x", pThis->regHbaPi);
7059 pHlp->pfnPrintf(pHlp, "HbaVs=%#x\n", pThis->regHbaVs);
7060 pHlp->pfnPrintf(pHlp, "HbaCccCtl=%#x\n", pThis->regHbaCccCtl);
7061 pHlp->pfnPrintf(pHlp, "HbaCccPorts=%#x\n", pThis->regHbaCccPorts);
7062 pHlp->pfnPrintf(pHlp, "PortsInterrupted=%#x\n", pThis->u32PortsInterrupted);
7063
7064 /*
7065 * Per port data.
7066 */
7067 for (unsigned i = 0; i < pThis->cPortsImpl; i++)
7068 {
7069 PAHCIPort pThisPort = &pThis->ahciPort[i];
7070
7071 pHlp->pfnPrintf(pHlp, "Port %d: async=%RTbool device-attached=%RTbool\n",
7072 pThisPort->iLUN, pThisPort->fAsyncInterface, pThisPort->pDrvBase != NULL);
7073 pHlp->pfnPrintf(pHlp, "PortClb=%#x\n", pThisPort->regCLB);
7074 pHlp->pfnPrintf(pHlp, "PortClbU=%#x\n", pThisPort->regCLBU);
7075 pHlp->pfnPrintf(pHlp, "PortFb=%#x\n", pThisPort->regFB);
7076 pHlp->pfnPrintf(pHlp, "PortFbU=%#x\n", pThisPort->regFBU);
7077 pHlp->pfnPrintf(pHlp, "PortIs=%#x\n", pThisPort->regIS);
7078 pHlp->pfnPrintf(pHlp, "PortIe=%#x\n", pThisPort->regIE);
7079 pHlp->pfnPrintf(pHlp, "PortCmd=%#x\n", pThisPort->regCMD);
7080 pHlp->pfnPrintf(pHlp, "PortTfd=%#x\n", pThisPort->regTFD);
7081 pHlp->pfnPrintf(pHlp, "PortSig=%#x\n", pThisPort->regSIG);
7082 pHlp->pfnPrintf(pHlp, "PortSSts=%#x\n", pThisPort->regSSTS);
7083 pHlp->pfnPrintf(pHlp, "PortSCtl=%#x\n", pThisPort->regSCTL);
7084 pHlp->pfnPrintf(pHlp, "PortSErr=%#x\n", pThisPort->regSERR);
7085 pHlp->pfnPrintf(pHlp, "PortSAct=%#x\n", pThisPort->regSACT);
7086 pHlp->pfnPrintf(pHlp, "PortCi=%#x\n", pThisPort->regCI);
7087 pHlp->pfnPrintf(pHlp, "PortPhysClb=%RGp\n", pThisPort->GCPhysAddrClb);
7088 pHlp->pfnPrintf(pHlp, "PortPhysFb=%RGp\n", pThisPort->GCPhysAddrFb);
7089 pHlp->pfnPrintf(pHlp, "PortActTasksActive=%u\n", pThisPort->cTasksActive);
7090 pHlp->pfnPrintf(pHlp, "PortPoweredOn=%RTbool\n", pThisPort->fPoweredOn);
7091 pHlp->pfnPrintf(pHlp, "PortSpunUp=%RTbool\n", pThisPort->fSpunUp);
7092 pHlp->pfnPrintf(pHlp, "PortFirstD2HFisSend=%RTbool\n", pThisPort->fFirstD2HFisSend);
7093 pHlp->pfnPrintf(pHlp, "PortATAPI=%RTbool\n", pThisPort->fATAPI);
7094 pHlp->pfnPrintf(pHlp, "PortTasksFinished=%#x\n", pThisPort->u32TasksFinished);
7095 pHlp->pfnPrintf(pHlp, "PortQueuedTasksFinished=%#x\n", pThisPort->u32QueuedTasksFinished);
7096 pHlp->pfnPrintf(pHlp, "PortTasksNew=%#x\n", pThisPort->u32TasksNew);
7097 pHlp->pfnPrintf(pHlp, "\n");
7098 }
7099}
7100
7101/* -=-=-=-=- Helper -=-=-=-=- */
7102
7103/**
7104 * Checks if all asynchronous I/O is finished, both AHCI and IDE.
7105 *
7106 * Used by ahciR3Reset, ahciR3Suspend and ahciR3PowerOff. ahciR3SavePrep makes
7107 * use of it in strict builds (which is why it's up here).
7108 *
7109 * @returns true if quiesced, false if busy.
7110 * @param pDevIns The device instance.
7111 */
7112static bool ahciR3AllAsyncIOIsFinished(PPDMDEVINS pDevIns)
7113{
7114 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
7115
7116 if (pThis->cThreadsActive)
7117 return false;
7118
7119 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->ahciPort); i++)
7120 {
7121 PAHCIPort pThisPort = &pThis->ahciPort[i];
7122 if (pThisPort->pDrvBase)
7123 {
7124 if ( (pThisPort->cTasksActive != 0)
7125 || (pThisPort->u32TasksNew != 0))
7126 return false;
7127 }
7128 }
7129 return true;
7130}
7131
7132/* -=-=-=-=- Saved State -=-=-=-=- */
7133
7134/**
7135 * @callback_method_impl{FNSSMDEVSAVEPREP}
7136 */
7137static DECLCALLBACK(int) ahciR3SavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7138{
7139 Assert(ahciR3AllAsyncIOIsFinished(pDevIns));
7140 return VINF_SUCCESS;
7141}
7142
7143/**
7144 * @callback_method_impl{FNSSMDEVLOADPREP}
7145 */
7146static DECLCALLBACK(int) ahciR3LoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7147{
7148 Assert(ahciR3AllAsyncIOIsFinished(pDevIns));
7149 return VINF_SUCCESS;
7150}
7151
7152/**
7153 * @callback_method_impl{FNSSMDEVLIVEEXEC}
7154 */
7155static DECLCALLBACK(int) ahciR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
7156{
7157 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
7158
7159 /* config. */
7160 SSMR3PutU32(pSSM, pThis->cPortsImpl);
7161 for (uint32_t i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
7162 {
7163 SSMR3PutBool(pSSM, pThis->ahciPort[i].pDrvBase != NULL);
7164 SSMR3PutBool(pSSM, pThis->ahciPort[i].fHotpluggable);
7165 SSMR3PutStrZ(pSSM, pThis->ahciPort[i].szSerialNumber);
7166 SSMR3PutStrZ(pSSM, pThis->ahciPort[i].szFirmwareRevision);
7167 SSMR3PutStrZ(pSSM, pThis->ahciPort[i].szModelNumber);
7168 }
7169
7170 static const char *s_apszIdeEmuPortNames[4] = { "PrimaryMaster", "PrimarySlave", "SecondaryMaster", "SecondarySlave" };
7171 for (size_t i = 0; i < RT_ELEMENTS(s_apszIdeEmuPortNames); i++)
7172 {
7173 uint32_t iPort;
7174 int rc = CFGMR3QueryU32Def(pDevIns->pCfg, s_apszIdeEmuPortNames[i], &iPort, i);
7175 AssertRCReturn(rc, rc);
7176 SSMR3PutU32(pSSM, iPort);
7177 }
7178
7179 return VINF_SSM_DONT_CALL_AGAIN;
7180}
7181
7182/**
7183 * @callback_method_impl{FNSSMDEVSAVEEXEC}
7184 */
7185static DECLCALLBACK(int) ahciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7186{
7187 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
7188 uint32_t i;
7189 int rc;
7190
7191 Assert(!pThis->f8ByteMMIO4BytesWrittenSuccessfully);
7192
7193 /* The config */
7194 rc = ahciR3LiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
7195 AssertRCReturn(rc, rc);
7196
7197 /* The main device structure. */
7198 SSMR3PutU32(pSSM, pThis->regHbaCap);
7199 SSMR3PutU32(pSSM, pThis->regHbaCtrl);
7200 SSMR3PutU32(pSSM, pThis->regHbaIs);
7201 SSMR3PutU32(pSSM, pThis->regHbaPi);
7202 SSMR3PutU32(pSSM, pThis->regHbaVs);
7203 SSMR3PutU32(pSSM, pThis->regHbaCccCtl);
7204 SSMR3PutU32(pSSM, pThis->regHbaCccPorts);
7205 SSMR3PutU8(pSSM, pThis->uCccPortNr);
7206 SSMR3PutU64(pSSM, pThis->uCccTimeout);
7207 SSMR3PutU32(pSSM, pThis->uCccNr);
7208 SSMR3PutU32(pSSM, pThis->uCccCurrentNr);
7209 SSMR3PutU32(pSSM, pThis->u32PortsInterrupted);
7210 SSMR3PutBool(pSSM, pThis->fReset);
7211 SSMR3PutBool(pSSM, pThis->f64BitAddr);
7212 SSMR3PutBool(pSSM, pThis->fR0Enabled);
7213 SSMR3PutBool(pSSM, pThis->fGCEnabled);
7214 SSMR3PutBool(pSSM, pThis->fLegacyPortResetMethod);
7215
7216 /* Now every port. */
7217 for (i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
7218 {
7219 Assert(pThis->ahciPort[i].cTasksActive == 0);
7220 SSMR3PutU32(pSSM, pThis->ahciPort[i].regCLB);
7221 SSMR3PutU32(pSSM, pThis->ahciPort[i].regCLBU);
7222 SSMR3PutU32(pSSM, pThis->ahciPort[i].regFB);
7223 SSMR3PutU32(pSSM, pThis->ahciPort[i].regFBU);
7224 SSMR3PutGCPhys(pSSM, pThis->ahciPort[i].GCPhysAddrClb);
7225 SSMR3PutGCPhys(pSSM, pThis->ahciPort[i].GCPhysAddrFb);
7226 SSMR3PutU32(pSSM, pThis->ahciPort[i].regIS);
7227 SSMR3PutU32(pSSM, pThis->ahciPort[i].regIE);
7228 SSMR3PutU32(pSSM, pThis->ahciPort[i].regCMD);
7229 SSMR3PutU32(pSSM, pThis->ahciPort[i].regTFD);
7230 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSIG);
7231 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSSTS);
7232 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSCTL);
7233 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSERR);
7234 SSMR3PutU32(pSSM, pThis->ahciPort[i].regSACT);
7235 SSMR3PutU32(pSSM, pThis->ahciPort[i].regCI);
7236 SSMR3PutU32(pSSM, pThis->ahciPort[i].PCHSGeometry.cCylinders);
7237 SSMR3PutU32(pSSM, pThis->ahciPort[i].PCHSGeometry.cHeads);
7238 SSMR3PutU32(pSSM, pThis->ahciPort[i].PCHSGeometry.cSectors);
7239 SSMR3PutU64(pSSM, pThis->ahciPort[i].cTotalSectors);
7240 SSMR3PutU32(pSSM, pThis->ahciPort[i].cMultSectors);
7241 SSMR3PutU8(pSSM, pThis->ahciPort[i].uATATransferMode);
7242 SSMR3PutBool(pSSM, pThis->ahciPort[i].fResetDevice);
7243 SSMR3PutBool(pSSM, pThis->ahciPort[i].fPoweredOn);
7244 SSMR3PutBool(pSSM, pThis->ahciPort[i].fSpunUp);
7245 SSMR3PutU32(pSSM, pThis->ahciPort[i].u32TasksFinished);
7246 SSMR3PutU32(pSSM, pThis->ahciPort[i].u32QueuedTasksFinished);
7247 SSMR3PutU32(pSSM, pThis->ahciPort[i].u32CurrentCommandSlot);
7248
7249 /* ATAPI saved state. */
7250 SSMR3PutBool(pSSM, pThis->ahciPort[i].fATAPI);
7251 SSMR3PutMem(pSSM, &pThis->ahciPort[i].abATAPISense[0], sizeof(pThis->ahciPort[i].abATAPISense));
7252 SSMR3PutU8(pSSM, pThis->ahciPort[i].cNotifiedMediaChange);
7253 SSMR3PutU32(pSSM, pThis->ahciPort[i].MediaEventStatus);
7254 }
7255
7256 return SSMR3PutU32(pSSM, UINT32_MAX); /* sanity/terminator */
7257}
7258
7259/**
7260 * Loads a saved legacy ATA emulated device state.
7261 *
7262 * @returns VBox status code.
7263 * @param pSSM The handle to the saved state.
7264 */
7265static int ahciR3LoadLegacyEmulationState(PSSMHANDLE pSSM)
7266{
7267 int rc;
7268 uint32_t u32Version;
7269 uint32_t u32;
7270 uint32_t u32IOBuffer;
7271
7272 /* Test for correct version. */
7273 rc = SSMR3GetU32(pSSM, &u32Version);
7274 AssertRCReturn(rc, rc);
7275 LogFlow(("LoadOldSavedStates u32Version = %d\n", u32Version));
7276
7277 if ( u32Version != ATA_CTL_SAVED_STATE_VERSION
7278 && u32Version != ATA_CTL_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE
7279 && u32Version != ATA_CTL_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS)
7280 {
7281 AssertMsgFailed(("u32Version=%d\n", u32Version));
7282 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
7283 }
7284
7285 SSMR3Skip(pSSM, 19 + 5 * sizeof(bool) + sizeof(BMDMAState));
7286
7287 for (uint32_t j = 0; j < 2; j++)
7288 {
7289 SSMR3Skip(pSSM, 88 + 5 * sizeof(bool) );
7290
7291 if (u32Version > ATA_CTL_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE)
7292 SSMR3Skip(pSSM, 64);
7293 else
7294 SSMR3Skip(pSSM, 2);
7295 /** @todo triple-check this hack after passthrough is working */
7296 SSMR3Skip(pSSM, 1);
7297
7298 if (u32Version > ATA_CTL_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS)
7299 SSMR3Skip(pSSM, 4);
7300
7301 SSMR3Skip(pSSM, sizeof(PDMLED));
7302 SSMR3GetU32(pSSM, &u32IOBuffer);
7303 if (u32IOBuffer)
7304 SSMR3Skip(pSSM, u32IOBuffer);
7305 }
7306
7307 rc = SSMR3GetU32(pSSM, &u32);
7308 if (RT_FAILURE(rc))
7309 return rc;
7310 if (u32 != ~0U)
7311 {
7312 AssertMsgFailed(("u32=%#x expected ~0\n", u32));
7313 rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
7314 return rc;
7315 }
7316
7317 return VINF_SUCCESS;
7318}
7319
7320/**
7321 * @callback_method_impl{FNSSMDEVLOADEXEC}
7322 */
7323static DECLCALLBACK(int) ahciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
7324{
7325 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
7326 uint32_t u32;
7327 int rc;
7328
7329 if ( uVersion > AHCI_SAVED_STATE_VERSION
7330 || uVersion < AHCI_SAVED_STATE_VERSION_VBOX_30)
7331 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
7332
7333 /* Deal with the priod after removing the saved IDE bits where the saved
7334 state version remained unchanged. */
7335 if ( uVersion == AHCI_SAVED_STATE_VERSION_IDE_EMULATION
7336 && SSMR3HandleRevision(pSSM) >= 79045
7337 && SSMR3HandleRevision(pSSM) < 79201)
7338 uVersion++;
7339
7340 /*
7341 * Check whether we have to resort to the legacy port reset method to
7342 * prevent older BIOS versions from failing after a reset.
7343 */
7344 if (uVersion <= AHCI_SAVED_STATE_VERSION_PRE_PORT_RESET_CHANGES)
7345 pThis->fLegacyPortResetMethod = true;
7346
7347 /* Verify config. */
7348 if (uVersion > AHCI_SAVED_STATE_VERSION_VBOX_30)
7349 {
7350 rc = SSMR3GetU32(pSSM, &u32);
7351 AssertRCReturn(rc, rc);
7352 if (u32 != pThis->cPortsImpl)
7353 {
7354 LogRel(("AHCI: Config mismatch: cPortsImpl - saved=%u config=%u\n", u32, pThis->cPortsImpl));
7355 if ( u32 < pThis->cPortsImpl
7356 || u32 > AHCI_MAX_NR_PORTS_IMPL)
7357 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: cPortsImpl - saved=%u config=%u"),
7358 u32, pThis->cPortsImpl);
7359 }
7360
7361 for (uint32_t i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
7362 {
7363 bool fInUse;
7364 rc = SSMR3GetBool(pSSM, &fInUse);
7365 AssertRCReturn(rc, rc);
7366 if (fInUse != (pThis->ahciPort[i].pDrvBase != NULL))
7367 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
7368 N_("The %s VM is missing a device on port %u. Please make sure the source and target VMs have compatible storage configurations"),
7369 fInUse ? "target" : "source", i );
7370
7371 if (uVersion > AHCI_SAVED_STATE_VERSION_PRE_HOTPLUG_FLAG)
7372 {
7373 bool fHotpluggable;
7374 rc = SSMR3GetBool(pSSM, &fHotpluggable);
7375 AssertRCReturn(rc, rc);
7376 if (fHotpluggable != pThis->ahciPort[i].fHotpluggable)
7377 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
7378 N_("AHCI: Port %u config mismatch: Hotplug flag - saved=%RTbool config=%RTbool\n"),
7379 i, fHotpluggable, pThis->ahciPort[i].fHotpluggable);
7380 }
7381 else
7382 Assert(pThis->ahciPort[i].fHotpluggable);
7383
7384 char szSerialNumber[AHCI_SERIAL_NUMBER_LENGTH+1];
7385 rc = SSMR3GetStrZ(pSSM, szSerialNumber, sizeof(szSerialNumber));
7386 AssertRCReturn(rc, rc);
7387 if (strcmp(szSerialNumber, pThis->ahciPort[i].szSerialNumber))
7388 LogRel(("AHCI: Port %u config mismatch: Serial number - saved='%s' config='%s'\n",
7389 i, szSerialNumber, pThis->ahciPort[i].szSerialNumber));
7390
7391 char szFirmwareRevision[AHCI_FIRMWARE_REVISION_LENGTH+1];
7392 rc = SSMR3GetStrZ(pSSM, szFirmwareRevision, sizeof(szFirmwareRevision));
7393 AssertRCReturn(rc, rc);
7394 if (strcmp(szFirmwareRevision, pThis->ahciPort[i].szFirmwareRevision))
7395 LogRel(("AHCI: Port %u config mismatch: Firmware revision - saved='%s' config='%s'\n",
7396 i, szFirmwareRevision, pThis->ahciPort[i].szFirmwareRevision));
7397
7398 char szModelNumber[AHCI_MODEL_NUMBER_LENGTH+1];
7399 rc = SSMR3GetStrZ(pSSM, szModelNumber, sizeof(szModelNumber));
7400 AssertRCReturn(rc, rc);
7401 if (strcmp(szModelNumber, pThis->ahciPort[i].szModelNumber))
7402 LogRel(("AHCI: Port %u config mismatch: Model number - saved='%s' config='%s'\n",
7403 i, szModelNumber, pThis->ahciPort[i].szModelNumber));
7404 }
7405
7406 static const char *s_apszIdeEmuPortNames[4] = { "PrimaryMaster", "PrimarySlave", "SecondaryMaster", "SecondarySlave" };
7407 for (size_t i = 0; i < RT_ELEMENTS(s_apszIdeEmuPortNames); i++)
7408 {
7409 uint32_t iPort;
7410 rc = CFGMR3QueryU32Def(pDevIns->pCfg, s_apszIdeEmuPortNames[i], &iPort, i);
7411 AssertRCReturn(rc, rc);
7412
7413 uint32_t iPortSaved;
7414 rc = SSMR3GetU32(pSSM, &iPortSaved);
7415 AssertRCReturn(rc, rc);
7416
7417 if (iPortSaved != iPort)
7418 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("IDE %s config mismatch: saved=%u config=%u"),
7419 s_apszIdeEmuPortNames[i], iPortSaved, iPort);
7420 }
7421 }
7422
7423 if (uPass == SSM_PASS_FINAL)
7424 {
7425 /* Restore data. */
7426
7427 /* The main device structure. */
7428 SSMR3GetU32(pSSM, &pThis->regHbaCap);
7429 SSMR3GetU32(pSSM, &pThis->regHbaCtrl);
7430 SSMR3GetU32(pSSM, &pThis->regHbaIs);
7431 SSMR3GetU32(pSSM, &pThis->regHbaPi);
7432 SSMR3GetU32(pSSM, &pThis->regHbaVs);
7433 SSMR3GetU32(pSSM, &pThis->regHbaCccCtl);
7434 SSMR3GetU32(pSSM, &pThis->regHbaCccPorts);
7435 SSMR3GetU8(pSSM, &pThis->uCccPortNr);
7436 SSMR3GetU64(pSSM, &pThis->uCccTimeout);
7437 SSMR3GetU32(pSSM, &pThis->uCccNr);
7438 SSMR3GetU32(pSSM, &pThis->uCccCurrentNr);
7439
7440 SSMR3GetU32(pSSM, (uint32_t *)&pThis->u32PortsInterrupted);
7441 SSMR3GetBool(pSSM, &pThis->fReset);
7442 SSMR3GetBool(pSSM, &pThis->f64BitAddr);
7443 SSMR3GetBool(pSSM, &pThis->fR0Enabled);
7444 SSMR3GetBool(pSSM, &pThis->fGCEnabled);
7445 if (uVersion > AHCI_SAVED_STATE_VERSION_PRE_PORT_RESET_CHANGES)
7446 SSMR3GetBool(pSSM, &pThis->fLegacyPortResetMethod);
7447
7448 /* Now every port. */
7449 for (uint32_t i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
7450 {
7451 PAHCIPort pAhciPort = &pThis->ahciPort[i];
7452
7453 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regCLB);
7454 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regCLBU);
7455 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regFB);
7456 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regFBU);
7457 SSMR3GetGCPhys(pSSM, (RTGCPHYS *)&pThis->ahciPort[i].GCPhysAddrClb);
7458 SSMR3GetGCPhys(pSSM, (RTGCPHYS *)&pThis->ahciPort[i].GCPhysAddrFb);
7459 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].regIS);
7460 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regIE);
7461 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regCMD);
7462 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regTFD);
7463 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSIG);
7464 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSSTS);
7465 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSCTL);
7466 SSMR3GetU32(pSSM, &pThis->ahciPort[i].regSERR);
7467 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].regSACT);
7468 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].regCI);
7469 SSMR3GetU32(pSSM, &pThis->ahciPort[i].PCHSGeometry.cCylinders);
7470 SSMR3GetU32(pSSM, &pThis->ahciPort[i].PCHSGeometry.cHeads);
7471 SSMR3GetU32(pSSM, &pThis->ahciPort[i].PCHSGeometry.cSectors);
7472 SSMR3GetU64(pSSM, &pThis->ahciPort[i].cTotalSectors);
7473 SSMR3GetU32(pSSM, &pThis->ahciPort[i].cMultSectors);
7474 SSMR3GetU8(pSSM, &pThis->ahciPort[i].uATATransferMode);
7475 SSMR3GetBool(pSSM, &pThis->ahciPort[i].fResetDevice);
7476
7477 if (uVersion <= AHCI_SAVED_STATE_VERSION_VBOX_30)
7478 SSMR3Skip(pSSM, AHCI_NR_COMMAND_SLOTS * sizeof(uint8_t)); /* no active data here */
7479
7480 if (uVersion < AHCI_SAVED_STATE_VERSION_IDE_EMULATION)
7481 {
7482 /* The old positions in the FIFO, not required. */
7483 SSMR3Skip(pSSM, 2*sizeof(uint8_t));
7484 }
7485 SSMR3GetBool(pSSM, &pThis->ahciPort[i].fPoweredOn);
7486 SSMR3GetBool(pSSM, &pThis->ahciPort[i].fSpunUp);
7487 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].u32TasksFinished);
7488 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].u32QueuedTasksFinished);
7489
7490 if (uVersion >= AHCI_SAVED_STATE_VERSION_IDE_EMULATION)
7491 SSMR3GetU32(pSSM, (uint32_t *)&pThis->ahciPort[i].u32CurrentCommandSlot);
7492
7493 if (uVersion > AHCI_SAVED_STATE_VERSION_PRE_ATAPI)
7494 {
7495 SSMR3GetBool(pSSM, &pThis->ahciPort[i].fATAPI);
7496 SSMR3GetMem(pSSM, pThis->ahciPort[i].abATAPISense, sizeof(pThis->ahciPort[i].abATAPISense));
7497 SSMR3GetU8(pSSM, &pThis->ahciPort[i].cNotifiedMediaChange);
7498 SSMR3GetU32(pSSM, (uint32_t*)&pThis->ahciPort[i].MediaEventStatus);
7499 }
7500 else if (pThis->ahciPort[i].fATAPI)
7501 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: atapi - saved=false config=true"));
7502
7503 /* Check if we have tasks pending. */
7504 uint32_t fTasksOutstanding = pAhciPort->regCI & ~pAhciPort->u32TasksFinished;
7505 uint32_t fQueuedTasksOutstanding = pAhciPort->regSACT & ~pAhciPort->u32QueuedTasksFinished;
7506
7507 pAhciPort->u32TasksNew = fTasksOutstanding | fQueuedTasksOutstanding;
7508
7509 if (pAhciPort->u32TasksNew)
7510 {
7511 /*
7512 * There are tasks pending. The VM was saved after a task failed
7513 * because of non-fatal error. Set the redo flag.
7514 */
7515 pAhciPort->fRedo = true;
7516 }
7517 }
7518
7519 if (uVersion <= AHCI_SAVED_STATE_VERSION_IDE_EMULATION)
7520 {
7521 for (uint32_t i = 0; i < 2; i++)
7522 {
7523 rc = ahciR3LoadLegacyEmulationState(pSSM);
7524 if(RT_FAILURE(rc))
7525 return rc;
7526 }
7527 }
7528
7529 rc = SSMR3GetU32(pSSM, &u32);
7530 if (RT_FAILURE(rc))
7531 return rc;
7532 AssertMsgReturn(u32 == UINT32_MAX, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
7533 }
7534
7535 return VINF_SUCCESS;
7536}
7537
7538/* -=-=-=-=- device PDM interface -=-=-=-=- */
7539
7540static DECLCALLBACK(void) ahciR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
7541{
7542 uint32_t i;
7543 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
7544
7545 pAhci->pDevInsRC += offDelta;
7546 pAhci->pHbaCccTimerRC = TMTimerRCPtr(pAhci->pHbaCccTimerR3);
7547 pAhci->pNotifierQueueRC = PDMQueueRCPtr(pAhci->pNotifierQueueR3);
7548
7549 /* Relocate every port. */
7550 for (i = 0; i < RT_ELEMENTS(pAhci->ahciPort); i++)
7551 {
7552 PAHCIPort pAhciPort = &pAhci->ahciPort[i];
7553 pAhciPort->pAhciRC += offDelta;
7554 pAhciPort->pDevInsRC += offDelta;
7555 }
7556}
7557
7558/**
7559 * SCSI_GET_EVENT_STATUS_NOTIFICATION should return "medium removed" event
7560 * from now on, regardless if there was a medium inserted or not.
7561 */
7562static void ahciMediumRemoved(PAHCIPort pAhciPort)
7563{
7564 ASMAtomicWriteU32(&pAhciPort->MediaEventStatus, ATA_EVENT_STATUS_MEDIA_REMOVED);
7565}
7566
7567/**
7568 * SCSI_GET_EVENT_STATUS_NOTIFICATION should return "medium inserted". If
7569 * there was already a medium inserted, don't forget to send the "medium
7570 * removed" event first.
7571 */
7572static void ahciMediumInserted(PAHCIPort pAhciPort)
7573{
7574 uint32_t OldStatus, NewStatus;
7575 do
7576 {
7577 OldStatus = ASMAtomicReadU32(&pAhciPort->MediaEventStatus);
7578 switch (OldStatus)
7579 {
7580 case ATA_EVENT_STATUS_MEDIA_CHANGED:
7581 case ATA_EVENT_STATUS_MEDIA_REMOVED:
7582 /* no change, we will send "medium removed" + "medium inserted" */
7583 NewStatus = ATA_EVENT_STATUS_MEDIA_CHANGED;
7584 break;
7585 default:
7586 NewStatus = ATA_EVENT_STATUS_MEDIA_NEW;
7587 break;
7588 }
7589 } while (!ASMAtomicCmpXchgU32(&pAhciPort->MediaEventStatus, NewStatus, OldStatus));
7590}
7591
7592/**
7593 * Called when a media is mounted.
7594 *
7595 * @param pInterface Pointer to the interface structure containing the called function pointer.
7596 */
7597static DECLCALLBACK(void) ahciR3MountNotify(PPDMIMOUNTNOTIFY pInterface)
7598{
7599 PAHCIPort pAhciPort = PDMIMOUNTNOTIFY_2_PAHCIPORT(pInterface);
7600 Log(("%s: changing LUN#%d\n", __FUNCTION__, pAhciPort->iLUN));
7601
7602 /* Ignore the call if we're called while being attached. */
7603 if (!pAhciPort->pDrvBlock)
7604 return;
7605
7606 if (pAhciPort->fATAPI)
7607 {
7608 pAhciPort->cTotalSectors = pAhciPort->pDrvBlock->pfnGetSize(pAhciPort->pDrvBlock) / 2048;
7609
7610 LogRel(("AHCI: LUN#%d: CD/DVD, total number of sectors %Ld, passthrough unchanged\n", pAhciPort->iLUN, pAhciPort->cTotalSectors));
7611
7612 /* Report media changed in TEST UNIT and other (probably incorrect) places. */
7613 if (pAhciPort->cNotifiedMediaChange < 2)
7614 pAhciPort->cNotifiedMediaChange = 2;
7615 ahciMediumInserted(pAhciPort);
7616 ahciMediumTypeSet(pAhciPort, ATA_MEDIA_TYPE_UNKNOWN);
7617 }
7618 else
7619 AssertMsgFailed(("Hard disks don't have a mount interface!\n"));
7620}
7621
7622/**
7623 * Called when a media is unmounted
7624 * @param pInterface Pointer to the interface structure containing the called function pointer.
7625 */
7626static DECLCALLBACK(void) ahciR3UnmountNotify(PPDMIMOUNTNOTIFY pInterface)
7627{
7628 PAHCIPort pAhciPort = PDMIMOUNTNOTIFY_2_PAHCIPORT(pInterface);
7629 Log(("%s:\n", __FUNCTION__));
7630
7631 /* Free all cached I/O tasks. */
7632 ahciR3PortCachedReqsFree(pAhciPort);
7633
7634 pAhciPort->cTotalSectors = 0;
7635
7636 if (pAhciPort->fATAPI)
7637 {
7638 /*
7639 * Whatever I do, XP will not use the GET MEDIA STATUS nor the EVENT stuff.
7640 * However, it will respond to TEST UNIT with a 0x6 0x28 (media changed) sense code.
7641 * So, we'll give it 4 TEST UNIT command to catch up, two which the media is not
7642 * present and 2 in which it is changed.
7643 */
7644 pAhciPort->cNotifiedMediaChange = 4;
7645 ahciMediumRemoved(pAhciPort);
7646 ahciMediumTypeSet(pAhciPort, ATA_MEDIA_TYPE_UNKNOWN);
7647 }
7648 else
7649 AssertMsgFailed(("Hard disks don't have a mount interface!\n"));
7650}
7651
7652/**
7653 * Configure the attached device for a port.
7654 *
7655 * Used by ahciR3Construct and ahciR3Attach.
7656 *
7657 * @returns VBox status code
7658 * @param pDevIns The device instance data.
7659 * @param pAhciPort The port for which the device is to be configured.
7660 */
7661static int ahciR3ConfigureLUN(PPDMDEVINS pDevIns, PAHCIPort pAhciPort)
7662{
7663 int rc = VINF_SUCCESS;
7664 PDMBLOCKTYPE enmType;
7665
7666 /*
7667 * Query the block and blockbios interfaces.
7668 */
7669 pAhciPort->pDrvBlock = PDMIBASE_QUERY_INTERFACE(pAhciPort->pDrvBase, PDMIBLOCK);
7670 if (!pAhciPort->pDrvBlock)
7671 {
7672 AssertMsgFailed(("Configuration error: LUN#%d hasn't a block interface!\n", pAhciPort->iLUN));
7673 return VERR_PDM_MISSING_INTERFACE;
7674 }
7675 pAhciPort->pDrvBlockBios = PDMIBASE_QUERY_INTERFACE(pAhciPort->pDrvBase, PDMIBLOCKBIOS);
7676 if (!pAhciPort->pDrvBlockBios)
7677 {
7678 AssertMsgFailed(("Configuration error: LUN#%d hasn't a block BIOS interface!\n", pAhciPort->iLUN));
7679 return VERR_PDM_MISSING_INTERFACE;
7680 }
7681
7682 pAhciPort->pDrvMount = PDMIBASE_QUERY_INTERFACE(pAhciPort->pDrvBase, PDMIMOUNT);
7683
7684 /* Try to get the optional async block interface. */
7685 pAhciPort->pDrvBlockAsync = PDMIBASE_QUERY_INTERFACE(pAhciPort->pDrvBase, PDMIBLOCKASYNC);
7686
7687 /*
7688 * Validate type.
7689 */
7690 enmType = pAhciPort->pDrvBlock->pfnGetType(pAhciPort->pDrvBlock);
7691
7692 if ( enmType != PDMBLOCKTYPE_HARD_DISK
7693 && enmType != PDMBLOCKTYPE_CDROM
7694 && enmType != PDMBLOCKTYPE_DVD)
7695 {
7696 AssertMsgFailed(("Configuration error: LUN#%d isn't a disk or cd/dvd. enmType=%d\n", pAhciPort->iLUN, enmType));
7697 return VERR_PDM_UNSUPPORTED_BLOCK_TYPE;
7698 }
7699
7700 if ( (enmType == PDMBLOCKTYPE_CDROM || enmType == PDMBLOCKTYPE_DVD)
7701 && !pAhciPort->pDrvMount)
7702 {
7703 AssertMsgFailed(("Internal error: CD/DVD-ROM without a mountable interface\n"));
7704 return VERR_INTERNAL_ERROR;
7705 }
7706 pAhciPort->fATAPI = (enmType == PDMBLOCKTYPE_CDROM || enmType == PDMBLOCKTYPE_DVD);
7707 pAhciPort->fATAPIPassthrough = pAhciPort->fATAPI ? (pAhciPort->pDrvBlock->pfnSendCmd != NULL) : false;
7708
7709 rc = RTCritSectInit(&pAhciPort->CritSectReqsFree);
7710 if (RT_FAILURE(rc))
7711 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
7712 N_("AHCI initialisation error: Failed to create critical section for free request list"));
7713
7714 pAhciPort->pListReqsFree = (PRTLISTANCHOR)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(RTLISTANCHOR));
7715 if (!pAhciPort->pListReqsFree)
7716 return PDMDevHlpVMSetError(pDevIns, VERR_NO_MEMORY, RT_SRC_POS,
7717 N_("AHCI initialisation error: Failed to allocate memory for free request list"));
7718
7719 RTListInit(pAhciPort->pListReqsFree);
7720
7721 if (pAhciPort->fATAPI)
7722 {
7723 pAhciPort->cTotalSectors = pAhciPort->pDrvBlock->pfnGetSize(pAhciPort->pDrvBlock) / 2048;
7724 pAhciPort->PCHSGeometry.cCylinders = 0;
7725 pAhciPort->PCHSGeometry.cHeads = 0;
7726 pAhciPort->PCHSGeometry.cSectors = 0;
7727 LogRel(("AHCI: LUN#%d: CD/DVD, total number of sectors %Ld, passthrough %s\n", pAhciPort->iLUN,
7728 pAhciPort->cTotalSectors, (pAhciPort->fATAPIPassthrough ? "enabled" : "disabled")));
7729 }
7730 else
7731 {
7732 pAhciPort->cbSector = pAhciPort->pDrvBlock->pfnGetSectorSize(pAhciPort->pDrvBlock);
7733 pAhciPort->cTotalSectors = pAhciPort->pDrvBlock->pfnGetSize(pAhciPort->pDrvBlock) / pAhciPort->cbSector;
7734 rc = pAhciPort->pDrvBlockBios->pfnGetPCHSGeometry(pAhciPort->pDrvBlockBios,
7735 &pAhciPort->PCHSGeometry);
7736 if (rc == VERR_PDM_MEDIA_NOT_MOUNTED)
7737 {
7738 pAhciPort->PCHSGeometry.cCylinders = 0;
7739 pAhciPort->PCHSGeometry.cHeads = 16; /*??*/
7740 pAhciPort->PCHSGeometry.cSectors = 63; /*??*/
7741 }
7742 else if (rc == VERR_PDM_GEOMETRY_NOT_SET)
7743 {
7744 pAhciPort->PCHSGeometry.cCylinders = 0; /* autodetect marker */
7745 rc = VINF_SUCCESS;
7746 }
7747 AssertRC(rc);
7748
7749 if ( pAhciPort->PCHSGeometry.cCylinders == 0
7750 || pAhciPort->PCHSGeometry.cHeads == 0
7751 || pAhciPort->PCHSGeometry.cSectors == 0)
7752 {
7753 uint64_t cCylinders = pAhciPort->cTotalSectors / (16 * 63);
7754 pAhciPort->PCHSGeometry.cCylinders = RT_MAX(RT_MIN(cCylinders, 16383), 1);
7755 pAhciPort->PCHSGeometry.cHeads = 16;
7756 pAhciPort->PCHSGeometry.cSectors = 63;
7757 /* Set the disk geometry information. Ignore errors. */
7758 pAhciPort->pDrvBlockBios->pfnSetPCHSGeometry(pAhciPort->pDrvBlockBios,
7759 &pAhciPort->PCHSGeometry);
7760 rc = VINF_SUCCESS;
7761 }
7762 LogRel(("AHCI: LUN#%d: disk, PCHS=%u/%u/%u, total number of sectors %Ld\n",
7763 pAhciPort->iLUN, pAhciPort->PCHSGeometry.cCylinders,
7764 pAhciPort->PCHSGeometry.cHeads, pAhciPort->PCHSGeometry.cSectors,
7765 pAhciPort->cTotalSectors));
7766 if (pAhciPort->pDrvBlock->pfnDiscard)
7767 LogRel(("AHCI: LUN#%d: Enabled TRIM support\n", pAhciPort->iLUN));
7768 }
7769 return rc;
7770}
7771
7772/**
7773 * Callback employed by ahciR3Suspend and ahciR3PowerOff..
7774 *
7775 * @returns true if we've quiesced, false if we're still working.
7776 * @param pDevIns The device instance.
7777 */
7778static DECLCALLBACK(bool) ahciR3IsAsyncSuspendOrPowerOffDone(PPDMDEVINS pDevIns)
7779{
7780 if (!ahciR3AllAsyncIOIsFinished(pDevIns))
7781 return false;
7782
7783 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
7784 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
7785 /*
7786 * Free all cached tasks here, not possible on destruct because the driver
7787 * is destroyed before us.
7788 */
7789 for (unsigned iPort = 0; iPort < pThis->cPortsImpl; iPort++)
7790 ahciR3PortCachedReqsFree(&pThis->ahciPort[iPort]);
7791 return true;
7792}
7793
7794/**
7795 * Common worker for ahciR3Suspend and ahciR3PowerOff.
7796 */
7797static void ahciR3SuspendOrPowerOff(PPDMDEVINS pDevIns)
7798{
7799 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
7800
7801 ASMAtomicWriteBool(&pThis->fSignalIdle, true);
7802 if (!ahciR3AllAsyncIOIsFinished(pDevIns))
7803 PDMDevHlpSetAsyncNotification(pDevIns, ahciR3IsAsyncSuspendOrPowerOffDone);
7804 else
7805 {
7806 /*
7807 * Free all cached tasks here, not possible on destruct because the driver
7808 * is destroyed before us.
7809 */
7810 for (unsigned iPort = 0; iPort < pThis->cPortsImpl; iPort++)
7811 ahciR3PortCachedReqsFree(&pThis->ahciPort[iPort]);
7812
7813 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
7814 }
7815}
7816
7817/**
7818 * Suspend notification.
7819 *
7820 * @param pDevIns The device instance data.
7821 */
7822static DECLCALLBACK(void) ahciR3Suspend(PPDMDEVINS pDevIns)
7823{
7824 Log(("ahciR3Suspend\n"));
7825 ahciR3SuspendOrPowerOff(pDevIns);
7826}
7827
7828/**
7829 * Resume notification.
7830 *
7831 * @param pDevIns The device instance data.
7832 */
7833static DECLCALLBACK(void) ahciR3Resume(PPDMDEVINS pDevIns)
7834{
7835 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
7836
7837 /*
7838 * Check if one of the ports has pending tasks.
7839 * Queue a notification item again in this case.
7840 */
7841 for (unsigned i = 0; i < RT_ELEMENTS(pAhci->ahciPort); i++)
7842 {
7843 PAHCIPort pAhciPort = &pAhci->ahciPort[i];
7844
7845 if (pAhciPort->u32TasksRedo)
7846 {
7847 PDEVPORTNOTIFIERQUEUEITEM pItem = (PDEVPORTNOTIFIERQUEUEITEM)PDMQueueAlloc(pAhci->CTX_SUFF(pNotifierQueue));
7848 AssertMsg(pItem, ("Allocating item for queue failed\n"));
7849
7850 pAhciPort->u32TasksNew |= pAhciPort->u32TasksRedo;
7851 pAhciPort->u32TasksRedo = 0;
7852
7853 Assert(pAhciPort->fRedo);
7854 pAhciPort->fRedo = false;
7855
7856 pItem->iPort = pAhci->ahciPort[i].iLUN;
7857 PDMQueueInsert(pAhci->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
7858 }
7859 }
7860
7861 Log(("%s:\n", __FUNCTION__));
7862}
7863
7864/**
7865 * Initializes the VPD data of a attached device.
7866 *
7867 * @returns VBox status code.
7868 * @param pDevIns The device instance.
7869 * @param pAhciPort The attached device.
7870 * @param szName Name of the port to get the CFGM node.
7871 */
7872static int ahciR3VpdInit(PPDMDEVINS pDevIns, PAHCIPort pAhciPort, const char *pszName)
7873{
7874 int rc = VINF_SUCCESS;
7875 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
7876
7877 /* Generate a default serial number. */
7878 char szSerial[AHCI_SERIAL_NUMBER_LENGTH+1];
7879 RTUUID Uuid;
7880
7881 if (pAhciPort->pDrvBlock)
7882 rc = pAhciPort->pDrvBlock->pfnGetUuid(pAhciPort->pDrvBlock, &Uuid);
7883 else
7884 RTUuidClear(&Uuid);
7885
7886 if (RT_FAILURE(rc) || RTUuidIsNull(&Uuid))
7887 {
7888 /* Generate a predictable serial for drives which don't have a UUID. */
7889 RTStrPrintf(szSerial, sizeof(szSerial), "VB%x-1a2b3c4d",
7890 pAhciPort->iLUN);
7891 }
7892 else
7893 RTStrPrintf(szSerial, sizeof(szSerial), "VB%08x-%08x", Uuid.au32[0], Uuid.au32[3]);
7894
7895 /* Get user config if present using defaults otherwise. */
7896 PCFGMNODE pCfgNode = CFGMR3GetChild(pDevIns->pCfg, pszName);
7897 rc = CFGMR3QueryStringDef(pCfgNode, "SerialNumber", pAhciPort->szSerialNumber, sizeof(pAhciPort->szSerialNumber),
7898 szSerial);
7899 if (RT_FAILURE(rc))
7900 {
7901 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
7902 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
7903 N_("AHCI configuration error: \"SerialNumber\" is longer than 20 bytes"));
7904 return PDMDEV_SET_ERROR(pDevIns, rc,
7905 N_("AHCI configuration error: failed to read \"SerialNumber\" as string"));
7906 }
7907
7908 rc = CFGMR3QueryStringDef(pCfgNode, "FirmwareRevision", pAhciPort->szFirmwareRevision, sizeof(pAhciPort->szFirmwareRevision),
7909 "1.0");
7910 if (RT_FAILURE(rc))
7911 {
7912 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
7913 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
7914 N_("AHCI configuration error: \"FirmwareRevision\" is longer than 8 bytes"));
7915 return PDMDEV_SET_ERROR(pDevIns, rc,
7916 N_("AHCI configuration error: failed to read \"FirmwareRevision\" as string"));
7917 }
7918
7919 rc = CFGMR3QueryStringDef(pCfgNode, "ModelNumber", pAhciPort->szModelNumber, sizeof(pAhciPort->szModelNumber),
7920 pAhciPort->fATAPI ? "VBOX CD-ROM" : "VBOX HARDDISK");
7921 if (RT_FAILURE(rc))
7922 {
7923 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
7924 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
7925 N_("AHCI configuration error: \"ModelNumber\" is longer than 40 bytes"));
7926 return PDMDEV_SET_ERROR(pDevIns, rc,
7927 N_("AHCI configuration error: failed to read \"ModelNumber\" as string"));
7928 }
7929
7930 rc = CFGMR3QueryBoolDef(pCfgNode, "NonRotationalMedium", &pAhciPort->fNonRotational, false);
7931 if (RT_FAILURE(rc))
7932 return PDMDEV_SET_ERROR(pDevIns, rc,
7933 N_("AHCI configuration error: failed to read \"NonRotationalMedium\" as boolean"));
7934
7935 rc = CFGMR3QueryU8Def(pCfgNode, "LogicalSectorsPerPhysical", &pAhciPort->cLogSectorsPerPhysicalExp, 0);
7936 if (RT_FAILURE(rc))
7937 return PDMDEV_SET_ERROR(pDevIns, rc,
7938 N_("AHCI configuration error: failed to read \"LogicalSectorsPerPhysical\" as integer"));
7939 if (pAhciPort->cLogSectorsPerPhysicalExp >= 16)
7940 return PDMDEV_SET_ERROR(pDevIns, rc,
7941 N_("AHCI configuration error: \"LogicalSectorsPerPhysical\" must be between 0 and 15"));
7942
7943 /* There are three other identification strings for CD drives used for INQUIRY */
7944 if (pAhciPort->fATAPI)
7945 {
7946 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIVendorId", pAhciPort->szInquiryVendorId, sizeof(pAhciPort->szInquiryVendorId),
7947 "VBOX");
7948 if (RT_FAILURE(rc))
7949 {
7950 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
7951 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
7952 N_("AHCI configuration error: \"ATAPIVendorId\" is longer than 16 bytes"));
7953 return PDMDEV_SET_ERROR(pDevIns, rc,
7954 N_("AHCI configuration error: failed to read \"ATAPIVendorId\" as string"));
7955 }
7956
7957 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIProductId", pAhciPort->szInquiryProductId, sizeof(pAhciPort->szInquiryProductId),
7958 "CD-ROM");
7959 if (RT_FAILURE(rc))
7960 {
7961 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
7962 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
7963 N_("AHCI configuration error: \"ATAPIProductId\" is longer than 16 bytes"));
7964 return PDMDEV_SET_ERROR(pDevIns, rc,
7965 N_("AHCI configuration error: failed to read \"ATAPIProductId\" as string"));
7966 }
7967
7968 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIRevision", pAhciPort->szInquiryRevision, sizeof(pAhciPort->szInquiryRevision),
7969 "1.0");
7970 if (RT_FAILURE(rc))
7971 {
7972 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
7973 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
7974 N_("AHCI configuration error: \"ATAPIRevision\" is longer than 4 bytes"));
7975 return PDMDEV_SET_ERROR(pDevIns, rc,
7976 N_("AHCI configuration error: failed to read \"ATAPIRevision\" as string"));
7977 }
7978 }
7979
7980 return rc;
7981}
7982
7983
7984/**
7985 * Detach notification.
7986 *
7987 * One harddisk at one port has been unplugged.
7988 * The VM is suspended at this point.
7989 *
7990 * @param pDevIns The device instance.
7991 * @param iLUN The logical unit which is being detached.
7992 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7993 */
7994static DECLCALLBACK(void) ahciR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7995{
7996 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
7997 PAHCIPort pAhciPort = &pAhci->ahciPort[iLUN];
7998 int rc = VINF_SUCCESS;
7999
8000 Log(("%s:\n", __FUNCTION__));
8001
8002 AssertMsg(iLUN < pAhci->cPortsImpl, ("iLUN=%u", iLUN));
8003 AssertMsgReturnVoid( pAhciPort->fHotpluggable
8004 || (fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
8005 ("AHCI: Port %d is not marked hotpluggable\n", pAhciPort->iLUN));
8006
8007
8008 if (pAhciPort->pAsyncIOThread)
8009 {
8010 int rcThread;
8011 /* Destroy the thread. */
8012 rc = PDMR3ThreadDestroy(pAhciPort->pAsyncIOThread, &rcThread);
8013 if (RT_FAILURE(rc) || RT_FAILURE(rcThread))
8014 AssertMsgFailed(("%s Failed to destroy async IO thread rc=%Rrc rcThread=%Rrc\n", __FUNCTION__, rc, rcThread));
8015
8016 pAhciPort->pAsyncIOThread = NULL;
8017 pAhciPort->fWrkThreadSleeping = true;
8018 }
8019
8020 if (pAhciPort->fATAPI)
8021 ahciMediumRemoved(pAhciPort);
8022
8023 /* Free all cached I/O tasks. */
8024 ahciR3PortCachedReqsFree(pAhciPort);
8025
8026 if (RTCritSectIsInitialized(&pAhciPort->CritSectReqsFree))
8027 RTCritSectDelete(&pAhciPort->CritSectReqsFree);
8028
8029 if (pAhciPort->pListReqsFree)
8030 MMR3HeapFree(pAhciPort->pListReqsFree);
8031
8032 pAhciPort->pListReqsFree = NULL;
8033
8034 if (!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG))
8035 {
8036 /*
8037 * Inform the guest about the removed device.
8038 */
8039 pAhciPort->regSSTS = 0;
8040 pAhciPort->regSIG = 0;
8041 /*
8042 * Clear CR bit too to prevent submission of new commands when CI is written
8043 * (AHCI Spec 1.2: 7.4 Interaction of the Command List and Port Change Status).
8044 */
8045 ASMAtomicAndU32(&pAhciPort->regCMD, ~(AHCI_PORT_CMD_CPS | AHCI_PORT_CMD_CR));
8046 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_CPDS | AHCI_PORT_IS_PRCS | AHCI_PORT_IS_PCS);
8047 ASMAtomicOrU32(&pAhciPort->regSERR, AHCI_PORT_SERR_X | AHCI_PORT_SERR_N);
8048 if ( (pAhciPort->regIE & AHCI_PORT_IE_CPDE)
8049 || (pAhciPort->regIE & AHCI_PORT_IE_PCE)
8050 || (pAhciPort->regIE & AHCI_PORT_IE_PRCE))
8051 ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
8052 }
8053
8054 /*
8055 * Zero some important members.
8056 */
8057 pAhciPort->pDrvBase = NULL;
8058 pAhciPort->pDrvBlock = NULL;
8059 pAhciPort->pDrvBlockAsync = NULL;
8060 pAhciPort->pDrvBlockBios = NULL;
8061}
8062
8063/**
8064 * Attach command.
8065 *
8066 * This is called when we change block driver for one port.
8067 * The VM is suspended at this point.
8068 *
8069 * @returns VBox status code.
8070 * @param pDevIns The device instance.
8071 * @param iLUN The logical unit which is being detached.
8072 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
8073 */
8074static DECLCALLBACK(int) ahciR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
8075{
8076 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
8077 PAHCIPort pAhciPort = &pThis->ahciPort[iLUN];
8078 int rc;
8079
8080 Log(("%s:\n", __FUNCTION__));
8081
8082 /* the usual paranoia */
8083 AssertMsg(iLUN < pThis->cPortsImpl, ("iLUN=%u", iLUN));
8084 AssertRelease(!pAhciPort->pDrvBase);
8085 AssertRelease(!pAhciPort->pDrvBlock);
8086 AssertRelease(!pAhciPort->pDrvBlockAsync);
8087 Assert(pAhciPort->iLUN == iLUN);
8088
8089 AssertMsgReturn( pAhciPort->fHotpluggable
8090 || (fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
8091 ("AHCI: Port %d is not marked hotpluggable\n", pAhciPort->iLUN),
8092 VERR_INVALID_PARAMETER);
8093
8094 /*
8095 * Try attach the block device and get the interfaces,
8096 * required as well as optional.
8097 */
8098 rc = PDMDevHlpDriverAttach(pDevIns, pAhciPort->iLUN, &pAhciPort->IBase, &pAhciPort->pDrvBase, NULL);
8099 if (RT_SUCCESS(rc))
8100 {
8101 rc = ahciR3ConfigureLUN(pDevIns, pAhciPort);
8102
8103 /*
8104 * In case there is a medium inserted.
8105 */
8106 ahciMediumInserted(pAhciPort);
8107 ahciMediumTypeSet(pAhciPort, ATA_MEDIA_TYPE_UNKNOWN);
8108 }
8109 else
8110 AssertMsgFailed(("Failed to attach LUN#%d. rc=%Rrc\n", pAhciPort->iLUN, rc));
8111
8112 if (RT_FAILURE(rc))
8113 {
8114 pAhciPort->pDrvBase = NULL;
8115 pAhciPort->pDrvBlock = NULL;
8116 }
8117 else
8118 {
8119 char szName[24];
8120 RTStrPrintf(szName, sizeof(szName), "Port%d", iLUN);
8121
8122 if ( pAhciPort->pDrvBlockAsync
8123 && !pAhciPort->fATAPI)
8124 pAhciPort->fAsyncInterface = true;
8125 else
8126 pAhciPort->fAsyncInterface = false;
8127
8128 rc = SUPSemEventCreate(pThis->pSupDrvSession, &pAhciPort->hEvtProcess);
8129 if (RT_FAILURE(rc))
8130 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
8131 N_("AHCI: Failed to create SUP event semaphore"));
8132
8133 /* Create the async IO thread. */
8134 rc = PDMDevHlpThreadCreate(pDevIns, &pAhciPort->pAsyncIOThread, pAhciPort, ahciAsyncIOLoop, ahciAsyncIOLoopWakeUp, 0,
8135 RTTHREADTYPE_IO, szName);
8136 if (RT_FAILURE(rc))
8137 return rc;
8138
8139 /*
8140 * Init vendor product data.
8141 */
8142 if (RT_SUCCESS(rc))
8143 rc = ahciR3VpdInit(pDevIns, pAhciPort, szName);
8144
8145 /* Inform the guest about the added device in case of hotplugging. */
8146 if ( RT_SUCCESS(rc)
8147 && !(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG))
8148 {
8149 AssertMsgReturn(pAhciPort->fHotpluggable,
8150 ("AHCI: Port %d is not marked hotpluggable\n", pAhciPort->iLUN),
8151 VERR_NOT_SUPPORTED);
8152
8153 /*
8154 * Initialize registers
8155 */
8156 ASMAtomicOrU32(&pAhciPort->regCMD, AHCI_PORT_CMD_CPS);
8157 ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_CPDS | AHCI_PORT_IS_PRCS | AHCI_PORT_IS_PCS);
8158 ASMAtomicOrU32(&pAhciPort->regSERR, AHCI_PORT_SERR_X | AHCI_PORT_SERR_N);
8159
8160 if (pAhciPort->fATAPI)
8161 pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
8162 else
8163 pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
8164 pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
8165 (0x02 << 4) | /* Generation 2 (3.0GBps) speed. */
8166 (0x03 << 0); /* Device detected and communication established. */
8167
8168 if ( (pAhciPort->regIE & AHCI_PORT_IE_CPDE)
8169 || (pAhciPort->regIE & AHCI_PORT_IE_PCE)
8170 || (pAhciPort->regIE & AHCI_PORT_IE_PRCE))
8171 ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
8172 }
8173
8174 }
8175
8176 return rc;
8177}
8178
8179/**
8180 * Common reset worker.
8181 *
8182 * @param pDevIns The device instance data.
8183 */
8184static int ahciR3ResetCommon(PPDMDEVINS pDevIns, bool fConstructor)
8185{
8186 PAHCI pAhci = PDMINS_2_DATA(pDevIns, PAHCI);
8187
8188 ahciHBAReset(pAhci);
8189
8190 /* Hardware reset for the ports. */
8191 for (uint32_t i = 0; i < RT_ELEMENTS(pAhci->ahciPort); i++)
8192 ahciPortHwReset(&pAhci->ahciPort[i]);
8193 return VINF_SUCCESS;
8194}
8195
8196/**
8197 * Callback employed by ahciR3Reset.
8198 *
8199 * @returns true if we've quiesced, false if we're still working.
8200 * @param pDevIns The device instance.
8201 */
8202static DECLCALLBACK(bool) ahciR3IsAsyncResetDone(PPDMDEVINS pDevIns)
8203{
8204 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
8205
8206 if (!ahciR3AllAsyncIOIsFinished(pDevIns))
8207 return false;
8208 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
8209
8210 ahciR3ResetCommon(pDevIns, false /*fConstructor*/);
8211 return true;
8212}
8213
8214/**
8215 * Reset notification.
8216 *
8217 * @param pDevIns The device instance data.
8218 */
8219static DECLCALLBACK(void) ahciR3Reset(PPDMDEVINS pDevIns)
8220{
8221 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
8222
8223 ASMAtomicWriteBool(&pThis->fSignalIdle, true);
8224 if (!ahciR3AllAsyncIOIsFinished(pDevIns))
8225 PDMDevHlpSetAsyncNotification(pDevIns, ahciR3IsAsyncResetDone);
8226 else
8227 {
8228 ASMAtomicWriteBool(&pThis->fSignalIdle, false);
8229 ahciR3ResetCommon(pDevIns, false /*fConstructor*/);
8230 }
8231}
8232
8233/**
8234 * Poweroff notification.
8235 *
8236 * @param pDevIns Pointer to the device instance
8237 */
8238static DECLCALLBACK(void) ahciR3PowerOff(PPDMDEVINS pDevIns)
8239{
8240 Log(("achiR3PowerOff\n"));
8241 ahciR3SuspendOrPowerOff(pDevIns);
8242}
8243
8244/**
8245 * Destroy a driver instance.
8246 *
8247 * Most VM resources are freed by the VM. This callback is provided so that any non-VM
8248 * resources can be freed correctly.
8249 *
8250 * @param pDevIns The device instance data.
8251 */
8252static DECLCALLBACK(int) ahciR3Destruct(PPDMDEVINS pDevIns)
8253{
8254 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
8255 int rc = VINF_SUCCESS;
8256 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
8257
8258 /*
8259 * At this point the async I/O thread is suspended and will not enter
8260 * this module again. So, no coordination is needed here and PDM
8261 * will take care of terminating and cleaning up the thread.
8262 */
8263 if (PDMCritSectIsInitialized(&pThis->lock))
8264 {
8265 TMR3TimerDestroy(pThis->CTX_SUFF(pHbaCccTimer));
8266 pThis->CTX_SUFF(pHbaCccTimer) = NULL;
8267
8268 Log(("%s: Destruct every port\n", __FUNCTION__));
8269 for (unsigned iActPort = 0; iActPort < pThis->cPortsImpl; iActPort++)
8270 {
8271 PAHCIPort pAhciPort = &pThis->ahciPort[iActPort];
8272
8273 if (pAhciPort->hEvtProcess != NIL_SUPSEMEVENT)
8274 {
8275 SUPSemEventClose(pThis->pSupDrvSession, pAhciPort->hEvtProcess);
8276 pAhciPort->hEvtProcess = NIL_SUPSEMEVENT;
8277 }
8278
8279 if (RTCritSectIsInitialized(&pAhciPort->CritSectReqsFree))
8280 RTCritSectDelete(&pAhciPort->CritSectReqsFree);
8281
8282#ifdef VBOX_STRICT
8283 for (uint32_t i = 0; i < AHCI_NR_COMMAND_SLOTS; i++)
8284 Assert(!pAhciPort->aActiveTasks[i]);
8285#endif
8286 }
8287
8288 PDMR3CritSectDelete(&pThis->lock);
8289 }
8290
8291 return rc;
8292}
8293
8294/**
8295 * @interface_method_impl{PDMDEVREG,pfnConstruct}
8296 */
8297static DECLCALLBACK(int) ahciR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
8298{
8299 PAHCI pThis = PDMINS_2_DATA(pDevIns, PAHCI);
8300 PPDMIBASE pBase;
8301 int rc = VINF_SUCCESS;
8302 unsigned i = 0;
8303 bool fGCEnabled = false;
8304 bool fR0Enabled = false;
8305 uint32_t cbTotalBufferSize = 0;
8306 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
8307
8308 LogFlowFunc(("pThis=%#p\n", pThis));
8309
8310 /*
8311 * Validate and read configuration.
8312 */
8313 if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0"
8314 "R0Enabled\0"
8315 "PrimaryMaster\0"
8316 "PrimarySlave\0"
8317 "SecondaryMaster\0"
8318 "SecondarySlave\0"
8319 "PortCount\0"
8320 "UseAsyncInterfaceIfAvailable\0"
8321 "Bootable\0"
8322 "CmdSlotsAvail\0"))
8323 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
8324 N_("AHCI configuration error: unknown option specified"));
8325
8326 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
8327 if (RT_FAILURE(rc))
8328 return PDMDEV_SET_ERROR(pDevIns, rc,
8329 N_("AHCI configuration error: failed to read GCEnabled as boolean"));
8330 Log(("%s: fGCEnabled=%d\n", __FUNCTION__, fGCEnabled));
8331
8332 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
8333 if (RT_FAILURE(rc))
8334 return PDMDEV_SET_ERROR(pDevIns, rc,
8335 N_("AHCI configuration error: failed to read R0Enabled as boolean"));
8336 Log(("%s: fR0Enabled=%d\n", __FUNCTION__, fR0Enabled));
8337
8338 rc = CFGMR3QueryU32Def(pCfg, "PortCount", &pThis->cPortsImpl, AHCI_MAX_NR_PORTS_IMPL);
8339 if (RT_FAILURE(rc))
8340 return PDMDEV_SET_ERROR(pDevIns, rc,
8341 N_("AHCI configuration error: failed to read PortCount as integer"));
8342 Log(("%s: cPortsImpl=%u\n", __FUNCTION__, pThis->cPortsImpl));
8343 if (pThis->cPortsImpl > AHCI_MAX_NR_PORTS_IMPL)
8344 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
8345 N_("AHCI configuration error: PortCount=%u should not exceed %u"),
8346 pThis->cPortsImpl, AHCI_MAX_NR_PORTS_IMPL);
8347 if (pThis->cPortsImpl < 1)
8348 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
8349 N_("AHCI configuration error: PortCount=%u should be at least 1"),
8350 pThis->cPortsImpl);
8351
8352 rc = CFGMR3QueryBoolDef(pCfg, "UseAsyncInterfaceIfAvailable", &pThis->fUseAsyncInterfaceIfAvailable, true);
8353 if (RT_FAILURE(rc))
8354 return PDMDEV_SET_ERROR(pDevIns, rc,
8355 N_("AHCI configuration error: failed to read UseAsyncInterfaceIfAvailable as boolean"));
8356
8357 rc = CFGMR3QueryBoolDef(pCfg, "Bootable", &pThis->fBootable, true);
8358 if (RT_FAILURE(rc))
8359 return PDMDEV_SET_ERROR(pDevIns, rc,
8360 N_("AHCI configuration error: failed to read Bootable as boolean"));
8361
8362 rc = CFGMR3QueryU32Def(pCfg, "CmdSlotsAvail", &pThis->cCmdSlotsAvail, AHCI_NR_COMMAND_SLOTS);
8363 if (RT_FAILURE(rc))
8364 return PDMDEV_SET_ERROR(pDevIns, rc,
8365 N_("AHCI configuration error: failed to read CmdSlotsAvail as integer"));
8366 Log(("%s: cCmdSlotsAvail=%u\n", __FUNCTION__, pThis->cCmdSlotsAvail));
8367 if (pThis->cCmdSlotsAvail > AHCI_NR_COMMAND_SLOTS)
8368 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
8369 N_("AHCI configuration error: CmdSlotsAvail=%u should not exceed %u"),
8370 pThis->cPortsImpl, AHCI_NR_COMMAND_SLOTS);
8371 if (pThis->cCmdSlotsAvail < 1)
8372 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
8373 N_("AHCI configuration error: CmdSlotsAvail=%u should be at least 1"),
8374 pThis->cCmdSlotsAvail);
8375
8376 /*
8377 * Initialize the instance data (everything touched by the destructor need
8378 * to be initialized here!).
8379 */
8380 pThis->fR0Enabled = fR0Enabled;
8381 pThis->fGCEnabled = fGCEnabled;
8382 pThis->pDevInsR3 = pDevIns;
8383 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
8384 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
8385 pThis->pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
8386
8387 PCIDevSetVendorId (&pThis->dev, 0x8086); /* Intel */
8388 PCIDevSetDeviceId (&pThis->dev, 0x2829); /* ICH-8M */
8389 PCIDevSetCommand (&pThis->dev, 0x0000);
8390#ifdef VBOX_WITH_MSI_DEVICES
8391 PCIDevSetStatus (&pThis->dev, VBOX_PCI_STATUS_CAP_LIST);
8392 PCIDevSetCapabilityList(&pThis->dev, 0x80);
8393#else
8394 PCIDevSetCapabilityList(&pThis->dev, 0x70);
8395#endif
8396 PCIDevSetRevisionId (&pThis->dev, 0x02);
8397 PCIDevSetClassProg (&pThis->dev, 0x01);
8398 PCIDevSetClassSub (&pThis->dev, 0x06);
8399 PCIDevSetClassBase (&pThis->dev, 0x01);
8400 PCIDevSetBaseAddress (&pThis->dev, 5, false, false, false, 0x00000000);
8401
8402 PCIDevSetInterruptLine(&pThis->dev, 0x00);
8403 PCIDevSetInterruptPin (&pThis->dev, 0x01);
8404
8405 pThis->dev.config[0x70] = VBOX_PCI_CAP_ID_PM; /* Capability ID: PCI Power Management Interface */
8406 pThis->dev.config[0x71] = 0xa8; /* next */
8407 pThis->dev.config[0x72] = 0x03; /* version ? */
8408
8409 pThis->dev.config[0x90] = 0x40; /* AHCI mode. */
8410 pThis->dev.config[0x92] = 0x3f;
8411 pThis->dev.config[0x94] = 0x80;
8412 pThis->dev.config[0x95] = 0x01;
8413 pThis->dev.config[0x97] = 0x78;
8414
8415 pThis->dev.config[0xa8] = 0x12; /* SATACR capability */
8416 pThis->dev.config[0xa9] = 0x00; /* next */
8417 PCIDevSetWord(&pThis->dev, 0xaa, 0x0010); /* Revision */
8418 PCIDevSetDWord(&pThis->dev, 0xac, 0x00000028); /* SATA Capability Register 1 */
8419
8420 pThis->cThreadsActive = 0;
8421
8422 /* Initialize port members. */
8423 for (i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
8424 {
8425 PAHCIPort pAhciPort = &pThis->ahciPort[i];
8426 pAhciPort->pDevInsR3 = pDevIns;
8427 pAhciPort->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
8428 pAhciPort->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
8429 pAhciPort->iLUN = i;
8430 pAhciPort->pAhciR3 = pThis;
8431 pAhciPort->pAhciR0 = PDMINS_2_DATA_R0PTR(pDevIns);
8432 pAhciPort->pAhciRC = PDMINS_2_DATA_RCPTR(pDevIns);
8433 pAhciPort->Led.u32Magic = PDMLED_MAGIC;
8434 pAhciPort->pDrvBase = NULL;
8435 pAhciPort->pAsyncIOThread = NULL;
8436 pAhciPort->hEvtProcess = NIL_SUPSEMEVENT;
8437 pAhciPort->fHotpluggable = true;
8438 }
8439
8440 /*
8441 * Init locks, using explicit locking where necessary.
8442 */
8443 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
8444 if (RT_FAILURE(rc))
8445 return rc;
8446
8447 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->lock, RT_SRC_POS, "AHCI#%u", iInstance);
8448 if (RT_FAILURE(rc))
8449 {
8450 Log(("%s: Failed to create critical section.\n", __FUNCTION__));
8451 return rc;
8452 }
8453
8454 /*
8455 * Register the PCI device, it's I/O regions.
8456 */
8457 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
8458 if (RT_FAILURE(rc))
8459 return rc;
8460
8461#ifdef VBOX_WITH_MSI_DEVICES
8462 PDMMSIREG MsiReg;
8463 RT_ZERO(MsiReg);
8464 MsiReg.cMsiVectors = 1;
8465 MsiReg.iMsiCapOffset = 0x80;
8466 MsiReg.iMsiNextOffset = 0x70;
8467 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
8468 if (RT_FAILURE(rc))
8469 {
8470 PCIDevSetCapabilityList(&pThis->dev, 0x70);
8471 /* That's OK, we can work without MSI */
8472 }
8473#endif
8474
8475 /*
8476 * Solaris 10 U5 fails to map the AHCI register space when the sets (0..5) for the legacy
8477 * IDE registers are not available.
8478 * We set up "fake" entries in the PCI configuration register.
8479 * That means they are available but read and writes from/to them have no effect.
8480 * No guest should access them anyway because the controller is marked as AHCI in the Programming interface
8481 * and we don't have an option to change to IDE emulation (real hardware provides an option in the BIOS
8482 * to switch to it which also changes device Id and other things in the PCI configuration space).
8483 */
8484 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 8, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
8485 if (RT_FAILURE(rc))
8486 return PDMDEV_SET_ERROR(pDevIns, rc,
8487 N_("AHCI cannot register PCI I/O region"));
8488
8489 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, 1, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
8490 if (RT_FAILURE(rc))
8491 return PDMDEV_SET_ERROR(pDevIns, rc,
8492 N_("AHCI cannot register PCI I/O region"));
8493
8494 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, 8, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
8495 if (RT_FAILURE(rc))
8496 return PDMDEV_SET_ERROR(pDevIns, rc,
8497 N_("AHCI cannot register PCI I/O region"));
8498
8499 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 3, 1, PCI_ADDRESS_SPACE_IO, ahciR3LegacyFakeIORangeMap);
8500 if (RT_FAILURE(rc))
8501 return PDMDEV_SET_ERROR(pDevIns, rc,
8502 N_("AHCI cannot register PCI I/O region"));
8503
8504 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 4, 0x10, PCI_ADDRESS_SPACE_IO, ahciR3IdxDataIORangeMap);
8505 if (RT_FAILURE(rc))
8506 return PDMDEV_SET_ERROR(pDevIns, rc,
8507 N_("AHCI cannot register PCI I/O region for BMDMA"));
8508
8509 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 5, 4352, PCI_ADDRESS_SPACE_MEM, ahciR3MMIOMap);
8510 if (RT_FAILURE(rc))
8511 return PDMDEV_SET_ERROR(pDevIns, rc,
8512 N_("AHCI cannot register PCI memory region for registers"));
8513
8514 /* Create the timer for command completion coalescing feature. */
8515 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, ahciCccTimer, pThis,
8516 TMTIMER_FLAGS_NO_CRIT_SECT, "AHCI CCC Timer", &pThis->pHbaCccTimerR3);
8517 if (RT_FAILURE(rc))
8518 {
8519 AssertMsgFailed(("pfnTMTimerCreate -> %Rrc\n", rc));
8520 return rc;
8521 }
8522 pThis->pHbaCccTimerR0 = TMTimerR0Ptr(pThis->pHbaCccTimerR3);
8523 pThis->pHbaCccTimerRC = TMTimerRCPtr(pThis->pHbaCccTimerR3);
8524
8525 /* Status LUN. */
8526 pThis->IBase.pfnQueryInterface = ahciR3Status_QueryInterface;
8527 pThis->ILeds.pfnQueryStatusLed = ahciR3Status_QueryStatusLed;
8528
8529 /*
8530 * Create the notification queue.
8531 *
8532 * We need 2 items for every port because of SMP races.
8533 */
8534 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(DEVPORTNOTIFIERQUEUEITEM), AHCI_MAX_NR_PORTS_IMPL * 2, 0,
8535 ahciNotifyQueueConsumer, true, "AHCI-Xmit", &pThis->pNotifierQueueR3);
8536 if (RT_FAILURE(rc))
8537 return rc;
8538 pThis->pNotifierQueueR0 = PDMQueueR0Ptr(pThis->pNotifierQueueR3);
8539 pThis->pNotifierQueueRC = PDMQueueRCPtr(pThis->pNotifierQueueR3);
8540
8541 /* Initialize static members on every port. */
8542 for (i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
8543 {
8544 PAHCIPort pAhciPort = &pThis->ahciPort[i];
8545
8546 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatDMA, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
8547 "Number of DMA transfers.", "/Devices/SATA%d/Port%d/DMA", iInstance, i);
8548 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatBytesRead, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_BYTES,
8549 "Amount of data read.", "/Devices/SATA%d/Port%d/ReadBytes", iInstance, i);
8550 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatBytesWritten, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_BYTES,
8551 "Amount of data written.", "/Devices/SATA%d/Port%d/WrittenBytes", iInstance, i);
8552 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatIORequestsPerSecond, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
8553 "Number of processed I/O requests per second.", "/Devices/SATA%d/Port%d/IORequestsPerSecond", iInstance, i);
8554#ifdef VBOX_WITH_STATISTICS
8555 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatProfileProcessTime, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_NS_PER_CALL,
8556 "Amount of time to process one request.", "/Devices/SATA%d/Port%d/ProfileProcessTime", iInstance, i);
8557 PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatProfileReadWrite, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_NS_PER_CALL,
8558 "Amount of time for the read/write operation to complete.", "/Devices/SATA%d/Port%d/ProfileReadWrite", iInstance, i);
8559#endif
8560
8561 ahciPortHwReset(pAhciPort);
8562 }
8563
8564 /* Attach drivers to every available port. */
8565 for (i = 0; i < pThis->cPortsImpl; i++)
8566 {
8567 char szName[24];
8568 RTStrPrintf(szName, sizeof(szName), "Port%u", i);
8569
8570 PAHCIPort pAhciPort = &pThis->ahciPort[i];
8571 /*
8572 * Init interfaces.
8573 */
8574 pAhciPort->IBase.pfnQueryInterface = ahciR3PortQueryInterface;
8575 pAhciPort->IPortAsync.pfnTransferCompleteNotify = ahciR3TransferCompleteNotify;
8576 pAhciPort->IPort.pfnQueryDeviceLocation = ahciR3PortQueryDeviceLocation;
8577 pAhciPort->IMountNotify.pfnMountNotify = ahciR3MountNotify;
8578 pAhciPort->IMountNotify.pfnUnmountNotify = ahciR3UnmountNotify;
8579 pAhciPort->fWrkThreadSleeping = true;
8580
8581 /* Query per port configuration options if available. */
8582 PCFGMNODE pCfgPort = CFGMR3GetChild(pDevIns->pCfg, szName);
8583 if (pCfgPort)
8584 {
8585 rc = CFGMR3QueryBoolDef(pCfgPort, "Hotpluggable", &pAhciPort->fHotpluggable, true);
8586 if (RT_FAILURE(rc))
8587 return PDMDEV_SET_ERROR(pDevIns, rc,
8588 N_("AHCI configuration error: failed to read Hotpluggable as boolean"));
8589 }
8590
8591 /*
8592 * Attach the block driver
8593 */
8594 rc = PDMDevHlpDriverAttach(pDevIns, pAhciPort->iLUN, &pAhciPort->IBase, &pAhciPort->pDrvBase, szName);
8595 if (RT_SUCCESS(rc))
8596 {
8597 rc = ahciR3ConfigureLUN(pDevIns, pAhciPort);
8598 if (RT_FAILURE(rc))
8599 {
8600 Log(("%s: Failed to configure the %s.\n", __FUNCTION__, szName));
8601 return rc;
8602 }
8603
8604 /* Mark that a device is present on that port */
8605 if (i < 6)
8606 pThis->dev.config[0x93] |= (1 << i);
8607
8608 /*
8609 * Init vendor product data.
8610 */
8611 rc = ahciR3VpdInit(pDevIns, pAhciPort, szName);
8612 if (RT_FAILURE(rc))
8613 return rc;
8614
8615 /*
8616 * If the new async interface is available we use a PDMQueue to transmit
8617 * the requests into R3.
8618 * Otherwise we use a event semaphore and a async I/O thread which processes them.
8619 */
8620 if (pAhciPort->pDrvBlockAsync && pThis->fUseAsyncInterfaceIfAvailable)
8621 {
8622 LogRel(("AHCI: LUN#%d: using async I/O\n", pAhciPort->iLUN));
8623 pAhciPort->fAsyncInterface = true;
8624 }
8625 else
8626 {
8627 LogRel(("AHCI: LUN#%d: using normal I/O\n", pAhciPort->iLUN));
8628 pAhciPort->fAsyncInterface = false;
8629 }
8630
8631 rc = SUPSemEventCreate(pThis->pSupDrvSession, &pAhciPort->hEvtProcess);
8632 if (RT_FAILURE(rc))
8633 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
8634 N_("AHCI: Failed to create SUP event semaphore"));
8635
8636 rc = PDMDevHlpThreadCreate(pDevIns, &pAhciPort->pAsyncIOThread, pAhciPort, ahciAsyncIOLoop,
8637 ahciAsyncIOLoopWakeUp, 0, RTTHREADTYPE_IO, szName);
8638 if (RT_FAILURE(rc))
8639 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
8640 N_("AHCI: Failed to create worker thread %s"), szName);
8641 }
8642 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
8643 {
8644 pAhciPort->pDrvBase = NULL;
8645 rc = VINF_SUCCESS;
8646 LogRel(("AHCI: %s: No driver attached\n", szName));
8647 }
8648 else
8649 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
8650 N_("AHCI: Failed to attach drive to %s"), szName);
8651 }
8652
8653 /*
8654 * Attach status driver (optional).
8655 */
8656 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
8657 if (RT_SUCCESS(rc))
8658 {
8659 pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
8660 pThis->pMediaNotify = PDMIBASE_QUERY_INTERFACE(pBase, PDMIMEDIANOTIFY);
8661 }
8662 else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
8663 {
8664 AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
8665 return PDMDEV_SET_ERROR(pDevIns, rc, N_("AHCI cannot attach to status driver"));
8666 }
8667 rc = PDMDevHlpSSMRegisterEx(pDevIns, AHCI_SAVED_STATE_VERSION, sizeof(*pThis) + cbTotalBufferSize, NULL,
8668 NULL, ahciR3LiveExec, NULL,
8669 ahciR3SavePrep, ahciR3SaveExec, NULL,
8670 ahciR3LoadPrep, ahciR3LoadExec, NULL);
8671 if (RT_FAILURE(rc))
8672 return rc;
8673
8674 /*
8675 * Register the info item.
8676 */
8677 char szTmp[128];
8678 RTStrPrintf(szTmp, sizeof(szTmp), "%s%d", pDevIns->pReg->szName, pDevIns->iInstance);
8679 PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "AHCI info", ahciR3Info);
8680
8681 return ahciR3ResetCommon(pDevIns, true /*fConstructor*/);
8682}
8683
8684/**
8685 * The device registration structure.
8686 */
8687const PDMDEVREG g_DeviceAHCI =
8688{
8689 /* u32Version */
8690 PDM_DEVREG_VERSION,
8691 /* szName */
8692 "ahci",
8693 /* szRCMod */
8694 "VBoxDDRC.rc",
8695 /* szR0Mod */
8696 "VBoxDDR0.r0",
8697 /* pszDescription */
8698 "Intel AHCI controller.\n",
8699 /* fFlags */
8700 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 |
8701 PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION | PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION |
8702 PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION,
8703 /* fClass */
8704 PDM_DEVREG_CLASS_STORAGE,
8705 /* cMaxInstances */
8706 ~0U,
8707 /* cbInstance */
8708 sizeof(AHCI),
8709 /* pfnConstruct */
8710 ahciR3Construct,
8711 /* pfnDestruct */
8712 ahciR3Destruct,
8713 /* pfnRelocate */
8714 ahciR3Relocate,
8715 /* pfnMemSetup */
8716 NULL,
8717 /* pfnPowerOn */
8718 NULL,
8719 /* pfnReset */
8720 ahciR3Reset,
8721 /* pfnSuspend */
8722 ahciR3Suspend,
8723 /* pfnResume */
8724 ahciR3Resume,
8725 /* pfnAttach */
8726 ahciR3Attach,
8727 /* pfnDetach */
8728 ahciR3Detach,
8729 /* pfnQueryInterface. */
8730 NULL,
8731 /* pfnInitComplete */
8732 NULL,
8733 /* pfnPowerOff */
8734 ahciR3PowerOff,
8735 /* pfnSoftReset */
8736 NULL,
8737 /* u32VersionEnd */
8738 PDM_DEVREG_VERSION
8739};
8740
8741#endif /* IN_RING3 */
8742#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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