ATAController.h@ 35214

Last change on this file since 35214 was 35214, checked in by vboxsync, 14 years ago
AHCI: Fix wrong Led assignments
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1	/* $Id: ATAController.h 35214 2010-12-17 10:10:07Z vboxsync $ */
2	/** @file
3	* DevATA, DevAHCI - Shared ATA/ATAPI controller types.
4	*/
5
6	/*
7	* Copyright (C) 2006-2008 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___Storage_ATAController_h
19	#define ___Storage_ATAController_h
20
21	/*******************************************************************************
22	* Header Files *
23	*******************************************************************************/
24	#include <VBox/pdmdev.h>
25	#ifdef IN_RING3
26	# include <iprt/semaphore.h>
27	# include <iprt/thread.h>
28	#endif /* IN_RING3 */
29	#include <iprt/critsect.h>
30	#include <VBox/stam.h>
31
32	#include "PIIX3ATABmDma.h"
33	#include "ide.h"
34
35
36	/*******************************************************************************
37	* Defined Constants And Macros *
38	*******************************************************************************/
39	/**
40	* Maximum number of sectors to transfer in a READ/WRITE MULTIPLE request.
41	* Set to 1 to disable multi-sector read support. According to the ATA
42	* specification this must be a power of 2 and it must fit in an 8 bit
43	* value. Thus the only valid values are 1, 2, 4, 8, 16, 32, 64 and 128.
44	*/
45	#define ATA_MAX_MULT_SECTORS 128
46
47	/**
48	* Fastest PIO mode supported by the drive.
49	*/
50	#define ATA_PIO_MODE_MAX 4
51	/**
52	* Fastest MDMA mode supported by the drive.
53	*/
54	#define ATA_MDMA_MODE_MAX 2
55	/**
56	* Fastest UDMA mode supported by the drive.
57	*/
58	#define ATA_UDMA_MODE_MAX 6
59
60	/** ATAPI sense info size. */
61	#define ATAPI_SENSE_SIZE 64
62
63	/** The maximum number of release log entries per device. */
64	#define MAX_LOG_REL_ERRORS 1024
65
66	/* MediaEventStatus */
67	#define ATA_EVENT_STATUS_UNCHANGED 0 /*< medium event status not changed /
68	#define ATA_EVENT_STATUS_MEDIA_NEW 1 /*< new medium inserted /
69	#define ATA_EVENT_STATUS_MEDIA_REMOVED 2 /*< medium removed /
70	#define ATA_EVENT_STATUS_MEDIA_CHANGED 3 /*< medium was removed + new medium was inserted /
71	#define ATA_EVENT_STATUS_MEDIA_EJECT_REQUESTED 4 /*< medium eject requested (eject button pressed) /
72
73
74	/*******************************************************************************
75	* Structures and Typedefs *
76	*******************************************************************************/
77	typedef struct AHCIATADevState {
78	/** Flag indicating whether the current command uses LBA48 mode. */
79	bool fLBA48;
80	/** Flag indicating whether this drive implements the ATAPI command set. */
81	bool fATAPI;
82	/** Set if this interface has asserted the IRQ. */
83	bool fIrqPending;
84	/** Currently configured number of sectors in a multi-sector transfer. */
85	uint8_t cMultSectors;
86	/** PCHS disk geometry. */
87	PDMMEDIAGEOMETRY PCHSGeometry;
88	/** Total number of sectors on this disk. */
89	uint64_t cTotalSectors;
90	/** Number of sectors to transfer per IRQ. */
91	uint32_t cSectorsPerIRQ;
92
93	/** ATA/ATAPI register 1: feature (write-only). */
94	uint8_t uATARegFeature;
95	/** ATA/ATAPI register 1: feature, high order byte. */
96	uint8_t uATARegFeatureHOB;
97	/** ATA/ATAPI register 1: error (read-only). */
98	uint8_t uATARegError;
99	/** ATA/ATAPI register 2: sector count (read/write). */
100	uint8_t uATARegNSector;
101	/** ATA/ATAPI register 2: sector count, high order byte. */
102	uint8_t uATARegNSectorHOB;
103	/** ATA/ATAPI register 3: sector (read/write). */
104	uint8_t uATARegSector;
105	/** ATA/ATAPI register 3: sector, high order byte. */
106	uint8_t uATARegSectorHOB;
107	/** ATA/ATAPI register 4: cylinder low (read/write). */
108	uint8_t uATARegLCyl;
109	/** ATA/ATAPI register 4: cylinder low, high order byte. */
110	uint8_t uATARegLCylHOB;
111	/** ATA/ATAPI register 5: cylinder high (read/write). */
112	uint8_t uATARegHCyl;
113	/** ATA/ATAPI register 5: cylinder high, high order byte. */
114	uint8_t uATARegHCylHOB;
115	/** ATA/ATAPI register 6: select drive/head (read/write). */
116	uint8_t uATARegSelect;
117	/** ATA/ATAPI register 7: status (read-only). */
118	uint8_t uATARegStatus;
119	/** ATA/ATAPI register 7: command (write-only). */
120	uint8_t uATARegCommand;
121	/** ATA/ATAPI drive control register (write-only). */
122	uint8_t uATARegDevCtl;
123
124	/** Currently active transfer mode (MDMA/UDMA) and speed. */
125	uint8_t uATATransferMode;
126	/** Current transfer direction. */
127	uint8_t uTxDir;
128	/** Index of callback for begin transfer. */
129	uint8_t iBeginTransfer;
130	/** Index of callback for source/sink of data. */
131	uint8_t iSourceSink;
132	/** Flag indicating whether the current command transfers data in DMA mode. */
133	bool fDMA;
134	/** Set to indicate that ATAPI transfer semantics must be used. */
135	bool fATAPITransfer;
136
137	/** Total ATA/ATAPI transfer size, shared PIO/DMA. */
138	uint32_t cbTotalTransfer;
139	/** Elementary ATA/ATAPI transfer size, shared PIO/DMA. */
140	uint32_t cbElementaryTransfer;
141	/** Current read/write buffer position, shared PIO/DMA. */
142	uint32_t iIOBufferCur;
143	/** First element beyond end of valid buffer content, shared PIO/DMA. */
144	uint32_t iIOBufferEnd;
145
146	/** ATA/ATAPI current PIO read/write transfer position. Not shared with DMA for safety reasons. */
147	uint32_t iIOBufferPIODataStart;
148	/** ATA/ATAPI current PIO read/write transfer end. Not shared with DMA for safety reasons. */
149	uint32_t iIOBufferPIODataEnd;
150
151	/** ATAPI current LBA position. */
152	uint32_t iATAPILBA;
153	/** ATAPI current sector size. */
154	uint32_t cbATAPISector;
155	/** ATAPI current command. */
156	uint8_t aATAPICmd[ATAPI_PACKET_SIZE];
157	/** ATAPI sense data. */
158	uint8_t abATAPISense[ATAPI_SENSE_SIZE];
159	/** HACK: Countdown till we report a newly unmounted drive as mounted. */
160	uint8_t cNotifiedMediaChange;
161	/** The same for GET_EVENT_STATUS for mechanism */
162	volatile uint32_t MediaEventStatus;
163
164	/** The status LED state for this drive. */
165	R3PTRTYPE(PPDMLED) pLed;
166	#if HC_ARCH_BITS == 64
167	uint32_t uAlignment3;
168	#endif
169
170	/** Size of I/O buffer. */
171	uint32_t cbIOBuffer;
172	/** Pointer to the I/O buffer. */
173	R3PTRTYPE(uint8_t *) pbIOBufferR3;
174	/** Pointer to the I/O buffer. */
175	R0PTRTYPE(uint8_t *) pbIOBufferR0;
176	/** Pointer to the I/O buffer. */
177	RCPTRTYPE(uint8_t *) pbIOBufferRC;
178
179	RTRCPTR Aligmnent1; /*< Align the statistics at an 8-byte boundary. /
180
181	/*
182	* No data that is part of the saved state after this point!!!!!
183	*/
184
185	/* Release statistics: number of ATA DMA commands. */
186	STAMCOUNTER StatATADMA;
187	/* Release statistics: number of ATA PIO commands. */
188	STAMCOUNTER StatATAPIO;
189	/* Release statistics: number of ATAPI PIO commands. */
190	STAMCOUNTER StatATAPIDMA;
191	/* Release statistics: number of ATAPI PIO commands. */
192	STAMCOUNTER StatATAPIPIO;
193	#ifdef VBOX_INSTRUMENT_DMA_WRITES
194	/* Release statistics: number of DMA sector writes and the time spent. */
195	STAMPROFILEADV StatInstrVDWrites;
196	#endif
197
198	/** Statistics: number of read operations and the time spent reading. */
199	STAMPROFILEADV StatReads;
200	/** Statistics: number of bytes read. */
201	R3PTRTYPE(PSTAMCOUNTER) pStatBytesRead;
202	#if HC_ARCH_BITS == 64
203	uint64_t uAlignment4;
204	#endif
205	/** Statistics: number of write operations and the time spent writing. */
206	STAMPROFILEADV StatWrites;
207	/** Statistics: number of bytes written. */
208	R3PTRTYPE(PSTAMCOUNTER) pStatBytesWritten;
209	#if HC_ARCH_BITS == 64
210	uint64_t uAlignment5;
211	#endif
212	/** Statistics: number of flush operations and the time spend flushing. */
213	STAMPROFILE StatFlushes;
214
215	/** Enable passing through commands directly to the ATAPI drive. */
216	bool fATAPIPassthrough;
217	/** Number of errors we've reported to the release log.
218	* This is to prevent flooding caused by something going horribly wrong.
219	* this value against MAX_LOG_REL_ERRORS in places likely to cause floods
220	* like the ones we currently seeing on the linux smoke tests (2006-11-10). */
221	uint32_t cErrors;
222	/** Timestamp of last started command. 0 if no command pending. */
223	uint64_t u64CmdTS;
224
225	/** Pointer to the attached driver's base interface. */
226	R3PTRTYPE(PPDMIBASE) pDrvBase;
227	/** Pointer to the attached driver's block interface. */
228	R3PTRTYPE(PPDMIBLOCK) pDrvBlock;
229	/** Pointer to the attached driver's block bios interface. */
230	R3PTRTYPE(PPDMIBLOCKBIOS) pDrvBlockBios;
231	/** Pointer to the attached driver's mount interface.
232	* This is NULL if the driver isn't a removable unit. */
233	R3PTRTYPE(PPDMIMOUNT) pDrvMount;
234	/** The base interface. */
235	PDMIBASE IBase;
236	/** The block port interface. */
237	PDMIBLOCKPORT IPort;
238	/** The mount notify interface. */
239	PDMIMOUNTNOTIFY IMountNotify;
240	/** The LUN #. */
241	RTUINT iLUN;
242	#if HC_ARCH_BITS == 64
243	RTUINT Alignment2; /*< Align pDevInsR3 correctly. /
244	#endif
245	/** Pointer to device instance. */
246	PPDMDEVINSR3 pDevInsR3;
247	/** Pointer to controller instance. */
248	R3PTRTYPE(struct AHCIATACONTROLLER *) pControllerR3;
249	/** Pointer to device instance. */
250	PPDMDEVINSR0 pDevInsR0;
251	/** Pointer to controller instance. */
252	R0PTRTYPE(struct AHCIATACONTROLLER *) pControllerR0;
253	/** Pointer to device instance. */
254	PPDMDEVINSRC pDevInsRC;
255	/** Pointer to controller instance. */
256	RCPTRTYPE(struct AHCIATACONTROLLER *) pControllerRC;
257	} AHCIATADevState;
258
259
260	typedef struct AHCIATATransferRequest
261	{
262	uint8_t iIf;
263	uint8_t iBeginTransfer;
264	uint8_t iSourceSink;
265	uint32_t cbTotalTransfer;
266	uint8_t uTxDir;
267	} AHCIATATransferRequest;
268
269
270	typedef struct AHCIATAAbortRequest
271	{
272	uint8_t iIf;
273	bool fResetDrive;
274	} AHCIATAAbortRequest;
275
276
277	typedef enum
278	{
279	/** Begin a new transfer. */
280	AHCIATA_AIO_NEW = 0,
281	/** Continue a DMA transfer. */
282	AHCIATA_AIO_DMA,
283	/** Continue a PIO transfer. */
284	AHCIATA_AIO_PIO,
285	/** Reset the drives on current controller, stop all transfer activity. */
286	AHCIATA_AIO_RESET_ASSERTED,
287	/** Reset the drives on current controller, resume operation. */
288	AHCIATA_AIO_RESET_CLEARED,
289	/** Abort the current transfer of a particular drive. */
290	AHCIATA_AIO_ABORT
291	} AHCIATAAIO;
292
293
294	typedef struct AHCIATARequest
295	{
296	AHCIATAAIO ReqType;
297	union
298	{
299	AHCIATATransferRequest t;
300	AHCIATAAbortRequest a;
301	} u;
302	} AHCIATARequest;
303
304
305	typedef struct AHCIATACONTROLLER
306	{
307	/** The base of the first I/O Port range. */
308	RTIOPORT IOPortBase1;
309	/** The base of the second I/O Port range. (0 if none) */
310	RTIOPORT IOPortBase2;
311	/** The assigned IRQ. */
312	RTUINT irq;
313	/** Access critical section */
314	PDMCRITSECT lock;
315
316	/** Selected drive. */
317	uint8_t iSelectedIf;
318	/** The interface on which to handle async I/O. */
319	uint8_t iAIOIf;
320	/** The state of the async I/O thread. */
321	uint8_t uAsyncIOState;
322	/** Flag indicating whether the next transfer is part of the current command. */
323	bool fChainedTransfer;
324	/** Set when the reset processing is currently active on this controller. */
325	bool fReset;
326	/** Flag whether the current transfer needs to be redone. */
327	bool fRedo;
328	/** Flag whether the redo suspend has been finished. */
329	bool fRedoIdle;
330	/** Flag whether the DMA operation to be redone is the final transfer. */
331	bool fRedoDMALastDesc;
332	/** The BusMaster DMA state. */
333	BMDMAState BmDma;
334	/** Pointer to first DMA descriptor. */
335	RTGCPHYS32 pFirstDMADesc;
336	/** Pointer to last DMA descriptor. */
337	RTGCPHYS32 pLastDMADesc;
338	/** Pointer to current DMA buffer (for redo operations). */
339	RTGCPHYS32 pRedoDMABuffer;
340	/** Size of current DMA buffer (for redo operations). */
341	uint32_t cbRedoDMABuffer;
342
343	/** The ATA/ATAPI interfaces of this controller. */
344	AHCIATADevState aIfs[2];
345
346	/** Pointer to device instance. */
347	PPDMDEVINSR3 pDevInsR3;
348	/** Pointer to device instance. */
349	PPDMDEVINSR0 pDevInsR0;
350	/** Pointer to device instance. */
351	PPDMDEVINSRC pDevInsRC;
352
353	/** Set when the destroying the device instance and the thread must exit. */
354	uint32_t volatile fShutdown;
355	/** The async I/O thread handle. NIL_RTTHREAD if no thread. */
356	RTTHREAD AsyncIOThread;
357	/** The event semaphore the thread is waiting on for requests. */
358	RTSEMEVENT AsyncIOSem;
359	/** The request queue for the AIO thread. One element is always unused. */
360	AHCIATARequest aAsyncIORequests[4];
361	/** The position at which to insert a new request for the AIO thread. */
362	uint8_t AsyncIOReqHead;
363	/** The position at which to get a new request for the AIO thread. */
364	uint8_t AsyncIOReqTail;
365	/** Whether to call RTThreadUserSignal and PDMDevHlpAsyncNotificationCompleted
366	* when idle. Before setting this, call RTThreadUserReset. */
367	bool volatile fSignalIdle;
368	uint8_t Alignment3[1]; /*< Explicit padding of the 1 byte gap. /
369	/** Magic delay before triggering interrupts in DMA mode. */
370	uint32_t DelayIRQMillies;
371	/** The mutex protecting the request queue. */
372	RTSEMMUTEX AsyncIORequestMutex;
373	/** The event semaphore the thread is waiting on during suspended I/O. */
374	RTSEMEVENT SuspendIOSem;
375	#if 0 /HC_ARCH_BITS == 32/
376	uint32_t Alignment0;
377	#endif
378
379	/* Statistics */
380	STAMCOUNTER StatAsyncOps;
381	uint64_t StatAsyncMinWait;
382	uint64_t StatAsyncMaxWait;
383	STAMCOUNTER StatAsyncTimeUS;
384	STAMPROFILEADV StatAsyncTime;
385	STAMPROFILE StatLockWait;
386	} AHCIATACONTROLLER, *PAHCIATACONTROLLER;
387
388	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
389
390	#define ATADEVSTATE_2_CONTROLLER(pIf) ( (pIf)->CTX_SUFF(pController) )
391	#define ATADEVSTATE_2_DEVINS(pIf) ( (pIf)->CTX_SUFF(pDevIns) )
392	#define CONTROLLER_2_DEVINS(pController) ( (pController)->CTX_SUFF(pDevIns) )
393	#define PDMIBASE_2_ATASTATE(pInterface) ( (AHCIATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCIATADevState, IBase)) )
394
395
396	/*******************************************************************************
397	* Internal Functions *
398	******************************************************************************/
399	RT_C_DECLS_BEGIN
400	int ataControllerIOPortWrite1(PAHCIATACONTROLLER pCtl, RTIOPORT Port, uint32_t u32, unsigned cb);
401	int ataControllerIOPortRead1(PAHCIATACONTROLLER pCtl, RTIOPORT Port, uint32_t *u32, unsigned cb);
402	int ataControllerIOPortWriteStr1(PAHCIATACONTROLLER pCtl, RTIOPORT Port, RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb);
403	int ataControllerIOPortReadStr1(PAHCIATACONTROLLER pCtl, RTIOPORT Port, RTGCPTR *pGCPtrDst, PRTGCUINTREG pcTransfer, unsigned cb);
404	int ataControllerIOPortWrite2(PAHCIATACONTROLLER pCtl, RTIOPORT Port, uint32_t u32, unsigned cb);
405	int ataControllerIOPortRead2(PAHCIATACONTROLLER pCtl, RTIOPORT Port, uint32_t *u32, unsigned cb);
406	int ataControllerBMDMAIOPortRead(PAHCIATACONTROLLER pCtl, RTIOPORT Port, uint32_t *pu32, unsigned cb);
407	int ataControllerBMDMAIOPortWrite(PAHCIATACONTROLLER pCtl, RTIOPORT Port, uint32_t u32, unsigned cb);
408	RT_C_DECLS_END
409
410	#ifdef IN_RING3
411	/**
412	* Initialize a controller state.
413	*
414	* @returns VBox status code.
415	* @param pDevIns Pointer to the device instance which creates a controller.
416	* @param pCtl Pointer to the unitialized ATA controller structure.
417	* @param pDrvBaseMaster Pointer to the base driver interface which acts as the master.
418	* @param pDrvBaseSlave Pointer to the base driver interface which acts as the slave.
419	* @param pcbSSMState Where to store the size of the device state for loading/saving.
420	* @param szName Name of the controller (Used to initialize the critical section).
421	*/
422	int ataControllerInit(PPDMDEVINS pDevIns, PAHCIATACONTROLLER pCtl,
423	unsigned iLUNMaster, PPDMIBASE pDrvBaseMaster, PPDMLED pLedMaster,
424	PSTAMCOUNTER pStatBytesReadMaster, PSTAMCOUNTER pStatBytesWrittenMaster,
425	unsigned iLUNSlave, PPDMIBASE pDrvBaseSlave, PPDMLED pLedSlave,
426	PSTAMCOUNTER pStatBytesReadSlave, PSTAMCOUNTER pStatBytesWrittenSlave,
427	uint32_t pcbSSMState, const char szName);
428
429	/**
430	* Free all allocated resources for one controller instance.
431	*
432	* @returns VBox status code.
433	* @param pCtl The controller instance.
434	*/
435	int ataControllerDestroy(PAHCIATACONTROLLER pCtl);
436
437	/**
438	* Tests if the controller is idle, leaving the PDM notifications on if busy.
439	*
440	* @returns true if idle, false if idle.
441	* @param pCtl the controller instance.
442	*/
443	bool ataControllerIsIdle(PAHCIATACONTROLLER pCtl);
444
445	/**
446	* Reset a controller instance to an initial state.
447	*
448	* @returns VBox status code.
449	* @param pCtl Pointer to the controller.
450	*/
451	void ataControllerReset(PAHCIATACONTROLLER pCtl);
452
453	/**
454	* Resume operation of an controller.
455	*
456	* @returns nothing
457	* @param pCtl The controller instance.
458	*/
459
460	void ataControllerResume(PAHCIATACONTROLLER pCtl);
461
462	/**
463	* Relocate necessary pointers.
464	*
465	* @returns nothing.
466	* @param pCtl The controller instance.
467	* @param offDelta The relocation delta relative to the old location.
468	*/
469	void ataControllerRelocate(PAHCIATACONTROLLER pCtl, RTGCINTPTR offDelta);
470
471	/**
472	* Execute state save operation.
473	*
474	* @returns VBox status code.
475	* @param pCtl The controller instance.
476	* @param pSSM SSM operation handle.
477	*/
478	int ataControllerSaveExec(PAHCIATACONTROLLER pCtl, PSSMHANDLE pSSM);
479
480	/**
481	* Excute state load operation.
482	*
483	* @returns VBox status code.
484	* @param pCtl The controller instance.
485	* @param pSSM SSM operation handle.
486	*/
487	int ataControllerLoadExec(PAHCIATACONTROLLER pCtl, PSSMHANDLE pSSM);
488
489	/**
490	* Attach command.
491	*
492	* This is called when we change block driver for the DVD drive.
493	*
494	* @returns VBox status code.
495	* @param pDevIns The device instance.
496	* @param iLUN The logical unit which is being detached.
497	*/
498	int ataControllerAttach(PAHCIATACONTROLLER pCtl, PPDMIBASE pDrvBase, bool fMaster);
499
500	/**
501	* Detach notification.
502	*
503	* The DVD drive has been unplugged.
504	*
505	* @param pDevIns The device instance.
506	* @param fMaster True if the master is detached
507	* false for the slave
508	*/
509	void ataControllerDetach(PAHCIATACONTROLLER pCtl, bool fMaster);
510
511	#endif /* IN_RING3 */
512
513	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
514	#endif /* !___Storage_ATAController_h */
515

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source: vbox/trunk/src/VBox/Devices/Storage/ATAController.h@ 35214

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