VirtualBox

source: vbox/trunk/src/VBox/Devices/Storage/ATAController.h@ 11347

Last change on this file since 11347 was 11159, checked in by vboxsync, 16 years ago

GC->RC: ATA and AHCI.
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1/* $Id: ATAController.h 11159 2008-08-05 23:23:18Z vboxsync $ */
2/** @file
3 * DevATA, DevAHCI - Shared ATA/ATAPI controller types.
4 */
5
6/*
7 * Copyright (C) 2006-2008 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___Storage_ATAController_h
23#define ___Storage_ATAController_h
24
25/*******************************************************************************
26* Header Files *
27*******************************************************************************/
28#include <VBox/pdmdev.h>
29#ifdef IN_RING3
30# include <iprt/semaphore.h>
31# include <iprt/thread.h>
32#endif /* IN_RING3 */
33#include <iprt/critsect.h>
34#include <VBox/stam.h>
35
36#include "PIIX3ATABmDma.h"
37#include "ide.h"
38
39
40/*******************************************************************************
41* Defined Constants And Macros *
42*******************************************************************************/
43/**
44 * Maximum number of sectors to transfer in a READ/WRITE MULTIPLE request.
45 * Set to 1 to disable multi-sector read support. According to the ATA
46 * specification this must be a power of 2 and it must fit in an 8 bit
47 * value. Thus the only valid values are 1, 2, 4, 8, 16, 32, 64 and 128.
48 */
49#define ATA_MAX_MULT_SECTORS 128
50
51/**
52 * Fastest PIO mode supported by the drive.
53 */
54#define ATA_PIO_MODE_MAX 4
55/**
56 * Fastest MDMA mode supported by the drive.
57 */
58#define ATA_MDMA_MODE_MAX 2
59/**
60 * Fastest UDMA mode supported by the drive.
61 */
62#define ATA_UDMA_MODE_MAX 6
63
64/** The maximum number of release log entries per device. */
65#define MAX_LOG_REL_ERRORS 1024
66
67
68/*******************************************************************************
69* Structures and Typedefs *
70*******************************************************************************/
71typedef struct ATADevState {
72 /** Flag indicating whether the current command uses LBA48 mode. */
73 bool fLBA48;
74 /** Flag indicating whether this drive implements the ATAPI command set. */
75 bool fATAPI;
76 /** Set if this interface has asserted the IRQ. */
77 bool fIrqPending;
78 /** Currently configured number of sectors in a multi-sector transfer. */
79 uint8_t cMultSectors;
80 /** PCHS disk geometry. */
81 PDMMEDIAGEOMETRY PCHSGeometry;
82 /** Total number of sectors on this disk. */
83 uint64_t cTotalSectors;
84 /** Number of sectors to transfer per IRQ. */
85 uint32_t cSectorsPerIRQ;
86
87 /** ATA/ATAPI register 1: feature (write-only). */
88 uint8_t uATARegFeature;
89 /** ATA/ATAPI register 1: feature, high order byte. */
90 uint8_t uATARegFeatureHOB;
91 /** ATA/ATAPI register 1: error (read-only). */
92 uint8_t uATARegError;
93 /** ATA/ATAPI register 2: sector count (read/write). */
94 uint8_t uATARegNSector;
95 /** ATA/ATAPI register 2: sector count, high order byte. */
96 uint8_t uATARegNSectorHOB;
97 /** ATA/ATAPI register 3: sector (read/write). */
98 uint8_t uATARegSector;
99 /** ATA/ATAPI register 3: sector, high order byte. */
100 uint8_t uATARegSectorHOB;
101 /** ATA/ATAPI register 4: cylinder low (read/write). */
102 uint8_t uATARegLCyl;
103 /** ATA/ATAPI register 4: cylinder low, high order byte. */
104 uint8_t uATARegLCylHOB;
105 /** ATA/ATAPI register 5: cylinder high (read/write). */
106 uint8_t uATARegHCyl;
107 /** ATA/ATAPI register 5: cylinder high, high order byte. */
108 uint8_t uATARegHCylHOB;
109 /** ATA/ATAPI register 6: select drive/head (read/write). */
110 uint8_t uATARegSelect;
111 /** ATA/ATAPI register 7: status (read-only). */
112 uint8_t uATARegStatus;
113 /** ATA/ATAPI register 7: command (write-only). */
114 uint8_t uATARegCommand;
115 /** ATA/ATAPI drive control register (write-only). */
116 uint8_t uATARegDevCtl;
117
118 /** Currently active transfer mode (MDMA/UDMA) and speed. */
119 uint8_t uATATransferMode;
120 /** Current transfer direction. */
121 uint8_t uTxDir;
122 /** Index of callback for begin transfer. */
123 uint8_t iBeginTransfer;
124 /** Index of callback for source/sink of data. */
125 uint8_t iSourceSink;
126 /** Flag indicating whether the current command transfers data in DMA mode. */
127 bool fDMA;
128 /** Set to indicate that ATAPI transfer semantics must be used. */
129 bool fATAPITransfer;
130
131 /** Total ATA/ATAPI transfer size, shared PIO/DMA. */
132 uint32_t cbTotalTransfer;
133 /** Elementary ATA/ATAPI transfer size, shared PIO/DMA. */
134 uint32_t cbElementaryTransfer;
135 /** Current read/write buffer position, shared PIO/DMA. */
136 uint32_t iIOBufferCur;
137 /** First element beyond end of valid buffer content, shared PIO/DMA. */
138 uint32_t iIOBufferEnd;
139
140 /** ATA/ATAPI current PIO read/write transfer position. Not shared with DMA for safety reasons. */
141 uint32_t iIOBufferPIODataStart;
142 /** ATA/ATAPI current PIO read/write transfer end. Not shared with DMA for safety reasons. */
143 uint32_t iIOBufferPIODataEnd;
144
145 /** ATAPI current LBA position. */
146 uint32_t iATAPILBA;
147 /** ATAPI current sector size. */
148 uint32_t cbATAPISector;
149 /** ATAPI current command. */
150 uint8_t aATAPICmd[ATAPI_PACKET_SIZE];
151 /** ATAPI sense key. */
152 uint8_t uATAPISenseKey;
153 /** ATAPI additional sense code. */
154 uint8_t uATAPIASC;
155 /** HACK: Countdown till we report a newly unmounted drive as mounted. */
156 uint8_t cNotifiedMediaChange;
157
158 /** The status LED state for this drive. */
159 PDMLED Led;
160
161 /** Size of I/O buffer. */
162 uint32_t cbIOBuffer;
163 /** Pointer to the I/O buffer. */
164 R3PTRTYPE(uint8_t *) pbIOBufferR3;
165 /** Pointer to the I/O buffer. */
166 R0PTRTYPE(uint8_t *) pbIOBufferR0;
167 /** Pointer to the I/O buffer. */
168 RCPTRTYPE(uint8_t *) pbIOBufferRC;
169#if 1 /*HC_ARCH_BITS == 64*/
170 RTRCPTR Aligmnent0; /**< Align the statistics at an 8-byte boundrary. */
171#endif
172
173 /*
174 * No data that is part of the saved state after this point!!!!!
175 */
176
177 /* Release statistics: number of ATA DMA commands. */
178 STAMCOUNTER StatATADMA;
179 /* Release statistics: number of ATA PIO commands. */
180 STAMCOUNTER StatATAPIO;
181 /* Release statistics: number of ATAPI PIO commands. */
182 STAMCOUNTER StatATAPIDMA;
183 /* Release statistics: number of ATAPI PIO commands. */
184 STAMCOUNTER StatATAPIPIO;
185#ifdef VBOX_INSTRUMENT_DMA_WRITES
186 /* Release statistics: number of DMA sector writes and the time spent. */
187 STAMPROFILEADV StatInstrVDWrites;
188#endif
189
190 /** Statistics: number of read operations and the time spent reading. */
191 STAMPROFILEADV StatReads;
192 /** Statistics: number of bytes read. */
193 STAMCOUNTER StatBytesRead;
194 /** Statistics: number of write operations and the time spent writing. */
195 STAMPROFILEADV StatWrites;
196 /** Statistics: number of bytes written. */
197 STAMCOUNTER StatBytesWritten;
198 /** Statistics: number of flush operations and the time spend flushing. */
199 STAMPROFILE StatFlushes;
200
201 /** Enable passing through commands directly to the ATAPI drive. */
202 bool fATAPIPassthrough;
203 /** Number of errors we've reported to the release log.
204 * This is to prevent flooding caused by something going horribly wrong.
205 * this value against MAX_LOG_REL_ERRORS in places likely to cause floods
206 * like the ones we currently seeing on the linux smoke tests (2006-11-10). */
207 uint32_t cErrors;
208 /** Timestamp of last started command. 0 if no command pending. */
209 uint64_t u64CmdTS;
210
211 /** Pointer to the attached driver's base interface. */
212 R3PTRTYPE(PPDMIBASE) pDrvBase;
213 /** Pointer to the attached driver's block interface. */
214 R3PTRTYPE(PPDMIBLOCK) pDrvBlock;
215 /** Pointer to the attached driver's block bios interface. */
216 R3PTRTYPE(PPDMIBLOCKBIOS) pDrvBlockBios;
217 /** Pointer to the attached driver's mount interface.
218 * This is NULL if the driver isn't a removable unit. */
219 R3PTRTYPE(PPDMIMOUNT) pDrvMount;
220 /** The base interface. */
221 PDMIBASE IBase;
222 /** The block port interface. */
223 PDMIBLOCKPORT IPort;
224 /** The mount notify interface. */
225 PDMIMOUNTNOTIFY IMountNotify;
226 /** The LUN #. */
227 RTUINT iLUN;
228#if HC_ARCH_BITS == 64
229 RTUINT Alignment2; /**< Align pDevInsR3 correctly. */
230#endif
231 /** Pointer to device instance. */
232 PPDMDEVINSR3 pDevInsR3;
233 /** Pointer to controller instance. */
234 R3PTRTYPE(struct ATACONTROLLER *) pControllerR3;
235 /** Pointer to device instance. */
236 PPDMDEVINSR0 pDevInsR0;
237 /** Pointer to controller instance. */
238 R0PTRTYPE(struct ATACONTROLLER *) pControllerR0;
239 /** Pointer to device instance. */
240 PPDMDEVINSRC pDevInsRC;
241 /** Pointer to controller instance. */
242 RCPTRTYPE(struct ATACONTROLLER *) pControllerRC;
243} ATADevState;
244
245
246typedef struct ATATransferRequest
247{
248 uint8_t iIf;
249 uint8_t iBeginTransfer;
250 uint8_t iSourceSink;
251 uint32_t cbTotalTransfer;
252 uint8_t uTxDir;
253} ATATransferRequest;
254
255
256typedef struct ATAAbortRequest
257{
258 uint8_t iIf;
259 bool fResetDrive;
260} ATAAbortRequest;
261
262
263typedef enum
264{
265 /** Begin a new transfer. */
266 ATA_AIO_NEW = 0,
267 /** Continue a DMA transfer. */
268 ATA_AIO_DMA,
269 /** Continue a PIO transfer. */
270 ATA_AIO_PIO,
271 /** Reset the drives on current controller, stop all transfer activity. */
272 ATA_AIO_RESET_ASSERTED,
273 /** Reset the drives on current controller, resume operation. */
274 ATA_AIO_RESET_CLEARED,
275 /** Abort the current transfer of a particular drive. */
276 ATA_AIO_ABORT
277} ATAAIO;
278
279
280typedef struct ATARequest
281{
282 ATAAIO ReqType;
283 union
284 {
285 ATATransferRequest t;
286 ATAAbortRequest a;
287 } u;
288} ATARequest;
289
290
291typedef struct ATACONTROLLER
292{
293 /** The base of the first I/O Port range. */
294 RTIOPORT IOPortBase1;
295 /** The base of the second I/O Port range. (0 if none) */
296 RTIOPORT IOPortBase2;
297 /** The assigned IRQ. */
298 RTUINT irq;
299 /** Access critical section */
300 PDMCRITSECT lock;
301
302 /** Selected drive. */
303 uint8_t iSelectedIf;
304 /** The interface on which to handle async I/O. */
305 uint8_t iAIOIf;
306 /** The state of the async I/O thread. */
307 uint8_t uAsyncIOState;
308 /** Flag indicating whether the next transfer is part of the current command. */
309 bool fChainedTransfer;
310 /** Set when the reset processing is currently active on this controller. */
311 bool fReset;
312 /** Flag whether the current transfer needs to be redone. */
313 bool fRedo;
314 /** Flag whether the redo suspend has been finished. */
315 bool fRedoIdle;
316 /** Flag whether the DMA operation to be redone is the final transfer. */
317 bool fRedoDMALastDesc;
318 /** The BusMaster DMA state. */
319 BMDMAState BmDma;
320 /** Pointer to first DMA descriptor. */
321 RTGCPHYS32 pFirstDMADesc;
322 /** Pointer to last DMA descriptor. */
323 RTGCPHYS32 pLastDMADesc;
324 /** Pointer to current DMA buffer (for redo operations). */
325 RTGCPHYS32 pRedoDMABuffer;
326 /** Size of current DMA buffer (for redo operations). */
327 uint32_t cbRedoDMABuffer;
328
329 /** The ATA/ATAPI interfaces of this controller. */
330 ATADevState aIfs[2];
331
332 /** Pointer to device instance. */
333 PPDMDEVINSR3 pDevInsR3;
334 /** Pointer to device instance. */
335 PPDMDEVINSR0 pDevInsR0;
336 /** Pointer to device instance. */
337 PPDMDEVINSRC pDevInsRC;
338
339 /** Set when the destroying the device instance and the thread must exit. */
340 uint32_t volatile fShutdown;
341 /** The async I/O thread handle. NIL_RTTHREAD if no thread. */
342 RTTHREAD AsyncIOThread;
343 /** The event semaphore the thread is waiting on for requests. */
344 RTSEMEVENT AsyncIOSem;
345 /** The request queue for the AIO thread. One element is always unused. */
346 ATARequest aAsyncIORequests[4];
347 /** The position at which to insert a new request for the AIO thread. */
348 uint8_t AsyncIOReqHead;
349 /** The position at which to get a new request for the AIO thread. */
350 uint8_t AsyncIOReqTail;
351 uint8_t Alignment3[2]; /**< Explicit padding of the 2 byte gap. */
352 /** Magic delay before triggering interrupts in DMA mode. */
353 uint32_t DelayIRQMillies;
354 /** The mutex protecting the request queue. */
355 RTSEMMUTEX AsyncIORequestMutex;
356 /** The event semaphore the thread is waiting on during suspended I/O. */
357 RTSEMEVENT SuspendIOSem;
358#if 0 /*HC_ARCH_BITS == 32*/
359 uint32_t Alignment0;
360#endif
361
362 /* Statistics */
363 STAMCOUNTER StatAsyncOps;
364 uint64_t StatAsyncMinWait;
365 uint64_t StatAsyncMaxWait;
366 STAMCOUNTER StatAsyncTimeUS;
367 STAMPROFILEADV StatAsyncTime;
368 STAMPROFILE StatLockWait;
369} ATACONTROLLER, *PATACONTROLLER;
370
371#ifndef VBOX_DEVICE_STRUCT_TESTCASE
372
373#define ATADEVSTATE_2_CONTROLLER(pIf) ( (pIf)->CTX_SUFF(pController) )
374#define ATADEVSTATE_2_DEVINS(pIf) ( (pIf)->CTX_SUFF(pDevIns) )
375#define CONTROLLER_2_DEVINS(pController) ( (pController)->CTX_SUFF(pDevIns) )
376#define PDMIBASE_2_ATASTATE(pInterface) ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IBase)) )
377
378
379/*******************************************************************************
380 * Internal Functions *
381 ******************************************************************************/
382__BEGIN_DECLS
383int ataControllerIOPortWrite1(PATACONTROLLER pCtl, RTIOPORT Port, uint32_t u32, unsigned cb);
384int ataControllerIOPortRead1(PATACONTROLLER pCtl, RTIOPORT Port, uint32_t *u32, unsigned cb);
385int ataControllerIOPortWriteStr1(PATACONTROLLER pCtl, RTIOPORT Port, RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb);
386int ataControllerIOPortReadStr1(PATACONTROLLER pCtl, RTIOPORT Port, RTGCPTR *pGCPtrDst, PRTGCUINTREG pcTransfer, unsigned cb);
387int ataControllerIOPortWrite2(PATACONTROLLER pCtl, RTIOPORT Port, uint32_t u32, unsigned cb);
388int ataControllerIOPortRead2(PATACONTROLLER pCtl, RTIOPORT Port, uint32_t *u32, unsigned cb);
389int ataControllerBMDMAIOPortRead(PATACONTROLLER pCtl, RTIOPORT Port, uint32_t *pu32, unsigned cb);
390int ataControllerBMDMAIOPortWrite(PATACONTROLLER pCtl, RTIOPORT Port, uint32_t u32, unsigned cb);
391__END_DECLS
392
393#ifdef IN_RING3
394/**
395 * Initialize a controller state.
396 *
397 * @returns VBox status code.
398 * @param pDevIns Pointer to the device instance which creates a controller.
399 * @param pCtl Pointer to the unitialized ATA controller structure.
400 * @param pDrvBaseMaster Pointer to the base driver interface which acts as the master.
401 * @param pDrvBaseSlave Pointer to the base driver interface which acts as the slave.
402 * @param pcbSSMState Where to store the size of the device state for loading/saving.
403 * @param szName Name of the controller (Used to initialize the critical section).
404 */
405int ataControllerInit(PPDMDEVINS pDevIns, PATACONTROLLER pCtl, PPDMIBASE pDrvBaseMaster, PPDMIBASE pDrvBaseSlave,
406 uint32_t *pcbSSMState, const char *szName);
407
408/**
409 * Free all allocated resources for one controller instance.
410 *
411 * @returns VBox status code.
412 * @param pCtl The controller instance.
413 */
414int ataControllerDestroy(PATACONTROLLER pCtl);
415
416/**
417 * Power off a controller.
418 *
419 * @returns nothing.
420 * @param pCtl the controller instance.
421 */
422void ataControllerPowerOff(PATACONTROLLER pCtl);
423
424/**
425 * Reset a controller instance to an initial state.
426 *
427 * @returns VBox status code.
428 * @param pCtl Pointer to the controller.
429 */
430void ataControllerReset(PATACONTROLLER pCtl);
431
432/**
433 * Suspend operation of an controller.
434 *
435 * @returns nothing
436 * @param pCtl The controller instance.
437 */
438void ataControllerSuspend(PATACONTROLLER pCtl);
439
440/**
441 * Resume operation of an controller.
442 *
443 * @returns nothing
444 * @param pCtl The controller instance.
445 */
446
447void ataControllerResume(PATACONTROLLER pCtl);
448
449/**
450 * Relocate neccessary pointers.
451 *
452 * @returns nothing.
453 * @param pCtl The controller instance.
454 * @param offDelta The relocation delta relative to the old location.
455 */
456void ataControllerRelocate(PATACONTROLLER pCtl, RTGCINTPTR offDelta);
457
458/**
459 * Execute state save operation.
460 *
461 * @returns VBox status code.
462 * @param pCtl The controller instance.
463 * @param pSSM SSM operation handle.
464 */
465int ataControllerSaveExec(PATACONTROLLER pCtl, PSSMHANDLE pSSM);
466
467/**
468 * Prepare state save operation.
469 *
470 * @returns VBox status code.
471 * @param pCtl The controller instance.
472 * @param pSSM SSM operation handle.
473 */
474int ataControllerSavePrep(PATACONTROLLER pCtl, PSSMHANDLE pSSM);
475
476/**
477 * Excute state load operation.
478 *
479 * @returns VBox status code.
480 * @param pCtl The controller instance.
481 * @param pSSM SSM operation handle.
482 */
483int ataControllerLoadExec(PATACONTROLLER pCtl, PSSMHANDLE pSSM);
484
485/**
486 * Prepare state load operation.
487 *
488 * @returns VBox status code.
489 * @param pCtl The controller instance.
490 * @param pSSM SSM operation handle.
491 */
492int ataControllerLoadPrep(PATACONTROLLER pCtl, PSSMHANDLE pSSM);
493
494#endif /* IN_RING3 */
495
496#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
497#endif /* !___Storage_ATAController_h */
498
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