| 1 | /* $Id: UartCore.h 98103 2023-01-17 14:15:46Z vboxsync $ */
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| 2 | /** @file
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| 3 | * UartCore - UART (16550A up to 16950) emulation.
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| 4 | *
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| 5 | * The documentation for this device was taken from the PC16550D spec from TI.
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| 6 | */
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| 7 |
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| 8 | /*
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| 9 | * Copyright (C) 2018-2023 Oracle and/or its affiliates.
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| 10 | *
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| 11 | * This file is part of VirtualBox base platform packages, as
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| 12 | * available from https://www.virtualbox.org.
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| 13 | *
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| 14 | * This program is free software; you can redistribute it and/or
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| 15 | * modify it under the terms of the GNU General Public License
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| 16 | * as published by the Free Software Foundation, in version 3 of the
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| 17 | * License.
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| 18 | *
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| 19 | * This program is distributed in the hope that it will be useful, but
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| 20 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 22 | * General Public License for more details.
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| 23 | *
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| 24 | * You should have received a copy of the GNU General Public License
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| 25 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 26 | *
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| 27 | * SPDX-License-Identifier: GPL-3.0-only
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| 28 | */
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| 29 |
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| 30 | #ifndef VBOX_INCLUDED_SRC_Serial_UartCore_h
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| 31 | #define VBOX_INCLUDED_SRC_Serial_UartCore_h
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| 32 | #ifndef RT_WITHOUT_PRAGMA_ONCE
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| 33 | # pragma once
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| 34 | #endif
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| 35 |
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| 36 | #include <VBox/types.h>
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| 37 | #include <VBox/vmm/pdmdev.h>
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| 38 | #include <VBox/vmm/pdmserialifs.h>
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| 39 | #include <VBox/vmm/ssm.h>
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| 40 | #include <iprt/assert.h>
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| 41 |
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| 42 | RT_C_DECLS_BEGIN
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| 43 |
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| 44 | /*********************************************************************************************************************************
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| 45 | * Defined Constants And Macros *
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| 46 | *********************************************************************************************************************************/
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| 47 |
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| 48 | /** The current serial code saved state version. */
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| 49 | #define UART_SAVED_STATE_VERSION 7
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| 50 | /** Saved state version before the TX timer for the connected device case was added. */
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| 51 | #define UART_SAVED_STATE_VERSION_PRE_UNCONNECTED_TX_TIMER 6
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| 52 | /** Saved state version of the legacy code which got replaced after 5.2. */
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| 53 | #define UART_SAVED_STATE_VERSION_LEGACY_CODE 5
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| 54 | /** Includes some missing bits from the previous saved state. */
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| 55 | #define UART_SAVED_STATE_VERSION_MISSING_BITS 4
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| 56 | /** Saved state version when only the 16450 variant was implemented. */
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| 57 | #define UART_SAVED_STATE_VERSION_16450 3
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| 58 |
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| 59 | /** Maximum size of a FIFO. */
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| 60 | #define UART_FIFO_LENGTH_MAX 128
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| 61 |
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| 62 |
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| 63 | /*********************************************************************************************************************************
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| 64 | * Structures and Typedefs *
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| 65 | *********************************************************************************************************************************/
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| 66 |
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| 67 | /** Pointer to the UART core state. */
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| 68 | typedef struct UARTCORE *PUARTCORE;
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| 69 |
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| 70 |
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| 71 | /**
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| 72 | * UART core IRQ request callback to let the core instance raise/clear interrupt requests.
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| 73 | *
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| 74 | * @returns nothing.
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| 75 | * @param pDevIns The owning device instance.
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| 76 | * @param pThis The shared UART core instance data.
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| 77 | * @param iLUN The LUN associated with the UART core.
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| 78 | * @param iLvl The interrupt level.
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| 79 | */
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| 80 | typedef DECLCALLBACKTYPE(void, FNUARTCOREIRQREQ,(PPDMDEVINS pDevIns, PUARTCORE pThis, unsigned iLUN, int iLvl));
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| 81 | /** Pointer to a UART core IRQ request callback. */
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| 82 | typedef FNUARTCOREIRQREQ *PFNUARTCOREIRQREQ;
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| 83 |
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| 84 |
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| 85 | /**
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| 86 | * UART type.
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| 87 | */
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| 88 | typedef enum UARTTYPE
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| 89 | {
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| 90 | /** Invalid UART type. */
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| 91 | UARTTYPE_INVALID = 0,
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| 92 | /** 16450 UART type. */
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| 93 | UARTTYPE_16450,
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| 94 | /** 16550A UART type. */
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| 95 | UARTTYPE_16550A,
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| 96 | /** 16750 UART type. */
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| 97 | UARTTYPE_16750,
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| 98 | /** 32bit hack. */
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| 99 | UARTTYPE_32BIT_HACK = 0x7fffffff
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| 100 | } UARTTYPE;
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| 101 |
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| 102 |
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| 103 | /**
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| 104 | * UART FIFO.
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| 105 | */
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| 106 | typedef struct UARTFIFO
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| 107 | {
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| 108 | /** Fifo size configured. */
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| 109 | uint8_t cbMax;
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| 110 | /** Current amount of bytes used. */
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| 111 | uint8_t cbUsed;
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| 112 | /** Next index to write to. */
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| 113 | uint8_t offWrite;
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| 114 | /** Next index to read from. */
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| 115 | uint8_t offRead;
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| 116 | /** The interrupt trigger level (only used for the receive FIFO). */
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| 117 | uint8_t cbItl;
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| 118 | /** The data in the FIFO. */
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| 119 | uint8_t abBuf[UART_FIFO_LENGTH_MAX];
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| 120 | /** Alignment to a 4 byte boundary. */
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| 121 | uint8_t au8Alignment0[3];
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| 122 | } UARTFIFO;
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| 123 | /** Pointer to a FIFO. */
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| 124 | typedef UARTFIFO *PUARTFIFO;
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| 125 |
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| 126 |
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| 127 | /**
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| 128 | * Shared UART core device state.
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| 129 | *
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| 130 | * @implements PDMIBASE
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| 131 | * @implements PDMISERIALPORT
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| 132 | */
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| 133 | typedef struct UARTCORE
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| 134 | {
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| 135 | /** Access critical section. */
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| 136 | PDMCRITSECT CritSect;
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| 137 | /** The LUN on the owning device instance for this core. */
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| 138 | uint32_t iLUN;
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| 139 | /** Configuration flags. */
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| 140 | uint32_t fFlags;
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| 141 | /** The selected UART type. */
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| 142 | UARTTYPE enmType;
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| 143 |
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| 144 | /** The divisor register (DLAB = 1). */
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| 145 | uint16_t uRegDivisor;
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| 146 | /** The Receiver Buffer Register (RBR, DLAB = 0). */
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| 147 | uint8_t uRegRbr;
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| 148 | /** The Transmitter Holding Register (THR, DLAB = 0). */
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| 149 | uint8_t uRegThr;
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| 150 | /** The Interrupt Enable Register (IER, DLAB = 0). */
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| 151 | uint8_t uRegIer;
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| 152 | /** The Interrupt Identification Register (IIR). */
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| 153 | uint8_t uRegIir;
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| 154 | /** The FIFO Control Register (FCR). */
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| 155 | uint8_t uRegFcr;
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| 156 | /** The Line Control Register (LCR). */
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| 157 | uint8_t uRegLcr;
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| 158 | /** The Modem Control Register (MCR). */
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| 159 | uint8_t uRegMcr;
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| 160 | /** The Line Status Register (LSR). */
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| 161 | uint8_t uRegLsr;
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| 162 | /** The Modem Status Register (MSR). */
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| 163 | uint8_t uRegMsr;
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| 164 | /** The Scratch Register (SCR). */
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| 165 | uint8_t uRegScr;
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| 166 |
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| 167 | /** Timer handle for the character timeout indication. */
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| 168 | TMTIMERHANDLE hTimerRcvFifoTimeout;
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| 169 | /** Timer handle for the send loop if no driver is connected/loopback mode is active. */
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| 170 | TMTIMERHANDLE hTimerTxUnconnected;
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| 171 |
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| 172 | /** Flag whether a character timeout interrupt is pending
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| 173 | * (no symbols were inserted or removed from the receive FIFO
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| 174 | * during an 4 times the character transmit/receive period and the FIFO
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| 175 | * is not empty). */
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| 176 | bool fIrqCtiPending;
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| 177 | /** Flag whether the transmitter holding register went empty since last time the
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| 178 | * IIR register was read. This gets reset when IIR is read so the guest will get this
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| 179 | * interrupt ID only once. */
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| 180 | bool fThreEmptyPending;
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| 181 | /** Explicit alignment. */
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| 182 | bool afAlignment1[2];
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| 183 | /** The transmit FIFO. */
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| 184 | UARTFIFO FifoXmit;
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| 185 | /** The receive FIFO. */
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| 186 | UARTFIFO FifoRecv;
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| 187 |
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| 188 | /** Time it takes to transmit/receive a single symbol in timer ticks. */
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| 189 | uint64_t cSymbolXferTicks;
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| 190 | /** Number of bytes available for reading from the layer below. */
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| 191 | volatile uint32_t cbAvailRdr;
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| 192 | /** Explicit alignment. */
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| 193 | uint32_t u32Alignment2;
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| 194 | } UARTCORE;
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| 195 | AssertCompileSizeAlignment(UARTCORE, 8);
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| 196 |
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| 197 |
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| 198 | /**
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| 199 | * Ring-3 UART core device state.
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| 200 | *
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| 201 | * @implements PDMIBASE
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| 202 | * @implements PDMISERIALPORT
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| 203 | */
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| 204 | typedef struct UARTCORER3
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| 205 | {
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| 206 | /** The LUN on the owning device instance for this core. */
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| 207 | uint32_t iLUN;
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| 208 | uint32_t u32Padding;
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| 209 | /** LUN\#0: The base interface. */
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| 210 | PDMIBASE IBase;
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| 211 | /** LUN\#0: The serial port interface. */
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| 212 | PDMISERIALPORT ISerialPort;
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| 213 | /** Pointer to the attached base driver. */
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| 214 | R3PTRTYPE(PPDMIBASE) pDrvBase;
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| 215 | /** Pointer to the attached serial driver. */
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| 216 | R3PTRTYPE(PPDMISERIALCONNECTOR) pDrvSerial;
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| 217 |
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| 218 | /** Interrupt request callback of the owning device. */
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| 219 | R3PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReq;
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| 220 |
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| 221 | /** Pointer to the shared data - for timers callbacks and interface methods
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| 222 | * only. */
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| 223 | R3PTRTYPE(PUARTCORE) pShared;
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| 224 | /** Pointer to the device instance - only for getting our bearings in
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| 225 | * interface methods. */
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| 226 | PPDMDEVINS pDevIns;
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| 227 | } UARTCORER3;
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| 228 | /** Pointer to the core ring-3 UART device state. */
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| 229 | typedef UARTCORER3 *PUARTCORER3;
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| 230 |
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| 231 |
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| 232 | /**
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| 233 | * Ring-0 UART core device state.
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| 234 | */
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| 235 | typedef struct UARTCORER0
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| 236 | {
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| 237 | /** Interrupt request callback of the owning device. */
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| 238 | R0PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReq;
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| 239 | } UARTCORER0;
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| 240 | /** Pointer to the core ring-0 UART device state. */
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| 241 | typedef UARTCORER0 *PUARTCORER0;
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| 242 |
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| 243 |
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| 244 | /**
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| 245 | * Raw-mode UART core device state.
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| 246 | */
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| 247 | typedef struct UARTCORERC
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| 248 | {
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| 249 | /** Interrupt request callback of the owning device. */
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| 250 | R0PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReq;
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| 251 | } UARTCORERC;
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| 252 | /** Pointer to the core raw-mode UART device state. */
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| 253 | typedef UARTCORERC *PUARTCORERC;
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| 254 |
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| 255 |
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| 256 | /** Current context UAR core device state. */
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| 257 | typedef CTX_SUFF(UARTCORE) UARTCORECC;
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| 258 | /** Pointer to the current context UAR core device state. */
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| 259 | typedef CTX_SUFF(PUARTCORE) PUARTCORECC;
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| 260 |
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| 261 |
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| 262 | #ifndef VBOX_DEVICE_STRUCT_TESTCASE
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| 263 |
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| 264 | /** Flag whether to yield the CPU on an LSR read. */
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| 265 | #define UART_CORE_YIELD_ON_LSR_READ RT_BIT_32(0)
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| 266 |
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| 267 | DECLHIDDEN(VBOXSTRICTRC) uartRegWrite(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC,
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| 268 | uint32_t uReg, uint32_t u32, size_t cb);
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| 269 | DECLHIDDEN(VBOXSTRICTRC) uartRegRead(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC,
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| 270 | uint32_t uReg, uint32_t *pu32, size_t cb);
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| 271 |
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| 272 | # ifdef IN_RING3
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| 273 | DECLHIDDEN(int) uartR3Init(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC,
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| 274 | UARTTYPE enmType, unsigned iLUN, uint32_t fFlags, PFNUARTCOREIRQREQ pfnUartIrqReq);
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| 275 | DECLHIDDEN(void) uartR3Destruct(PPDMDEVINS pDevIns, PUARTCORE pThis);
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| 276 | DECLHIDDEN(void) uartR3Detach(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC);
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| 277 | DECLHIDDEN(int) uartR3Attach(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, unsigned iLUN);
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| 278 | DECLHIDDEN(void) uartR3Reset(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC);
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| 279 | DECLHIDDEN(int) uartR3SaveExec(PPDMDEVINS pDevIns, PUARTCORE pThis, PSSMHANDLE pSSM);
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| 280 | DECLHIDDEN(int) uartR3LoadExec(PPDMDEVINS pDevIns, PUARTCORE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass,
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| 281 | uint8_t *puIrq, RTIOPORT *pPortBase);
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| 282 | DECLHIDDEN(int) uartR3LoadDone(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, PSSMHANDLE pSSM);
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| 283 |
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| 284 | # endif /* IN_RING3 */
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| 285 | # if !defined(IN_RING3) || defined(DOXYGEN_RUNNING)
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| 286 | DECLHIDDEN(int) uartRZInit(PUARTCORECC pThisCC, PFNUARTCOREIRQREQ pfnUartIrqReq);
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| 287 | # endif
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| 288 |
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| 289 | #endif
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| 290 |
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| 291 | RT_C_DECLS_END
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| 292 |
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| 293 | #endif /* !VBOX_INCLUDED_SRC_Serial_UartCore_h */
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