VirtualBox

source: vbox/trunk/src/VBox/Devices/Serial/UartCore.cpp@ 93492

Last change on this file since 93492 was 93115, checked in by vboxsync, 3 years ago

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1/* $Id: UartCore.cpp 93115 2022-01-01 11:31:46Z vboxsync $ */
2/** @file
3 * UartCore - UART (16550A up to 16950) emulation.
4 *
5 * The documentation for this device was taken from the PC16550D spec from TI.
6 */
7
8/*
9 * Copyright (C) 2018-2022 Oracle Corporation
10 *
11 * This file is part of VirtualBox Open Source Edition (OSE), as
12 * available from http://www.virtualbox.org. This file is free software;
13 * you can redistribute it and/or modify it under the terms of the GNU
14 * General Public License (GPL) as published by the Free Software
15 * Foundation, in version 2 as it comes in the "COPYING" file of the
16 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18 */
19
20
21/*********************************************************************************************************************************
22* Header Files *
23*********************************************************************************************************************************/
24#define LOG_GROUP LOG_GROUP_DEV_SERIAL
25#include <VBox/vmm/tm.h>
26#include <iprt/log.h>
27#include <iprt/uuid.h>
28#include <iprt/assert.h>
29
30#include "VBoxDD.h"
31#include "UartCore.h"
32
33
34/*********************************************************************************************************************************
35* Defined Constants And Macros *
36*********************************************************************************************************************************/
37
38/** The RBR/DLL register index (from the base of the port range). */
39#define UART_REG_RBR_DLL_INDEX 0
40
41/** The THR/DLL register index (from the base of the port range). */
42#define UART_REG_THR_DLL_INDEX 0
43
44/** The IER/DLM register index (from the base of the port range). */
45#define UART_REG_IER_DLM_INDEX 1
46/** Enable received data available interrupt */
47# define UART_REG_IER_ERBFI RT_BIT(0)
48/** Enable transmitter holding register empty interrupt */
49# define UART_REG_IER_ETBEI RT_BIT(1)
50/** Enable receiver line status interrupt */
51# define UART_REG_IER_ELSI RT_BIT(2)
52/** Enable modem status interrupt. */
53# define UART_REG_IER_EDSSI RT_BIT(3)
54/** Sleep mode enable. */
55# define UART_REG_IER_SLEEP_MODE_EN RT_BIT(4)
56/** Low power mode enable. */
57# define UART_REG_IER_LP_MODE_EN RT_BIT(5)
58/** Mask of writeable bits. */
59# define UART_REG_IER_MASK_WR 0x0f
60/** Mask of writeable bits for 16750+. */
61# define UART_REG_IER_MASK_WR_16750 0x3f
62
63/** The IIR register index (from the base of the port range). */
64#define UART_REG_IIR_INDEX 2
65/** Interrupt Pending - high means no interrupt pending. */
66# define UART_REG_IIR_IP_NO_INT RT_BIT(0)
67/** Interrupt identification mask. */
68# define UART_REG_IIR_ID_MASK 0x0e
69/** Sets the interrupt identification to the given value. */
70# define UART_REG_IIR_ID_SET(a_Val) (((a_Val) << 1) & UART_REG_IIR_ID_MASK)
71/** Gets the interrupt identification from the given IIR register value. */
72# define UART_REG_IIR_ID_GET(a_Val) (((a_Val) & UART_REG_IIR_ID_MASK) >> 1)
73/** Receiver Line Status interrupt. */
74# define UART_REG_IIR_ID_RCL 0x3
75/** Received Data Available interrupt. */
76# define UART_REG_IIR_ID_RDA 0x2
77/** Character Timeou Indicator interrupt. */
78# define UART_REG_IIR_ID_CTI 0x6
79/** Transmitter Holding Register Empty interrupt. */
80# define UART_REG_IIR_ID_THRE 0x1
81/** Modem Status interrupt. */
82# define UART_REG_IIR_ID_MS 0x0
83/** 64 byte FIFOs enabled (15750+ only). */
84# define UART_REG_IIR_64BYTE_FIFOS_EN RT_BIT(5)
85/** FIFOs enabled. */
86# define UART_REG_IIR_FIFOS_EN 0xc0
87/** Bits relevant for checking whether the interrupt status has changed. */
88# define UART_REG_IIR_CHANGED_MASK 0x0f
89
90/** The FCR register index (from the base of the port range). */
91#define UART_REG_FCR_INDEX 2
92/** Enable the TX/RX FIFOs. */
93# define UART_REG_FCR_FIFO_EN RT_BIT(0)
94/** Reset the receive FIFO. */
95# define UART_REG_FCR_RCV_FIFO_RST RT_BIT(1)
96/** Reset the transmit FIFO. */
97# define UART_REG_FCR_XMIT_FIFO_RST RT_BIT(2)
98/** DMA Mode Select. */
99# define UART_REG_FCR_DMA_MODE_SEL RT_BIT(3)
100/** 64 Byte FIFO enable (15750+ only). */
101# define UART_REG_FCR_64BYTE_FIFO_EN RT_BIT(5)
102/** Receiver level interrupt trigger. */
103# define UART_REG_FCR_RCV_LVL_IRQ_MASK 0xc0
104/** Returns the receive level trigger value from the given FCR register. */
105# define UART_REG_FCR_RCV_LVL_IRQ_GET(a_Fcr) (((a_Fcr) & UART_REG_FCR_RCV_LVL_IRQ_MASK) >> 6)
106/** RCV Interrupt trigger level - 1 byte. */
107# define UART_REG_FCR_RCV_LVL_IRQ_1 0x0
108/** RCV Interrupt trigger level - 4 bytes. */
109# define UART_REG_FCR_RCV_LVL_IRQ_4 0x1
110/** RCV Interrupt trigger level - 8 bytes. */
111# define UART_REG_FCR_RCV_LVL_IRQ_8 0x2
112/** RCV Interrupt trigger level - 14 bytes. */
113# define UART_REG_FCR_RCV_LVL_IRQ_14 0x3
114/** Mask of writeable bits. */
115# define UART_REG_FCR_MASK_WR 0xcf
116/** Mask of sticky bits. */
117# define UART_REG_FCR_MASK_STICKY 0xe9
118
119/** The LCR register index (from the base of the port range). */
120#define UART_REG_LCR_INDEX 3
121/** Word Length Select Mask. */
122# define UART_REG_LCR_WLS_MASK 0x3
123/** Returns the WLS value form the given LCR register value. */
124# define UART_REG_LCR_WLS_GET(a_Lcr) ((a_Lcr) & UART_REG_LCR_WLS_MASK)
125/** Number of stop bits. */
126# define UART_REG_LCR_STB RT_BIT(2)
127/** Parity Enable. */
128# define UART_REG_LCR_PEN RT_BIT(3)
129/** Even Parity. */
130# define UART_REG_LCR_EPS RT_BIT(4)
131/** Stick parity. */
132# define UART_REG_LCR_PAR_STICK RT_BIT(5)
133/** Set Break. */
134# define UART_REG_LCR_BRK_SET RT_BIT(6)
135/** Divisor Latch Access Bit. */
136# define UART_REG_LCR_DLAB RT_BIT(7)
137
138/** The MCR register index (from the base of the port range). */
139#define UART_REG_MCR_INDEX 4
140/** Data Terminal Ready. */
141# define UART_REG_MCR_DTR RT_BIT(0)
142/** Request To Send. */
143# define UART_REG_MCR_RTS RT_BIT(1)
144/** Out1. */
145# define UART_REG_MCR_OUT1 RT_BIT(2)
146/** Out2. */
147# define UART_REG_MCR_OUT2 RT_BIT(3)
148/** Loopback connection. */
149# define UART_REG_MCR_LOOP RT_BIT(4)
150/** Flow Control Enable (15750+ only). */
151# define UART_REG_MCR_AFE RT_BIT(5)
152/** Mask of writeable bits (15450 and 15550A). */
153# define UART_REG_MCR_MASK_WR 0x1f
154/** Mask of writeable bits (15750+). */
155# define UART_REG_MCR_MASK_WR_15750 0x3f
156
157/** The LSR register index (from the base of the port range). */
158#define UART_REG_LSR_INDEX 5
159/** Data Ready. */
160# define UART_REG_LSR_DR RT_BIT(0)
161/** Overrun Error. */
162# define UART_REG_LSR_OE RT_BIT(1)
163/** Parity Error. */
164# define UART_REG_LSR_PE RT_BIT(2)
165/** Framing Error. */
166# define UART_REG_LSR_FE RT_BIT(3)
167/** Break Interrupt. */
168# define UART_REG_LSR_BI RT_BIT(4)
169/** Transmitter Holding Register. */
170# define UART_REG_LSR_THRE RT_BIT(5)
171/** Transmitter Empty. */
172# define UART_REG_LSR_TEMT RT_BIT(6)
173/** Error in receiver FIFO. */
174# define UART_REG_LSR_RCV_FIFO_ERR RT_BIT(7)
175/** The bits to check in this register when checking for the RCL interrupt. */
176# define UART_REG_LSR_BITS_IIR_RCL 0x1e
177
178/** The MSR register index (from the base of the port range). */
179#define UART_REG_MSR_INDEX 6
180/** Delta Clear to Send. */
181# define UART_REG_MSR_DCTS RT_BIT(0)
182/** Delta Data Set Ready. */
183# define UART_REG_MSR_DDSR RT_BIT(1)
184/** Trailing Edge Ring Indicator. */
185# define UART_REG_MSR_TERI RT_BIT(2)
186/** Delta Data Carrier Detect. */
187# define UART_REG_MSR_DDCD RT_BIT(3)
188/** Clear to Send. */
189# define UART_REG_MSR_CTS RT_BIT(4)
190/** Data Set Ready. */
191# define UART_REG_MSR_DSR RT_BIT(5)
192/** Ring Indicator. */
193# define UART_REG_MSR_RI RT_BIT(6)
194/** Data Carrier Detect. */
195# define UART_REG_MSR_DCD RT_BIT(7)
196/** The bits to check in this register when checking for the MS interrupt. */
197# define UART_REG_MSR_BITS_IIR_MS 0x0f
198
199/** The SCR register index (from the base of the port range). */
200#define UART_REG_SCR_INDEX 7
201
202/** Set the specified bits in the given register. */
203#define UART_REG_SET(a_Reg, a_Set) ((a_Reg) |= (a_Set))
204/** Clear the specified bits in the given register. */
205#define UART_REG_CLR(a_Reg, a_Clr) ((a_Reg) &= ~(a_Clr))
206
207
208/*********************************************************************************************************************************
209* Structures and Typedefs *
210*********************************************************************************************************************************/
211
212#ifndef VBOX_DEVICE_STRUCT_TESTCASE
213
214
215/*********************************************************************************************************************************
216* Global Variables *
217*********************************************************************************************************************************/
218
219#ifdef IN_RING3
220/**
221 * FIFO ITL levels.
222 */
223static struct
224{
225 /** ITL level for a 16byte FIFO. */
226 uint8_t cbItl16;
227 /** ITL level for a 64byte FIFO. */
228 uint8_t cbItl64;
229} s_aFifoItl[] =
230{
231 /* cbItl16 cbItl64 */
232 { 1, 1 },
233 { 4, 16 },
234 { 8, 32 },
235 { 14, 56 }
236};
237
238
239/**
240 * String versions of the parity enum.
241 */
242static const char *s_aszParity[] =
243{
244 "INVALID",
245 "NONE",
246 "EVEN",
247 "ODD",
248 "MARK",
249 "SPACE",
250 "INVALID"
251};
252
253
254/**
255 * String versions of the stop bits enum.
256 */
257static const char *s_aszStopBits[] =
258{
259 "INVALID",
260 "1",
261 "1.5",
262 "2",
263 "INVALID"
264};
265#endif
266
267
268/*********************************************************************************************************************************
269* Internal Functions *
270*********************************************************************************************************************************/
271
272
273/**
274 * Updates the IRQ state based on the current device state.
275 *
276 * @returns nothing.
277 * @param pDevIns The device instance.
278 * @param pThis The shared serial port instance data.
279 * @param pThisCC The serial port instance data for the current context.
280 */
281static void uartIrqUpdate(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
282{
283 LogFlowFunc(("pThis=%#p\n", pThis));
284
285 /*
286 * The interrupt uses a priority scheme, only the interrupt with the
287 * highest priority is indicated in the interrupt identification register.
288 *
289 * The priorities are as follows (high to low):
290 * * Receiver line status
291 * * Received data available
292 * * Character timeout indication (only in FIFO mode).
293 * * Transmitter holding register empty
294 * * Modem status change.
295 */
296 uint8_t uRegIirNew = UART_REG_IIR_IP_NO_INT;
297 if ( (pThis->uRegLsr & UART_REG_LSR_BITS_IIR_RCL)
298 && (pThis->uRegIer & UART_REG_IER_ELSI))
299 uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RCL);
300 else if ( (pThis->uRegIer & UART_REG_IER_ERBFI)
301 && pThis->fIrqCtiPending)
302 uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_CTI);
303 else if ( (pThis->uRegLsr & UART_REG_LSR_DR)
304 && (pThis->uRegIer & UART_REG_IER_ERBFI)
305 && ( !(pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
306 || pThis->FifoRecv.cbUsed >= pThis->FifoRecv.cbItl))
307 uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RDA);
308 else if ( (pThis->uRegIer & UART_REG_IER_ETBEI)
309 && pThis->fThreEmptyPending)
310 uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_THRE);
311 else if ( (pThis->uRegMsr & UART_REG_MSR_BITS_IIR_MS)
312 && (pThis->uRegIer & UART_REG_IER_EDSSI))
313 uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_MS);
314
315 LogFlowFunc((" uRegIirNew=%#x uRegIir=%#x\n", uRegIirNew, pThis->uRegIir));
316
317 if (uRegIirNew != (pThis->uRegIir & UART_REG_IIR_CHANGED_MASK))
318 LogFlow((" Interrupt source changed from %#x -> %#x (IRQ %d -> %d)\n",
319 pThis->uRegIir, uRegIirNew,
320 pThis->uRegIir == UART_REG_IIR_IP_NO_INT ? 0 : 1,
321 uRegIirNew == UART_REG_IIR_IP_NO_INT ? 0 : 1));
322 else
323 LogFlow((" No change in interrupt source\n"));
324
325 /*
326 * Set interrupt value accordingly. As this is an ISA device most guests
327 * configure the IRQ as edge triggered instead of level triggered.
328 * So this needs to be done everytime, even if the internal interrupt state
329 * doesn't change in order to avoid the guest losing interrupts (reading one byte at
330 * a time from the FIFO for instance which doesn't change the interrupt source).
331 */
332 if (uRegIirNew == UART_REG_IIR_IP_NO_INT)
333 pThisCC->pfnUartIrqReq(pDevIns, pThis, pThis->iLUN, 0);
334 else
335 pThisCC->pfnUartIrqReq(pDevIns, pThis, pThis->iLUN, 1);
336
337 if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
338 uRegIirNew |= UART_REG_IIR_FIFOS_EN;
339 if (pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN)
340 uRegIirNew |= UART_REG_IIR_64BYTE_FIFOS_EN;
341
342 pThis->uRegIir = uRegIirNew;
343}
344
345
346/**
347 * Returns the amount of bytes stored in the given FIFO.
348 *
349 * @returns Amount of bytes stored in the FIFO.
350 * @param pFifo The FIFO.
351 */
352DECLINLINE(size_t) uartFifoUsedGet(PUARTFIFO pFifo)
353{
354 return pFifo->cbUsed;
355}
356
357
358/**
359 * Puts a new character into the given FIFO.
360 *
361 * @returns Flag whether the FIFO overflowed.
362 * @param pFifo The FIFO to put the data into.
363 * @param fOvrWr Flag whether to overwrite data if the FIFO is full.
364 * @param bData The data to add.
365 */
366DECLINLINE(bool) uartFifoPut(PUARTFIFO pFifo, bool fOvrWr, uint8_t bData)
367{
368 if (fOvrWr || pFifo->cbUsed < pFifo->cbMax)
369 {
370 pFifo->abBuf[pFifo->offWrite] = bData;
371 pFifo->offWrite = (pFifo->offWrite + 1) % pFifo->cbMax;
372 }
373
374 bool fOverFlow = false;
375 if (pFifo->cbUsed < pFifo->cbMax)
376 pFifo->cbUsed++;
377 else
378 {
379 fOverFlow = true;
380 if (fOvrWr) /* Advance the read position to account for the lost character. */
381 pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
382 }
383
384 return fOverFlow;
385}
386
387
388/**
389 * Returns the next character in the FIFO.
390 *
391 * @return Next byte in the FIFO.
392 * @param pFifo The FIFO to get data from.
393 */
394DECLINLINE(uint8_t) uartFifoGet(PUARTFIFO pFifo)
395{
396 uint8_t bRet = 0;
397
398 if (pFifo->cbUsed)
399 {
400 bRet = pFifo->abBuf[pFifo->offRead];
401 pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
402 pFifo->cbUsed--;
403 }
404
405 return bRet;
406}
407
408#ifdef IN_RING3
409
410/**
411 * Clears the given FIFO.
412 *
413 * @returns nothing.
414 * @param pFifo The FIFO to clear.
415 */
416DECLINLINE(void) uartFifoClear(PUARTFIFO pFifo)
417{
418 memset(&pFifo->abBuf[0], 0, sizeof(pFifo->abBuf));
419 pFifo->cbUsed = 0;
420 pFifo->offWrite = 0;
421 pFifo->offRead = 0;
422}
423
424
425/**
426 * Returns the amount of free bytes in the given FIFO.
427 *
428 * @returns The amount of bytes free in the given FIFO.
429 * @param pFifo The FIFO.
430 */
431DECLINLINE(size_t) uartFifoFreeGet(PUARTFIFO pFifo)
432{
433 return pFifo->cbMax - pFifo->cbUsed;
434}
435
436
437/**
438 * Tries to copy the requested amount of data from the given FIFO into the provided buffer.
439 *
440 * @returns Amount of bytes actually copied.
441 * @param pFifo The FIFO to copy data from.
442 * @param pvDst Where to copy the data to.
443 * @param cbCopy How much to copy.
444 */
445DECLINLINE(size_t) uartFifoCopyTo(PUARTFIFO pFifo, void *pvDst, size_t cbCopy)
446{
447 size_t cbCopied = 0;
448 uint8_t *pbDst = (uint8_t *)pvDst;
449
450 cbCopy = RT_MIN(cbCopy, pFifo->cbUsed);
451 while (cbCopy)
452 {
453 uint8_t cbThisCopy = (uint8_t)RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offRead));
454 memcpy(pbDst, &pFifo->abBuf[pFifo->offRead], cbThisCopy);
455
456 pFifo->offRead = (pFifo->offRead + cbThisCopy) % pFifo->cbMax;
457 pFifo->cbUsed -= cbThisCopy;
458 pbDst += cbThisCopy;
459 cbCopied += cbThisCopy;
460 cbCopy -= cbThisCopy;
461 }
462
463 return cbCopied;
464}
465
466
467#if 0 /* unused */
468/**
469 * Tries to copy the requested amount of data from the provided buffer into the given FIFO.
470 *
471 * @returns Amount of bytes actually copied.
472 * @param pFifo The FIFO to copy data to.
473 * @param pvSrc Where to copy the data from.
474 * @param cbCopy How much to copy.
475 */
476DECLINLINE(size_t) uartFifoCopyFrom(PUARTFIFO pFifo, void *pvSrc, size_t cbCopy)
477{
478 size_t cbCopied = 0;
479 uint8_t *pbSrc = (uint8_t *)pvSrc;
480
481 cbCopy = RT_MIN(cbCopy, uartFifoFreeGet(pFifo));
482 while (cbCopy)
483 {
484 uint8_t cbThisCopy = (uint8_t)RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
485 memcpy(&pFifo->abBuf[pFifo->offWrite], pbSrc, cbThisCopy);
486
487 pFifo->offWrite = (pFifo->offWrite + cbThisCopy) % pFifo->cbMax;
488 pFifo->cbUsed += cbThisCopy;
489 pbSrc += cbThisCopy;
490 cbCopied += cbThisCopy;
491 cbCopy -= cbThisCopy;
492 }
493
494 return cbCopied;
495}
496#endif
497
498
499/**
500 * Updates the delta bits for the given MSR register value which has the status line
501 * bits set.
502 *
503 * @returns nothing.
504 * @param pDevIns The device instance.
505 * @param pThis The shared serial port instance data.
506 * @param pThisCC The serial port instance data for the current context.
507 * @param uMsrSts MSR value with the appropriate status bits set.
508 */
509static void uartR3MsrUpdate(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t uMsrSts)
510{
511 /* Compare current and new states and set remaining bits accordingly. */
512 if ((uMsrSts & UART_REG_MSR_CTS) != (pThis->uRegMsr & UART_REG_MSR_CTS))
513 uMsrSts |= UART_REG_MSR_DCTS;
514 if ((uMsrSts & UART_REG_MSR_DSR) != (pThis->uRegMsr & UART_REG_MSR_DSR))
515 uMsrSts |= UART_REG_MSR_DDSR;
516 if ((uMsrSts & UART_REG_MSR_RI) != 0 && (pThis->uRegMsr & UART_REG_MSR_RI) == 0)
517 uMsrSts |= UART_REG_MSR_TERI;
518 if ((uMsrSts & UART_REG_MSR_DCD) != (pThis->uRegMsr & UART_REG_MSR_DCD))
519 uMsrSts |= UART_REG_MSR_DDCD;
520
521 pThis->uRegMsr = uMsrSts;
522
523 uartIrqUpdate(pDevIns, pThis, pThisCC);
524}
525
526
527/**
528 * Updates the serial port parameters of the attached driver with the current configuration.
529 *
530 * @returns nothing.
531 * @param pDevIns The device instance.
532 * @param pThis The shared serial port instance data.
533 * @param pThisCC The serial port instance data for the current context.
534 */
535static void uartR3ParamsUpdate(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
536{
537 if ( pThis->uRegDivisor != 0
538 && pThisCC->pDrvSerial)
539 {
540 uint32_t uBps = 115200 / pThis->uRegDivisor; /* This is for PC compatible serial port with a 1.8432 MHz crystal. */
541 unsigned cDataBits = UART_REG_LCR_WLS_GET(pThis->uRegLcr) + 5;
542 uint32_t cFrameBits = cDataBits;
543 PDMSERIALSTOPBITS enmStopBits = PDMSERIALSTOPBITS_ONE;
544 PDMSERIALPARITY enmParity = PDMSERIALPARITY_NONE;
545
546 if (pThis->uRegLcr & UART_REG_LCR_STB)
547 {
548 enmStopBits = cDataBits == 5 ? PDMSERIALSTOPBITS_ONEPOINTFIVE : PDMSERIALSTOPBITS_TWO;
549 cFrameBits += 2;
550 }
551 else
552 cFrameBits++;
553
554 if (pThis->uRegLcr & UART_REG_LCR_PEN)
555 {
556 /* Select the correct parity mode based on the even and stick parity bits. */
557 switch (pThis->uRegLcr & (UART_REG_LCR_EPS | UART_REG_LCR_PAR_STICK))
558 {
559 case 0:
560 enmParity = PDMSERIALPARITY_ODD;
561 break;
562 case UART_REG_LCR_EPS:
563 enmParity = PDMSERIALPARITY_EVEN;
564 break;
565 case UART_REG_LCR_EPS | UART_REG_LCR_PAR_STICK:
566 enmParity = PDMSERIALPARITY_SPACE;
567 break;
568 case UART_REG_LCR_PAR_STICK:
569 enmParity = PDMSERIALPARITY_MARK;
570 break;
571 default:
572 /* We should never get here as all cases where caught earlier. */
573 AssertMsgFailed(("This shouldn't happen at all: %#x\n",
574 pThis->uRegLcr & (UART_REG_LCR_EPS | UART_REG_LCR_PAR_STICK)));
575 }
576
577 cFrameBits++;
578 }
579
580 uint64_t uTimerFreq = PDMDevHlpTimerGetFreq(pDevIns, pThis->hTimerRcvFifoTimeout);
581 pThis->cSymbolXferTicks = (uTimerFreq / uBps) * cFrameBits;
582
583 LogFlowFunc(("Changing parameters to: %u,%s,%u,%s\n",
584 uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits]));
585
586 int rc = pThisCC->pDrvSerial->pfnChgParams(pThisCC->pDrvSerial, uBps, enmParity, cDataBits, enmStopBits);
587 if (RT_FAILURE(rc))
588 LogRelMax(10, ("Serial#%d: Failed to change parameters to %u,%s,%u,%s -> %Rrc\n",
589 pDevIns->iInstance, uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits], rc));
590
591 /* Changed parameters will flush all receive queues, so there won't be any data to read even if indicated. */
592 pThisCC->pDrvSerial->pfnQueuesFlush(pThisCC->pDrvSerial, true /*fQueueRecv*/, false /*fQueueXmit*/);
593 ASMAtomicWriteU32(&pThis->cbAvailRdr, 0);
594 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
595 }
596}
597
598
599/**
600 * Updates the internal device state with the given PDM status line states.
601 *
602 * @returns nothing.
603 * @param pDevIns The device instance.
604 * @param pThis The shared serial port instance data.
605 * @param pThisCC The serial port instance data for the current context.
606 * @param fStsLines The PDM status line states.
607 */
608static void uartR3StsLinesUpdate(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint32_t fStsLines)
609{
610 uint8_t uRegMsrNew = 0; /* The new MSR value. */
611
612 if (fStsLines & PDMISERIALPORT_STS_LINE_DCD)
613 uRegMsrNew |= UART_REG_MSR_DCD;
614 if (fStsLines & PDMISERIALPORT_STS_LINE_RI)
615 uRegMsrNew |= UART_REG_MSR_RI;
616 if (fStsLines & PDMISERIALPORT_STS_LINE_DSR)
617 uRegMsrNew |= UART_REG_MSR_DSR;
618 if (fStsLines & PDMISERIALPORT_STS_LINE_CTS)
619 uRegMsrNew |= UART_REG_MSR_CTS;
620
621 uartR3MsrUpdate(pDevIns, pThis, pThisCC, uRegMsrNew);
622}
623
624
625/**
626 * Fills up the receive FIFO with as much data as possible.
627 *
628 * @returns nothing.
629 * @param pDevIns The device instance.
630 * @param pThis The shared serial port instance data.
631 * @param pThisCC The serial port instance data for the current context.
632 */
633static void uartR3RecvFifoFill(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
634{
635 LogFlowFunc(("pThis=%#p\n", pThis));
636
637 PUARTFIFO pFifo = &pThis->FifoRecv;
638 size_t cbFill = RT_MIN(uartFifoFreeGet(pFifo),
639 ASMAtomicReadU32(&pThis->cbAvailRdr));
640 size_t cbFilled = 0;
641
642 while (cbFilled < cbFill)
643 {
644 size_t cbThisRead = cbFill - cbFilled;
645
646 if (pFifo->offRead <= pFifo->offWrite)
647 cbThisRead = RT_MIN(cbThisRead, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
648 else
649 cbThisRead = RT_MIN(cbThisRead, (uint8_t)(pFifo->offRead - pFifo->offWrite));
650
651 size_t cbRead = 0;
652 int rc = pThisCC->pDrvSerial->pfnReadRdr(pThisCC->pDrvSerial, &pFifo->abBuf[pFifo->offWrite], cbThisRead, &cbRead);
653 AssertRC(rc); Assert(cbRead <= UINT8_MAX); RT_NOREF(rc);
654
655 pFifo->offWrite = (pFifo->offWrite + (uint8_t)cbRead) % pFifo->cbMax;
656 pFifo->cbUsed += (uint8_t)cbRead;
657 cbFilled += cbRead;
658
659 if (cbRead < cbThisRead)
660 break;
661 }
662
663 if (cbFilled)
664 {
665 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
666 if (pFifo->cbUsed < pFifo->cbItl)
667 {
668 pThis->fIrqCtiPending = false;
669 PDMDevHlpTimerSetRelative(pDevIns, pThis->hTimerRcvFifoTimeout, pThis->cSymbolXferTicks * 4, NULL);
670 }
671 uartIrqUpdate(pDevIns, pThis, pThisCC);
672 }
673
674 Assert(cbFilled <= (size_t)pThis->cbAvailRdr);
675 ASMAtomicSubU32(&pThis->cbAvailRdr, (uint32_t)cbFilled);
676}
677
678
679/**
680 * Fetches a single byte and writes it to RBR.
681 *
682 * @returns nothing.
683 * @param pDevIns The device instance.
684 * @param pThis The shared serial port instance data.
685 * @param pThisCC The serial port instance data for the current context.
686 */
687static void uartR3ByteFetch(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
688{
689 if (ASMAtomicReadU32(&pThis->cbAvailRdr))
690 {
691 size_t cbRead = 0;
692 int rc2 = pThisCC->pDrvSerial->pfnReadRdr(pThisCC->pDrvSerial, &pThis->uRegRbr, 1, &cbRead);
693 AssertMsg(RT_SUCCESS(rc2) && cbRead == 1, ("This shouldn't fail and always return one byte!\n")); RT_NOREF(rc2);
694 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
695 uartIrqUpdate(pDevIns, pThis, pThisCC);
696 }
697}
698
699
700/**
701 * Fetches a ready data based on the FIFO setting.
702 *
703 * @returns nothing.
704 * @param pDevIns The device instance.
705 * @param pThis The shared serial port instance data.
706 * @param pThisCC The serial port instance data for the current context.
707 */
708static void uartR3DataFetch(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
709{
710 AssertPtrReturnVoid(pThisCC->pDrvSerial);
711
712 if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
713 uartR3RecvFifoFill(pDevIns, pThis, pThisCC);
714 else
715 uartR3ByteFetch(pDevIns, pThis, pThisCC);
716}
717
718
719/**
720 * Reset the transmit/receive related bits to the standard values
721 * (after a detach/attach/reset event).
722 *
723 * @returns nothing.
724 * @param pDevIns The device instance.
725 * @param pThis The shared serial port instance data.
726 * @param pThisCC The serial port instance data for the current context.
727 */
728static void uartR3XferReset(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
729{
730 PDMDevHlpTimerStop(pDevIns, pThis->hTimerRcvFifoTimeout);
731 PDMDevHlpTimerStop(pDevIns, pThis->hTimerTxUnconnected);
732 pThis->uRegLsr = UART_REG_LSR_THRE | UART_REG_LSR_TEMT;
733 pThis->fThreEmptyPending = false;
734
735 uartFifoClear(&pThis->FifoXmit);
736 uartFifoClear(&pThis->FifoRecv);
737 uartR3ParamsUpdate(pDevIns, pThis, pThisCC);
738 uartIrqUpdate(pDevIns, pThis, pThisCC);
739
740 if (pThisCC->pDrvSerial)
741 {
742 /* Set the modem lines to reflect the current state. */
743 int rc = pThisCC->pDrvSerial->pfnChgModemLines(pThisCC->pDrvSerial, false /*fRts*/, false /*fDtr*/);
744 if (RT_FAILURE(rc))
745 LogRel(("Serial#%d: Failed to set modem lines with %Rrc during reset\n",
746 pDevIns->iInstance, rc));
747
748 uint32_t fStsLines = 0;
749 rc = pThisCC->pDrvSerial->pfnQueryStsLines(pThisCC->pDrvSerial, &fStsLines);
750 if (RT_SUCCESS(rc))
751 uartR3StsLinesUpdate(pDevIns, pThis, pThisCC, fStsLines);
752 else
753 LogRel(("Serial#%d: Failed to query status line status with %Rrc during reset\n",
754 pDevIns->iInstance, rc));
755 }
756
757}
758
759
760/**
761 * Tries to copy the specified amount of data from the active TX queue (register or FIFO).
762 *
763 * @returns nothing.
764 * @param pDevIns The device instance.
765 * @param pThis The shared serial port instance data.
766 * @param pThisCC The serial port instance data for the current context.
767 * @param pvBuf Where to store the data.
768 * @param cbRead How much to read from the TX queue.
769 * @param pcbRead Where to store the amount of data read.
770 */
771static void uartR3TxQueueCopyFrom(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC,
772 void *pvBuf, size_t cbRead, size_t *pcbRead)
773{
774 if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
775 {
776 *pcbRead = uartFifoCopyTo(&pThis->FifoXmit, pvBuf, cbRead);
777 if (!pThis->FifoXmit.cbUsed)
778 {
779 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
780 pThis->fThreEmptyPending = true;
781 }
782 if (*pcbRead)
783 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
784 uartIrqUpdate(pDevIns, pThis, pThisCC);
785 }
786 else if (!(pThis->uRegLsr & UART_REG_LSR_THRE))
787 {
788 *(uint8_t *)pvBuf = pThis->uRegThr;
789 *pcbRead = 1;
790 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
791 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
792 pThis->fThreEmptyPending = true;
793 uartIrqUpdate(pDevIns, pThis, pThisCC);
794 }
795 else
796 {
797 /*
798 * This can happen if there was data in the FIFO when the connection was closed,
799 * indicate this condition to the lower driver by returning 0 bytes.
800 */
801 *pcbRead = 0;
802 }
803}
804
805#endif /* IN_RING3 */
806
807
808/**
809 * Transmits the given byte.
810 *
811 * @returns Strict VBox status code.
812 * @param pDevIns The device instance.
813 * @param pThis The shared serial port instance data.
814 * @param pThisCC The serial port instance data for the current context.
815 * @param bVal Byte to transmit.
816 */
817static VBOXSTRICTRC uartXmit(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t bVal)
818{
819 int rc = VINF_SUCCESS;
820#ifdef IN_RING3
821 bool fNotifyDrv = false;
822#endif
823
824 if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
825 {
826#ifndef IN_RING3
827 RT_NOREF(pDevIns, pThisCC);
828 if (!uartFifoUsedGet(&pThis->FifoXmit))
829 rc = VINF_IOM_R3_IOPORT_WRITE;
830 else
831 {
832 uartFifoPut(&pThis->FifoXmit, true /*fOvrWr*/, bVal);
833 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE | UART_REG_LSR_TEMT);
834 }
835#else
836 uartFifoPut(&pThis->FifoXmit, true /*fOvrWr*/, bVal);
837 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE | UART_REG_LSR_TEMT);
838 pThis->fThreEmptyPending = false;
839 uartIrqUpdate(pDevIns, pThis, pThisCC);
840 if (uartFifoUsedGet(&pThis->FifoXmit) == 1)
841 fNotifyDrv = true;
842#endif
843 }
844 else
845 {
846 /* Notify the lower driver about available data only if the register was empty before. */
847 if (pThis->uRegLsr & UART_REG_LSR_THRE)
848 {
849#ifndef IN_RING3
850 rc = VINF_IOM_R3_IOPORT_WRITE;
851#else
852 pThis->uRegThr = bVal;
853 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE | UART_REG_LSR_TEMT);
854 pThis->fThreEmptyPending = false;
855 uartIrqUpdate(pDevIns, pThis, pThisCC);
856 fNotifyDrv = true;
857#endif
858 }
859 else
860 pThis->uRegThr = bVal;
861 }
862
863#ifdef IN_RING3
864 if (fNotifyDrv)
865 {
866 /* Leave the device critical section before calling into the lower driver. */
867 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
868
869 if ( pThisCC->pDrvSerial
870 && !(pThis->uRegMcr & UART_REG_MCR_LOOP))
871 {
872 int rc2 = pThisCC->pDrvSerial->pfnDataAvailWrNotify(pThisCC->pDrvSerial);
873 if (RT_FAILURE(rc2))
874 LogRelMax(10, ("Serial#%d: Failed to send data with %Rrc\n", pDevIns->iInstance, rc2));
875 }
876 else
877 PDMDevHlpTimerSetRelative(pDevIns, pThis->hTimerTxUnconnected, pThis->cSymbolXferTicks, NULL);
878
879 rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VINF_SUCCESS);
880 }
881#endif
882
883 return rc;
884}
885
886
887/**
888 * Write handler for the THR/DLL register (depending on the DLAB bit in LCR).
889 *
890 * @returns Strict VBox status code.
891 * @param pDevIns The device instance.
892 * @param pThis The shared serial port instance data.
893 * @param pThisCC The serial port instance data for the current context.
894 * @param uVal The value to write.
895 */
896DECLINLINE(VBOXSTRICTRC) uartRegThrDllWrite(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t uVal)
897{
898 VBOXSTRICTRC rc = VINF_SUCCESS;
899
900 /* A set DLAB causes a write to the lower 8bits of the divisor latch. */
901 if (pThis->uRegLcr & UART_REG_LCR_DLAB)
902 {
903 if (uVal != (pThis->uRegDivisor & 0xff))
904 {
905#ifndef IN_RING3
906 rc = VINF_IOM_R3_IOPORT_WRITE;
907#else
908 pThis->uRegDivisor = (pThis->uRegDivisor & 0xff00) | uVal;
909 uartR3ParamsUpdate(pDevIns, pThis, pThisCC);
910#endif
911 }
912 }
913 else
914 rc = uartXmit(pDevIns, pThis, pThisCC, uVal);
915
916 return rc;
917}
918
919
920/**
921 * Write handler for the IER/DLM register (depending on the DLAB bit in LCR).
922 *
923 * @returns Strict VBox status code.
924 * @param pDevIns The device instance.
925 * @param pThis The shared serial port instance data.
926 * @param pThisCC The serial port instance data for the current context.
927 * @param uVal The value to write.
928 */
929DECLINLINE(VBOXSTRICTRC) uartRegIerDlmWrite(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t uVal)
930{
931 /* A set DLAB causes a write to the higher 8bits of the divisor latch. */
932 if (pThis->uRegLcr & UART_REG_LCR_DLAB)
933 {
934 if (uVal != (pThis->uRegDivisor & 0xff00) >> 8)
935 {
936#ifndef IN_RING3
937 return VINF_IOM_R3_IOPORT_WRITE;
938#else
939 pThis->uRegDivisor = (pThis->uRegDivisor & 0xff) | (uVal << 8);
940 uartR3ParamsUpdate(pDevIns, pThis, pThisCC);
941#endif
942 }
943 }
944 else
945 {
946 if (pThis->enmType < UARTTYPE_16750)
947 pThis->uRegIer = uVal & UART_REG_IER_MASK_WR;
948 else
949 pThis->uRegIer = uVal & UART_REG_IER_MASK_WR_16750;
950
951 if (pThis->uRegLsr & UART_REG_LSR_THRE)
952 pThis->fThreEmptyPending = true;
953
954 uartIrqUpdate(pDevIns, pThis, pThisCC);
955 }
956 return VINF_SUCCESS;
957}
958
959
960/**
961 * Write handler for the FCR register.
962 *
963 * @returns Strict VBox status code.
964 * @param pDevIns The device instance.
965 * @param pThis The shared serial port instance data.
966 * @param pThisCC The serial port instance data for the current context.
967 * @param uVal The value to write.
968 */
969DECLINLINE(VBOXSTRICTRC) uartRegFcrWrite(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t uVal)
970{
971#ifndef IN_RING3
972 RT_NOREF(pDevIns, pThis, pThisCC, uVal);
973 return VINF_IOM_R3_IOPORT_WRITE;
974#else /* IN_RING3 */
975 if ( pThis->enmType >= UARTTYPE_16550A
976 && uVal != pThis->uRegFcr)
977 {
978 /* A change in the FIFO enable bit clears both FIFOs automatically. */
979 if ((uVal ^ pThis->uRegFcr) & UART_REG_FCR_FIFO_EN)
980 {
981 uartFifoClear(&pThis->FifoXmit);
982 uartFifoClear(&pThis->FifoRecv);
983
984 /*
985 * If the FIFO is about to be enabled and the DR bit is ready we have an unacknowledged
986 * byte in the RBR register which will be lost so we have to adjust the available bytes.
987 */
988 if ( ASMAtomicReadU32(&pThis->cbAvailRdr) > 0
989 && (uVal & UART_REG_FCR_FIFO_EN))
990 ASMAtomicDecU32(&pThis->cbAvailRdr);
991
992 /* Clear the DR bit too. */
993 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
994 }
995
996 /** @todo r=bird: Why was this here: if (rc == VINF_SUCCESS) */
997 {
998 if (uVal & UART_REG_FCR_RCV_FIFO_RST)
999 {
1000 PDMDevHlpTimerStop(pDevIns, pThis->hTimerRcvFifoTimeout);
1001 pThis->fIrqCtiPending = false;
1002 uartFifoClear(&pThis->FifoRecv);
1003 }
1004 if (uVal & UART_REG_FCR_XMIT_FIFO_RST)
1005 uartFifoClear(&pThis->FifoXmit);
1006
1007 /*
1008 * The 64byte FIFO enable bit is only changeable for 16750
1009 * and if the DLAB bit in LCR is set.
1010 */
1011 if ( pThis->enmType < UARTTYPE_16750
1012 || !(pThis->uRegLcr & UART_REG_LCR_DLAB))
1013 uVal &= ~UART_REG_FCR_64BYTE_FIFO_EN;
1014 else /* Use previous value. */
1015 uVal |= pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN;
1016
1017 if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
1018 {
1019 pThis->FifoRecv.cbMax = 64;
1020 pThis->FifoXmit.cbMax = 64;
1021 }
1022 else
1023 {
1024 pThis->FifoRecv.cbMax = 16;
1025 pThis->FifoXmit.cbMax = 16;
1026 }
1027
1028 if (uVal & UART_REG_FCR_FIFO_EN)
1029 {
1030 uint8_t idxItl = UART_REG_FCR_RCV_LVL_IRQ_GET(uVal);
1031 if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
1032 pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl64;
1033 else
1034 pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl16;
1035 }
1036
1037 /* The FIFO reset bits are self clearing. */
1038 pThis->uRegFcr = uVal & UART_REG_FCR_MASK_STICKY;
1039 uartIrqUpdate(pDevIns, pThis, pThisCC);
1040 }
1041
1042 /* Fill in the next data. */
1043 if (ASMAtomicReadU32(&pThis->cbAvailRdr))
1044 uartR3DataFetch(pDevIns, pThis, pThisCC);
1045 }
1046
1047 return VINF_SUCCESS;
1048#endif /* IN_RING3 */
1049}
1050
1051
1052/**
1053 * Write handler for the LCR register.
1054 *
1055 * @returns Strict VBox status code.
1056 * @param pDevIns The device instance.
1057 * @param pThis The shared serial port instance data.
1058 * @param pThisCC The serial port instance data for the current context.
1059 * @param uVal The value to write.
1060 */
1061DECLINLINE(VBOXSTRICTRC) uartRegLcrWrite(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t uVal)
1062{
1063 /* Any change except the DLAB bit causes a switch to R3. */
1064 if ((pThis->uRegLcr & ~UART_REG_LCR_DLAB) != (uVal & ~UART_REG_LCR_DLAB))
1065 {
1066#ifndef IN_RING3
1067 RT_NOREF(pThisCC, pDevIns);
1068 return VINF_IOM_R3_IOPORT_WRITE;
1069#else
1070 /* Check whether the BREAK bit changed before updating the LCR value. */
1071 bool fBrkEn = RT_BOOL(uVal & UART_REG_LCR_BRK_SET);
1072 bool fBrkChg = fBrkEn != RT_BOOL(pThis->uRegLcr & UART_REG_LCR_BRK_SET);
1073 pThis->uRegLcr = uVal;
1074 uartR3ParamsUpdate(pDevIns, pThis, pThisCC);
1075
1076 if ( fBrkChg
1077 && pThisCC->pDrvSerial)
1078 pThisCC->pDrvSerial->pfnChgBrk(pThisCC->pDrvSerial, fBrkEn);
1079#endif
1080 }
1081 else
1082 pThis->uRegLcr = uVal;
1083
1084 return VINF_SUCCESS;
1085}
1086
1087
1088/**
1089 * Write handler for the MCR register.
1090 *
1091 * @returns Strict VBox status code.
1092 * @param pDevIns The device instance.
1093 * @param pThis The shared serial port instance data.
1094 * @param pThisCC The serial port instance data for the current context.
1095 * @param uVal The value to write.
1096 */
1097DECLINLINE(VBOXSTRICTRC) uartRegMcrWrite(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t uVal)
1098{
1099 if (pThis->enmType < UARTTYPE_16750)
1100 uVal &= UART_REG_MCR_MASK_WR;
1101 else
1102 uVal &= UART_REG_MCR_MASK_WR_15750;
1103 if (pThis->uRegMcr != uVal)
1104 {
1105#ifndef IN_RING3
1106 RT_NOREF(pThisCC, pDevIns);
1107 return VINF_IOM_R3_IOPORT_WRITE;
1108#else
1109 /*
1110 * When loopback mode is activated the RTS, DTR, OUT1 and OUT2 lines are
1111 * disconnected and looped back to MSR.
1112 */
1113 if ( (uVal & UART_REG_MCR_LOOP)
1114 && !(pThis->uRegMcr & UART_REG_MCR_LOOP)
1115 && pThisCC->pDrvSerial)
1116 pThisCC->pDrvSerial->pfnChgModemLines(pThisCC->pDrvSerial, false /*fRts*/, false /*fDtr*/);
1117
1118 pThis->uRegMcr = uVal;
1119 if (uVal & UART_REG_MCR_LOOP)
1120 {
1121 uint8_t uRegMsrSts = 0;
1122
1123 if (uVal & UART_REG_MCR_RTS)
1124 uRegMsrSts |= UART_REG_MSR_CTS;
1125 if (uVal & UART_REG_MCR_DTR)
1126 uRegMsrSts |= UART_REG_MSR_DSR;
1127 if (uVal & UART_REG_MCR_OUT1)
1128 uRegMsrSts |= UART_REG_MSR_RI;
1129 if (uVal & UART_REG_MCR_OUT2)
1130 uRegMsrSts |= UART_REG_MSR_DCD;
1131 uartR3MsrUpdate(pDevIns, pThis, pThisCC, uRegMsrSts);
1132 }
1133 else if (pThisCC->pDrvSerial)
1134 {
1135 pThisCC->pDrvSerial->pfnChgModemLines(pThisCC->pDrvSerial,
1136 RT_BOOL(uVal & UART_REG_MCR_RTS),
1137 RT_BOOL(uVal & UART_REG_MCR_DTR));
1138
1139 uint32_t fStsLines = 0;
1140 int rc = pThisCC->pDrvSerial->pfnQueryStsLines(pThisCC->pDrvSerial, &fStsLines);
1141 if (RT_SUCCESS(rc))
1142 uartR3StsLinesUpdate(pDevIns, pThis, pThisCC, fStsLines);
1143 else
1144 LogRelMax(10, ("Serial#%d: Failed to query status line status with %Rrc during reset\n",
1145 pDevIns->iInstance, rc));
1146 }
1147 else /* Loopback mode got disabled and no driver attached, fake presence. */
1148 uartR3MsrUpdate(pDevIns, pThis, pThisCC, UART_REG_MSR_DCD | UART_REG_MSR_CTS | UART_REG_MSR_DSR);
1149#endif
1150 }
1151
1152 return VINF_SUCCESS;
1153}
1154
1155
1156/**
1157 * Read handler for the RBR/DLL register (depending on the DLAB bit in LCR).
1158 *
1159 * @returns VBox status code.
1160 * @param pDevIns The device instance.
1161 * @param pThis The shared serial port instance data.
1162 * @param pThisCC The serial port instance data for the current context.
1163 * @param puVal Where to store the read value on success.
1164 */
1165DECLINLINE(VBOXSTRICTRC) uartRegRbrDllRead(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint32_t *puVal)
1166{
1167 VBOXSTRICTRC rc = VINF_SUCCESS;
1168
1169 /* A set DLAB causes a read from the lower 8bits of the divisor latch. */
1170 if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1171 *puVal = pThis->uRegDivisor & 0xff;
1172 else
1173 {
1174 if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1175 {
1176 /*
1177 * Only go back to R3 if there is new data available for the FIFO
1178 * and we would clear the interrupt to fill it up again.
1179 */
1180 if ( pThis->FifoRecv.cbUsed <= pThis->FifoRecv.cbItl
1181 && ASMAtomicReadU32(&pThis->cbAvailRdr) > 0)
1182 {
1183#ifndef IN_RING3
1184 rc = VINF_IOM_R3_IOPORT_READ;
1185#else
1186 uartR3RecvFifoFill(pDevIns, pThis, pThisCC);
1187#endif
1188 }
1189
1190 if (rc == VINF_SUCCESS)
1191 {
1192 *puVal = uartFifoGet(&pThis->FifoRecv);
1193 pThis->fIrqCtiPending = false;
1194 if (!pThis->FifoRecv.cbUsed)
1195 {
1196 PDMDevHlpTimerStop(pDevIns, pThis->hTimerRcvFifoTimeout);
1197 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
1198 }
1199 else if (pThis->FifoRecv.cbUsed < pThis->FifoRecv.cbItl)
1200 PDMDevHlpTimerSetRelative(pDevIns, pThis->hTimerRcvFifoTimeout,
1201 pThis->cSymbolXferTicks * 4, NULL);
1202 uartIrqUpdate(pDevIns, pThis, pThisCC);
1203 }
1204 }
1205 else
1206 {
1207 *puVal = pThis->uRegRbr;
1208
1209 if (pThis->uRegLsr & UART_REG_LSR_DR)
1210 {
1211 Assert(pThis->cbAvailRdr);
1212 uint32_t cbAvail = ASMAtomicDecU32(&pThis->cbAvailRdr);
1213 if (!cbAvail)
1214 {
1215 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
1216 uartIrqUpdate(pDevIns, pThis, pThisCC);
1217 }
1218 else
1219 {
1220#ifndef IN_RING3
1221 /* Restore state and go back to R3. */
1222 ASMAtomicIncU32(&pThis->cbAvailRdr);
1223 rc = VINF_IOM_R3_IOPORT_READ;
1224#else
1225 /* Fetch new data and keep the DR bit set. */
1226 uartR3DataFetch(pDevIns, pThis, pThisCC);
1227#endif
1228 }
1229 }
1230 }
1231 }
1232
1233 return rc;
1234}
1235
1236
1237/**
1238 * Read handler for the IER/DLM register (depending on the DLAB bit in LCR).
1239 *
1240 * @param pThis The shared serial port instance data.
1241 * @param puVal Where to store the read value on success.
1242 */
1243DECLINLINE(void) uartRegIerDlmRead(PUARTCORE pThis, uint32_t *puVal)
1244{
1245 /* A set DLAB causes a read from the upper 8bits of the divisor latch. */
1246 if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1247 *puVal = (pThis->uRegDivisor & 0xff00) >> 8;
1248 else
1249 *puVal = pThis->uRegIer;
1250}
1251
1252
1253/**
1254 * Read handler for the IIR register.
1255 *
1256 * @param pDevIns The device instance.
1257 * @param pThis The shared serial port instance data.
1258 * @param pThisCC The serial port instance data for the current context.
1259 * @param puVal Where to store the read value on success.
1260 */
1261DECLINLINE(void) uartRegIirRead(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint32_t *puVal)
1262{
1263 *puVal = pThis->uRegIir;
1264 /* Reset the THRE empty interrupt id when this gets returned to the guest (see table 3 UART Reset configuration). */
1265 if (UART_REG_IIR_ID_GET(pThis->uRegIir) == UART_REG_IIR_ID_THRE)
1266 {
1267 pThis->fThreEmptyPending = false;
1268 uartIrqUpdate(pDevIns, pThis, pThisCC);
1269 }
1270}
1271
1272
1273/**
1274 * Read handler for the LSR register.
1275 *
1276 * @returns Strict VBox status code.
1277 * @param pDevIns The device instance.
1278 * @param pThis The shared serial port instance data.
1279 * @param pThisCC The serial port instance data for the current context.
1280 * @param puVal Where to store the read value on success.
1281 */
1282DECLINLINE(VBOXSTRICTRC) uartRegLsrRead(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint32_t *puVal)
1283{
1284 /* Yield if configured and there is no data available. */
1285 if ( !(pThis->uRegLsr & UART_REG_LSR_DR)
1286 && (pThis->fFlags & UART_CORE_YIELD_ON_LSR_READ))
1287 {
1288#ifndef IN_RING3
1289 return VINF_IOM_R3_IOPORT_READ;
1290#else
1291 RTThreadYield();
1292#endif
1293 }
1294
1295 *puVal = pThis->uRegLsr;
1296 /*
1297 * Reading this register clears the Overrun (OE), Parity (PE) and Framing (FE) error
1298 * as well as the Break Interrupt (BI).
1299 */
1300 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_BITS_IIR_RCL);
1301 uartIrqUpdate(pDevIns, pThis, pThisCC);
1302
1303 return VINF_SUCCESS;
1304}
1305
1306
1307/**
1308 * Read handler for the MSR register.
1309 *
1310 * @param pDevIns The device instance.
1311 * @param pThis The shared serial port instance data.
1312 * @param pThisCC The serial port instance data for the current context.
1313 * @param puVal Where to store the read value on success.
1314 */
1315DECLINLINE(void) uartRegMsrRead(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint32_t *puVal)
1316{
1317 *puVal = pThis->uRegMsr;
1318
1319 /* Clear any of the delta bits. */
1320 UART_REG_CLR(pThis->uRegMsr, UART_REG_MSR_BITS_IIR_MS);
1321 uartIrqUpdate(pDevIns, pThis, pThisCC);
1322}
1323
1324
1325#ifdef LOG_ENABLED
1326/**
1327 * Converts the register index into a sensible memnonic.
1328 *
1329 * @returns Register memnonic.
1330 * @param pThis The shared serial port instance data.
1331 * @param idxReg Register index.
1332 * @param fWrite Flag whether the register gets written.
1333 */
1334DECLINLINE(const char *) uartRegIdx2Str(PUARTCORE pThis, uint8_t idxReg, bool fWrite)
1335{
1336 const char *psz = "INV";
1337
1338 switch (idxReg)
1339 {
1340 /*case UART_REG_THR_DLL_INDEX:*/
1341 case UART_REG_RBR_DLL_INDEX:
1342 if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1343 psz = "DLL";
1344 else if (fWrite)
1345 psz = "THR";
1346 else
1347 psz = "RBR";
1348 break;
1349 case UART_REG_IER_DLM_INDEX:
1350 if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1351 psz = "DLM";
1352 else
1353 psz = "IER";
1354 break;
1355 /*case UART_REG_IIR_INDEX:*/
1356 case UART_REG_FCR_INDEX:
1357 if (fWrite)
1358 psz = "FCR";
1359 else
1360 psz = "IIR";
1361 break;
1362 case UART_REG_LCR_INDEX:
1363 psz = "LCR";
1364 break;
1365 case UART_REG_MCR_INDEX:
1366 psz = "MCR";
1367 break;
1368 case UART_REG_LSR_INDEX:
1369 psz = "LSR";
1370 break;
1371 case UART_REG_MSR_INDEX:
1372 psz = "MSR";
1373 break;
1374 case UART_REG_SCR_INDEX:
1375 psz = "SCR";
1376 break;
1377 }
1378
1379 return psz;
1380}
1381#endif
1382
1383
1384/**
1385 * Performs a register write to the given register offset.
1386 *
1387 * @returns Strict VBox status code.
1388 * @param pDevIns The device instance.
1389 * @param pThis The shared UART core instance data.
1390 * @param pThisCC The current context UART core instance data.
1391 * @param uReg The register offset (byte offset) to start writing to.
1392 * @param u32 The value to write.
1393 * @param cb Number of bytes to write.
1394 */
1395DECLHIDDEN(VBOXSTRICTRC) uartRegWrite(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC,
1396 uint32_t uReg, uint32_t u32, size_t cb)
1397{
1398 AssertMsgReturn(cb == 1, ("uReg=%#x cb=%d u32=%#x\n", uReg, cb, u32), VINF_SUCCESS);
1399
1400 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VINF_IOM_R3_IOPORT_WRITE);
1401 if (rc == VINF_SUCCESS)
1402 {
1403 uint8_t idxReg = uReg & 0x7;
1404 LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u\n",
1405 pThis, uReg, uartRegIdx2Str(pThis, idxReg, true /*fWrite*/), u32, cb));
1406
1407 uint8_t uVal = (uint8_t)u32;
1408 switch (idxReg)
1409 {
1410 case UART_REG_THR_DLL_INDEX:
1411 rc = uartRegThrDllWrite(pDevIns, pThis, pThisCC, uVal);
1412 break;
1413 case UART_REG_IER_DLM_INDEX:
1414 rc = uartRegIerDlmWrite(pDevIns, pThis, pThisCC, uVal);
1415 break;
1416 case UART_REG_FCR_INDEX:
1417 rc = uartRegFcrWrite(pDevIns, pThis, pThisCC, uVal);
1418 break;
1419 case UART_REG_LCR_INDEX:
1420 rc = uartRegLcrWrite(pDevIns, pThis, pThisCC, uVal);
1421 break;
1422 case UART_REG_MCR_INDEX:
1423 rc = uartRegMcrWrite(pDevIns, pThis, pThisCC, uVal);
1424 break;
1425 case UART_REG_SCR_INDEX:
1426 pThis->uRegScr = uVal;
1427 break;
1428 default:
1429 break;
1430 }
1431
1432 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1433 }
1434 LogFlowFunc(("-> %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1435 return rc;
1436}
1437
1438
1439/**
1440 * Performs a register read from the given register offset.
1441 *
1442 * @returns VBox status code.
1443 * @param pDevIns The device instance.
1444 * @param pThis The shared UART core instance data.
1445 * @param pThisCC The current context UART core instance data.
1446 * @param uReg The register offset (byte offset) to start reading from.
1447 * @param pu32 Where to store the read value.
1448 * @param cb Number of bytes to read.
1449 */
1450DECLHIDDEN(VBOXSTRICTRC) uartRegRead(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC,
1451 uint32_t uReg, uint32_t *pu32, size_t cb)
1452{
1453 if (cb != 1)
1454 return VERR_IOM_IOPORT_UNUSED;
1455
1456 VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
1457 if (rc == VINF_SUCCESS)
1458 {
1459 uint8_t idxReg = uReg & 0x7;
1460 switch (idxReg)
1461 {
1462 case UART_REG_RBR_DLL_INDEX:
1463 rc = uartRegRbrDllRead(pDevIns, pThis, pThisCC, pu32);
1464 break;
1465 case UART_REG_IER_DLM_INDEX:
1466 uartRegIerDlmRead(pThis, pu32);
1467 break;
1468 case UART_REG_IIR_INDEX:
1469 uartRegIirRead(pDevIns, pThis, pThisCC, pu32);
1470 break;
1471 case UART_REG_LCR_INDEX:
1472 *pu32 = pThis->uRegLcr;
1473 break;
1474 case UART_REG_MCR_INDEX:
1475 *pu32 = pThis->uRegMcr;
1476 break;
1477 case UART_REG_LSR_INDEX:
1478 rc = uartRegLsrRead(pDevIns, pThis, pThisCC, pu32);
1479 break;
1480 case UART_REG_MSR_INDEX:
1481 uartRegMsrRead(pDevIns, pThis, pThisCC, pu32);
1482 break;
1483 case UART_REG_SCR_INDEX:
1484 *pu32 = pThis->uRegScr;
1485 break;
1486 default:
1487 rc = VERR_IOM_IOPORT_UNUSED;
1488 }
1489 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1490 LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u -> %Rrc\n",
1491 pThis, uReg, uartRegIdx2Str(pThis, idxReg, false /*fWrite*/), *pu32, cb, VBOXSTRICTRC_VAL(rc)));
1492 }
1493 else
1494 LogFlowFunc(("-> %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1495 return rc;
1496}
1497
1498
1499#ifdef IN_RING3
1500
1501/* -=-=-=-=-=-=-=-=- Timer callbacks -=-=-=-=-=-=-=-=- */
1502
1503/**
1504 * @callback_method_impl{FNTMTIMERDEV, Fifo timer function.}
1505 */
1506static DECLCALLBACK(void) uartR3RcvFifoTimeoutTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
1507{
1508 LogFlowFunc(("pDevIns=%#p hTimer=%#p pvUser=%#p\n", pDevIns, hTimer, pvUser));
1509 PUARTCORER3 pThisCC = (PUARTCORECC)pvUser;
1510 PUARTCORE pThis = pThisCC->pShared;
1511 RT_NOREF(hTimer);
1512
1513 if (pThis->FifoRecv.cbUsed < pThis->FifoRecv.cbItl)
1514 {
1515 pThis->fIrqCtiPending = true;
1516 uartIrqUpdate(pDevIns, pThis, pThisCC);
1517 }
1518}
1519
1520/**
1521 * @callback_method_impl{FNTMTIMERDEV,
1522 * TX timer function when there is no driver connected for
1523 * draining the THR/FIFO.}
1524 */
1525static DECLCALLBACK(void) uartR3TxUnconnectedTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
1526{
1527 LogFlowFunc(("pDevIns=%#p hTimer=%#p pvUser=%#p\n", pDevIns, hTimer, pvUser));
1528 PUARTCORER3 pThisCC = (PUARTCORECC)pvUser;
1529 PUARTCORE pThis = pThisCC->pShared;
1530 Assert(hTimer == pThis->hTimerTxUnconnected);
1531
1532 VBOXSTRICTRC rc1 = PDMDevHlpTimerLockClock2(pDevIns, hTimer, &pThis->CritSect, VINF_SUCCESS /* must get it */);
1533 AssertRCReturnVoid(VBOXSTRICTRC_VAL(rc1));
1534
1535 uint8_t bVal = 0;
1536 size_t cbRead = 0;
1537 uartR3TxQueueCopyFrom(pDevIns, pThis, pThisCC, &bVal, sizeof(bVal), &cbRead);
1538 if (pThis->uRegMcr & UART_REG_MCR_LOOP)
1539 {
1540 /* Loopback mode is active, feed in the data at the receiving end. */
1541 uint32_t cbAvailOld = ASMAtomicAddU32(&pThis->cbAvailRdr, 1);
1542 if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1543 {
1544 PUARTFIFO pFifo = &pThis->FifoRecv;
1545 if (uartFifoFreeGet(pFifo) > 0)
1546 {
1547 pFifo->abBuf[pFifo->offWrite] = bVal;
1548 pFifo->offWrite = (pFifo->offWrite + 1) % pFifo->cbMax;
1549 pFifo->cbUsed++;
1550
1551 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
1552 if (pFifo->cbUsed < pFifo->cbItl)
1553 {
1554 pThis->fIrqCtiPending = false;
1555 PDMDevHlpTimerSetRelative(pDevIns, pThis->hTimerRcvFifoTimeout,
1556 pThis->cSymbolXferTicks * 4, NULL);
1557 }
1558 uartIrqUpdate(pDevIns, pThis, pThisCC);
1559 }
1560
1561 ASMAtomicSubU32(&pThis->cbAvailRdr, 1);
1562 }
1563 else if (!cbAvailOld)
1564 {
1565 pThis->uRegRbr = bVal;
1566 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
1567 uartIrqUpdate(pDevIns, pThis, pThisCC);
1568 }
1569 else
1570 ASMAtomicSubU32(&pThis->cbAvailRdr, 1);
1571 }
1572
1573 if (cbRead == 1)
1574 PDMDevHlpTimerSetRelative(pDevIns, hTimer, pThis->cSymbolXferTicks, NULL);
1575 else
1576 {
1577 /* NO data left, set the transmitter holding register as empty. */
1578 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_TEMT);
1579 }
1580
1581 PDMDevHlpTimerUnlockClock2(pDevIns, hTimer, &pThis->CritSect);
1582}
1583
1584
1585/* -=-=-=-=-=-=-=-=- PDMISERIALPORT on LUN#0 -=-=-=-=-=-=-=-=- */
1586
1587
1588/**
1589 * @interface_method_impl{PDMISERIALPORT,pfnDataAvailRdrNotify}
1590 */
1591static DECLCALLBACK(int) uartR3DataAvailRdrNotify(PPDMISERIALPORT pInterface, size_t cbAvail)
1592{
1593 LogFlowFunc(("pInterface=%#p cbAvail=%zu\n", pInterface, cbAvail));
1594 PUARTCORECC pThisCC = RT_FROM_MEMBER(pInterface, UARTCORECC, ISerialPort);
1595 PUARTCORE pThis = pThisCC->pShared;
1596 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1597
1598 AssertMsg((uint32_t)cbAvail == cbAvail, ("Too much data available\n"));
1599
1600 int rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1601 AssertRCReturn(rcLock, rcLock);
1602
1603 uint32_t cbAvailOld = ASMAtomicAddU32(&pThis->cbAvailRdr, (uint32_t)cbAvail);
1604 LogFlow((" cbAvailRdr=%u -> cbAvailRdr=%u\n", cbAvailOld, cbAvail + cbAvailOld));
1605 if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1606 uartR3RecvFifoFill(pDevIns, pThis, pThisCC);
1607 else if (!cbAvailOld)
1608 {
1609 size_t cbRead = 0;
1610 int rc = pThisCC->pDrvSerial->pfnReadRdr(pThisCC->pDrvSerial, &pThis->uRegRbr, 1, &cbRead);
1611 AssertRC(rc);
1612
1613 if (cbRead)
1614 {
1615 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
1616 uartIrqUpdate(pDevIns, pThis, pThisCC);
1617 }
1618 }
1619
1620 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1621 return VINF_SUCCESS;
1622}
1623
1624
1625/**
1626 * @interface_method_impl{PDMISERIALPORT,pfnDataSentNotify}
1627 */
1628static DECLCALLBACK(int) uartR3DataSentNotify(PPDMISERIALPORT pInterface)
1629{
1630 LogFlowFunc(("pInterface=%#p\n", pInterface));
1631 PUARTCORECC pThisCC = RT_FROM_MEMBER(pInterface, UARTCORECC, ISerialPort);
1632 PUARTCORE pThis = pThisCC->pShared;
1633 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1634
1635 /* Set the transmitter empty bit because everything was sent. */
1636 int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1637 AssertRCReturn(rcLock, rcLock);
1638
1639 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_TEMT);
1640 uartIrqUpdate(pDevIns, pThis, pThisCC);
1641
1642 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1643 return VINF_SUCCESS;
1644}
1645
1646
1647/**
1648 * @interface_method_impl{PDMISERIALPORT,pfnReadWr}
1649 */
1650static DECLCALLBACK(int) uartR3ReadWr(PPDMISERIALPORT pInterface, void *pvBuf, size_t cbRead, size_t *pcbRead)
1651{
1652 LogFlowFunc(("pInterface=%#p pvBuf=%#p cbRead=%zu pcbRead=%#p\n", pInterface, pvBuf, cbRead, pcbRead));
1653 PUARTCORECC pThisCC = RT_FROM_MEMBER(pInterface, UARTCORECC, ISerialPort);
1654 PUARTCORE pThis = pThisCC->pShared;
1655 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1656
1657 AssertReturn(cbRead > 0, VERR_INVALID_PARAMETER);
1658
1659 int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1660 AssertRCReturn(rcLock, rcLock);
1661
1662 uartR3TxQueueCopyFrom(pDevIns, pThis, pThisCC, pvBuf, cbRead, pcbRead);
1663
1664 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1665 LogFlowFunc(("-> VINF_SUCCESS{*pcbRead=%zu}\n", *pcbRead));
1666 return VINF_SUCCESS;
1667}
1668
1669
1670/**
1671 * @interface_method_impl{PDMISERIALPORT,pfnNotifyStsLinesChanged}
1672 */
1673static DECLCALLBACK(int) uartR3NotifyStsLinesChanged(PPDMISERIALPORT pInterface, uint32_t fNewStatusLines)
1674{
1675 LogFlowFunc(("pInterface=%#p fNewStatusLines=%#x\n", pInterface, fNewStatusLines));
1676 PUARTCORECC pThisCC = RT_FROM_MEMBER(pInterface, UARTCORECC, ISerialPort);
1677 PUARTCORE pThis = pThisCC->pShared;
1678 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1679 int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1680 AssertRCReturn(rcLock, rcLock);
1681
1682 uartR3StsLinesUpdate(pDevIns, pThis, pThisCC, fNewStatusLines);
1683
1684 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1685 return VINF_SUCCESS;
1686}
1687
1688
1689/**
1690 * @interface_method_impl{PDMISERIALPORT,pfnNotifyBrk}
1691 */
1692static DECLCALLBACK(int) uartR3NotifyBrk(PPDMISERIALPORT pInterface)
1693{
1694 LogFlowFunc(("pInterface=%#p\n", pInterface));
1695 PUARTCORECC pThisCC = RT_FROM_MEMBER(pInterface, UARTCORECC, ISerialPort);
1696 PUARTCORE pThis = pThisCC->pShared;
1697 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1698 int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1699 AssertRCReturn(rcLock, rcLock);
1700
1701 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_BI);
1702 uartIrqUpdate(pDevIns, pThis, pThisCC);
1703
1704 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1705 return VINF_SUCCESS;
1706}
1707
1708
1709/* -=-=-=-=-=-=-=-=- PDMIBASE -=-=-=-=-=-=-=-=- */
1710
1711/**
1712 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
1713 */
1714static DECLCALLBACK(void *) uartR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
1715{
1716 PUARTCORECC pThisCC = RT_FROM_MEMBER(pInterface, UARTCORECC, IBase);
1717 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
1718 PDMIBASE_RETURN_INTERFACE(pszIID, PDMISERIALPORT, &pThisCC->ISerialPort);
1719 return NULL;
1720}
1721
1722
1723/**
1724 * Saves the UART state to the given SSM handle.
1725 *
1726 * @returns VBox status code.
1727 * @param pDevIns The device instance.
1728 * @param pThis The UART core instance.
1729 * @param pSSM The SSM handle to save to.
1730 */
1731DECLHIDDEN(int) uartR3SaveExec(PPDMDEVINS pDevIns, PUARTCORE pThis, PSSMHANDLE pSSM)
1732{
1733 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1734
1735 pHlp->pfnSSMPutU16(pSSM, pThis->uRegDivisor);
1736 pHlp->pfnSSMPutU8(pSSM, pThis->uRegRbr);
1737 pHlp->pfnSSMPutU8(pSSM, pThis->uRegThr);
1738 pHlp->pfnSSMPutU8(pSSM, pThis->uRegIer);
1739 pHlp->pfnSSMPutU8(pSSM, pThis->uRegIir);
1740 pHlp->pfnSSMPutU8(pSSM, pThis->uRegFcr);
1741 pHlp->pfnSSMPutU8(pSSM, pThis->uRegLcr);
1742 pHlp->pfnSSMPutU8(pSSM, pThis->uRegMcr);
1743 pHlp->pfnSSMPutU8(pSSM, pThis->uRegLsr);
1744 pHlp->pfnSSMPutU8(pSSM, pThis->uRegMsr);
1745 pHlp->pfnSSMPutU8(pSSM, pThis->uRegScr);
1746 pHlp->pfnSSMPutBool(pSSM, pThis->fIrqCtiPending);
1747 pHlp->pfnSSMPutBool(pSSM, pThis->fThreEmptyPending);
1748 pHlp->pfnSSMPutU8(pSSM, pThis->FifoXmit.cbMax);
1749 pHlp->pfnSSMPutU8(pSSM, pThis->FifoXmit.cbItl);
1750 pHlp->pfnSSMPutU8(pSSM, pThis->FifoRecv.cbMax);
1751 pHlp->pfnSSMPutU8(pSSM, pThis->FifoRecv.cbItl);
1752
1753 int rc = PDMDevHlpTimerSave(pDevIns, pThis->hTimerRcvFifoTimeout, pSSM);
1754 if (RT_SUCCESS(rc))
1755 rc = PDMDevHlpTimerSave(pDevIns, pThis->hTimerTxUnconnected, pSSM);
1756
1757 return rc;
1758}
1759
1760
1761/**
1762 * Loads the UART state from the given SSM handle.
1763 *
1764 * @returns VBox status code.
1765 * @param pDevIns The device instance.
1766 * @param pThis The UART core instance.
1767 * @param pSSM The SSM handle to load from.
1768 * @param uVersion Saved state version.
1769 * @param uPass The SSM pass the call is done in.
1770 * @param pbIrq Where to store the IRQ value for legacy
1771 * saved states - optional.
1772 * @param pPortBase Where to store the I/O port base for legacy
1773 * saved states - optional.
1774 */
1775DECLHIDDEN(int) uartR3LoadExec(PPDMDEVINS pDevIns, PUARTCORE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass,
1776 uint8_t *pbIrq, RTIOPORT *pPortBase)
1777{
1778 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1779 int rc;
1780 RT_NOREF(uPass);
1781
1782 if (uVersion > UART_SAVED_STATE_VERSION_LEGACY_CODE)
1783 {
1784 pHlp->pfnSSMGetU16(pSSM, &pThis->uRegDivisor);
1785 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegRbr);
1786 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegThr);
1787 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegIer);
1788 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegIir);
1789 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegFcr);
1790 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegLcr);
1791 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegMcr);
1792 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegLsr);
1793 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegMsr);
1794 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegScr);
1795 pHlp->pfnSSMGetBool(pSSM, &pThis->fIrqCtiPending);
1796 pHlp->pfnSSMGetBool(pSSM, &pThis->fThreEmptyPending);
1797 pHlp->pfnSSMGetU8(pSSM, &pThis->FifoXmit.cbMax);
1798 pHlp->pfnSSMGetU8(pSSM, &pThis->FifoXmit.cbItl);
1799 pHlp->pfnSSMGetU8(pSSM, &pThis->FifoRecv.cbMax);
1800 pHlp->pfnSSMGetU8(pSSM, &pThis->FifoRecv.cbItl);
1801
1802 rc = PDMDevHlpTimerLoad(pDevIns, pThis->hTimerRcvFifoTimeout, pSSM);
1803 if (uVersion > UART_SAVED_STATE_VERSION_PRE_UNCONNECTED_TX_TIMER)
1804 rc = PDMDevHlpTimerLoad(pDevIns, pThis->hTimerTxUnconnected, pSSM);
1805 }
1806 else
1807 {
1808 AssertPtr(pbIrq);
1809 AssertPtr(pPortBase);
1810 if (uVersion == UART_SAVED_STATE_VERSION_16450)
1811 {
1812 pThis->enmType = UARTTYPE_16450;
1813 LogRel(("Serial#%d: falling back to 16450 mode from load state\n", pDevIns->iInstance));
1814 }
1815
1816 pHlp->pfnSSMGetU16(pSSM, &pThis->uRegDivisor);
1817 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegRbr);
1818 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegIer);
1819 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegLcr);
1820 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegMcr);
1821 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegLsr);
1822 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegMsr);
1823 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegScr);
1824 if (uVersion > UART_SAVED_STATE_VERSION_16450)
1825 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegFcr);
1826
1827 int32_t iTmp = 0;
1828 pHlp->pfnSSMGetS32(pSSM, &iTmp);
1829 pThis->fThreEmptyPending = RT_BOOL(iTmp);
1830
1831 rc = pHlp->pfnSSMGetS32(pSSM, &iTmp);
1832 AssertRCReturn(rc, rc);
1833 *pbIrq = (uint8_t)iTmp;
1834
1835 pHlp->pfnSSMSkip(pSSM, sizeof(int32_t)); /* was: last_break_enable */
1836
1837 uint32_t uPortBaseTmp = 0;
1838 rc = pHlp->pfnSSMGetU32(pSSM, &uPortBaseTmp);
1839 AssertRCReturn(rc, rc);
1840 *pPortBase = (RTIOPORT)uPortBaseTmp;
1841
1842 rc = pHlp->pfnSSMSkip(pSSM, sizeof(bool)); /* was: msr_changed */
1843 if ( RT_SUCCESS(rc)
1844 && uVersion > UART_SAVED_STATE_VERSION_MISSING_BITS)
1845 {
1846 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegThr);
1847 pHlp->pfnSSMSkip(pSSM, sizeof(uint8_t)); /* The old transmit shift register, not used anymore. */
1848 pHlp->pfnSSMGetU8(pSSM, &pThis->uRegIir);
1849
1850 int32_t iTimeoutPending = 0;
1851 pHlp->pfnSSMGetS32(pSSM, &iTimeoutPending);
1852 pThis->fIrqCtiPending = RT_BOOL(iTimeoutPending);
1853
1854 rc = PDMDevHlpTimerLoad(pDevIns, pThis->hTimerRcvFifoTimeout, pSSM);
1855 AssertRCReturn(rc, rc);
1856
1857 bool fWasActiveIgn;
1858 rc = pHlp->pfnTimerSkipLoad(pSSM, &fWasActiveIgn); /* was: transmit_timerR3 */
1859 AssertRCReturn(rc, rc);
1860
1861 pHlp->pfnSSMGetU8(pSSM, &pThis->FifoRecv.cbItl);
1862 rc = pHlp->pfnSSMGetU8(pSSM, &pThis->FifoRecv.cbItl);
1863 }
1864 }
1865
1866 return rc;
1867}
1868
1869
1870/**
1871 * Called when loading the state completed, updates the parameters of any driver underneath.
1872 *
1873 * @returns VBox status code.
1874 * @param pDevIns The device instance.
1875 * @param pThis The shared serial port instance data.
1876 * @param pThisCC The serial port instance data for the current context.
1877 * @param pSSM The SSM handle.
1878 */
1879DECLHIDDEN(int) uartR3LoadDone(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, PSSMHANDLE pSSM)
1880{
1881 RT_NOREF(pSSM);
1882
1883 uartR3ParamsUpdate(pDevIns, pThis, pThisCC);
1884 uartIrqUpdate(pDevIns, pThis, pThisCC);
1885
1886 if (pThisCC->pDrvSerial)
1887 {
1888 /* Set the modem lines to reflect the current state. */
1889 int rc = pThisCC->pDrvSerial->pfnChgModemLines(pThisCC->pDrvSerial,
1890 RT_BOOL(pThis->uRegMcr & UART_REG_MCR_RTS),
1891 RT_BOOL(pThis->uRegMcr & UART_REG_MCR_DTR));
1892 if (RT_FAILURE(rc))
1893 LogRel(("Serial#%d: Failed to set modem lines with %Rrc during saved state load\n",
1894 pDevIns->iInstance, rc));
1895
1896 uint32_t fStsLines = 0;
1897 rc = pThisCC->pDrvSerial->pfnQueryStsLines(pThisCC->pDrvSerial, &fStsLines);
1898 if (RT_SUCCESS(rc))
1899 uartR3StsLinesUpdate(pDevIns, pThis, pThisCC, fStsLines);
1900 else
1901 LogRel(("Serial#%d: Failed to query status line status with %Rrc during reset\n",
1902 pDevIns->iInstance, rc));
1903 }
1904
1905 return VINF_SUCCESS;
1906}
1907
1908
1909/**
1910 * Resets the given UART core instance.
1911 *
1912 * @returns nothing.
1913 * @param pDevIns The device instance.
1914 * @param pThis The shared serial port instance data.
1915 * @param pThisCC The serial port instance data for the current context.
1916 */
1917DECLHIDDEN(void) uartR3Reset(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
1918{
1919 pThis->uRegDivisor = 0x0c; /* Default to 9600 Baud. */
1920 pThis->uRegRbr = 0;
1921 pThis->uRegThr = 0;
1922 pThis->uRegIer = 0;
1923 pThis->uRegIir = UART_REG_IIR_IP_NO_INT;
1924 pThis->uRegFcr = 0;
1925 pThis->uRegLcr = 0; /* 5 data bits, no parity, 1 stop bit. */
1926 pThis->uRegMcr = 0;
1927 pThis->uRegLsr = UART_REG_LSR_THRE | UART_REG_LSR_TEMT;
1928 pThis->uRegMsr = UART_REG_MSR_DCD | UART_REG_MSR_CTS | UART_REG_MSR_DSR | UART_REG_MSR_DCTS | UART_REG_MSR_DDSR | UART_REG_MSR_DDCD;
1929 pThis->uRegScr = 0;
1930 pThis->fIrqCtiPending = false;
1931 pThis->fThreEmptyPending = true;
1932
1933 /* Standard FIFO size for 15550A. */
1934 pThis->FifoXmit.cbMax = 16;
1935 pThis->FifoRecv.cbMax = 16;
1936 pThis->FifoRecv.cbItl = 1;
1937
1938 uartR3XferReset(pDevIns, pThis, pThisCC);
1939}
1940
1941
1942/**
1943 * Attaches the given UART core instance to the drivers at the given LUN.
1944 *
1945 * @returns VBox status code.
1946 * @param pDevIns The device instance.
1947 * @param pThis The shared serial port instance data.
1948 * @param pThisCC The serial port instance data for the current context.
1949 * @param iLUN The LUN being attached.
1950 */
1951DECLHIDDEN(int) uartR3Attach(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, unsigned iLUN)
1952{
1953 int rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThisCC->IBase, &pThisCC->pDrvBase, "Serial Char");
1954 if (RT_SUCCESS(rc))
1955 {
1956 pThisCC->pDrvSerial = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMISERIALCONNECTOR);
1957 if (!pThisCC->pDrvSerial)
1958 {
1959 AssertLogRelMsgFailed(("Configuration error: instance %d has no serial interface!\n", pDevIns->iInstance));
1960 return VERR_PDM_MISSING_INTERFACE;
1961 }
1962 rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1963 if (RT_SUCCESS(rc))
1964 {
1965 uartR3XferReset(pDevIns, pThis, pThisCC);
1966 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1967 }
1968 }
1969 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1970 {
1971 pThisCC->pDrvBase = NULL;
1972 pThisCC->pDrvSerial = NULL;
1973 rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1974 if (RT_SUCCESS(rc))
1975 {
1976 uartR3XferReset(pDevIns, pThis, pThisCC);
1977 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1978 }
1979 LogRel(("Serial#%d: no unit\n", pDevIns->iInstance));
1980 }
1981 else /* Don't call VMSetError here as we assume that the driver already set an appropriate error */
1982 LogRel(("Serial#%d: Failed to attach to serial driver. rc=%Rrc\n", pDevIns->iInstance, rc));
1983
1984 return rc;
1985}
1986
1987
1988/**
1989 * Detaches any attached driver from the given UART core instance.
1990 *
1991 * @returns nothing.
1992 * @param pDevIns The device instance.
1993 * @param pThis The shared serial port instance data.
1994 * @param pThisCC The serial port instance data for the current context.
1995 */
1996DECLHIDDEN(void) uartR3Detach(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
1997{
1998 /* Zero out important members. */
1999 pThisCC->pDrvBase = NULL;
2000 pThisCC->pDrvSerial = NULL;
2001 int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
2002 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
2003
2004 uartR3XferReset(pDevIns, pThis, pThisCC);
2005
2006 PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
2007}
2008
2009
2010/**
2011 * Destroys the given UART core instance freeing all allocated resources.
2012 *
2013 * @returns nothing.
2014 * @param pDevIns The device instance.
2015 * @param pThis The shared UART core instance data..
2016 */
2017DECLHIDDEN(void) uartR3Destruct(PPDMDEVINS pDevIns, PUARTCORE pThis)
2018{
2019 PDMDevHlpCritSectDelete(pDevIns, &pThis->CritSect);
2020}
2021
2022
2023/**
2024 * Initializes the given UART core instance using the provided configuration.
2025 *
2026 * @returns VBox status code.
2027 * @param pDevIns The device instance pointer.
2028 * @param pThis The shared UART core instance data to
2029 * initialize.
2030 * @param pThisCC The ring-3 UART core instance data to
2031 * initialize.
2032 * @param enmType The type of UART emulated.
2033 * @param iLUN The LUN the UART should look for attached drivers.
2034 * @param fFlags Additional flags controlling device behavior.
2035 * @param pfnUartIrqReq Pointer to the interrupt request callback.
2036 */
2037DECLHIDDEN(int) uartR3Init(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC,
2038 UARTTYPE enmType, unsigned iLUN, uint32_t fFlags, PFNUARTCOREIRQREQ pfnUartIrqReq)
2039{
2040 /*
2041 * Initialize the instance data.
2042 * (Do this early or the destructor might choke on something!)
2043 */
2044 pThis->iLUN = iLUN;
2045 pThis->enmType = enmType;
2046 pThis->fFlags = fFlags;
2047
2048 pThisCC->iLUN = iLUN;
2049 pThisCC->pDevIns = pDevIns;
2050 pThisCC->pShared = pThis;
2051 pThisCC->pfnUartIrqReq = pfnUartIrqReq;
2052
2053 /* IBase */
2054 pThisCC->IBase.pfnQueryInterface = uartR3QueryInterface;
2055
2056 /* ISerialPort */
2057 pThisCC->ISerialPort.pfnDataAvailRdrNotify = uartR3DataAvailRdrNotify;
2058 pThisCC->ISerialPort.pfnDataSentNotify = uartR3DataSentNotify;
2059 pThisCC->ISerialPort.pfnReadWr = uartR3ReadWr;
2060 pThisCC->ISerialPort.pfnNotifyStsLinesChanged = uartR3NotifyStsLinesChanged;
2061 pThisCC->ISerialPort.pfnNotifyBrk = uartR3NotifyBrk;
2062
2063 int rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "Uart{%s#%d}#%d",
2064 pDevIns->pReg->szName, pDevIns->iInstance, iLUN);
2065 AssertRCReturn(rc, rc);
2066
2067 /*
2068 * Attach the char driver and get the interfaces.
2069 */
2070 rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThisCC->IBase, &pThisCC->pDrvBase, "UART");
2071 if (RT_SUCCESS(rc))
2072 {
2073 pThisCC->pDrvSerial = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMISERIALCONNECTOR);
2074 if (!pThisCC->pDrvSerial)
2075 {
2076 AssertLogRelMsgFailed(("Configuration error: instance %d has no serial interface!\n", iLUN));
2077 return VERR_PDM_MISSING_INTERFACE;
2078 }
2079 }
2080 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2081 {
2082 pThisCC->pDrvBase = NULL;
2083 pThisCC->pDrvSerial = NULL;
2084 LogRel(("Serial#%d: no unit\n", iLUN));
2085 }
2086 else
2087 {
2088 AssertLogRelMsgFailed(("Serial#%d: Failed to attach to char driver. rc=%Rrc\n", iLUN, rc));
2089 /* Don't call VMSetError here as we assume that the driver already set an appropriate error */
2090 return rc;
2091 }
2092
2093 /*
2094 * Create the receive FIFO character timeout indicator timer.
2095 */
2096 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, uartR3RcvFifoTimeoutTimer, pThisCC,
2097 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "UART Rcv FIFO",
2098 &pThis->hTimerRcvFifoTimeout);
2099 AssertRCReturn(rc, rc);
2100
2101 rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->hTimerRcvFifoTimeout, &pThis->CritSect);
2102 AssertRCReturn(rc, rc);
2103
2104 /*
2105 * Create the transmit timer when no device is connected.
2106 */
2107 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, uartR3TxUnconnectedTimer, pThisCC,
2108 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_NO_RING0, "UART TX unconnect",
2109 &pThis->hTimerTxUnconnected);
2110 AssertRCReturn(rc, rc);
2111
2112 uartR3Reset(pDevIns, pThis, pThisCC);
2113 return VINF_SUCCESS;
2114}
2115
2116#else /* !IN_RING3 */
2117
2118/**
2119 * Initializes the ring-0 / raw-mode instance data.
2120 *
2121 * @returns VBox status code.
2122 * @param pThisCC The serial port instance data for the current context.
2123 * @param pfnUartIrqReq Pointer to the interrupt request callback.
2124 */
2125DECLHIDDEN(int) uartRZInit(PUARTCORECC pThisCC, PFNUARTCOREIRQREQ pfnUartIrqReq)
2126{
2127 AssertPtrReturn(pfnUartIrqReq, VERR_INVALID_POINTER);
2128 AssertPtrReturn(pThisCC, VERR_INVALID_POINTER);
2129 pThisCC->pfnUartIrqReq = pfnUartIrqReq;
2130 return VINF_SUCCESS;
2131}
2132
2133#endif /* !IN_RING3 */
2134
2135#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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