1 | /* $Id: DevSerial.cpp 11277 2008-08-08 20:15:59Z vboxsync $ */
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2 | /** @file
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3 | * DevSerial - 16450 UART emulation.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2007 Sun Microsystems, Inc.
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | *
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17 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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18 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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19 | * additional information or have any questions.
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20 | */
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21 |
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22 | /*
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23 | * This code is based on:
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24 | *
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25 | * QEMU 16450 UART emulation
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26 | *
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27 | * Copyright (c) 2003-2004 Fabrice Bellard
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28 | *
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29 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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30 | * of this software and associated documentation files (the "Software"), to deal
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31 | * in the Software without restriction, including without limitation the rights
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32 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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33 | * copies of the Software, and to permit persons to whom the Software is
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34 | * furnished to do so, subject to the following conditions:
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35 | *
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36 | * The above copyright notice and this permission notice shall be included in
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37 | * all copies or substantial portions of the Software.
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38 | *
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39 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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40 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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41 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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42 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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43 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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44 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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45 | * THE SOFTWARE.
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46 | *
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47 | */
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48 |
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49 | /*******************************************************************************
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50 | * Header Files *
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51 | *******************************************************************************/
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52 | #define LOG_GROUP LOG_GROUP_DEV_SERIAL
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53 | #include <VBox/pdmdev.h>
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54 | #include <iprt/assert.h>
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55 | #include <iprt/uuid.h>
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56 | #include <iprt/string.h>
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57 | #include <iprt/semaphore.h>
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58 | #include <iprt/critsect.h>
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59 |
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60 | #include "../Builtins.h"
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61 |
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62 | #undef VBOX_SERIAL_PCI /* The PCI variant has lots of problems: wrong IRQ line and wrong IO base assigned. */
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63 |
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64 | #ifdef VBOX_SERIAL_PCI
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65 | # include <VBox/pci.h>
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66 | #endif /* VBOX_SERIAL_PCI */
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67 |
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68 |
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69 | /*******************************************************************************
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70 | * Defined Constants And Macros *
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71 | *******************************************************************************/
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72 | #define SERIAL_SAVED_STATE_VERSION 3
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73 |
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74 | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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75 |
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76 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
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77 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
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78 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
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79 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
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80 |
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81 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
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82 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
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83 |
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84 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */
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85 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
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86 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
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87 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
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88 |
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89 | /*
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90 | * These are the definitions for the Modem Control Register
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91 | */
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92 | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
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93 | #define UART_MCR_OUT2 0x08 /* Out2 complement */
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94 | #define UART_MCR_OUT1 0x04 /* Out1 complement */
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95 | #define UART_MCR_RTS 0x02 /* RTS complement */
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96 | #define UART_MCR_DTR 0x01 /* DTR complement */
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97 |
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98 | /*
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99 | * These are the definitions for the Modem Status Register
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100 | */
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101 | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
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102 | #define UART_MSR_RI 0x40 /* Ring Indicator */
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103 | #define UART_MSR_DSR 0x20 /* Data Set Ready */
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104 | #define UART_MSR_CTS 0x10 /* Clear to Send */
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105 | #define UART_MSR_DDCD 0x08 /* Delta DCD */
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106 | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
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107 | #define UART_MSR_DDSR 0x02 /* Delta DSR */
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108 | #define UART_MSR_DCTS 0x01 /* Delta CTS */
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109 | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
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110 |
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111 | #define UART_LSR_TEMT 0x40 /* Transmitter empty */
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112 | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
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113 | #define UART_LSR_BI 0x10 /* Break interrupt indicator */
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114 | #define UART_LSR_FE 0x08 /* Frame error indicator */
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115 | #define UART_LSR_PE 0x04 /* Parity error indicator */
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116 | #define UART_LSR_OE 0x02 /* Overrun error indicator */
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117 | #define UART_LSR_DR 0x01 /* Receiver data ready */
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118 |
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119 |
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120 | /*******************************************************************************
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121 | * Structures and Typedefs *
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122 | *******************************************************************************/
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123 | struct SerialState
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124 | {
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125 | /** Access critical section. */
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126 | PDMCRITSECT CritSect;
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127 |
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128 | /** Pointer to the device instance - R3 Ptr. */
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129 | PPDMDEVINSR3 pDevInsR3;
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130 | /** Pointer to the device instance - R0 Ptr. */
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131 | PPDMDEVINSR0 pDevInsR0;
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132 | /** Pointer to the device instance - RC Ptr. */
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133 | PPDMDEVINSRC pDevInsRC;
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134 | RTRCPTR Alignment0; /**< Alignment. */
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135 | /** The base interface. */
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136 | PDMIBASE IBase;
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137 | /** The character port interface. */
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138 | PDMICHARPORT ICharPort;
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139 | /** Pointer to the attached base driver. */
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140 | R3PTRTYPE(PPDMIBASE) pDrvBase;
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141 | /** Pointer to the attached character driver. */
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142 | R3PTRTYPE(PPDMICHAR) pDrvChar;
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143 |
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144 | uint16_t divider;
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145 | uint16_t auAlignment[3];
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146 | uint8_t rbr; /* receive register */
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147 | uint8_t ier;
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148 | uint8_t iir; /* read only */
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149 | uint8_t lcr;
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150 | uint8_t mcr;
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151 | uint8_t lsr; /* read only */
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152 | uint8_t msr; /* read only */
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153 | uint8_t scr;
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154 | /* NOTE: this hidden state is necessary for tx irq generation as
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155 | it can be reset while reading iir */
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156 | int thr_ipending;
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157 | int irq;
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158 | bool msr_changed;
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159 |
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160 | bool fGCEnabled;
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161 | bool fR0Enabled;
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162 | bool afAlignment[5];
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163 |
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164 | RTSEMEVENT ReceiveSem;
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165 | int last_break_enable;
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166 | uint32_t base;
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167 |
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168 | #ifdef VBOX_SERIAL_PCI
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169 | PCIDEVICE dev;
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170 | #endif /* VBOX_SERIAL_PCI */
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171 | };
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172 |
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173 | #ifndef VBOX_DEVICE_STRUCT_TESTCASE
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174 |
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175 |
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176 | #ifdef VBOX_SERIAL_PCI
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177 | #define PCIDEV_2_SERIALSTATE(pPciDev) ( (SerialState *)((uintptr_t)(pPciDev) - RT_OFFSETOF(SerialState, dev)) )
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178 | #endif /* VBOX_SERIAL_PCI */
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179 | #define PDMIBASE_2_SERIALSTATE(pInstance) ( (SerialState *)((uintptr_t)(pInterface) - RT_OFFSETOF(SerialState, IBase)) )
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180 | #define PDMICHARPORT_2_SERIALSTATE(pInstance) ( (SerialState *)((uintptr_t)(pInterface) - RT_OFFSETOF(SerialState, ICharPort)) )
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181 |
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182 |
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183 | /*******************************************************************************
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184 | * Internal Functions *
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185 | *******************************************************************************/
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186 | __BEGIN_DECLS
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187 | PDMBOTHCBDECL(int) serialIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
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188 | PDMBOTHCBDECL(int) serialIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
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189 | __END_DECLS
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190 |
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191 | #ifdef IN_RING3
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192 |
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193 | static void serial_update_irq(SerialState *s)
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194 | {
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195 | if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
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196 | s->iir = UART_IIR_RDI;
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197 | } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
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198 | s->iir = UART_IIR_THRI;
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199 | } else if (s->msr_changed && (s->ier & UART_IER_RLSI)) {
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200 | s->iir = UART_IIR_RLSI;
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201 | } else {
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202 | s->iir = UART_IIR_NO_INT;
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203 | }
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204 | if (s->iir != UART_IIR_NO_INT) {
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205 | Log(("serial_update_irq %d 1\n", s->irq));
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206 | # ifdef VBOX_SERIAL_PCI
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207 | PDMDevHlpPCISetIrqNoWait(s->CTX_SUFF(pDevIns), 0, 1);
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208 | # else /* !VBOX_SERIAL_PCI */
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209 | PDMDevHlpISASetIrqNoWait(s->CTX_SUFF(pDevIns), s->irq, 1);
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210 | # endif /* !VBOX_SERIAL_PCI */
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211 | } else {
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212 | Log(("serial_update_irq %d 0\n", s->irq));
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213 | # ifdef VBOX_SERIAL_PCI
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214 | PDMDevHlpPCISetIrqNoWait(s->CTX_SUFF(pDevIns), 0, 0);
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215 | # else /* !VBOX_SERIAL_PCI */
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216 | PDMDevHlpISASetIrqNoWait(s->CTX_SUFF(pDevIns), s->irq, 0);
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217 | # endif /* !VBOX_SERIAL_PCI */
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218 | }
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219 | }
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220 |
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221 | static void serial_update_parameters(SerialState *s)
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222 | {
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223 | int speed, parity, data_bits, stop_bits;
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224 |
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225 | if (s->lcr & 0x08) {
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226 | if (s->lcr & 0x10)
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227 | parity = 'E';
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228 | else
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229 | parity = 'O';
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230 | } else {
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231 | parity = 'N';
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232 | }
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233 | if (s->lcr & 0x04)
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234 | stop_bits = 2;
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235 | else
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236 | stop_bits = 1;
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237 | data_bits = (s->lcr & 0x03) + 5;
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238 | if (s->divider == 0)
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239 | return;
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240 | speed = 115200 / s->divider;
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241 | Log(("speed=%d parity=%c data=%d stop=%d\n", speed, parity, data_bits, stop_bits));
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242 | if (RT_LIKELY(s->pDrvChar))
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243 | s->pDrvChar->pfnSetParameters(s->pDrvChar, speed, parity, data_bits, stop_bits);
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244 | }
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245 |
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246 | #endif /* IN_RING3 */
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247 |
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248 | static int serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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249 | {
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250 | SerialState *s = (SerialState *)opaque;
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251 | unsigned char ch;
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252 |
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253 | addr &= 7;
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254 | LogFlow(("serial: write addr=0x%02x val=0x%02x\n", addr, val));
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255 |
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256 | #ifndef IN_RING3
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257 | NOREF(ch);
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258 | NOREF(s);
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259 | return VINF_IOM_HC_IOPORT_WRITE;
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260 | #else
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261 | switch(addr) {
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262 | default:
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263 | case 0:
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264 | if (s->lcr & UART_LCR_DLAB) {
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265 | s->divider = (s->divider & 0xff00) | val;
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266 | serial_update_parameters(s);
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267 | } else {
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268 | s->thr_ipending = 0;
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269 | s->lsr &= ~UART_LSR_THRE;
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270 | serial_update_irq(s);
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271 | ch = val;
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272 | if (RT_LIKELY(s->pDrvChar))
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273 | {
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274 | Log(("serial_io_port_write: write 0x%X\n", ch));
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275 | int rc = s->pDrvChar->pfnWrite(s->pDrvChar, &ch, 1);
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276 | AssertRC(rc);
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277 | }
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278 | s->thr_ipending = 1;
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279 | s->lsr |= UART_LSR_THRE;
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280 | s->lsr |= UART_LSR_TEMT;
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281 | serial_update_irq(s);
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282 | }
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283 | break;
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284 | case 1:
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285 | if (s->lcr & UART_LCR_DLAB) {
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286 | s->divider = (s->divider & 0x00ff) | (val << 8);
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287 | serial_update_parameters(s);
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288 | } else {
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289 | s->ier = val & 0x0f;
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290 | if (s->lsr & UART_LSR_THRE) {
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291 | s->thr_ipending = 1;
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292 | }
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293 | serial_update_irq(s);
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294 | }
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295 | break;
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296 | case 2:
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297 | break;
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298 | case 3:
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299 | {
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300 | int break_enable;
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301 | if (s->lcr != val)
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302 | {
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303 | s->lcr = val;
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304 | serial_update_parameters(s);
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305 | }
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306 | break_enable = (val >> 6) & 1;
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307 | if (break_enable != s->last_break_enable) {
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308 | s->last_break_enable = break_enable;
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309 | }
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310 | }
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311 | break;
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312 | case 4:
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313 | s->mcr = val & 0x1f;
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314 | if (RT_LIKELY(s->pDrvChar))
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315 | {
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316 | int rc = s->pDrvChar->pfnSetModemLines(s->pDrvChar, !!(s->mcr & UART_MCR_RTS), !!(s->mcr & UART_MCR_DTR));
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317 | AssertRC(rc);
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318 | }
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319 | break;
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320 | case 5:
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321 | break;
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322 | case 6:
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323 | break;
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324 | case 7:
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325 | s->scr = val;
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326 | break;
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327 | }
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328 | return VINF_SUCCESS;
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329 | #endif
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330 | }
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331 |
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332 | static uint32_t serial_ioport_read(void *opaque, uint32_t addr, int *pRC)
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333 | {
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334 | SerialState *s = (SerialState *)opaque;
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335 | uint32_t ret = ~0U;
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336 |
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337 | *pRC = VINF_SUCCESS;
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338 |
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339 | addr &= 7;
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340 | switch(addr) {
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341 | default:
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342 | case 0:
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343 | if (s->lcr & UART_LCR_DLAB) {
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344 | ret = s->divider & 0xff;
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345 | } else {
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346 | #ifndef IN_RING3
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347 | *pRC = VINF_IOM_HC_IOPORT_READ;
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348 | #else
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349 | Log(("serial_io_port_read: read 0x%X\n", s->rbr));
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350 | ret = s->rbr;
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351 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
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352 | serial_update_irq(s);
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353 | {
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354 | int rc = RTSemEventSignal(s->ReceiveSem);
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355 | AssertRC(rc);
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356 | }
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357 | #endif
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358 | }
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359 | break;
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360 | case 1:
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361 | if (s->lcr & UART_LCR_DLAB) {
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362 | ret = (s->divider >> 8) & 0xff;
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363 | } else {
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364 | ret = s->ier;
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365 | }
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366 | break;
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367 | case 2:
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368 | #ifndef IN_RING3
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369 | *pRC = VINF_IOM_HC_IOPORT_READ;
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370 | #else
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371 | ret = s->iir;
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372 | /* reset THR pending bit */
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373 | if ((ret & 0x7) == UART_IIR_THRI)
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374 | s->thr_ipending = 0;
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375 | /* reset msr changed bit */
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376 | s->msr_changed = false;
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377 | serial_update_irq(s);
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378 | #endif
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379 | break;
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380 | case 3:
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381 | ret = s->lcr;
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382 | break;
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383 | case 4:
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384 | ret = s->mcr;
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385 | break;
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386 | case 5:
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387 | ret = s->lsr;
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388 | break;
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389 | case 6:
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390 | if (s->mcr & UART_MCR_LOOP) {
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391 | /* in loopback, the modem output pins are connected to the
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392 | inputs */
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393 | ret = (s->mcr & 0x0c) << 4;
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394 | ret |= (s->mcr & 0x02) << 3;
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395 | ret |= (s->mcr & 0x01) << 5;
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396 | } else {
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397 | ret = s->msr;
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398 | /* Reset delta bits. */
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399 | s->msr &= ~UART_MSR_ANY_DELTA;
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400 | }
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401 | break;
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402 | case 7:
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403 | ret = s->scr;
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404 | break;
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405 | }
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406 | LogFlow(("serial: read addr=0x%02x val=0x%02x\n", addr, ret));
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407 | return ret;
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408 | }
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409 |
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410 | #ifdef IN_RING3
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411 |
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412 | static DECLCALLBACK(int) serialNotifyRead(PPDMICHARPORT pInterface, const void *pvBuf, size_t *pcbRead)
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413 | {
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414 | SerialState *pThis = PDMICHARPORT_2_SERIALSTATE(pInterface);
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415 | int rc;
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416 |
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417 | Assert(*pcbRead != 0);
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418 |
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419 | PDMCritSectEnter(&pThis->CritSect, VERR_PERMISSION_DENIED);
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420 | if (pThis->lsr & UART_LSR_DR)
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421 | {
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422 | /* If a character is still in the read queue, then wait for it to be emptied. */
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423 | PDMCritSectLeave(&pThis->CritSect);
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424 | rc = RTSemEventWait(pThis->ReceiveSem, 250);
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425 | if (RT_FAILURE(rc))
|
---|
426 | return rc;
|
---|
427 |
|
---|
428 | PDMCritSectEnter(&pThis->CritSect, VERR_PERMISSION_DENIED);
|
---|
429 | }
|
---|
430 |
|
---|
431 | if (!(pThis->lsr & UART_LSR_DR))
|
---|
432 | {
|
---|
433 | pThis->rbr = *(const char *)pvBuf;
|
---|
434 | pThis->lsr |= UART_LSR_DR;
|
---|
435 | serial_update_irq(pThis);
|
---|
436 | *pcbRead = 1;
|
---|
437 | rc = VINF_SUCCESS;
|
---|
438 | }
|
---|
439 | else
|
---|
440 | rc = VERR_TIMEOUT;
|
---|
441 |
|
---|
442 | PDMCritSectLeave(&pThis->CritSect);
|
---|
443 |
|
---|
444 | return rc;
|
---|
445 | }
|
---|
446 |
|
---|
447 | static DECLCALLBACK(int) serialNotifyStatusLinesChanged(PPDMICHARPORT pInterface, uint32_t newStatusLines)
|
---|
448 | {
|
---|
449 | SerialState *pThis = PDMICHARPORT_2_SERIALSTATE(pInterface);
|
---|
450 | uint8_t newMsr = 0;
|
---|
451 |
|
---|
452 | Log(("%s: pInterface=%p newStatusLines=%u\n", __FUNCTION__, pInterface, newStatusLines));
|
---|
453 |
|
---|
454 | PDMCritSectEnter(&pThis->CritSect, VERR_PERMISSION_DENIED);
|
---|
455 |
|
---|
456 | /* Set new states. */
|
---|
457 | if (newStatusLines & PDM_ICHAR_STATUS_LINES_DCD)
|
---|
458 | newMsr |= UART_MSR_DCD;
|
---|
459 | if (newStatusLines & PDM_ICHAR_STATUS_LINES_RI)
|
---|
460 | newMsr |= UART_MSR_RI;
|
---|
461 | if (newStatusLines & PDM_ICHAR_STATUS_LINES_DSR)
|
---|
462 | newMsr |= UART_MSR_DSR;
|
---|
463 | if (newStatusLines & PDM_ICHAR_STATUS_LINES_CTS)
|
---|
464 | newMsr |= UART_MSR_CTS;
|
---|
465 |
|
---|
466 | /* Compare the old and the new states and set the delta bits accordingly. */
|
---|
467 | if ((newMsr & UART_MSR_DCD) != (pThis->msr & UART_MSR_DCD))
|
---|
468 | newMsr |= UART_MSR_DDCD;
|
---|
469 | if ((newMsr & UART_MSR_RI) == 1 && (pThis->msr & UART_MSR_RI) == 0)
|
---|
470 | newMsr |= UART_MSR_TERI;
|
---|
471 | if ((newMsr & UART_MSR_DSR) != (pThis->msr & UART_MSR_DSR))
|
---|
472 | newMsr |= UART_MSR_DDSR;
|
---|
473 | if ((newMsr & UART_MSR_CTS) != (pThis->msr & UART_MSR_CTS))
|
---|
474 | newMsr |= UART_MSR_DCTS;
|
---|
475 |
|
---|
476 | pThis->msr = newMsr;
|
---|
477 | pThis->msr_changed = true;
|
---|
478 | serial_update_irq(pThis);
|
---|
479 |
|
---|
480 | PDMCritSectLeave(&pThis->CritSect);
|
---|
481 |
|
---|
482 | return VINF_SUCCESS;
|
---|
483 | }
|
---|
484 |
|
---|
485 | #endif /* IN_RING3 */
|
---|
486 |
|
---|
487 | /**
|
---|
488 | * Port I/O Handler for OUT operations.
|
---|
489 | *
|
---|
490 | * @returns VBox status code.
|
---|
491 | *
|
---|
492 | * @param pDevIns The device instance.
|
---|
493 | * @param pvUser User argument.
|
---|
494 | * @param Port Port number used for the IN operation.
|
---|
495 | * @param u32 The value to output.
|
---|
496 | * @param cb The value size in bytes.
|
---|
497 | */
|
---|
498 | PDMBOTHCBDECL(int) serialIOPortWrite(PPDMDEVINS pDevIns, void *pvUser,
|
---|
499 | RTIOPORT Port, uint32_t u32, unsigned cb)
|
---|
500 | {
|
---|
501 | SerialState *pThis = PDMINS_2_DATA(pDevIns, SerialState *);
|
---|
502 | int rc = VINF_SUCCESS;
|
---|
503 |
|
---|
504 | if (cb == 1)
|
---|
505 | {
|
---|
506 | rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_HC_IOPORT_WRITE);
|
---|
507 | if (rc == VINF_SUCCESS)
|
---|
508 | {
|
---|
509 | Log2(("%s: port %#06x val %#04x\n", __FUNCTION__, Port, u32));
|
---|
510 | rc = serial_ioport_write(pThis, Port, u32);
|
---|
511 | PDMCritSectLeave(&pThis->CritSect);
|
---|
512 | }
|
---|
513 | }
|
---|
514 | else
|
---|
515 | AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
|
---|
516 |
|
---|
517 | return rc;
|
---|
518 | }
|
---|
519 |
|
---|
520 | /**
|
---|
521 | * Port I/O Handler for IN operations.
|
---|
522 | *
|
---|
523 | * @returns VBox status code.
|
---|
524 | *
|
---|
525 | * @param pDevIns The device instance.
|
---|
526 | * @param pvUser User argument.
|
---|
527 | * @param Port Port number used for the IN operation.
|
---|
528 | * @param u32 The value to output.
|
---|
529 | * @param cb The value size in bytes.
|
---|
530 | */
|
---|
531 | PDMBOTHCBDECL(int) serialIOPortRead(PPDMDEVINS pDevIns, void *pvUser,
|
---|
532 | RTIOPORT Port, uint32_t *pu32, unsigned cb)
|
---|
533 | {
|
---|
534 | SerialState *pThis = PDMINS_2_DATA(pDevIns, SerialState *);
|
---|
535 | int rc = VINF_SUCCESS;
|
---|
536 |
|
---|
537 | if (cb == 1)
|
---|
538 | {
|
---|
539 | rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_HC_IOPORT_READ);
|
---|
540 | if (rc == VINF_SUCCESS)
|
---|
541 | {
|
---|
542 | *pu32 = serial_ioport_read(pThis, Port, &rc);
|
---|
543 | Log2(("%s: port %#06x val %#04x\n", __FUNCTION__, Port, *pu32));
|
---|
544 | PDMCritSectLeave(&pThis->CritSect);
|
---|
545 | }
|
---|
546 | }
|
---|
547 | else
|
---|
548 | rc = VERR_IOM_IOPORT_UNUSED;
|
---|
549 |
|
---|
550 | return rc;
|
---|
551 | }
|
---|
552 |
|
---|
553 | #ifdef IN_RING3
|
---|
554 |
|
---|
555 | /**
|
---|
556 | * Saves a state of the serial port device.
|
---|
557 | *
|
---|
558 | * @returns VBox status code.
|
---|
559 | * @param pDevIns The device instance.
|
---|
560 | * @param pSSMHandle The handle to save the state to.
|
---|
561 | */
|
---|
562 | static DECLCALLBACK(int) serialSaveExec(PPDMDEVINS pDevIns,
|
---|
563 | PSSMHANDLE pSSMHandle)
|
---|
564 | {
|
---|
565 | SerialState *pThis = PDMINS_2_DATA(pDevIns, SerialState *);
|
---|
566 |
|
---|
567 | SSMR3PutU16(pSSMHandle, pThis->divider);
|
---|
568 | SSMR3PutU8(pSSMHandle, pThis->rbr);
|
---|
569 | SSMR3PutU8(pSSMHandle, pThis->ier);
|
---|
570 | SSMR3PutU8(pSSMHandle, pThis->lcr);
|
---|
571 | SSMR3PutU8(pSSMHandle, pThis->mcr);
|
---|
572 | SSMR3PutU8(pSSMHandle, pThis->lsr);
|
---|
573 | SSMR3PutU8(pSSMHandle, pThis->msr);
|
---|
574 | SSMR3PutU8(pSSMHandle, pThis->scr);
|
---|
575 | SSMR3PutS32(pSSMHandle, pThis->thr_ipending);
|
---|
576 | SSMR3PutS32(pSSMHandle, pThis->irq);
|
---|
577 | SSMR3PutS32(pSSMHandle, pThis->last_break_enable);
|
---|
578 | SSMR3PutU32(pSSMHandle, pThis->base);
|
---|
579 | SSMR3PutBool(pSSMHandle, pThis->msr_changed);
|
---|
580 | return SSMR3PutU32(pSSMHandle, ~0); /* sanity/terminator */
|
---|
581 | }
|
---|
582 |
|
---|
583 | /**
|
---|
584 | * Loads a saved serial port device state.
|
---|
585 | *
|
---|
586 | * @returns VBox status code.
|
---|
587 | * @param pDevIns The device instance.
|
---|
588 | * @param pSSMHandle The handle to the saved state.
|
---|
589 | * @param u32Version The data unit version number.
|
---|
590 | */
|
---|
591 | static DECLCALLBACK(int) serialLoadExec(PPDMDEVINS pDevIns,
|
---|
592 | PSSMHANDLE pSSMHandle,
|
---|
593 | uint32_t u32Version)
|
---|
594 | {
|
---|
595 | int rc;
|
---|
596 | uint32_t u32;
|
---|
597 | SerialState *pThis = PDMINS_2_DATA(pDevIns, SerialState *);
|
---|
598 |
|
---|
599 | if (u32Version != SERIAL_SAVED_STATE_VERSION)
|
---|
600 | {
|
---|
601 | AssertMsgFailed(("u32Version=%d\n", u32Version));
|
---|
602 | return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
|
---|
603 | }
|
---|
604 |
|
---|
605 | SSMR3GetU16(pSSMHandle, &pThis->divider);
|
---|
606 | SSMR3GetU8(pSSMHandle, &pThis->rbr);
|
---|
607 | SSMR3GetU8(pSSMHandle, &pThis->ier);
|
---|
608 | SSMR3GetU8(pSSMHandle, &pThis->lcr);
|
---|
609 | SSMR3GetU8(pSSMHandle, &pThis->mcr);
|
---|
610 | SSMR3GetU8(pSSMHandle, &pThis->lsr);
|
---|
611 | SSMR3GetU8(pSSMHandle, &pThis->msr);
|
---|
612 | SSMR3GetU8(pSSMHandle, &pThis->scr);
|
---|
613 | SSMR3GetS32(pSSMHandle, &pThis->thr_ipending);
|
---|
614 | SSMR3GetS32(pSSMHandle, &pThis->irq);
|
---|
615 | SSMR3GetS32(pSSMHandle, &pThis->last_break_enable);
|
---|
616 | SSMR3GetU32(pSSMHandle, &pThis->base);
|
---|
617 | SSMR3GetBool(pSSMHandle, &pThis->msr_changed);
|
---|
618 |
|
---|
619 | rc = SSMR3GetU32(pSSMHandle, &u32);
|
---|
620 | if (RT_FAILURE(rc))
|
---|
621 | return rc;
|
---|
622 |
|
---|
623 | if (u32 != ~0U)
|
---|
624 | {
|
---|
625 | AssertLogRelMsgFailed(("u32=%#x expected ~0\n", u32));
|
---|
626 | return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
|
---|
627 | }
|
---|
628 | /* Be careful with pointers in the structure; they are not preserved
|
---|
629 | * in the saved state. */
|
---|
630 |
|
---|
631 | if (pThis->lsr & UART_LSR_DR)
|
---|
632 | {
|
---|
633 | int rc = RTSemEventSignal(pThis->ReceiveSem);
|
---|
634 | AssertRC(rc);
|
---|
635 | }
|
---|
636 |
|
---|
637 | /* this isn't strictly necessary but cannot hurt... */
|
---|
638 | pThis->pDevInsR3 = pDevIns;
|
---|
639 | pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
|
---|
640 | pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
|
---|
641 | return VINF_SUCCESS;
|
---|
642 | }
|
---|
643 |
|
---|
644 |
|
---|
645 | /**
|
---|
646 | * @copydoc FNPDMDEVRELOCATE
|
---|
647 | */
|
---|
648 | static DECLCALLBACK(void) serialRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
|
---|
649 | {
|
---|
650 | SerialState *pThis = PDMINS_2_DATA(pDevIns, SerialState *);
|
---|
651 | pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
|
---|
652 | }
|
---|
653 |
|
---|
654 | #ifdef VBOX_SERIAL_PCI
|
---|
655 |
|
---|
656 | static DECLCALLBACK(int) serialIOPortRegionMap(PPCIDEVICE pPciDev, /* unsigned */ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
|
---|
657 | {
|
---|
658 | SerialState *pThis = PCIDEV_2_SERIALSTATE(pPciDev);
|
---|
659 | int rc = VINF_SUCCESS;
|
---|
660 |
|
---|
661 | Assert(enmType == PCI_ADDRESS_SPACE_IO);
|
---|
662 | Assert(iRegion == 0);
|
---|
663 | Assert(cb == 8);
|
---|
664 | AssertMsg(RT_ALIGN(GCPhysAddress, 8) == GCPhysAddress, ("Expected 8 byte alignment. GCPhysAddress=%#x\n", GCPhysAddress));
|
---|
665 |
|
---|
666 | pThis->base = (RTIOPORT)GCPhysAddress;
|
---|
667 | LogRel(("Serial#%d: mapping I/O at %#06x\n", pThis->pDevIns->iInstance, pThis->base));
|
---|
668 |
|
---|
669 | /*
|
---|
670 | * Register our port IO handlers.
|
---|
671 | */
|
---|
672 | rc = PDMDevHlpIOPortRegister(pPciDev->pDevIns, (RTIOPORT)GCPhysAddress, 8, (void *)pThis,
|
---|
673 | serial_io_write, serial_io_read, NULL, NULL, "SERIAL");
|
---|
674 | AssertRC(rc);
|
---|
675 | return rc;
|
---|
676 | }
|
---|
677 |
|
---|
678 | #endif /* VBOX_SERIAL_PCI */
|
---|
679 |
|
---|
680 |
|
---|
681 | /** @copyfrom PIBASE::pfnqueryInterface */
|
---|
682 | static DECLCALLBACK(void *) serialQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
|
---|
683 | {
|
---|
684 | SerialState *pThis = PDMIBASE_2_SERIALSTATE(pInterface);
|
---|
685 | switch (enmInterface)
|
---|
686 | {
|
---|
687 | case PDMINTERFACE_BASE:
|
---|
688 | return &pThis->IBase;
|
---|
689 | case PDMINTERFACE_CHAR_PORT:
|
---|
690 | return &pThis->ICharPort;
|
---|
691 | default:
|
---|
692 | return NULL;
|
---|
693 | }
|
---|
694 | }
|
---|
695 |
|
---|
696 | /**
|
---|
697 | * Destruct a device instance.
|
---|
698 | *
|
---|
699 | * Most VM resources are freed by the VM. This callback is provided so that any non-VM
|
---|
700 | * resources can be freed correctly.
|
---|
701 | *
|
---|
702 | * @returns VBox status.
|
---|
703 | * @param pDevIns The device instance data.
|
---|
704 | */
|
---|
705 | static DECLCALLBACK(int) serialDestruct(PPDMDEVINS pDevIns)
|
---|
706 | {
|
---|
707 | SerialState *pThis = PDMINS_2_DATA(pDevIns, SerialState *);
|
---|
708 |
|
---|
709 | RTSemEventDestroy(pThis->ReceiveSem);
|
---|
710 | pThis->ReceiveSem = NIL_RTSEMEVENT;
|
---|
711 |
|
---|
712 | PDMR3CritSectDelete(&pThis->CritSect);
|
---|
713 | return VINF_SUCCESS;
|
---|
714 | }
|
---|
715 |
|
---|
716 |
|
---|
717 | /**
|
---|
718 | * Construct a device instance for a VM.
|
---|
719 | *
|
---|
720 | * @returns VBox status.
|
---|
721 | * @param pDevIns The device instance data.
|
---|
722 | * If the registration structure is needed, pDevIns->pDevReg points to it.
|
---|
723 | * @param iInstance Instance number. Use this to figure out which registers and such to use.
|
---|
724 | * The device number is also found in pDevIns->iInstance, but since it's
|
---|
725 | * likely to be freqently used PDM passes it as parameter.
|
---|
726 | * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
|
---|
727 | * of the device instance. It's also found in pDevIns->pCfgHandle, but like
|
---|
728 | * iInstance it's expected to be used a bit in this function.
|
---|
729 | */
|
---|
730 | static DECLCALLBACK(int) serialConstruct(PPDMDEVINS pDevIns,
|
---|
731 | int iInstance,
|
---|
732 | PCFGMNODE pCfgHandle)
|
---|
733 | {
|
---|
734 | int rc;
|
---|
735 | SerialState *pThis = PDMINS_2_DATA(pDevIns, SerialState*);
|
---|
736 | uint16_t io_base;
|
---|
737 | uint8_t irq_lvl;
|
---|
738 |
|
---|
739 | Assert(iInstance < 4);
|
---|
740 |
|
---|
741 | /*
|
---|
742 | * Initialize the instance data.
|
---|
743 | * (Do this early or the destructor might choke on something!)
|
---|
744 | */
|
---|
745 | pThis->pDevInsR3 = pDevIns;
|
---|
746 | pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
|
---|
747 | pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
|
---|
748 |
|
---|
749 | pThis->lsr = UART_LSR_TEMT | UART_LSR_THRE;
|
---|
750 | pThis->iir = UART_IIR_NO_INT;
|
---|
751 | pThis->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
|
---|
752 |
|
---|
753 | /* IBase */
|
---|
754 | pThis->IBase.pfnQueryInterface = serialQueryInterface;
|
---|
755 |
|
---|
756 | /* ICharPort */
|
---|
757 | pThis->ICharPort.pfnNotifyRead = serialNotifyRead;
|
---|
758 | pThis->ICharPort.pfnNotifyStatusLinesChanged = serialNotifyStatusLinesChanged;
|
---|
759 |
|
---|
760 | #ifdef VBOX_SERIAL_PCI
|
---|
761 | /* the PCI device */
|
---|
762 | pThis->dev.config[0x00] = 0xee; /* Vendor: ??? */
|
---|
763 | pThis->dev.config[0x01] = 0x80;
|
---|
764 | pThis->dev.config[0x02] = 0x01; /* Device: ??? */
|
---|
765 | pThis->dev.config[0x03] = 0x01;
|
---|
766 | pThis->dev.config[0x04] = PCI_COMMAND_IOACCESS;
|
---|
767 | pThis->dev.config[0x09] = 0x01; /* Programming interface: 16450 */
|
---|
768 | pThis->dev.config[0x0a] = 0x00; /* Subclass: Serial controller */
|
---|
769 | pThis->dev.config[0x0b] = 0x07; /* Class: Communication controller */
|
---|
770 | pThis->dev.config[0x0e] = 0x00; /* Header type: standard */
|
---|
771 | pThis->dev.config[0x3c] = irq_lvl; /* preconfigure IRQ number (0 = autoconfig)*/
|
---|
772 | pThis->dev.config[0x3d] = 1; /* interrupt pin 0 */
|
---|
773 | #endif /* VBOX_SERIAL_PCI */
|
---|
774 |
|
---|
775 | /*
|
---|
776 | * Validate and read the configuration.
|
---|
777 | */
|
---|
778 | if (!CFGMR3AreValuesValid(pCfgHandle, "IRQ\0" "IOBase\0" "GCEnabled\0" "R0Enabled\0"))
|
---|
779 | {
|
---|
780 | AssertMsgFailed(("serialConstruct Invalid configuration values\n"));
|
---|
781 | return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
|
---|
782 | }
|
---|
783 |
|
---|
784 | rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &pThis->fGCEnabled, true);
|
---|
785 | if (RT_FAILURE(rc))
|
---|
786 | return PDMDEV_SET_ERROR(pDevIns, rc,
|
---|
787 | N_("Configuration error: Failed to get the \"GCEnabled\" value"));
|
---|
788 |
|
---|
789 | rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &pThis->fR0Enabled, true);
|
---|
790 | if (RT_FAILURE(rc))
|
---|
791 | return PDMDEV_SET_ERROR(pDevIns, rc,
|
---|
792 | N_("Configuration error: Failed to get the \"R0Enabled\" value"));
|
---|
793 |
|
---|
794 | rc = CFGMR3QueryU8(pCfgHandle, "IRQ", &irq_lvl);
|
---|
795 | if (rc == VERR_CFGM_VALUE_NOT_FOUND)
|
---|
796 | {
|
---|
797 | /* Provide sensible defaults. */
|
---|
798 | if (iInstance == 0)
|
---|
799 | irq_lvl = 4;
|
---|
800 | else if (iInstance == 1)
|
---|
801 | irq_lvl = 3;
|
---|
802 | else
|
---|
803 | AssertReleaseFailed(); /* irq_lvl is undefined. */
|
---|
804 | }
|
---|
805 | else if (RT_FAILURE(rc))
|
---|
806 | return PDMDEV_SET_ERROR(pDevIns, rc,
|
---|
807 | N_("Configuration error: Failed to get the \"IRQ\" value"));
|
---|
808 |
|
---|
809 | rc = CFGMR3QueryU16(pCfgHandle, "IOBase", &io_base);
|
---|
810 | if (rc == VERR_CFGM_VALUE_NOT_FOUND)
|
---|
811 | {
|
---|
812 | if (iInstance == 0)
|
---|
813 | io_base = 0x3f8;
|
---|
814 | else if (iInstance == 1)
|
---|
815 | io_base = 0x2f8;
|
---|
816 | else
|
---|
817 | AssertReleaseFailed(); /* io_base is undefined */
|
---|
818 | }
|
---|
819 | else if (RT_FAILURE(rc))
|
---|
820 | return PDMDEV_SET_ERROR(pDevIns, rc,
|
---|
821 | N_("Configuration error: Failed to get the \"IOBase\" value"));
|
---|
822 |
|
---|
823 | Log(("DevSerial: instance %d iobase=%04x irq=%d\n", iInstance, io_base, irq_lvl));
|
---|
824 |
|
---|
825 | pThis->irq = irq_lvl;
|
---|
826 | #ifdef VBOX_SERIAL_PCI
|
---|
827 | pThis->base = -1;
|
---|
828 | #else
|
---|
829 | pThis->base = io_base;
|
---|
830 | #endif
|
---|
831 |
|
---|
832 | /*
|
---|
833 | * Initialize critical section and the semaphore.
|
---|
834 | * This must of course be done before attaching drivers or anything else which can call us back..
|
---|
835 | */
|
---|
836 | char szName[24];
|
---|
837 | RTStrPrintf(szName, sizeof(szName), "Serial#%d", iInstance);
|
---|
838 | rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, szName);
|
---|
839 | if (RT_FAILURE(rc))
|
---|
840 | return rc;
|
---|
841 |
|
---|
842 | rc = RTSemEventCreate(&pThis->ReceiveSem);
|
---|
843 | AssertRC(rc);
|
---|
844 |
|
---|
845 | #ifdef VBOX_SERIAL_PCI
|
---|
846 | /*
|
---|
847 | * Register the PCI Device and region.
|
---|
848 | */
|
---|
849 | rc = PDMDevHlpPCIRegister(pDevIns, &pThis->dev);
|
---|
850 | if (RT_FAILURE(rc))
|
---|
851 | return rc;
|
---|
852 | rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 8, PCI_ADDRESS_SPACE_IO, serialIOPortRegionMap);
|
---|
853 | if (RT_FAILURE(rc))
|
---|
854 | return rc;
|
---|
855 |
|
---|
856 | #else /* !VBOX_SERIAL_PCI */
|
---|
857 | /*
|
---|
858 | * Register the I/O ports.
|
---|
859 | */
|
---|
860 | pThis->base = io_base;
|
---|
861 | rc = PDMDevHlpIOPortRegister(pDevIns, io_base, 8, 0,
|
---|
862 | serialIOPortWrite, serialIOPortRead,
|
---|
863 | NULL, NULL, "SERIAL");
|
---|
864 | if (RT_FAILURE(rc))
|
---|
865 | return rc;
|
---|
866 |
|
---|
867 | if (pThis->fGCEnabled)
|
---|
868 | rc = PDMDevHlpIOPortRegisterGC(pDevIns, io_base, 8, 0, "serialIOPortWrite",
|
---|
869 | "serialIOPortRead", NULL, NULL, "Serial");
|
---|
870 |
|
---|
871 | if (pThis->fR0Enabled)
|
---|
872 | rc = PDMDevHlpIOPortRegisterR0(pDevIns, io_base, 8, 0, "serialIOPortWrite",
|
---|
873 | "serialIOPortRead", NULL, NULL, "Serial");
|
---|
874 | #endif /* !VBOX_SERIAL_PCI */
|
---|
875 |
|
---|
876 | /*
|
---|
877 | * Saved state.
|
---|
878 | */
|
---|
879 | rc = PDMDevHlpSSMRegister(
|
---|
880 | pDevIns, /* pDevIns */
|
---|
881 | pDevIns->pDevReg->szDeviceName, /* pszName */
|
---|
882 | iInstance, /* u32Instance */
|
---|
883 | SERIAL_SAVED_STATE_VERSION, /* u32Version */
|
---|
884 | sizeof (*pThis), /* cbGuess */
|
---|
885 | NULL, /* pfnSavePrep */
|
---|
886 | serialSaveExec, /* pfnSaveExec */
|
---|
887 | NULL, /* pfnSaveDone */
|
---|
888 | NULL, /* pfnLoadPrep */
|
---|
889 | serialLoadExec, /* pfnLoadExec */
|
---|
890 | NULL /* pfnLoadDone */
|
---|
891 | );
|
---|
892 | if (RT_FAILURE(rc))
|
---|
893 | return rc;
|
---|
894 |
|
---|
895 | /*
|
---|
896 | * Attach the char driver and get the interfaces.
|
---|
897 | * For now no run-time changes are supported.
|
---|
898 | */
|
---|
899 | rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Serial Char");
|
---|
900 | if (RT_SUCCESS(rc))
|
---|
901 | {
|
---|
902 | pThis->pDrvChar = (PDMICHAR *)pThis->pDrvBase->pfnQueryInterface(pThis->pDrvBase, PDMINTERFACE_CHAR);
|
---|
903 | if (!pThis->pDrvChar)
|
---|
904 | {
|
---|
905 | AssertLogRelMsgFailed(("Configuration error: instance %d has no char interface!\n", iInstance));
|
---|
906 | return VERR_PDM_MISSING_INTERFACE;
|
---|
907 | }
|
---|
908 | /** @todo provide read notification interface!!!! */
|
---|
909 | }
|
---|
910 | else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
|
---|
911 | {
|
---|
912 | pThis->pDrvBase = NULL;
|
---|
913 | pThis->pDrvChar = NULL;
|
---|
914 | LogRel(("Serial%d: no unit\n", iInstance));
|
---|
915 | }
|
---|
916 | else
|
---|
917 | {
|
---|
918 | AssertLogRelMsgFailed(("Serial%d: Failed to attach to char driver. rc=%Vrc\n", iInstance, rc));
|
---|
919 | /* Don't call VMSetError here as we assume that the driver already set an appropriate error */
|
---|
920 | return rc;
|
---|
921 | }
|
---|
922 |
|
---|
923 | return VINF_SUCCESS;
|
---|
924 | }
|
---|
925 |
|
---|
926 |
|
---|
927 | /**
|
---|
928 | * The device registration structure.
|
---|
929 | */
|
---|
930 | const PDMDEVREG g_DeviceSerialPort =
|
---|
931 | {
|
---|
932 | /* u32Version */
|
---|
933 | PDM_DEVREG_VERSION,
|
---|
934 | /* szDeviceName */
|
---|
935 | "serial",
|
---|
936 | /* szGCMod */
|
---|
937 | "VBoxDDGC.gc",
|
---|
938 | /* szR0Mod */
|
---|
939 | "VBoxDDR0.r0",
|
---|
940 | /* pszDescription */
|
---|
941 | "Serial Communication Port",
|
---|
942 | /* fFlags */
|
---|
943 | PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GC | PDM_DEVREG_FLAGS_R0,
|
---|
944 | /* fClass */
|
---|
945 | PDM_DEVREG_CLASS_SERIAL,
|
---|
946 | /* cMaxInstances */
|
---|
947 | 1,
|
---|
948 | /* cbInstance */
|
---|
949 | sizeof(SerialState),
|
---|
950 | /* pfnConstruct */
|
---|
951 | serialConstruct,
|
---|
952 | /* pfnDestruct */
|
---|
953 | serialDestruct,
|
---|
954 | /* pfnRelocate */
|
---|
955 | serialRelocate,
|
---|
956 | /* pfnIOCtl */
|
---|
957 | NULL,
|
---|
958 | /* pfnPowerOn */
|
---|
959 | NULL,
|
---|
960 | /* pfnReset */
|
---|
961 | NULL,
|
---|
962 | /* pfnSuspend */
|
---|
963 | NULL,
|
---|
964 | /* pfnResume */
|
---|
965 | NULL,
|
---|
966 | /* pfnAttach */
|
---|
967 | NULL,
|
---|
968 | /* pfnDetach */
|
---|
969 | NULL,
|
---|
970 | /* pfnQueryInterface. */
|
---|
971 | NULL
|
---|
972 | };
|
---|
973 | #endif /* IN_RING3 */
|
---|
974 |
|
---|
975 |
|
---|
976 | #endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
|
---|