VirtualBox

source: vbox/trunk/src/VBox/Devices/Serial/DevOxPcie958.cpp@ 99739

Last change on this file since 99739 was 99739, checked in by vboxsync, 19 months ago

*: doxygen corrections (mostly about removing @returns from functions returning void).
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1/* $Id: DevOxPcie958.cpp 99739 2023-05-11 01:01:08Z vboxsync $ */
2/** @file
3 * DevOxPcie958 - Oxford Semiconductor OXPCIe958 PCI Express bridge to octal serial port emulation
4 */
5
6/*
7 * Copyright (C) 2018-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28/** @page pg_dev_oxpcie958 OXPCIe958 - Oxford Semiconductor OXPCIe958 PCI Express bridge to octal serial port emulation.
29 * @todo Write something
30 */
31
32
33/*********************************************************************************************************************************
34* Header Files *
35*********************************************************************************************************************************/
36#define LOG_GROUP LOG_GROUP_DEV_SERIAL
37#include <VBox/pci.h>
38#include <VBox/msi.h>
39#include <VBox/vmm/pdm.h>
40#include <VBox/vmm/pdmpci.h>
41#include <VBox/err.h>
42#include <VBox/log.h>
43#include <iprt/assert.h>
44#include <iprt/list.h>
45#include <iprt/asm.h>
46
47#include "VBoxDD.h"
48#include "UartCore.h"
49
50
51/** @name PCI device related constants.
52 * @{ */
53/** The PCI device ID. */
54#define OX958_PCI_DEVICE_ID 0xc308
55/** The PCI vendor ID. */
56#define OX958_PCI_VENDOR_ID 0x1415
57/** Where the MSI capability starts. */
58#define OX958_PCI_MSI_CAP_OFS 0x80
59/** Where the MSI-X capability starts. */
60#define OX958_PCI_MSIX_CAP_OFS (OX958_PCI_MSI_CAP_OFS + VBOX_MSI_CAP_SIZE_64)
61/** The BAR for the MSI-X related functionality. */
62#define OX958_PCI_MSIX_BAR 1
63/** @} */
64
65/** Maximum number of UARTs supported by the device. */
66#define OX958_UARTS_MAX 16
67
68/** Offset op the class code and revision ID register. */
69#define OX958_REG_CC_REV_ID 0x00
70/** Offset fof the UART count register. */
71#define OX958_REG_UART_CNT 0x04
72/** Offset of the global UART IRQ status register. */
73#define OX958_REG_UART_IRQ_STS 0x08
74/** Offset of the global UART IRQ enable register. */
75#define OX958_REG_UART_IRQ_ENABLE 0x0c
76/** Offset of the global UART IRQ disable register. */
77#define OX958_REG_UART_IRQ_DISABLE 0x10
78/** Offset of the global UART wake IRQ enable register. */
79#define OX958_REG_UART_WAKE_IRQ_ENABLE 0x14
80/** Offset of the global UART wake IRQ disable register. */
81#define OX958_REG_UART_WAKE_IRQ_DISABLE 0x18
82/** Offset of the region in MMIO space where the UARTs actually start. */
83#define OX958_REG_UART_REGION_OFFSET 0x1000
84/** Register region size for each UART. */
85#define OX958_REG_UART_REGION_SIZE 0x200
86/** Offset where the DMA channels registers start for each UART. */
87#define OX958_REG_UART_DMA_REGION_OFFSET 0x100
88
89
90/**
91 * Shared OXPCIe958 UART core.
92 */
93typedef struct OX958UART
94{
95 /** The UART core. */
96 UARTCORE UartCore;
97 /** DMA address configured. */
98 RTGCPHYS GCPhysDmaAddr;
99 /** The DMA transfer length configured. */
100 uint32_t cbDmaXfer;
101 /** The DMA status registers. */
102 uint32_t u32RegDmaSts;
103} OX958UART;
104/** Pointer to a shared OXPCIe958 UART core. */
105typedef OX958UART *POX958UART;
106
107/**
108 * Ring-3 OXPCIe958 UART core.
109 */
110typedef struct OX958UARTR3
111{
112 /** The ring-3 UART core. */
113 UARTCORER3 UartCore;
114} OX958UARTR3;
115/** Pointer to a ring-3 OXPCIe958 UART core. */
116typedef OX958UARTR3 *POX958UARTR3;
117
118/**
119 * Ring-0 OXPCIe958 UART core.
120 */
121typedef struct OX958UARTR0
122{
123 /** The ring-0 UART core. */
124 UARTCORER0 UartCore;
125} OX958UARTR0;
126/** Pointer to a ring-0 OXPCIe958 UART core. */
127typedef OX958UARTR0 *POX958UARTR0;
128
129
130/**
131 * Raw-mode OXPCIe958 UART core.
132 */
133typedef struct OX958UARTRC
134{
135 /** The raw-mode UART core. */
136 UARTCORERC UartCore;
137} OX958UARTRC;
138/** Pointer to a raw-mode OXPCIe958 UART core. */
139typedef OX958UARTRC *POX958UARTRC;
140
141/** Current context OXPCIe958 UART core. */
142typedef CTX_SUFF(OX958UART) OX958UARTCC;
143/** Pointer to a current context OXPCIe958 UART core. */
144typedef CTX_SUFF(POX958UART) POX958UARTCC;
145
146
147/**
148 * Shared OXPCIe958 device instance data.
149 */
150typedef struct DEVOX958
151{
152 /** UART global IRQ status. */
153 volatile uint32_t u32RegIrqStsGlob;
154 /** UART global IRQ enable mask. */
155 volatile uint32_t u32RegIrqEnGlob;
156 /** UART wake IRQ enable mask. */
157 volatile uint32_t u32RegIrqEnWake;
158 /** Number of UARTs configured. */
159 uint32_t cUarts;
160 /** Handle to the MMIO region (PCI region \#0). */
161 IOMMMIOHANDLE hMmio;
162 /** The UARTs. */
163 OX958UART aUarts[OX958_UARTS_MAX];
164} DEVOX958;
165/** Pointer to shared OXPCIe958 device instance data. */
166typedef DEVOX958 *PDEVOX958;
167
168/**
169 * Ring-3 OXPCIe958 device instance data.
170 */
171typedef struct DEVOX958R3
172{
173 /** The UARTs. */
174 OX958UARTR3 aUarts[OX958_UARTS_MAX];
175} DEVOX958R3;
176/** Pointer to ring-3 OXPCIe958 device instance data. */
177typedef DEVOX958R3 *PDEVOX958R3;
178
179/**
180 * Ring-0 OXPCIe958 device instance data.
181 */
182typedef struct DEVOX958R0
183{
184 /** The UARTs. */
185 OX958UARTR0 aUarts[OX958_UARTS_MAX];
186} DEVOX958R0;
187/** Pointer to ring-0 OXPCIe958 device instance data. */
188typedef DEVOX958R0 *PDEVOX958R0;
189
190/**
191 * Raw-mode OXPCIe958 device instance data.
192 */
193typedef struct DEVOX958RC
194{
195 /** The UARTs. */
196 OX958UARTRC aUarts[OX958_UARTS_MAX];
197} DEVOX958RC;
198/** Pointer to raw-mode OXPCIe958 device instance data. */
199typedef DEVOX958RC *PDEVOX958RC;
200
201/** Current context OXPCIe958 device instance data. */
202typedef CTX_SUFF(DEVOX958) DEVOX958CC;
203/** Pointer to current context OXPCIe958 device instance data. */
204typedef CTX_SUFF(PDEVOX958) PDEVOX958CC;
205
206
207#ifndef VBOX_DEVICE_STRUCT_TESTCASE
208
209
210
211/**
212 * Update IRQ status of the device.
213 *
214 * @param pDevIns The device instance.
215 * @param pThis The shared OXPCIe958 device instance data.
216 */
217static void ox958IrqUpdate(PPDMDEVINS pDevIns, PDEVOX958 pThis)
218{
219 uint32_t u32IrqSts = ASMAtomicReadU32(&pThis->u32RegIrqStsGlob);
220 uint32_t u32IrqEn = ASMAtomicReadU32(&pThis->u32RegIrqEnGlob);
221
222 if (u32IrqSts & u32IrqEn)
223 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
224 else
225 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
226}
227
228
229/**
230 * Performs a register read from the given UART.
231 *
232 * @returns Strict VBox status code.
233 * @param pDevIns The device instance.
234 * @param pThis The shared OXPCIe958 device instance data.
235 * @param pUart The UART accessed, shared bits.
236 * @param pUartCC The UART accessed, current context bits.
237 * @param offUartReg Offset of the register being read.
238 * @param pv Where to store the read data.
239 * @param cb Number of bytes to read.
240 */
241static VBOXSTRICTRC ox958UartRegRead(PPDMDEVINS pDevIns, PDEVOX958 pThis, POX958UART pUart, POX958UARTCC pUartCC,
242 uint32_t offUartReg, void *pv, unsigned cb)
243{
244 VBOXSTRICTRC rc;
245 RT_NOREF(pThis);
246
247 if (offUartReg >= OX958_REG_UART_DMA_REGION_OFFSET)
248 {
249 /* Access to the DMA registers. */
250 rc = VINF_SUCCESS;
251 }
252 else /* Access UART registers. */
253 rc = uartRegRead(pDevIns, &pUart->UartCore, &pUartCC->UartCore, offUartReg, (uint32_t *)pv, cb);
254
255 return rc;
256}
257
258
259/**
260 * Performs a register write to the given UART.
261 *
262 * @returns Strict VBox status code.
263 * @param pDevIns The device instance.
264 * @param pThis The shared OXPCIe958 device instance data.
265 * @param pUart The UART accessed, shared bits.
266 * @param pUartCC The UART accessed, current context bits.
267 * @param offUartReg Offset of the register being written.
268 * @param pv The data to write.
269 * @param cb Number of bytes to write.
270 */
271static VBOXSTRICTRC ox958UartRegWrite(PPDMDEVINS pDevIns, PDEVOX958 pThis, POX958UART pUart, POX958UARTCC pUartCC,
272 uint32_t offUartReg, const void *pv, unsigned cb)
273{
274 VBOXSTRICTRC rc;
275 RT_NOREF(pThis);
276
277 if (offUartReg >= OX958_REG_UART_DMA_REGION_OFFSET)
278 {
279 /* Access to the DMA registers. */
280 rc = VINF_SUCCESS;
281 }
282 else /* Access UART registers. */
283 rc = uartRegWrite(pDevIns, &pUart->UartCore, &pUartCC->UartCore, offUartReg, *(const uint32_t *)pv, cb);
284
285 return rc;
286}
287
288
289/**
290 * UART core IRQ request callback.
291 *
292 * @param pDevIns The device instance.
293 * @param pUart The UART requesting an IRQ update.
294 * @param iLUN The UART index.
295 * @param iLvl IRQ level requested.
296 */
297static DECLCALLBACK(void) ox958IrqReq(PPDMDEVINS pDevIns, PUARTCORE pUart, unsigned iLUN, int iLvl)
298{
299 RT_NOREF(pUart);
300 PDEVOX958 pThis = PDMDEVINS_2_DATA(pDevIns, PDEVOX958);
301
302 if (iLvl)
303 ASMAtomicOrU32(&pThis->u32RegIrqStsGlob, RT_BIT_32(iLUN));
304 else
305 ASMAtomicAndU32(&pThis->u32RegIrqStsGlob, ~RT_BIT_32(iLUN));
306 ox958IrqUpdate(pDevIns, pThis);
307}
308
309
310/**
311 * @callback_method_impl{FNIOMMMIONEWREAD}
312 */
313static DECLCALLBACK(VBOXSTRICTRC) ox958MmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
314{
315 PDEVOX958 pThis = PDMDEVINS_2_DATA(pDevIns, PDEVOX958);
316 PDEVOX958CC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVOX958CC);
317 VBOXSTRICTRC rc = VINF_SUCCESS;
318 RT_NOREF(pvUser);
319
320 if (off < OX958_REG_UART_REGION_OFFSET)
321 {
322 uint32_t *pu32 = (uint32_t *)pv;
323 Assert(cb == 4);
324
325 switch ((uint32_t)off)
326 {
327 case OX958_REG_CC_REV_ID:
328 *pu32 = 0x00070002;
329 break;
330 case OX958_REG_UART_CNT:
331 *pu32 = pThis->cUarts;
332 break;
333 case OX958_REG_UART_IRQ_STS:
334 *pu32 = ASMAtomicReadU32(&pThis->u32RegIrqStsGlob);
335 break;
336 case OX958_REG_UART_IRQ_ENABLE:
337 *pu32 = ASMAtomicReadU32(&pThis->u32RegIrqEnGlob);
338 break;
339 case OX958_REG_UART_IRQ_DISABLE:
340 *pu32 = ~ASMAtomicReadU32(&pThis->u32RegIrqEnGlob);
341 break;
342 case OX958_REG_UART_WAKE_IRQ_ENABLE:
343 *pu32 = ASMAtomicReadU32(&pThis->u32RegIrqEnWake);
344 break;
345 case OX958_REG_UART_WAKE_IRQ_DISABLE:
346 *pu32 = ~ASMAtomicReadU32(&pThis->u32RegIrqEnWake);
347 break;
348 default:
349 rc = VINF_IOM_MMIO_UNUSED_00;
350 }
351 }
352 else
353 {
354 /* Figure out the UART accessed from the offset. */
355 off -= OX958_REG_UART_REGION_OFFSET;
356 uint32_t iUart = (uint32_t)off / OX958_REG_UART_REGION_SIZE;
357 uint32_t offUartReg = (uint32_t)off % OX958_REG_UART_REGION_SIZE;
358 if (iUart < RT_MIN(pThis->cUarts, RT_ELEMENTS(pThis->aUarts)))
359 {
360 POX958UART pUart = &pThis->aUarts[iUart];
361 POX958UARTCC pUartCC = &pThisCC->aUarts[iUart];
362 rc = ox958UartRegRead(pDevIns, pThis, pUart, pUartCC, offUartReg, pv, cb);
363 if (rc == VINF_IOM_R3_IOPORT_READ)
364 rc = VINF_IOM_R3_MMIO_READ;
365 }
366 else
367 rc = VINF_IOM_MMIO_UNUSED_00;
368 }
369
370 return rc;
371}
372
373
374/**
375 * @callback_method_impl{FNIOMMMIONEWWRITE}
376 */
377static DECLCALLBACK(VBOXSTRICTRC) ox958MmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
378{
379 PDEVOX958 pThis = PDMDEVINS_2_DATA(pDevIns, PDEVOX958);
380 PDEVOX958CC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVOX958CC);
381 VBOXSTRICTRC rc = VINF_SUCCESS;
382 RT_NOREF1(pvUser);
383
384 if (off < OX958_REG_UART_REGION_OFFSET)
385 {
386 const uint32_t u32 = *(const uint32_t *)pv;
387 Assert(cb == 4);
388
389 switch ((uint32_t)off)
390 {
391 case OX958_REG_UART_IRQ_ENABLE:
392 ASMAtomicOrU32(&pThis->u32RegIrqEnGlob, u32);
393 ox958IrqUpdate(pDevIns, pThis);
394 break;
395 case OX958_REG_UART_IRQ_DISABLE:
396 ASMAtomicAndU32(&pThis->u32RegIrqEnGlob, ~u32);
397 ox958IrqUpdate(pDevIns, pThis);
398 break;
399 case OX958_REG_UART_WAKE_IRQ_ENABLE:
400 ASMAtomicOrU32(&pThis->u32RegIrqEnWake, u32);
401 break;
402 case OX958_REG_UART_WAKE_IRQ_DISABLE:
403 ASMAtomicAndU32(&pThis->u32RegIrqEnWake, ~u32);
404 break;
405 case OX958_REG_UART_IRQ_STS: /* Readonly */
406 case OX958_REG_CC_REV_ID: /* Readonly */
407 case OX958_REG_UART_CNT: /* Readonly */
408 default:
409 break;
410 }
411 }
412 else
413 {
414 /* Figure out the UART accessed from the offset. */
415 off -= OX958_REG_UART_REGION_OFFSET;
416 uint32_t iUart = (uint32_t)off / OX958_REG_UART_REGION_SIZE;
417 uint32_t offUartReg = (uint32_t)off % OX958_REG_UART_REGION_SIZE;
418 if (iUart < RT_MIN(pThis->cUarts, RT_ELEMENTS(pThis->aUarts)))
419 {
420 POX958UART pUart = &pThis->aUarts[iUart];
421 POX958UARTCC pUartCC = &pThisCC->aUarts[iUart];
422 rc = ox958UartRegWrite(pDevIns, pThis, pUart, pUartCC, offUartReg, pv, cb);
423 if (rc == VINF_IOM_R3_IOPORT_WRITE)
424 rc = VINF_IOM_R3_MMIO_WRITE;
425 }
426 }
427
428 return rc;
429}
430
431
432#ifdef IN_RING3
433
434/** @interface_method_impl{PDMDEVREG,pfnDetach} */
435static DECLCALLBACK(void) ox958R3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
436{
437 PDEVOX958 pThis = PDMDEVINS_2_DATA(pDevIns, PDEVOX958);
438 PDEVOX958CC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVOX958CC);
439 AssertReturnVoid(iLUN >= pThis->cUarts);
440
441 RT_NOREF(fFlags);
442
443 return uartR3Detach(pDevIns, &pThis->aUarts[iLUN].UartCore, &pThisCC->aUarts[iLUN].UartCore);
444}
445
446
447/** @interface_method_impl{PDMDEVREG,pfnAttach} */
448static DECLCALLBACK(int) ox958R3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
449{
450 PDEVOX958 pThis = PDMDEVINS_2_DATA(pDevIns, PDEVOX958);
451 PDEVOX958CC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVOX958CC);
452
453 RT_NOREF(fFlags);
454
455 if (iLUN >= RT_MIN(pThis->cUarts, RT_ELEMENTS(pThis->aUarts)))
456 return VERR_PDM_LUN_NOT_FOUND;
457
458 return uartR3Attach(pDevIns, &pThis->aUarts[iLUN].UartCore, &pThisCC->aUarts[iLUN].UartCore, iLUN);
459}
460
461
462/** @interface_method_impl{PDMDEVREG,pfnReset} */
463static DECLCALLBACK(void) ox958R3Reset(PPDMDEVINS pDevIns)
464{
465 PDEVOX958 pThis = PDMDEVINS_2_DATA(pDevIns, PDEVOX958);
466 PDEVOX958CC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVOX958CC);
467
468 pThis->u32RegIrqStsGlob = 0x00;
469 pThis->u32RegIrqEnGlob = 0x00;
470 pThis->u32RegIrqEnWake = 0x00;
471
472 uint32_t const cUarts = RT_MIN(pThis->cUarts, RT_ELEMENTS(pThis->aUarts));
473 for (uint32_t i = 0; i < cUarts; i++)
474 uartR3Reset(pDevIns, &pThis->aUarts[i].UartCore, &pThisCC->aUarts[i].UartCore);
475}
476
477
478/** @interface_method_impl{PDMDEVREG,pfnDestruct} */
479static DECLCALLBACK(int) ox958R3Destruct(PPDMDEVINS pDevIns)
480{
481 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
482 PDEVOX958 pThis = PDMDEVINS_2_DATA(pDevIns, PDEVOX958);
483
484 uint32_t const cUarts = RT_MIN(pThis->cUarts, RT_ELEMENTS(pThis->aUarts));
485 for (uint32_t i = 0; i < cUarts; i++)
486 uartR3Destruct(pDevIns, &pThis->aUarts[i].UartCore);
487
488 return VINF_SUCCESS;
489}
490
491
492/** @interface_method_impl{PDMDEVREG,pfnConstruct} */
493static DECLCALLBACK(int) ox958R3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
494{
495 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
496 RT_NOREF(iInstance);
497 PDEVOX958 pThis = PDMDEVINS_2_DATA(pDevIns, PDEVOX958);
498 PDEVOX958R3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVOX958CC);
499 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
500 bool fMsiXSupported = false;
501 int rc;
502
503 /*
504 * Init instance data.
505 */
506 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
507 AssertRCReturn(rc, rc);
508
509 /*
510 * Validate and read configuration.
511 */
512 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "MsiXSupported|UartCount", "");
513
514 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "MsiXSupported", &fMsiXSupported, true);
515 if (RT_FAILURE(rc))
516 return PDMDEV_SET_ERROR(pDevIns, rc, N_("OXPCIe958 configuration error: failed to read \"MsiXSupported\" as boolean"));
517
518 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "UartCount", &pThis->cUarts, OX958_UARTS_MAX);
519 if (RT_FAILURE(rc))
520 return PDMDEV_SET_ERROR(pDevIns, rc, N_("OXPCIe958 configuration error: failed to read \"UartCount\" as unsigned 32bit integer"));
521
522 if (!pThis->cUarts || pThis->cUarts > OX958_UARTS_MAX)
523 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
524 N_("OXPCIe958 configuration error: \"UartCount\" has invalid value %u (must be in range [1 .. %u]"),
525 pThis->cUarts, OX958_UARTS_MAX);
526
527 /*
528 * Fill PCI config space.
529 */
530 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
531 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
532
533 PDMPciDevSetVendorId(pPciDev, OX958_PCI_VENDOR_ID);
534 PDMPciDevSetDeviceId(pPciDev, OX958_PCI_DEVICE_ID);
535 PDMPciDevSetCommand(pPciDev, 0x0000);
536# ifdef VBOX_WITH_MSI_DEVICES
537 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST);
538 PDMPciDevSetCapabilityList(pPciDev, OX958_PCI_MSI_CAP_OFS);
539# else
540 PDMPciDevSetCapabilityList(pPciDev, 0x70);
541# endif
542 PDMPciDevSetRevisionId(pPciDev, 0x00);
543 PDMPciDevSetClassBase(pPciDev, 0x07); /* Communication controller. */
544 PDMPciDevSetClassSub(pPciDev, 0x00); /* Serial controller. */
545 PDMPciDevSetClassProg(pPciDev, 0x02); /* 16550. */
546
547 PDMPciDevSetRevisionId(pPciDev, 0x00);
548 PDMPciDevSetSubSystemVendorId(pPciDev, OX958_PCI_VENDOR_ID);
549 PDMPciDevSetSubSystemId(pPciDev, OX958_PCI_DEVICE_ID);
550
551 PDMPciDevSetInterruptLine(pPciDev, 0x00);
552 PDMPciDevSetInterruptPin(pPciDev, 0x01);
553 /** @todo More Capabilities. */
554
555 /*
556 * Register PCI device and I/O region.
557 */
558 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
559 if (RT_FAILURE(rc))
560 return rc;
561
562# ifdef VBOX_WITH_MSI_DEVICES
563 PDMMSIREG MsiReg;
564 RT_ZERO(MsiReg);
565 MsiReg.cMsiVectors = 1;
566 MsiReg.iMsiCapOffset = OX958_PCI_MSI_CAP_OFS;
567 MsiReg.iMsiNextOffset = OX958_PCI_MSIX_CAP_OFS;
568 MsiReg.fMsi64bit = true;
569 if (fMsiXSupported)
570 {
571 MsiReg.cMsixVectors = VBOX_MSIX_MAX_ENTRIES;
572 MsiReg.iMsixCapOffset = OX958_PCI_MSIX_CAP_OFS;
573 MsiReg.iMsixNextOffset = 0x00;
574 MsiReg.iMsixBar = OX958_PCI_MSIX_BAR;
575 }
576 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
577 if (RT_FAILURE(rc))
578 {
579 PDMPciDevSetCapabilityList(pPciDev, 0x0);
580 /* That's OK, we can work without MSI */
581 }
582# endif
583
584 rc = PDMDevHlpPCIIORegionCreateMmio(pDevIns, 0 /*iPciRegion*/, _16K, PCI_ADDRESS_SPACE_MEM,
585 ox958MmioWrite, ox958MmioRead, NULL /*pvUser*/,
586 IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
587 "OxPCIe958", &pThis->hMmio);
588 AssertRCReturn(rc, rc);
589
590
591 /*
592 * Initialize the UARTs.
593 */
594 for (uint32_t i = 0; i < pThis->cUarts; i++)
595 {
596 POX958UART pUart = &pThis->aUarts[i];
597 POX958UARTCC pUartCC = &pThisCC->aUarts[i];
598 rc = uartR3Init(pDevIns, &pUart->UartCore, &pUartCC->UartCore, UARTTYPE_16550A, i, 0, ox958IrqReq);
599 if (RT_FAILURE(rc))
600 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
601 N_("OXPCIe958 configuration error: failed to initialize UART %u"), i);
602 }
603
604 ox958R3Reset(pDevIns);
605 return VINF_SUCCESS;
606}
607
608#else /* !IN_RING3 */
609
610/**
611 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
612 */
613static DECLCALLBACK(int) ox958RZConstruct(PPDMDEVINS pDevIns)
614{
615 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
616 PDEVOX958 pThis = PDMDEVINS_2_DATA(pDevIns, PDEVOX958);
617 PDEVOX958CC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVOX958CC);
618
619 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
620 AssertRCReturn(rc, rc);
621
622 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ox958MmioWrite, ox958MmioRead, NULL /*pvUser*/);
623 AssertRCReturn(rc, rc);
624
625 uint32_t const cUarts = RT_MIN(pThis->cUarts, RT_ELEMENTS(pThis->aUarts));
626 for (uint32_t i = 0; i < cUarts; i++)
627 {
628 POX958UARTCC pUartCC = &pThisCC->aUarts[i];
629 rc = uartRZInit(&pUartCC->UartCore, ox958IrqReq);
630 AssertRCReturn(rc, rc);
631 }
632
633 return VINF_SUCCESS;
634}
635
636#endif /* !IN_RING3 */
637
638
639const PDMDEVREG g_DeviceOxPcie958 =
640{
641 /* .u32version = */ PDM_DEVREG_VERSION,
642 /* .uReserved0 = */ 0,
643 /* .szName = */ "oxpcie958uart",
644 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
645 /* .fClass = */ PDM_DEVREG_CLASS_SERIAL,
646 /* .cMaxInstances = */ ~0U,
647 /* .uSharedVersion = */ 42,
648 /* .cbInstanceShared = */ sizeof(DEVOX958),
649 /* .cbInstanceCC = */ sizeof(DEVOX958CC),
650 /* .cbInstanceRC = */ sizeof(DEVOX958RC),
651 /* .cMaxPciDevices = */ 1,
652 /* .cMaxMsixVectors = */ VBOX_MSIX_MAX_ENTRIES,
653 /* .pszDescription = */ "OXPCIe958 based UART controller.\n",
654#if defined(IN_RING3)
655 /* .pszRCMod = */ "VBoxDDRC.rc",
656 /* .pszR0Mod = */ "VBoxDDR0.r0",
657 /* .pfnConstruct = */ ox958R3Construct,
658 /* .pfnDestruct = */ ox958R3Destruct,
659 /* .pfnRelocate = */ NULL,
660 /* .pfnMemSetup = */ NULL,
661 /* .pfnPowerOn = */ NULL,
662 /* .pfnReset = */ ox958R3Reset,
663 /* .pfnSuspend = */ NULL,
664 /* .pfnResume = */ NULL,
665 /* .pfnAttach = */ ox958R3Attach,
666 /* .pfnDetach = */ ox958R3Detach,
667 /* .pfnQueryInterface = */ NULL,
668 /* .pfnInitComplete = */ NULL,
669 /* .pfnPowerOff = */ NULL,
670 /* .pfnSoftReset = */ NULL,
671 /* .pfnReserved0 = */ NULL,
672 /* .pfnReserved1 = */ NULL,
673 /* .pfnReserved2 = */ NULL,
674 /* .pfnReserved3 = */ NULL,
675 /* .pfnReserved4 = */ NULL,
676 /* .pfnReserved5 = */ NULL,
677 /* .pfnReserved6 = */ NULL,
678 /* .pfnReserved7 = */ NULL,
679#elif defined(IN_RING0)
680 /* .pfnEarlyConstruct = */ NULL,
681 /* .pfnConstruct = */ ox958RZConstruct,
682 /* .pfnDestruct = */ NULL,
683 /* .pfnFinalDestruct = */ NULL,
684 /* .pfnRequest = */ NULL,
685 /* .pfnReserved0 = */ NULL,
686 /* .pfnReserved1 = */ NULL,
687 /* .pfnReserved2 = */ NULL,
688 /* .pfnReserved3 = */ NULL,
689 /* .pfnReserved4 = */ NULL,
690 /* .pfnReserved5 = */ NULL,
691 /* .pfnReserved6 = */ NULL,
692 /* .pfnReserved7 = */ NULL,
693#elif defined(IN_RC)
694 /* .pfnConstruct = */ ox958RZConstruct,
695 /* .pfnReserved0 = */ NULL,
696 /* .pfnReserved1 = */ NULL,
697 /* .pfnReserved2 = */ NULL,
698 /* .pfnReserved3 = */ NULL,
699 /* .pfnReserved4 = */ NULL,
700 /* .pfnReserved5 = */ NULL,
701 /* .pfnReserved6 = */ NULL,
702 /* .pfnReserved7 = */ NULL,
703#else
704# error "Not in IN_RING3, IN_RING0 or IN_RC!"
705#endif
706 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
707};
708
709#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
710
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