VirtualBox

source: vbox/trunk/src/VBox/Devices/Serial/DevOxPcie958.cpp@ 97698

Last change on this file since 97698 was 96407, checked in by vboxsync, 2 years ago

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1/* $Id: DevOxPcie958.cpp 96407 2022-08-22 17:43:14Z vboxsync $ */
2/** @file
3 * DevOxPcie958 - Oxford Semiconductor OXPCIe958 PCI Express bridge to octal serial port emulation
4 */
5
6/*
7 * Copyright (C) 2018-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28/** @page pg_dev_oxpcie958 OXPCIe958 - Oxford Semiconductor OXPCIe958 PCI Express bridge to octal serial port emulation.
29 * @todo Write something
30 */
31
32
33/*********************************************************************************************************************************
34* Header Files *
35*********************************************************************************************************************************/
36#define LOG_GROUP LOG_GROUP_DEV_SERIAL
37#include <VBox/pci.h>
38#include <VBox/msi.h>
39#include <VBox/vmm/pdm.h>
40#include <VBox/vmm/pdmpci.h>
41#include <VBox/err.h>
42#include <VBox/log.h>
43#include <iprt/assert.h>
44#include <iprt/list.h>
45#include <iprt/asm.h>
46
47#include "VBoxDD.h"
48#include "UartCore.h"
49
50
51/** @name PCI device related constants.
52 * @{ */
53/** The PCI device ID. */
54#define OX958_PCI_DEVICE_ID 0xc308
55/** The PCI vendor ID. */
56#define OX958_PCI_VENDOR_ID 0x1415
57/** Where the MSI capability starts. */
58#define OX958_PCI_MSI_CAP_OFS 0x80
59/** Where the MSI-X capability starts. */
60#define OX958_PCI_MSIX_CAP_OFS (OX958_PCI_MSI_CAP_OFS + VBOX_MSI_CAP_SIZE_64)
61/** The BAR for the MSI-X related functionality. */
62#define OX958_PCI_MSIX_BAR 1
63/** @} */
64
65/** Maximum number of UARTs supported by the device. */
66#define OX958_UARTS_MAX 16
67
68/** Offset op the class code and revision ID register. */
69#define OX958_REG_CC_REV_ID 0x00
70/** Offset fof the UART count register. */
71#define OX958_REG_UART_CNT 0x04
72/** Offset of the global UART IRQ status register. */
73#define OX958_REG_UART_IRQ_STS 0x08
74/** Offset of the global UART IRQ enable register. */
75#define OX958_REG_UART_IRQ_ENABLE 0x0c
76/** Offset of the global UART IRQ disable register. */
77#define OX958_REG_UART_IRQ_DISABLE 0x10
78/** Offset of the global UART wake IRQ enable register. */
79#define OX958_REG_UART_WAKE_IRQ_ENABLE 0x14
80/** Offset of the global UART wake IRQ disable register. */
81#define OX958_REG_UART_WAKE_IRQ_DISABLE 0x18
82/** Offset of the region in MMIO space where the UARTs actually start. */
83#define OX958_REG_UART_REGION_OFFSET 0x1000
84/** Register region size for each UART. */
85#define OX958_REG_UART_REGION_SIZE 0x200
86/** Offset where the DMA channels registers start for each UART. */
87#define OX958_REG_UART_DMA_REGION_OFFSET 0x100
88
89
90/**
91 * Shared OXPCIe958 UART core.
92 */
93typedef struct OX958UART
94{
95 /** The UART core. */
96 UARTCORE UartCore;
97 /** DMA address configured. */
98 RTGCPHYS GCPhysDmaAddr;
99 /** The DMA transfer length configured. */
100 uint32_t cbDmaXfer;
101 /** The DMA status registers. */
102 uint32_t u32RegDmaSts;
103} OX958UART;
104/** Pointer to a shared OXPCIe958 UART core. */
105typedef OX958UART *POX958UART;
106
107/**
108 * Ring-3 OXPCIe958 UART core.
109 */
110typedef struct OX958UARTR3
111{
112 /** The ring-3 UART core. */
113 UARTCORER3 UartCore;
114} OX958UARTR3;
115/** Pointer to a ring-3 OXPCIe958 UART core. */
116typedef OX958UARTR3 *POX958UARTR3;
117
118/**
119 * Ring-0 OXPCIe958 UART core.
120 */
121typedef struct OX958UARTR0
122{
123 /** The ring-0 UART core. */
124 UARTCORER0 UartCore;
125} OX958UARTR0;
126/** Pointer to a ring-0 OXPCIe958 UART core. */
127typedef OX958UARTR0 *POX958UARTR0;
128
129
130/**
131 * Raw-mode OXPCIe958 UART core.
132 */
133typedef struct OX958UARTRC
134{
135 /** The raw-mode UART core. */
136 UARTCORERC UartCore;
137} OX958UARTRC;
138/** Pointer to a raw-mode OXPCIe958 UART core. */
139typedef OX958UARTRC *POX958UARTRC;
140
141/** Current context OXPCIe958 UART core. */
142typedef CTX_SUFF(OX958UART) OX958UARTCC;
143/** Pointer to a current context OXPCIe958 UART core. */
144typedef CTX_SUFF(POX958UART) POX958UARTCC;
145
146
147/**
148 * Shared OXPCIe958 device instance data.
149 */
150typedef struct DEVOX958
151{
152 /** UART global IRQ status. */
153 volatile uint32_t u32RegIrqStsGlob;
154 /** UART global IRQ enable mask. */
155 volatile uint32_t u32RegIrqEnGlob;
156 /** UART wake IRQ enable mask. */
157 volatile uint32_t u32RegIrqEnWake;
158 /** Number of UARTs configured. */
159 uint32_t cUarts;
160 /** Handle to the MMIO region (PCI region \#0). */
161 IOMMMIOHANDLE hMmio;
162 /** The UARTs. */
163 OX958UART aUarts[OX958_UARTS_MAX];
164} DEVOX958;
165/** Pointer to shared OXPCIe958 device instance data. */
166typedef DEVOX958 *PDEVOX958;
167
168/**
169 * Ring-3 OXPCIe958 device instance data.
170 */
171typedef struct DEVOX958R3
172{
173 /** The UARTs. */
174 OX958UARTR3 aUarts[OX958_UARTS_MAX];
175} DEVOX958R3;
176/** Pointer to ring-3 OXPCIe958 device instance data. */
177typedef DEVOX958R3 *PDEVOX958R3;
178
179/**
180 * Ring-0 OXPCIe958 device instance data.
181 */
182typedef struct DEVOX958R0
183{
184 /** The UARTs. */
185 OX958UARTR0 aUarts[OX958_UARTS_MAX];
186} DEVOX958R0;
187/** Pointer to ring-0 OXPCIe958 device instance data. */
188typedef DEVOX958R0 *PDEVOX958R0;
189
190/**
191 * Raw-mode OXPCIe958 device instance data.
192 */
193typedef struct DEVOX958RC
194{
195 /** The UARTs. */
196 OX958UARTRC aUarts[OX958_UARTS_MAX];
197} DEVOX958RC;
198/** Pointer to raw-mode OXPCIe958 device instance data. */
199typedef DEVOX958RC *PDEVOX958RC;
200
201/** Current context OXPCIe958 device instance data. */
202typedef CTX_SUFF(DEVOX958) DEVOX958CC;
203/** Pointer to current context OXPCIe958 device instance data. */
204typedef CTX_SUFF(PDEVOX958) PDEVOX958CC;
205
206
207#ifndef VBOX_DEVICE_STRUCT_TESTCASE
208
209
210
211/**
212 * Update IRQ status of the device.
213 *
214 * @returns nothing.
215 * @param pDevIns The device instance.
216 * @param pThis The shared OXPCIe958 device instance data.
217 */
218static void ox958IrqUpdate(PPDMDEVINS pDevIns, PDEVOX958 pThis)
219{
220 uint32_t u32IrqSts = ASMAtomicReadU32(&pThis->u32RegIrqStsGlob);
221 uint32_t u32IrqEn = ASMAtomicReadU32(&pThis->u32RegIrqEnGlob);
222
223 if (u32IrqSts & u32IrqEn)
224 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
225 else
226 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
227}
228
229
230/**
231 * Performs a register read from the given UART.
232 *
233 * @returns Strict VBox status code.
234 * @param pDevIns The device instance.
235 * @param pThis The shared OXPCIe958 device instance data.
236 * @param pUart The UART accessed, shared bits.
237 * @param pUartCC The UART accessed, current context bits.
238 * @param offUartReg Offset of the register being read.
239 * @param pv Where to store the read data.
240 * @param cb Number of bytes to read.
241 */
242static VBOXSTRICTRC ox958UartRegRead(PPDMDEVINS pDevIns, PDEVOX958 pThis, POX958UART pUart, POX958UARTCC pUartCC,
243 uint32_t offUartReg, void *pv, unsigned cb)
244{
245 VBOXSTRICTRC rc;
246 RT_NOREF(pThis);
247
248 if (offUartReg >= OX958_REG_UART_DMA_REGION_OFFSET)
249 {
250 /* Access to the DMA registers. */
251 rc = VINF_SUCCESS;
252 }
253 else /* Access UART registers. */
254 rc = uartRegRead(pDevIns, &pUart->UartCore, &pUartCC->UartCore, offUartReg, (uint32_t *)pv, cb);
255
256 return rc;
257}
258
259
260/**
261 * Performs a register write to the given UART.
262 *
263 * @returns Strict VBox status code.
264 * @param pDevIns The device instance.
265 * @param pThis The shared OXPCIe958 device instance data.
266 * @param pUart The UART accessed, shared bits.
267 * @param pUartCC The UART accessed, current context bits.
268 * @param offUartReg Offset of the register being written.
269 * @param pv The data to write.
270 * @param cb Number of bytes to write.
271 */
272static VBOXSTRICTRC ox958UartRegWrite(PPDMDEVINS pDevIns, PDEVOX958 pThis, POX958UART pUart, POX958UARTCC pUartCC,
273 uint32_t offUartReg, const void *pv, unsigned cb)
274{
275 VBOXSTRICTRC rc;
276 RT_NOREF(pThis);
277
278 if (offUartReg >= OX958_REG_UART_DMA_REGION_OFFSET)
279 {
280 /* Access to the DMA registers. */
281 rc = VINF_SUCCESS;
282 }
283 else /* Access UART registers. */
284 rc = uartRegWrite(pDevIns, &pUart->UartCore, &pUartCC->UartCore, offUartReg, *(const uint32_t *)pv, cb);
285
286 return rc;
287}
288
289
290/**
291 * UART core IRQ request callback.
292 *
293 * @returns nothing.
294 * @param pDevIns The device instance.
295 * @param pUart The UART requesting an IRQ update.
296 * @param iLUN The UART index.
297 * @param iLvl IRQ level requested.
298 */
299static DECLCALLBACK(void) ox958IrqReq(PPDMDEVINS pDevIns, PUARTCORE pUart, unsigned iLUN, int iLvl)
300{
301 RT_NOREF(pUart);
302 PDEVOX958 pThis = PDMDEVINS_2_DATA(pDevIns, PDEVOX958);
303
304 if (iLvl)
305 ASMAtomicOrU32(&pThis->u32RegIrqStsGlob, RT_BIT_32(iLUN));
306 else
307 ASMAtomicAndU32(&pThis->u32RegIrqStsGlob, ~RT_BIT_32(iLUN));
308 ox958IrqUpdate(pDevIns, pThis);
309}
310
311
312/**
313 * @callback_method_impl{FNIOMMMIONEWREAD}
314 */
315static DECLCALLBACK(VBOXSTRICTRC) ox958MmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
316{
317 PDEVOX958 pThis = PDMDEVINS_2_DATA(pDevIns, PDEVOX958);
318 PDEVOX958CC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVOX958CC);
319 VBOXSTRICTRC rc = VINF_SUCCESS;
320 RT_NOREF(pvUser);
321
322 if (off < OX958_REG_UART_REGION_OFFSET)
323 {
324 uint32_t *pu32 = (uint32_t *)pv;
325 Assert(cb == 4);
326
327 switch ((uint32_t)off)
328 {
329 case OX958_REG_CC_REV_ID:
330 *pu32 = 0x00070002;
331 break;
332 case OX958_REG_UART_CNT:
333 *pu32 = pThis->cUarts;
334 break;
335 case OX958_REG_UART_IRQ_STS:
336 *pu32 = ASMAtomicReadU32(&pThis->u32RegIrqStsGlob);
337 break;
338 case OX958_REG_UART_IRQ_ENABLE:
339 *pu32 = ASMAtomicReadU32(&pThis->u32RegIrqEnGlob);
340 break;
341 case OX958_REG_UART_IRQ_DISABLE:
342 *pu32 = ~ASMAtomicReadU32(&pThis->u32RegIrqEnGlob);
343 break;
344 case OX958_REG_UART_WAKE_IRQ_ENABLE:
345 *pu32 = ASMAtomicReadU32(&pThis->u32RegIrqEnWake);
346 break;
347 case OX958_REG_UART_WAKE_IRQ_DISABLE:
348 *pu32 = ~ASMAtomicReadU32(&pThis->u32RegIrqEnWake);
349 break;
350 default:
351 rc = VINF_IOM_MMIO_UNUSED_00;
352 }
353 }
354 else
355 {
356 /* Figure out the UART accessed from the offset. */
357 off -= OX958_REG_UART_REGION_OFFSET;
358 uint32_t iUart = (uint32_t)off / OX958_REG_UART_REGION_SIZE;
359 uint32_t offUartReg = (uint32_t)off % OX958_REG_UART_REGION_SIZE;
360 if (iUart < RT_MIN(pThis->cUarts, RT_ELEMENTS(pThis->aUarts)))
361 {
362 POX958UART pUart = &pThis->aUarts[iUart];
363 POX958UARTCC pUartCC = &pThisCC->aUarts[iUart];
364 rc = ox958UartRegRead(pDevIns, pThis, pUart, pUartCC, offUartReg, pv, cb);
365 if (rc == VINF_IOM_R3_IOPORT_READ)
366 rc = VINF_IOM_R3_MMIO_READ;
367 }
368 else
369 rc = VINF_IOM_MMIO_UNUSED_00;
370 }
371
372 return rc;
373}
374
375
376/**
377 * @callback_method_impl{FNIOMMMIONEWWRITE}
378 */
379static DECLCALLBACK(VBOXSTRICTRC) ox958MmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
380{
381 PDEVOX958 pThis = PDMDEVINS_2_DATA(pDevIns, PDEVOX958);
382 PDEVOX958CC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVOX958CC);
383 VBOXSTRICTRC rc = VINF_SUCCESS;
384 RT_NOREF1(pvUser);
385
386 if (off < OX958_REG_UART_REGION_OFFSET)
387 {
388 const uint32_t u32 = *(const uint32_t *)pv;
389 Assert(cb == 4);
390
391 switch ((uint32_t)off)
392 {
393 case OX958_REG_UART_IRQ_ENABLE:
394 ASMAtomicOrU32(&pThis->u32RegIrqEnGlob, u32);
395 ox958IrqUpdate(pDevIns, pThis);
396 break;
397 case OX958_REG_UART_IRQ_DISABLE:
398 ASMAtomicAndU32(&pThis->u32RegIrqEnGlob, ~u32);
399 ox958IrqUpdate(pDevIns, pThis);
400 break;
401 case OX958_REG_UART_WAKE_IRQ_ENABLE:
402 ASMAtomicOrU32(&pThis->u32RegIrqEnWake, u32);
403 break;
404 case OX958_REG_UART_WAKE_IRQ_DISABLE:
405 ASMAtomicAndU32(&pThis->u32RegIrqEnWake, ~u32);
406 break;
407 case OX958_REG_UART_IRQ_STS: /* Readonly */
408 case OX958_REG_CC_REV_ID: /* Readonly */
409 case OX958_REG_UART_CNT: /* Readonly */
410 default:
411 break;
412 }
413 }
414 else
415 {
416 /* Figure out the UART accessed from the offset. */
417 off -= OX958_REG_UART_REGION_OFFSET;
418 uint32_t iUart = (uint32_t)off / OX958_REG_UART_REGION_SIZE;
419 uint32_t offUartReg = (uint32_t)off % OX958_REG_UART_REGION_SIZE;
420 if (iUart < RT_MIN(pThis->cUarts, RT_ELEMENTS(pThis->aUarts)))
421 {
422 POX958UART pUart = &pThis->aUarts[iUart];
423 POX958UARTCC pUartCC = &pThisCC->aUarts[iUart];
424 rc = ox958UartRegWrite(pDevIns, pThis, pUart, pUartCC, offUartReg, pv, cb);
425 if (rc == VINF_IOM_R3_IOPORT_WRITE)
426 rc = VINF_IOM_R3_MMIO_WRITE;
427 }
428 }
429
430 return rc;
431}
432
433
434#ifdef IN_RING3
435
436/** @interface_method_impl{PDMDEVREG,pfnDetach} */
437static DECLCALLBACK(void) ox958R3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
438{
439 PDEVOX958 pThis = PDMDEVINS_2_DATA(pDevIns, PDEVOX958);
440 PDEVOX958CC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVOX958CC);
441 AssertReturnVoid(iLUN >= pThis->cUarts);
442
443 RT_NOREF(fFlags);
444
445 return uartR3Detach(pDevIns, &pThis->aUarts[iLUN].UartCore, &pThisCC->aUarts[iLUN].UartCore);
446}
447
448
449/** @interface_method_impl{PDMDEVREG,pfnAttach} */
450static DECLCALLBACK(int) ox958R3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
451{
452 PDEVOX958 pThis = PDMDEVINS_2_DATA(pDevIns, PDEVOX958);
453 PDEVOX958CC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVOX958CC);
454
455 RT_NOREF(fFlags);
456
457 if (iLUN >= RT_MIN(pThis->cUarts, RT_ELEMENTS(pThis->aUarts)))
458 return VERR_PDM_LUN_NOT_FOUND;
459
460 return uartR3Attach(pDevIns, &pThis->aUarts[iLUN].UartCore, &pThisCC->aUarts[iLUN].UartCore, iLUN);
461}
462
463
464/** @interface_method_impl{PDMDEVREG,pfnReset} */
465static DECLCALLBACK(void) ox958R3Reset(PPDMDEVINS pDevIns)
466{
467 PDEVOX958 pThis = PDMDEVINS_2_DATA(pDevIns, PDEVOX958);
468 PDEVOX958CC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVOX958CC);
469
470 pThis->u32RegIrqStsGlob = 0x00;
471 pThis->u32RegIrqEnGlob = 0x00;
472 pThis->u32RegIrqEnWake = 0x00;
473
474 uint32_t const cUarts = RT_MIN(pThis->cUarts, RT_ELEMENTS(pThis->aUarts));
475 for (uint32_t i = 0; i < cUarts; i++)
476 uartR3Reset(pDevIns, &pThis->aUarts[i].UartCore, &pThisCC->aUarts[i].UartCore);
477}
478
479
480/** @interface_method_impl{PDMDEVREG,pfnDestruct} */
481static DECLCALLBACK(int) ox958R3Destruct(PPDMDEVINS pDevIns)
482{
483 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
484 PDEVOX958 pThis = PDMDEVINS_2_DATA(pDevIns, PDEVOX958);
485
486 uint32_t const cUarts = RT_MIN(pThis->cUarts, RT_ELEMENTS(pThis->aUarts));
487 for (uint32_t i = 0; i < cUarts; i++)
488 uartR3Destruct(pDevIns, &pThis->aUarts[i].UartCore);
489
490 return VINF_SUCCESS;
491}
492
493
494/** @interface_method_impl{PDMDEVREG,pfnConstruct} */
495static DECLCALLBACK(int) ox958R3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
496{
497 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
498 RT_NOREF(iInstance);
499 PDEVOX958 pThis = PDMDEVINS_2_DATA(pDevIns, PDEVOX958);
500 PDEVOX958R3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVOX958CC);
501 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
502 bool fMsiXSupported = false;
503 int rc;
504
505 /*
506 * Init instance data.
507 */
508 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
509 AssertRCReturn(rc, rc);
510
511 /*
512 * Validate and read configuration.
513 */
514 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "MsiXSupported|UartCount", "");
515
516 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "MsiXSupported", &fMsiXSupported, true);
517 if (RT_FAILURE(rc))
518 return PDMDEV_SET_ERROR(pDevIns, rc, N_("OXPCIe958 configuration error: failed to read \"MsiXSupported\" as boolean"));
519
520 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "UartCount", &pThis->cUarts, OX958_UARTS_MAX);
521 if (RT_FAILURE(rc))
522 return PDMDEV_SET_ERROR(pDevIns, rc, N_("OXPCIe958 configuration error: failed to read \"UartCount\" as unsigned 32bit integer"));
523
524 if (!pThis->cUarts || pThis->cUarts > OX958_UARTS_MAX)
525 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
526 N_("OXPCIe958 configuration error: \"UartCount\" has invalid value %u (must be in range [1 .. %u]"),
527 pThis->cUarts, OX958_UARTS_MAX);
528
529 /*
530 * Fill PCI config space.
531 */
532 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
533 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
534
535 PDMPciDevSetVendorId(pPciDev, OX958_PCI_VENDOR_ID);
536 PDMPciDevSetDeviceId(pPciDev, OX958_PCI_DEVICE_ID);
537 PDMPciDevSetCommand(pPciDev, 0x0000);
538# ifdef VBOX_WITH_MSI_DEVICES
539 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST);
540 PDMPciDevSetCapabilityList(pPciDev, OX958_PCI_MSI_CAP_OFS);
541# else
542 PDMPciDevSetCapabilityList(pPciDev, 0x70);
543# endif
544 PDMPciDevSetRevisionId(pPciDev, 0x00);
545 PDMPciDevSetClassBase(pPciDev, 0x07); /* Communication controller. */
546 PDMPciDevSetClassSub(pPciDev, 0x00); /* Serial controller. */
547 PDMPciDevSetClassProg(pPciDev, 0x02); /* 16550. */
548
549 PDMPciDevSetRevisionId(pPciDev, 0x00);
550 PDMPciDevSetSubSystemVendorId(pPciDev, OX958_PCI_VENDOR_ID);
551 PDMPciDevSetSubSystemId(pPciDev, OX958_PCI_DEVICE_ID);
552
553 PDMPciDevSetInterruptLine(pPciDev, 0x00);
554 PDMPciDevSetInterruptPin(pPciDev, 0x01);
555 /** @todo More Capabilities. */
556
557 /*
558 * Register PCI device and I/O region.
559 */
560 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
561 if (RT_FAILURE(rc))
562 return rc;
563
564# ifdef VBOX_WITH_MSI_DEVICES
565 PDMMSIREG MsiReg;
566 RT_ZERO(MsiReg);
567 MsiReg.cMsiVectors = 1;
568 MsiReg.iMsiCapOffset = OX958_PCI_MSI_CAP_OFS;
569 MsiReg.iMsiNextOffset = OX958_PCI_MSIX_CAP_OFS;
570 MsiReg.fMsi64bit = true;
571 if (fMsiXSupported)
572 {
573 MsiReg.cMsixVectors = VBOX_MSIX_MAX_ENTRIES;
574 MsiReg.iMsixCapOffset = OX958_PCI_MSIX_CAP_OFS;
575 MsiReg.iMsixNextOffset = 0x00;
576 MsiReg.iMsixBar = OX958_PCI_MSIX_BAR;
577 }
578 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
579 if (RT_FAILURE(rc))
580 {
581 PDMPciDevSetCapabilityList(pPciDev, 0x0);
582 /* That's OK, we can work without MSI */
583 }
584# endif
585
586 rc = PDMDevHlpPCIIORegionCreateMmio(pDevIns, 0 /*iPciRegion*/, _16K, PCI_ADDRESS_SPACE_MEM,
587 ox958MmioWrite, ox958MmioRead, NULL /*pvUser*/,
588 IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
589 "OxPCIe958", &pThis->hMmio);
590 AssertRCReturn(rc, rc);
591
592
593 /*
594 * Initialize the UARTs.
595 */
596 for (uint32_t i = 0; i < pThis->cUarts; i++)
597 {
598 POX958UART pUart = &pThis->aUarts[i];
599 POX958UARTCC pUartCC = &pThisCC->aUarts[i];
600 rc = uartR3Init(pDevIns, &pUart->UartCore, &pUartCC->UartCore, UARTTYPE_16550A, i, 0, ox958IrqReq);
601 if (RT_FAILURE(rc))
602 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
603 N_("OXPCIe958 configuration error: failed to initialize UART %u"), i);
604 }
605
606 ox958R3Reset(pDevIns);
607 return VINF_SUCCESS;
608}
609
610#else /* !IN_RING3 */
611
612/**
613 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
614 */
615static DECLCALLBACK(int) ox958RZConstruct(PPDMDEVINS pDevIns)
616{
617 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
618 PDEVOX958 pThis = PDMDEVINS_2_DATA(pDevIns, PDEVOX958);
619 PDEVOX958CC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVOX958CC);
620
621 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
622 AssertRCReturn(rc, rc);
623
624 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ox958MmioWrite, ox958MmioRead, NULL /*pvUser*/);
625 AssertRCReturn(rc, rc);
626
627 uint32_t const cUarts = RT_MIN(pThis->cUarts, RT_ELEMENTS(pThis->aUarts));
628 for (uint32_t i = 0; i < cUarts; i++)
629 {
630 POX958UARTCC pUartCC = &pThisCC->aUarts[i];
631 rc = uartRZInit(&pUartCC->UartCore, ox958IrqReq);
632 AssertRCReturn(rc, rc);
633 }
634
635 return VINF_SUCCESS;
636}
637
638#endif /* !IN_RING3 */
639
640
641const PDMDEVREG g_DeviceOxPcie958 =
642{
643 /* .u32version = */ PDM_DEVREG_VERSION,
644 /* .uReserved0 = */ 0,
645 /* .szName = */ "oxpcie958uart",
646 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
647 /* .fClass = */ PDM_DEVREG_CLASS_SERIAL,
648 /* .cMaxInstances = */ ~0U,
649 /* .uSharedVersion = */ 42,
650 /* .cbInstanceShared = */ sizeof(DEVOX958),
651 /* .cbInstanceCC = */ sizeof(DEVOX958CC),
652 /* .cbInstanceRC = */ sizeof(DEVOX958RC),
653 /* .cMaxPciDevices = */ 1,
654 /* .cMaxMsixVectors = */ VBOX_MSIX_MAX_ENTRIES,
655 /* .pszDescription = */ "OXPCIe958 based UART controller.\n",
656#if defined(IN_RING3)
657 /* .pszRCMod = */ "VBoxDDRC.rc",
658 /* .pszR0Mod = */ "VBoxDDR0.r0",
659 /* .pfnConstruct = */ ox958R3Construct,
660 /* .pfnDestruct = */ ox958R3Destruct,
661 /* .pfnRelocate = */ NULL,
662 /* .pfnMemSetup = */ NULL,
663 /* .pfnPowerOn = */ NULL,
664 /* .pfnReset = */ ox958R3Reset,
665 /* .pfnSuspend = */ NULL,
666 /* .pfnResume = */ NULL,
667 /* .pfnAttach = */ ox958R3Attach,
668 /* .pfnDetach = */ ox958R3Detach,
669 /* .pfnQueryInterface = */ NULL,
670 /* .pfnInitComplete = */ NULL,
671 /* .pfnPowerOff = */ NULL,
672 /* .pfnSoftReset = */ NULL,
673 /* .pfnReserved0 = */ NULL,
674 /* .pfnReserved1 = */ NULL,
675 /* .pfnReserved2 = */ NULL,
676 /* .pfnReserved3 = */ NULL,
677 /* .pfnReserved4 = */ NULL,
678 /* .pfnReserved5 = */ NULL,
679 /* .pfnReserved6 = */ NULL,
680 /* .pfnReserved7 = */ NULL,
681#elif defined(IN_RING0)
682 /* .pfnEarlyConstruct = */ NULL,
683 /* .pfnConstruct = */ ox958RZConstruct,
684 /* .pfnDestruct = */ NULL,
685 /* .pfnFinalDestruct = */ NULL,
686 /* .pfnRequest = */ NULL,
687 /* .pfnReserved0 = */ NULL,
688 /* .pfnReserved1 = */ NULL,
689 /* .pfnReserved2 = */ NULL,
690 /* .pfnReserved3 = */ NULL,
691 /* .pfnReserved4 = */ NULL,
692 /* .pfnReserved5 = */ NULL,
693 /* .pfnReserved6 = */ NULL,
694 /* .pfnReserved7 = */ NULL,
695#elif defined(IN_RC)
696 /* .pfnConstruct = */ ox958RZConstruct,
697 /* .pfnReserved0 = */ NULL,
698 /* .pfnReserved1 = */ NULL,
699 /* .pfnReserved2 = */ NULL,
700 /* .pfnReserved3 = */ NULL,
701 /* .pfnReserved4 = */ NULL,
702 /* .pfnReserved5 = */ NULL,
703 /* .pfnReserved6 = */ NULL,
704 /* .pfnReserved7 = */ NULL,
705#else
706# error "Not in IN_RING3, IN_RING0 or IN_RC!"
707#endif
708 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
709};
710
711#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
712
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