1 | /* $Id: DevParallel.cpp 82122 2019-11-23 00:04:34Z vboxsync $ */
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2 | /** @file
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3 | * DevParallel - Parallel (Port) Device Emulation.
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4 | *
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5 | * Contributed by: Alexander Eichner
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6 | * Based on DevSerial.cpp
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7 | */
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8 |
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9 | /*
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10 | * Copyright (C) 2006-2019 Oracle Corporation
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11 | *
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12 | * This file is part of VirtualBox Open Source Edition (OSE), as
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13 | * available from http://www.virtualbox.org. This file is free software;
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14 | * you can redistribute it and/or modify it under the terms of the GNU
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15 | * General Public License (GPL) as published by the Free Software
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16 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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17 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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18 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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19 | */
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20 |
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21 |
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22 | /*********************************************************************************************************************************
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23 | * Header Files *
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24 | *********************************************************************************************************************************/
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25 | #define LOG_GROUP LOG_GROUP_DEV_PARALLEL
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26 | #include <VBox/vmm/pdmdev.h>
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27 | #include <VBox/AssertGuest.h>
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28 | #include <iprt/assert.h>
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29 | #include <iprt/uuid.h>
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30 | #include <iprt/string.h>
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31 | #include <iprt/semaphore.h>
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32 |
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33 | #include "VBoxDD.h"
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34 |
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35 |
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36 | /*********************************************************************************************************************************
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37 | * Defined Constants And Macros *
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38 | *********************************************************************************************************************************/
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39 | #define PARALLEL_SAVED_STATE_VERSION 1
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40 |
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41 | /* defines for accessing the register bits */
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42 | #define LPT_STATUS_BUSY 0x80
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43 | #define LPT_STATUS_ACK 0x40
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44 | #define LPT_STATUS_PAPER_OUT 0x20
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45 | #define LPT_STATUS_SELECT_IN 0x10
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46 | #define LPT_STATUS_ERROR 0x08
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47 | #define LPT_STATUS_IRQ 0x04
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48 | #define LPT_STATUS_BIT1 0x02 /* reserved (only for completeness) */
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49 | #define LPT_STATUS_EPP_TIMEOUT 0x01
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50 |
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51 | #define LPT_CONTROL_BIT7 0x80 /* reserved (only for completeness) */
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52 | #define LPT_CONTROL_BIT6 0x40 /* reserved (only for completeness) */
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53 | #define LPT_CONTROL_ENABLE_BIDIRECT 0x20
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54 | #define LPT_CONTROL_ENABLE_IRQ_VIA_ACK 0x10
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55 | #define LPT_CONTROL_SELECT_PRINTER 0x08
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56 | #define LPT_CONTROL_RESET 0x04
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57 | #define LPT_CONTROL_AUTO_LINEFEED 0x02
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58 | #define LPT_CONTROL_STROBE 0x01
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59 |
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60 | /** mode defines for the extended control register */
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61 | #define LPT_ECP_ECR_CHIPMODE_MASK 0xe0
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62 | #define LPT_ECP_ECR_CHIPMODE_GET_BITS(reg) ((reg) >> 5)
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63 | #define LPT_ECP_ECR_CHIPMODE_SET_BITS(val) ((val) << 5)
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64 | #define LPT_ECP_ECR_CHIPMODE_CONFIGURATION 0x07
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65 | #define LPT_ECP_ECR_CHIPMODE_FIFO_TEST 0x06
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66 | #define LPT_ECP_ECR_CHIPMODE_RESERVED 0x05
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67 | #define LPT_ECP_ECR_CHIPMODE_EPP 0x04
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68 | #define LPT_ECP_ECR_CHIPMODE_ECP_FIFO 0x03
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69 | #define LPT_ECP_ECR_CHIPMODE_PP_FIFO 0x02
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70 | #define LPT_ECP_ECR_CHIPMODE_BYTE 0x01
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71 | #define LPT_ECP_ECR_CHIPMODE_COMPAT 0x00
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72 |
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73 | /** FIFO status bits in extended control register */
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74 | #define LPT_ECP_ECR_FIFO_MASK 0x03
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75 | #define LPT_ECP_ECR_FIFO_SOME_DATA 0x00
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76 | #define LPT_ECP_ECR_FIFO_FULL 0x02
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77 | #define LPT_ECP_ECR_FIFO_EMPTY 0x01
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78 |
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79 | #define LPT_ECP_CONFIGA_FIFO_WITDH_MASK 0x70
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80 | #define LPT_ECP_CONFIGA_FIFO_WIDTH_GET_BITS(reg) ((reg) >> 4)
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81 | #define LPT_ECP_CONFIGA_FIFO_WIDTH_SET_BITS(val) ((val) << 4)
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82 | #define LPT_ECP_CONFIGA_FIFO_WIDTH_16 0x00
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83 | #define LPT_ECP_CONFIGA_FIFO_WIDTH_32 0x20
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84 | #define LPT_ECP_CONFIGA_FIFO_WIDTH_8 0x10
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85 |
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86 | #define LPT_ECP_FIFO_DEPTH 2
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87 |
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88 |
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89 | /*********************************************************************************************************************************
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90 | * Structures and Typedefs *
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91 | *********************************************************************************************************************************/
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92 | /**
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93 | * The shared parallel device state.
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94 | */
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95 | typedef struct PARALLELPORT
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96 | {
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97 | /** Flag whether an EPP timeout occurred (error handling). */
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98 | bool fEppTimeout;
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99 | bool fAlignment1;
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100 | /** Base I/O port of the parallel port. */
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101 | RTIOPORT IOBase;
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102 | /** IRQ number assigned ot the parallel port. */
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103 | int32_t iIrq;
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104 | /** Data register. */
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105 | uint8_t regData;
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106 | /** Status register. */
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107 | uint8_t regStatus;
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108 | /** Control register. */
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109 | uint8_t regControl;
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110 | /** EPP address register. */
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111 | uint8_t regEppAddr;
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112 | /** EPP data register. */
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113 | uint8_t regEppData;
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114 | /** More alignment. */
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115 | uint8_t abAlignment2[3];
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116 |
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117 | #if 0 /* Data for ECP implementation, currently unused. */
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118 | uint8_t reg_ecp_ecr;
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119 | uint8_t reg_ecp_base_plus_400h; /* has different meanings */
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120 | uint8_t reg_ecp_config_b;
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121 |
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122 | /** The ECP FIFO implementation*/
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123 | uint8_t ecp_fifo[LPT_ECP_FIFO_DEPTH];
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124 | uint8_t abAlignemnt[3];
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125 | int32_t act_fifo_pos_write;
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126 | int32_t act_fifo_pos_read;
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127 | #endif
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128 | /** Handle to the regular I/O ports. */
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129 | IOMIOPORTHANDLE hIoPorts;
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130 | /** Handle to the ECP I/O ports. */
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131 | IOMIOPORTHANDLE hIoPortsEcp;
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132 | } PARALLELPORT;
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133 | /** Pointer to the shared parallel device state. */
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134 | typedef PARALLELPORT *PPARALLELPORT;
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135 |
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136 |
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137 | /**
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138 | * The parallel device state for ring-3.
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139 | *
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140 | * @implements PDMIBASE
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141 | * @implements PDMIHOSTPARALLELPORT
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142 | */
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143 | typedef struct PARALLELPORTR3
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144 | {
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145 | /** Pointer to the device instance.
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146 | * @note Only for getting our bearings when arriving here via an interface
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147 | * method. */
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148 | PPDMDEVINSR3 pDevIns;
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149 | /** LUN\#0: The base interface. */
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150 | PDMIBASE IBase;
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151 | /** LUN\#0: The host device port interface. */
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152 | PDMIHOSTPARALLELPORT IHostParallelPort;
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153 | /** Pointer to the attached base driver. */
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154 | R3PTRTYPE(PPDMIBASE) pDrvBase;
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155 | /** Pointer to the attached host device. */
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156 | R3PTRTYPE(PPDMIHOSTPARALLELCONNECTOR) pDrvHostParallelConnector;
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157 | } PARALLELPORTR3;
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158 | /** Pointer to the parallel device state for ring-3. */
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159 | typedef PARALLELPORTR3 *PPARALLELPORTR3;
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160 |
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161 |
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162 | #ifndef VBOX_DEVICE_STRUCT_TESTCASE /* Rest of file, does not count wrt indentation. */
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163 |
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164 | #ifdef IN_RING3
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165 |
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166 | static void parallelR3IrqSet(PPDMDEVINS pDevIns, PARALLELPORT *pThis)
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167 | {
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168 | if (pThis->regControl & LPT_CONTROL_ENABLE_IRQ_VIA_ACK)
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169 | {
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170 | LogFlowFunc(("%d 1\n", pThis->iIrq));
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171 | PDMDevHlpISASetIrqNoWait(pDevIns, pThis->iIrq, 1);
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172 | }
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173 | }
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174 |
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175 | static void parallelR3IrqClear(PPDMDEVINS pDevIns, PARALLELPORT *pThis)
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176 | {
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177 | LogFlowFunc(("%d 0\n", pThis->iIrq));
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178 | PDMDevHlpISASetIrqNoWait(pDevIns, pThis->iIrq, 0);
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179 | }
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180 |
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181 | #endif /* IN_RING3 */
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182 |
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183 | #if 0
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184 | static int parallel_ioport_write_ecp(void *opaque, uint32_t addr, uint32_t val)
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185 | {
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186 | PARALLELPORT *s = (PARALLELPORT *)opaque;
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187 | unsigned char ch;
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188 |
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189 | addr &= 7;
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190 | LogFlow(("parallel: write ecp addr=0x%02x val=0x%02x\n", addr, val));
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191 | ch = val;
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192 | switch (addr) {
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193 | default:
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194 | case 0:
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195 | if (LPT_ECP_ECR_CHIPMODE_GET_BITS(s->reg_ecp_ecr) == LPT_ECP_ECR_CHIPMODE_FIFO_TEST) {
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196 | s->ecp_fifo[s->act_fifo_pos_write] = ch;
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197 | s->act_fifo_pos_write++;
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198 | if (s->act_fifo_pos_write < LPT_ECP_FIFO_DEPTH) {
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199 | /* FIFO has some data (clear both FIFO bits) */
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200 | s->reg_ecp_ecr &= ~(LPT_ECP_ECR_FIFO_EMPTY | LPT_ECP_ECR_FIFO_FULL);
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201 | } else {
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202 | /* FIFO is full */
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203 | /* Clear FIFO empty bit */
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204 | s->reg_ecp_ecr &= ~LPT_ECP_ECR_FIFO_EMPTY;
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205 | /* Set FIFO full bit */
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206 | s->reg_ecp_ecr |= LPT_ECP_ECR_FIFO_FULL;
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207 | s->act_fifo_pos_write = 0;
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208 | }
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209 | } else {
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210 | s->reg_ecp_base_plus_400h = ch;
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211 | }
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212 | break;
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213 | case 1:
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214 | s->reg_ecp_config_b = ch;
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215 | break;
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216 | case 2:
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217 | /* If we change the mode clear FIFO */
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218 | if ((ch & LPT_ECP_ECR_CHIPMODE_MASK) != (s->reg_ecp_ecr & LPT_ECP_ECR_CHIPMODE_MASK)) {
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219 | /* reset the fifo */
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220 | s->act_fifo_pos_write = 0;
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221 | s->act_fifo_pos_read = 0;
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222 | /* Set FIFO empty bit */
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223 | s->reg_ecp_ecr |= LPT_ECP_ECR_FIFO_EMPTY;
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224 | /* Clear FIFO full bit */
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225 | s->reg_ecp_ecr &= ~LPT_ECP_ECR_FIFO_FULL;
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226 | }
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227 | /* Set new mode */
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228 | s->reg_ecp_ecr |= LPT_ECP_ECR_CHIPMODE_SET_BITS(LPT_ECP_ECR_CHIPMODE_GET_BITS(ch));
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229 | break;
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230 | case 3:
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231 | break;
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232 | case 4:
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233 | break;
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234 | case 5:
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235 | break;
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236 | case 6:
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237 | break;
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238 | case 7:
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239 | break;
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240 | }
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241 | return VINF_SUCCESS;
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242 | }
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243 |
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244 | static uint32_t parallel_ioport_read_ecp(void *opaque, uint32_t addr, int *pRC)
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245 | {
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246 | PARALLELPORT *s = (PARALLELPORT *)opaque;
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247 | uint32_t ret = ~0U;
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248 |
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249 | *pRC = VINF_SUCCESS;
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250 |
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251 | addr &= 7;
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252 | switch (addr) {
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253 | default:
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254 | case 0:
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255 | if (LPT_ECP_ECR_CHIPMODE_GET_BITS(s->reg_ecp_ecr) == LPT_ECP_ECR_CHIPMODE_FIFO_TEST) {
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256 | ret = s->ecp_fifo[s->act_fifo_pos_read];
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257 | s->act_fifo_pos_read++;
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258 | if (s->act_fifo_pos_read == LPT_ECP_FIFO_DEPTH)
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259 | s->act_fifo_pos_read = 0; /* end of FIFO, start at beginning */
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260 | if (s->act_fifo_pos_read == s->act_fifo_pos_write) {
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261 | /* FIFO is empty */
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262 | /* Set FIFO empty bit */
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263 | s->reg_ecp_ecr |= LPT_ECP_ECR_FIFO_EMPTY;
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264 | /* Clear FIFO full bit */
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265 | s->reg_ecp_ecr &= ~LPT_ECP_ECR_FIFO_FULL;
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266 | } else {
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267 | /* FIFO has some data (clear all FIFO bits) */
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268 | s->reg_ecp_ecr &= ~(LPT_ECP_ECR_FIFO_EMPTY | LPT_ECP_ECR_FIFO_FULL);
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269 | }
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270 | } else {
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271 | ret = s->reg_ecp_base_plus_400h;
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272 | }
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273 | break;
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274 | case 1:
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275 | ret = s->reg_ecp_config_b;
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276 | break;
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277 | case 2:
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278 | ret = s->reg_ecp_ecr;
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279 | break;
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280 | case 3:
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281 | break;
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282 | case 4:
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283 | break;
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284 | case 5:
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285 | break;
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286 | case 6:
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287 | break;
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288 | case 7:
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289 | break;
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290 | }
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291 | LogFlow(("parallel: read ecp addr=0x%02x val=0x%02x\n", addr, ret));
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292 | return ret;
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293 | }
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294 | #endif
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295 |
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296 | #ifdef IN_RING3
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297 | /**
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298 | * @interface_method_impl{PDMIHOSTPARALLELPORT,pfnNotifyInterrupt}
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299 | */
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300 | static DECLCALLBACK(int) parallelR3NotifyInterrupt(PPDMIHOSTPARALLELPORT pInterface)
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301 | {
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302 | PPARALLELPORTR3 pThisCC = RT_FROM_MEMBER(pInterface, PARALLELPORTR3, IHostParallelPort);
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303 | PPDMDEVINS pDevIns = pThisCC->pDevIns;
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304 | PPARALLELPORT pThis = PDMDEVINS_2_DATA(pDevIns, PPARALLELPORT);
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305 |
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306 | PDMCritSectEnter(pDevIns->pCritSectRoR3, VINF_SUCCESS);
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307 | parallelR3IrqSet(pDevIns, pThis);
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308 | PDMCritSectLeave(pDevIns->pCritSectRoR3);
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309 |
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310 | return VINF_SUCCESS;
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311 | }
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312 | #endif /* IN_RING3 */
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313 |
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314 |
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315 | /**
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316 | * @callback_method_impl{FNIOMIOPORTNEWOUT}
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317 | */
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318 | static DECLCALLBACK(VBOXSTRICTRC)
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319 | parallelIoPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
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320 | {
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321 | PPARALLELPORT pThis = PDMDEVINS_2_DATA(pDevIns, PPARALLELPORT);
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322 | #ifdef IN_RING3
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323 | PPARALLELPORTR3 pThisCC = PDMDEVINS_2_DATA(pDevIns, PPARALLELPORTR3);
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324 | #endif
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325 | VBOXSTRICTRC rc = VINF_SUCCESS;
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326 | RT_NOREF_PV(pvUser);
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327 |
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328 | if (cb == 1)
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329 | {
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330 | uint8_t u8 = u32;
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331 |
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332 | Log2(("%s: Port=%#06x+%x val %#04x\n", __FUNCTION__, pThis->IOBase, offPort, u32));
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333 |
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334 | offPort &= 7;
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335 | switch (offPort)
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336 | {
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337 | case 0:
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338 | #ifndef IN_RING3
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339 | NOREF(u8);
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340 | rc = VINF_IOM_R3_IOPORT_WRITE;
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341 | #else
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342 | pThis->regData = u8;
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343 | if (RT_LIKELY(pThisCC->pDrvHostParallelConnector))
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344 | {
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345 | LogFlowFunc(("Set data lines 0x%X\n", u8));
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346 | rc = pThisCC->pDrvHostParallelConnector->pfnWrite(pThisCC->pDrvHostParallelConnector, &u8, 1, PDM_PARALLEL_PORT_MODE_SPP);
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347 | AssertRC(rc);
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348 | }
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349 | #endif
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350 | break;
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351 | case 1:
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352 | break;
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353 | case 2:
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354 | /* Set the reserved bits to one */
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355 | u8 |= (LPT_CONTROL_BIT6 | LPT_CONTROL_BIT7);
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356 | if (u8 != pThis->regControl)
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357 | {
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358 | #ifndef IN_RING3
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359 | return VINF_IOM_R3_IOPORT_WRITE;
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360 | #else
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361 | if (RT_LIKELY(pThisCC->pDrvHostParallelConnector))
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362 | {
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363 | /* Set data direction. */
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364 | if (u8 & LPT_CONTROL_ENABLE_BIDIRECT)
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365 | rc = pThisCC->pDrvHostParallelConnector->pfnSetPortDirection(pThisCC->pDrvHostParallelConnector, false /* fForward */);
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366 | else
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367 | rc = pThisCC->pDrvHostParallelConnector->pfnSetPortDirection(pThisCC->pDrvHostParallelConnector, true /* fForward */);
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368 | AssertRC(rc);
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369 |
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370 | u8 &= ~LPT_CONTROL_ENABLE_BIDIRECT; /* Clear bit. */
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371 |
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372 | rc = pThisCC->pDrvHostParallelConnector->pfnWriteControl(pThisCC->pDrvHostParallelConnector, u8);
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373 | AssertRC(rc);
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374 | }
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375 | else
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376 | u8 &= ~LPT_CONTROL_ENABLE_BIDIRECT; /* Clear bit. */
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377 |
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378 | pThis->regControl = u8;
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379 | #endif
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380 | }
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381 | break;
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382 | case 3:
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383 | #ifndef IN_RING3
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384 | NOREF(u8);
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385 | rc = VINF_IOM_R3_IOPORT_WRITE;
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386 | #else
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387 | pThis->regEppAddr = u8;
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388 | if (RT_LIKELY(pThisCC->pDrvHostParallelConnector))
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389 | {
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390 | LogFlowFunc(("Write EPP address 0x%X\n", u8));
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391 | rc = pThisCC->pDrvHostParallelConnector->pfnWrite(pThisCC->pDrvHostParallelConnector, &u8, 1, PDM_PARALLEL_PORT_MODE_EPP_ADDR);
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392 | AssertRC(rc);
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393 | }
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394 | #endif
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395 | break;
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396 | case 4:
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397 | #ifndef IN_RING3
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398 | NOREF(u8);
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399 | rc = VINF_IOM_R3_IOPORT_WRITE;
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400 | #else
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401 | pThis->regEppData = u8;
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402 | if (RT_LIKELY(pThisCC->pDrvHostParallelConnector))
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403 | {
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404 | LogFlowFunc(("Write EPP data 0x%X\n", u8));
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405 | rc = pThisCC->pDrvHostParallelConnector->pfnWrite(pThisCC->pDrvHostParallelConnector, &u8, 1, PDM_PARALLEL_PORT_MODE_EPP_DATA);
|
---|
406 | AssertRC(rc);
|
---|
407 | }
|
---|
408 | #endif
|
---|
409 | break;
|
---|
410 | case 5:
|
---|
411 | break;
|
---|
412 | case 6:
|
---|
413 | break;
|
---|
414 | case 7:
|
---|
415 | default:
|
---|
416 | break;
|
---|
417 | }
|
---|
418 | }
|
---|
419 | else
|
---|
420 | ASSERT_GUEST_MSG_FAILED(("Port=%#x+%x cb=%d u32=%#x\n", pThis->IOBase, offPort, cb, u32));
|
---|
421 |
|
---|
422 | return rc;
|
---|
423 | }
|
---|
424 |
|
---|
425 |
|
---|
426 | /**
|
---|
427 | * @callback_method_impl{FNIOMIOPORTNEWIN}
|
---|
428 | */
|
---|
429 | static DECLCALLBACK(VBOXSTRICTRC)
|
---|
430 | parallelIoPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
|
---|
431 | {
|
---|
432 | PPARALLELPORT pThis = PDMDEVINS_2_DATA(pDevIns, PPARALLELPORT);
|
---|
433 | #ifdef IN_RING3
|
---|
434 | PPARALLELPORTR3 pThisCC = PDMDEVINS_2_DATA(pDevIns, PPARALLELPORTR3);
|
---|
435 | #endif
|
---|
436 | VBOXSTRICTRC rc = VINF_SUCCESS;
|
---|
437 | RT_NOREF_PV(pvUser);
|
---|
438 |
|
---|
439 | if (cb == 1)
|
---|
440 | {
|
---|
441 | offPort &= 7;
|
---|
442 | switch (offPort)
|
---|
443 | {
|
---|
444 | case 0:
|
---|
445 | if (!(pThis->regControl & LPT_CONTROL_ENABLE_BIDIRECT))
|
---|
446 | *pu32 = pThis->regData;
|
---|
447 | else
|
---|
448 | {
|
---|
449 | #ifndef IN_RING3
|
---|
450 | rc = VINF_IOM_R3_IOPORT_READ;
|
---|
451 | #else
|
---|
452 | if (RT_LIKELY(pThisCC->pDrvHostParallelConnector))
|
---|
453 | {
|
---|
454 | rc = pThisCC->pDrvHostParallelConnector->pfnRead(pThisCC->pDrvHostParallelConnector, &pThis->regData,
|
---|
455 | 1, PDM_PARALLEL_PORT_MODE_SPP);
|
---|
456 | Log(("Read data lines 0x%X\n", pThis->regData));
|
---|
457 | AssertRC(VBOXSTRICTRC_VAL(rc));
|
---|
458 | }
|
---|
459 | *pu32 = pThis->regData;
|
---|
460 | #endif
|
---|
461 | }
|
---|
462 | break;
|
---|
463 | case 1:
|
---|
464 | #ifndef IN_RING3
|
---|
465 | rc = VINF_IOM_R3_IOPORT_READ;
|
---|
466 | #else
|
---|
467 | if (RT_LIKELY(pThisCC->pDrvHostParallelConnector))
|
---|
468 | {
|
---|
469 | rc = pThisCC->pDrvHostParallelConnector->pfnReadStatus(pThisCC->pDrvHostParallelConnector, &pThis->regStatus);
|
---|
470 | AssertRC(VBOXSTRICTRC_VAL(rc));
|
---|
471 | }
|
---|
472 | *pu32 = pThis->regStatus;
|
---|
473 | parallelR3IrqClear(pDevIns, pThis);
|
---|
474 | #endif
|
---|
475 | break;
|
---|
476 | case 2:
|
---|
477 | #ifndef IN_RING3
|
---|
478 | rc = VINF_IOM_R3_IOPORT_READ;
|
---|
479 | #else
|
---|
480 | if (RT_LIKELY(pThisCC->pDrvHostParallelConnector))
|
---|
481 | {
|
---|
482 | rc = pThisCC->pDrvHostParallelConnector->pfnReadControl(pThisCC->pDrvHostParallelConnector, &pThis->regControl);
|
---|
483 | AssertRC(VBOXSTRICTRC_VAL(rc));
|
---|
484 | pThis->regControl |= LPT_CONTROL_BIT6 | LPT_CONTROL_BIT7;
|
---|
485 | }
|
---|
486 |
|
---|
487 | *pu32 = pThis->regControl;
|
---|
488 | #endif
|
---|
489 | break;
|
---|
490 | case 3:
|
---|
491 | #ifndef IN_RING3
|
---|
492 | rc = VINF_IOM_R3_IOPORT_READ;
|
---|
493 | #else
|
---|
494 | if (RT_LIKELY(pThisCC->pDrvHostParallelConnector))
|
---|
495 | {
|
---|
496 | rc = pThisCC->pDrvHostParallelConnector->pfnRead(pThisCC->pDrvHostParallelConnector, &pThis->regEppAddr,
|
---|
497 | 1, PDM_PARALLEL_PORT_MODE_EPP_ADDR);
|
---|
498 | Log(("Read EPP address 0x%X\n", pThis->regEppAddr));
|
---|
499 | AssertRC(VBOXSTRICTRC_VAL(rc));
|
---|
500 | }
|
---|
501 | *pu32 = pThis->regEppAddr;
|
---|
502 | #endif
|
---|
503 | break;
|
---|
504 | case 4:
|
---|
505 | #ifndef IN_RING3
|
---|
506 | rc = VINF_IOM_R3_IOPORT_READ;
|
---|
507 | #else
|
---|
508 | if (RT_LIKELY(pThisCC->pDrvHostParallelConnector))
|
---|
509 | {
|
---|
510 | rc = pThisCC->pDrvHostParallelConnector->pfnRead(pThisCC->pDrvHostParallelConnector, &pThis->regEppData,
|
---|
511 | 1, PDM_PARALLEL_PORT_MODE_EPP_DATA);
|
---|
512 | Log(("Read EPP data 0x%X\n", pThis->regEppData));
|
---|
513 | AssertRC(VBOXSTRICTRC_VAL(rc));
|
---|
514 | }
|
---|
515 | *pu32 = pThis->regEppData;
|
---|
516 | #endif
|
---|
517 | break;
|
---|
518 | case 5:
|
---|
519 | break;
|
---|
520 | case 6:
|
---|
521 | break;
|
---|
522 | case 7:
|
---|
523 | break;
|
---|
524 | }
|
---|
525 | }
|
---|
526 | else
|
---|
527 | rc = VERR_IOM_IOPORT_UNUSED;
|
---|
528 |
|
---|
529 | return rc;
|
---|
530 | }
|
---|
531 |
|
---|
532 | #if 0
|
---|
533 | /**
|
---|
534 | * @callback_method_impl{FNIOMIOPORTNEWOUT, ECP registers.}
|
---|
535 | */
|
---|
536 | static DECLCALLBACK(VBOXSTRICTRC)
|
---|
537 | parallelIoPortWriteECP(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
|
---|
538 | {
|
---|
539 | PPARALLELPORT pThis = PDMDEVINS_2_DATA(pDevIns, PPARALLELPORT);
|
---|
540 | VBOXSTRICTRC rc = VINF_SUCCESS;
|
---|
541 |
|
---|
542 | if (cb == 1)
|
---|
543 | {
|
---|
544 | Log2(("%s: ecp port %#06x+%x val %#04x\n", __FUNCTION__, pThis->IOBase + 0x400, offPort, u32));
|
---|
545 | rc = parallel_ioport_write_ecp(pThis, Port, u32);
|
---|
546 | }
|
---|
547 | else
|
---|
548 | ASSERT_GUEST_MSG_FAILED(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
|
---|
549 |
|
---|
550 | return rc;
|
---|
551 | }
|
---|
552 |
|
---|
553 | /**
|
---|
554 | * @callback_method_impl{FNIOMIOPORTNEWOUT, ECP registers.}
|
---|
555 | */
|
---|
556 | static DECLCALLBACK(VBOXSTRICTRC)
|
---|
557 | parallelIoPortReadECP(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
|
---|
558 | {
|
---|
559 | PPARALLELPORT pThis = PDMDEVINS_2_DATA(pDevIns, PPARALLELPORT);
|
---|
560 | VBOXSTRICTRC rc = VINF_SUCCESS;
|
---|
561 |
|
---|
562 | if (cb == 1)
|
---|
563 | {
|
---|
564 | *pu32 = parallel_ioport_read_ecp(pThis, Port, &rc);
|
---|
565 | Log2(("%s: ecp port %#06x+%x val %#04x\n", __FUNCTION__, pThis->IOBase + 0x400, offPort, *pu32));
|
---|
566 | }
|
---|
567 | else
|
---|
568 | rc = VERR_IOM_IOPORT_UNUSED;
|
---|
569 |
|
---|
570 | return rc;
|
---|
571 | }
|
---|
572 | #endif
|
---|
573 |
|
---|
574 | #ifdef IN_RING3
|
---|
575 |
|
---|
576 | /**
|
---|
577 | * @callback_method_impl{FNSSMDEVLIVEEXEC}
|
---|
578 | */
|
---|
579 | static DECLCALLBACK(int) parallelR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
|
---|
580 | {
|
---|
581 | PPARALLELPORT pThis = PDMDEVINS_2_DATA(pDevIns, PPARALLELPORT);
|
---|
582 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
583 | RT_NOREF(uPass);
|
---|
584 |
|
---|
585 | pHlp->pfnSSMPutS32(pSSM, pThis->iIrq);
|
---|
586 | pHlp->pfnSSMPutU32(pSSM, pThis->IOBase);
|
---|
587 | pHlp->pfnSSMPutU32(pSSM, UINT32_MAX); /* sanity/terminator */
|
---|
588 | return VINF_SSM_DONT_CALL_AGAIN;
|
---|
589 | }
|
---|
590 |
|
---|
591 |
|
---|
592 | /**
|
---|
593 | * @callback_method_impl{FNSSMDEVSAVEEXEC}
|
---|
594 | */
|
---|
595 | static DECLCALLBACK(int) parallelR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
|
---|
596 | {
|
---|
597 | PPARALLELPORT pThis = PDMDEVINS_2_DATA(pDevIns, PPARALLELPORT);
|
---|
598 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
599 |
|
---|
600 | pHlp->pfnSSMPutU8(pSSM, pThis->regData);
|
---|
601 | pHlp->pfnSSMPutU8(pSSM, pThis->regStatus);
|
---|
602 | pHlp->pfnSSMPutU8(pSSM, pThis->regControl);
|
---|
603 |
|
---|
604 | parallelR3LiveExec(pDevIns, pSSM, 0);
|
---|
605 | return VINF_SUCCESS;
|
---|
606 | }
|
---|
607 |
|
---|
608 |
|
---|
609 | /**
|
---|
610 | * @callback_method_impl{FNSSMDEVLOADEXEC}
|
---|
611 | */
|
---|
612 | static DECLCALLBACK(int) parallelR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
|
---|
613 | {
|
---|
614 | PPARALLELPORT pThis = PDMDEVINS_2_DATA(pDevIns, PPARALLELPORT);
|
---|
615 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
616 |
|
---|
617 | AssertMsgReturn(uVersion == PARALLEL_SAVED_STATE_VERSION, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
|
---|
618 | Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
|
---|
619 | if (uPass == SSM_PASS_FINAL)
|
---|
620 | {
|
---|
621 | pHlp->pfnSSMGetU8(pSSM, &pThis->regData);
|
---|
622 | pHlp->pfnSSMGetU8(pSSM, &pThis->regStatus);
|
---|
623 | pHlp->pfnSSMGetU8(pSSM, &pThis->regControl);
|
---|
624 | }
|
---|
625 |
|
---|
626 | /* the config */
|
---|
627 | int32_t iIrq;
|
---|
628 | pHlp->pfnSSMGetS32(pSSM, &iIrq);
|
---|
629 | uint32_t uIoBase;
|
---|
630 | pHlp->pfnSSMGetU32(pSSM, &uIoBase);
|
---|
631 | uint32_t u32;
|
---|
632 | int rc = pHlp->pfnSSMGetU32(pSSM, &u32);
|
---|
633 | AssertRCReturn(rc, rc);
|
---|
634 | AssertMsgReturn(u32 == UINT32_MAX, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
|
---|
635 |
|
---|
636 | if (pThis->iIrq != iIrq)
|
---|
637 | return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("IRQ changed: config=%#x state=%#x"), pThis->iIrq, iIrq);
|
---|
638 |
|
---|
639 | if (pThis->IOBase != uIoBase)
|
---|
640 | return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("IOBase changed: config=%#x state=%#x"), pThis->IOBase, uIoBase);
|
---|
641 |
|
---|
642 | return VINF_SUCCESS;
|
---|
643 | }
|
---|
644 |
|
---|
645 |
|
---|
646 | /**
|
---|
647 | * @interface_method_impl{PDMIBASE,pfnQueryInterface}
|
---|
648 | */
|
---|
649 | static DECLCALLBACK(void *) parallelR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
|
---|
650 | {
|
---|
651 | PPARALLELPORTR3 pThisCC = RT_FROM_MEMBER(pInterface, PARALLELPORTR3, IBase);
|
---|
652 | PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
|
---|
653 | PDMIBASE_RETURN_INTERFACE(pszIID, PDMIHOSTPARALLELPORT, &pThisCC->IHostParallelPort);
|
---|
654 | return NULL;
|
---|
655 | }
|
---|
656 |
|
---|
657 |
|
---|
658 | /**
|
---|
659 | * @interface_method_impl{PDMDEVREG,pfnConstruct}
|
---|
660 | */
|
---|
661 | static DECLCALLBACK(int) parallelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
|
---|
662 | {
|
---|
663 | PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
|
---|
664 | PPARALLELPORT pThis = PDMDEVINS_2_DATA(pDevIns, PPARALLELPORT);
|
---|
665 | PPARALLELPORTR3 pThisCC = PDMDEVINS_2_DATA(pDevIns, PPARALLELPORTR3);
|
---|
666 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
667 | int rc;
|
---|
668 |
|
---|
669 | Assert(iInstance < 4);
|
---|
670 |
|
---|
671 | /*
|
---|
672 | * Init the data.
|
---|
673 | */
|
---|
674 | pThisCC->pDevIns = pDevIns;
|
---|
675 |
|
---|
676 | /* IBase */
|
---|
677 | pThisCC->IBase.pfnQueryInterface = parallelR3QueryInterface;
|
---|
678 |
|
---|
679 | /* IHostParallelPort */
|
---|
680 | pThisCC->IHostParallelPort.pfnNotifyInterrupt = parallelR3NotifyInterrupt;
|
---|
681 |
|
---|
682 | /* Init parallel state */
|
---|
683 | pThis->regData = 0;
|
---|
684 | #if 0 /* ECP implementation not complete. */
|
---|
685 | pThis->reg_ecp_ecr = LPT_ECP_ECR_CHIPMODE_COMPAT | LPT_ECP_ECR_FIFO_EMPTY;
|
---|
686 | pThis->act_fifo_pos_read = 0;
|
---|
687 | pThis->act_fifo_pos_write = 0;
|
---|
688 | #endif
|
---|
689 |
|
---|
690 | /*
|
---|
691 | * Validate and read the configuration.
|
---|
692 | */
|
---|
693 | PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "IRQ|IOBase", "");
|
---|
694 |
|
---|
695 | rc = pHlp->pfnCFGMQueryS32Def(pCfg, "IRQ", &pThis->iIrq, 7);
|
---|
696 | if (RT_FAILURE(rc))
|
---|
697 | return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"IRQ\" value"));
|
---|
698 |
|
---|
699 | rc = pHlp->pfnCFGMQueryU16Def(pCfg, "IOBase", &pThis->IOBase, 0x378);
|
---|
700 | if (RT_FAILURE(rc))
|
---|
701 | return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"IOBase\" value"));
|
---|
702 |
|
---|
703 | int cPorts = (pThis->IOBase == 0x3BC) ? 4 : 8;
|
---|
704 | /*
|
---|
705 | * Register the I/O ports and saved state.
|
---|
706 | */
|
---|
707 | rc = PDMDevHlpIoPortCreateAndMap(pDevIns, pThis->IOBase, cPorts, parallelIoPortWrite, parallelIoPortRead,
|
---|
708 | "Parallel", NULL /*paExtDesc*/, &pThis->hIoPorts);
|
---|
709 | AssertRCReturn(rc, rc);
|
---|
710 |
|
---|
711 | #if 0
|
---|
712 | /* register ecp registers */
|
---|
713 | rc = PDMDevHlpIoPortCreateAndMap(pDevIns, pThis->IOBase + 0x400, 8, parallelIoPortWriteECP, parallelIoPortReadECP,
|
---|
714 | "Parallel ECP", NULL /*paExtDesc*/, &pThis->hIoPortsEcp);
|
---|
715 | AssertRCReturn(rc, rc);
|
---|
716 | #endif
|
---|
717 |
|
---|
718 |
|
---|
719 | rc = PDMDevHlpSSMRegister3(pDevIns, PARALLEL_SAVED_STATE_VERSION, sizeof(*pThis),
|
---|
720 | parallelR3LiveExec, parallelR3SaveExec, parallelR3LoadExec);
|
---|
721 | AssertRCReturn(rc, rc);
|
---|
722 |
|
---|
723 |
|
---|
724 | /*
|
---|
725 | * Attach the parallel port driver and get the interfaces.
|
---|
726 | * For now no run-time changes are supported.
|
---|
727 | */
|
---|
728 | rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "Parallel Host");
|
---|
729 | if (RT_SUCCESS(rc))
|
---|
730 | {
|
---|
731 | pThisCC->pDrvHostParallelConnector = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIHOSTPARALLELCONNECTOR);
|
---|
732 |
|
---|
733 | /* Set compatibility mode */
|
---|
734 | //pThisCC->pDrvHostParallelConnector->pfnSetMode(pThisCC->pDrvHostParallelConnector, PDM_PARALLEL_PORT_MODE_COMPAT);
|
---|
735 | /* Get status of control register */
|
---|
736 | pThisCC->pDrvHostParallelConnector->pfnReadControl(pThisCC->pDrvHostParallelConnector, &pThis->regControl);
|
---|
737 |
|
---|
738 | AssertMsgReturn(pThisCC->pDrvHostParallelConnector,
|
---|
739 | ("Configuration error: instance %d has no host parallel interface!\n", iInstance),
|
---|
740 | VERR_PDM_MISSING_INTERFACE);
|
---|
741 | }
|
---|
742 | else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
|
---|
743 | {
|
---|
744 | pThisCC->pDrvBase = NULL;
|
---|
745 | pThisCC->pDrvHostParallelConnector = NULL;
|
---|
746 | LogRel(("Parallel%d: no unit\n", iInstance));
|
---|
747 | }
|
---|
748 | else
|
---|
749 | AssertMsgFailedReturn(("Parallel%d: Failed to attach to host driver. rc=%Rrc\n", iInstance, rc),
|
---|
750 | PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
|
---|
751 | N_("Parallel device %d cannot attach to host driver"), iInstance));
|
---|
752 |
|
---|
753 | return VINF_SUCCESS;
|
---|
754 | }
|
---|
755 |
|
---|
756 | #else /* !IN_RING3 */
|
---|
757 |
|
---|
758 | /**
|
---|
759 | * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
|
---|
760 | */
|
---|
761 | static DECLCALLBACK(int) parallelRZConstruct(PPDMDEVINS pDevIns)
|
---|
762 | {
|
---|
763 | PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
|
---|
764 | PPARALLELPORT pThis = PDMDEVINS_2_DATA(pDevIns, PPARALLELPORT);
|
---|
765 |
|
---|
766 | int rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPorts, parallelIoPortWrite, parallelIoPortRead, NULL /*pvUser*/);
|
---|
767 | AssertRCReturn(rc, rc);
|
---|
768 |
|
---|
769 | # if 0
|
---|
770 | rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsEcp, parallelIoPortWriteECP, parallelIoPortReadECP, NULL /*pvUser*/);
|
---|
771 | AssertRCReturn(rc, rc);
|
---|
772 | # endif
|
---|
773 |
|
---|
774 | return VINF_SUCCESS;
|
---|
775 | }
|
---|
776 |
|
---|
777 | #endif /* !IN_RING3 */
|
---|
778 |
|
---|
779 | /**
|
---|
780 | * The device registration structure.
|
---|
781 | */
|
---|
782 | const PDMDEVREG g_DeviceParallelPort =
|
---|
783 | {
|
---|
784 | /* .u32Version = */ PDM_DEVREG_VERSION,
|
---|
785 | /* .uReserved0 = */ 0,
|
---|
786 | /* .szName = */ "parallel",
|
---|
787 | /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
|
---|
788 | /* .fClass = */ PDM_DEVREG_CLASS_PARALLEL,
|
---|
789 | /* .cMaxInstances = */ 2,
|
---|
790 | /* .uSharedVersion = */ 42,
|
---|
791 | /* .cbInstanceShared = */ sizeof(PARALLELPORT),
|
---|
792 | /* .cbInstanceCC = */ CTX_EXPR(sizeof(PARALLELPORTR3), 0, 0),
|
---|
793 | /* .cbInstanceRC = */ 0,
|
---|
794 | /* .cMaxPciDevices = */ 0,
|
---|
795 | /* .cMaxMsixVectors = */ 0,
|
---|
796 | /* .pszDescription = */ "Parallel Communication Port",
|
---|
797 | #if defined(IN_RING3)
|
---|
798 | /* .pszRCMod = */ "VBoxDDRC.rc",
|
---|
799 | /* .pszR0Mod = */ "VBoxDDR0.r0",
|
---|
800 | /* .pfnConstruct = */ parallelR3Construct,
|
---|
801 | /* .pfnDestruct = */ NULL,
|
---|
802 | /* .pfnRelocate = */ NULL,
|
---|
803 | /* .pfnMemSetup = */ NULL,
|
---|
804 | /* .pfnPowerOn = */ NULL,
|
---|
805 | /* .pfnReset = */ NULL,
|
---|
806 | /* .pfnSuspend = */ NULL,
|
---|
807 | /* .pfnResume = */ NULL,
|
---|
808 | /* .pfnAttach = */ NULL,
|
---|
809 | /* .pfnDetach = */ NULL,
|
---|
810 | /* .pfnQueryInterface = */ NULL,
|
---|
811 | /* .pfnInitComplete = */ NULL,
|
---|
812 | /* .pfnPowerOff = */ NULL,
|
---|
813 | /* .pfnSoftReset = */ NULL,
|
---|
814 | /* .pfnReserved0 = */ NULL,
|
---|
815 | /* .pfnReserved1 = */ NULL,
|
---|
816 | /* .pfnReserved2 = */ NULL,
|
---|
817 | /* .pfnReserved3 = */ NULL,
|
---|
818 | /* .pfnReserved4 = */ NULL,
|
---|
819 | /* .pfnReserved5 = */ NULL,
|
---|
820 | /* .pfnReserved6 = */ NULL,
|
---|
821 | /* .pfnReserved7 = */ NULL,
|
---|
822 | #elif defined(IN_RING0)
|
---|
823 | /* .pfnEarlyConstruct = */ NULL,
|
---|
824 | /* .pfnConstruct = */ parallelRZConstruct,
|
---|
825 | /* .pfnDestruct = */ NULL,
|
---|
826 | /* .pfnFinalDestruct = */ NULL,
|
---|
827 | /* .pfnRequest = */ NULL,
|
---|
828 | /* .pfnReserved0 = */ NULL,
|
---|
829 | /* .pfnReserved1 = */ NULL,
|
---|
830 | /* .pfnReserved2 = */ NULL,
|
---|
831 | /* .pfnReserved3 = */ NULL,
|
---|
832 | /* .pfnReserved4 = */ NULL,
|
---|
833 | /* .pfnReserved5 = */ NULL,
|
---|
834 | /* .pfnReserved6 = */ NULL,
|
---|
835 | /* .pfnReserved7 = */ NULL,
|
---|
836 | #elif defined(IN_RC)
|
---|
837 | /* .pfnConstruct = */ parallelRZConstruct,
|
---|
838 | /* .pfnReserved0 = */ NULL,
|
---|
839 | /* .pfnReserved1 = */ NULL,
|
---|
840 | /* .pfnReserved2 = */ NULL,
|
---|
841 | /* .pfnReserved3 = */ NULL,
|
---|
842 | /* .pfnReserved4 = */ NULL,
|
---|
843 | /* .pfnReserved5 = */ NULL,
|
---|
844 | /* .pfnReserved6 = */ NULL,
|
---|
845 | /* .pfnReserved7 = */ NULL,
|
---|
846 | #else
|
---|
847 | # error "Not in IN_RING3, IN_RING0 or IN_RC!"
|
---|
848 | #endif
|
---|
849 | /* .u32VersionEnd = */ PDM_DEVREG_VERSION
|
---|
850 | };
|
---|
851 |
|
---|
852 | #endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
|
---|
853 |
|
---|