VirtualBox

source: vbox/trunk/src/VBox/Devices/Parallel/DevParallel.cpp@ 73097

Last change on this file since 73097 was 73097, checked in by vboxsync, 6 years ago

*: Made RT_UOFFSETOF, RT_OFFSETOF, RT_UOFFSETOF_ADD and RT_OFFSETOF_ADD work like builtin_offsetof() and require compile time resolvable requests, adding RT_UOFFSETOF_DYN for the dynamic questions that can only be answered at runtime.

  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 29.4 KB
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1/* $Id: DevParallel.cpp 73097 2018-07-12 21:06:33Z vboxsync $ */
2/** @file
3 * DevParallel - Parallel (Port) Device Emulation.
4 *
5 * Contributed by: Alexander Eichner
6 * Based on DevSerial.cpp
7 */
8
9/*
10 * Copyright (C) 2006-2017 Oracle Corporation
11 *
12 * This file is part of VirtualBox Open Source Edition (OSE), as
13 * available from http://www.virtualbox.org. This file is free software;
14 * you can redistribute it and/or modify it under the terms of the GNU
15 * General Public License (GPL) as published by the Free Software
16 * Foundation, in version 2 as it comes in the "COPYING" file of the
17 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19 */
20
21
22/*********************************************************************************************************************************
23* Header Files *
24*********************************************************************************************************************************/
25#define LOG_GROUP LOG_GROUP_DEV_PARALLEL
26#include <VBox/vmm/pdmdev.h>
27#include <iprt/assert.h>
28#include <iprt/uuid.h>
29#include <iprt/string.h>
30#include <iprt/semaphore.h>
31
32#include "VBoxDD.h"
33
34
35/*********************************************************************************************************************************
36* Defined Constants And Macros *
37*********************************************************************************************************************************/
38#define PARALLEL_SAVED_STATE_VERSION 1
39
40/* defines for accessing the register bits */
41#define LPT_STATUS_BUSY 0x80
42#define LPT_STATUS_ACK 0x40
43#define LPT_STATUS_PAPER_OUT 0x20
44#define LPT_STATUS_SELECT_IN 0x10
45#define LPT_STATUS_ERROR 0x08
46#define LPT_STATUS_IRQ 0x04
47#define LPT_STATUS_BIT1 0x02 /* reserved (only for completeness) */
48#define LPT_STATUS_EPP_TIMEOUT 0x01
49
50#define LPT_CONTROL_BIT7 0x80 /* reserved (only for completeness) */
51#define LPT_CONTROL_BIT6 0x40 /* reserved (only for completeness) */
52#define LPT_CONTROL_ENABLE_BIDIRECT 0x20
53#define LPT_CONTROL_ENABLE_IRQ_VIA_ACK 0x10
54#define LPT_CONTROL_SELECT_PRINTER 0x08
55#define LPT_CONTROL_RESET 0x04
56#define LPT_CONTROL_AUTO_LINEFEED 0x02
57#define LPT_CONTROL_STROBE 0x01
58
59/** mode defines for the extended control register */
60#define LPT_ECP_ECR_CHIPMODE_MASK 0xe0
61#define LPT_ECP_ECR_CHIPMODE_GET_BITS(reg) ((reg) >> 5)
62#define LPT_ECP_ECR_CHIPMODE_SET_BITS(val) ((val) << 5)
63#define LPT_ECP_ECR_CHIPMODE_CONFIGURATION 0x07
64#define LPT_ECP_ECR_CHIPMODE_FIFO_TEST 0x06
65#define LPT_ECP_ECR_CHIPMODE_RESERVED 0x05
66#define LPT_ECP_ECR_CHIPMODE_EPP 0x04
67#define LPT_ECP_ECR_CHIPMODE_ECP_FIFO 0x03
68#define LPT_ECP_ECR_CHIPMODE_PP_FIFO 0x02
69#define LPT_ECP_ECR_CHIPMODE_BYTE 0x01
70#define LPT_ECP_ECR_CHIPMODE_COMPAT 0x00
71
72/** FIFO status bits in extended control register */
73#define LPT_ECP_ECR_FIFO_MASK 0x03
74#define LPT_ECP_ECR_FIFO_SOME_DATA 0x00
75#define LPT_ECP_ECR_FIFO_FULL 0x02
76#define LPT_ECP_ECR_FIFO_EMPTY 0x01
77
78#define LPT_ECP_CONFIGA_FIFO_WITDH_MASK 0x70
79#define LPT_ECP_CONFIGA_FIFO_WIDTH_GET_BITS(reg) ((reg) >> 4)
80#define LPT_ECP_CONFIGA_FIFO_WIDTH_SET_BITS(val) ((val) << 4)
81#define LPT_ECP_CONFIGA_FIFO_WIDTH_16 0x00
82#define LPT_ECP_CONFIGA_FIFO_WIDTH_32 0x20
83#define LPT_ECP_CONFIGA_FIFO_WIDTH_8 0x10
84
85#define LPT_ECP_FIFO_DEPTH 2
86
87
88/*********************************************************************************************************************************
89* Structures and Typedefs *
90*********************************************************************************************************************************/
91/**
92 * Parallel device state.
93 *
94 * @implements PDMIBASE
95 * @implements PDMIHOSTPARALLELPORT
96 */
97typedef struct PARALLELPORT
98{
99 /** Pointer to the device instance - R3 Ptr */
100 PPDMDEVINSR3 pDevInsR3;
101 /** Pointer to the device instance - R0 Ptr */
102 PPDMDEVINSR0 pDevInsR0;
103 /** Pointer to the device instance - RC Ptr */
104 PPDMDEVINSRC pDevInsRC;
105 /** Alignment. */
106 RTRCPTR Alignment0;
107 /** LUN\#0: The base interface. */
108 PDMIBASE IBase;
109 /** LUN\#0: The host device port interface. */
110 PDMIHOSTPARALLELPORT IHostParallelPort;
111 /** Pointer to the attached base driver. */
112 R3PTRTYPE(PPDMIBASE) pDrvBase;
113 /** Pointer to the attached host device. */
114 R3PTRTYPE(PPDMIHOSTPARALLELCONNECTOR) pDrvHostParallelConnector;
115 /** Flag whether the device has its RC component enabled. */
116 bool fGCEnabled;
117 /** Flag whether the device has its R0 component enabled. */
118 bool fR0Enabled;
119 /** Flag whether an EPP timeout occurred (error handling). */
120 bool fEppTimeout;
121 /** Base I/O port of the parallel port. */
122 RTIOPORT IOBase;
123 /** IRQ number assigned ot the parallel port. */
124 int iIrq;
125 /** Data register. */
126 uint8_t regData;
127 /** Status register. */
128 uint8_t regStatus;
129 /** Control register. */
130 uint8_t regControl;
131 /** EPP address register. */
132 uint8_t regEppAddr;
133 /** EPP data register. */
134 uint8_t regEppData;
135 /** More alignment. */
136 uint32_t u32Alignment;
137
138#if 0 /* Data for ECP implementation, currently unused. */
139 uint8_t reg_ecp_ecr;
140 uint8_t reg_ecp_base_plus_400h; /* has different meanings */
141 uint8_t reg_ecp_config_b;
142
143 /** The ECP FIFO implementation*/
144 uint8_t ecp_fifo[LPT_ECP_FIFO_DEPTH];
145 uint8_t abAlignemnt[2];
146 int act_fifo_pos_write;
147 int act_fifo_pos_read;
148#endif
149} PARALLELPORT, *PPARALLELPORT;
150
151#ifndef VBOX_DEVICE_STRUCT_TESTCASE
152
153#define PDMIHOSTPARALLELPORT_2_PARALLELPORT(pInstance) ( (PARALLELPORT *)((uintptr_t)(pInterface) - RT_UOFFSETOF(PARALLELPORT, IHostParallelPort)) )
154#define PDMIHOSTDEVICEPORT_2_PARALLELPORT(pInstance) ( (PARALLELPORT *)((uintptr_t)(pInterface) - RT_UOFFSETOF(PARALLELPORT, IHostDevicePort)) )
155#define PDMIBASE_2_PARALLELPORT(pInstance) ( (PARALLELPORT *)((uintptr_t)(pInterface) - RT_UOFFSETOF(PARALLELPORT, IBase)) )
156
157
158/*********************************************************************************************************************************
159* Internal Functions *
160*********************************************************************************************************************************/
161RT_C_DECLS_BEGIN
162PDMBOTHCBDECL(int) parallelIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb);
163PDMBOTHCBDECL(int) parallelIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb);
164#if 0
165PDMBOTHCBDECL(int) parallelIOPortReadECP(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
166PDMBOTHCBDECL(int) parallelIOPortWriteECP(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
167#endif
168RT_C_DECLS_END
169
170
171#ifdef IN_RING3
172static void parallelR3IrqSet(PARALLELPORT *pThis)
173{
174 if (pThis->regControl & LPT_CONTROL_ENABLE_IRQ_VIA_ACK)
175 {
176 LogFlowFunc(("%d 1\n", pThis->iIrq));
177 PDMDevHlpISASetIrqNoWait(pThis->CTX_SUFF(pDevIns), pThis->iIrq, 1);
178 }
179}
180
181static void parallelR3IrqClear(PARALLELPORT *pThis)
182{
183 LogFlowFunc(("%d 0\n", pThis->iIrq));
184 PDMDevHlpISASetIrqNoWait(pThis->CTX_SUFF(pDevIns), pThis->iIrq, 0);
185}
186#endif
187
188#if 0
189static int parallel_ioport_write_ecp(void *opaque, uint32_t addr, uint32_t val)
190{
191 PARALLELPORT *s = (PARALLELPORT *)opaque;
192 unsigned char ch;
193
194 addr &= 7;
195 LogFlow(("parallel: write ecp addr=0x%02x val=0x%02x\n", addr, val));
196 ch = val;
197 switch (addr) {
198 default:
199 case 0:
200 if (LPT_ECP_ECR_CHIPMODE_GET_BITS(s->reg_ecp_ecr) == LPT_ECP_ECR_CHIPMODE_FIFO_TEST) {
201 s->ecp_fifo[s->act_fifo_pos_write] = ch;
202 s->act_fifo_pos_write++;
203 if (s->act_fifo_pos_write < LPT_ECP_FIFO_DEPTH) {
204 /* FIFO has some data (clear both FIFO bits) */
205 s->reg_ecp_ecr &= ~(LPT_ECP_ECR_FIFO_EMPTY | LPT_ECP_ECR_FIFO_FULL);
206 } else {
207 /* FIFO is full */
208 /* Clear FIFO empty bit */
209 s->reg_ecp_ecr &= ~LPT_ECP_ECR_FIFO_EMPTY;
210 /* Set FIFO full bit */
211 s->reg_ecp_ecr |= LPT_ECP_ECR_FIFO_FULL;
212 s->act_fifo_pos_write = 0;
213 }
214 } else {
215 s->reg_ecp_base_plus_400h = ch;
216 }
217 break;
218 case 1:
219 s->reg_ecp_config_b = ch;
220 break;
221 case 2:
222 /* If we change the mode clear FIFO */
223 if ((ch & LPT_ECP_ECR_CHIPMODE_MASK) != (s->reg_ecp_ecr & LPT_ECP_ECR_CHIPMODE_MASK)) {
224 /* reset the fifo */
225 s->act_fifo_pos_write = 0;
226 s->act_fifo_pos_read = 0;
227 /* Set FIFO empty bit */
228 s->reg_ecp_ecr |= LPT_ECP_ECR_FIFO_EMPTY;
229 /* Clear FIFO full bit */
230 s->reg_ecp_ecr &= ~LPT_ECP_ECR_FIFO_FULL;
231 }
232 /* Set new mode */
233 s->reg_ecp_ecr |= LPT_ECP_ECR_CHIPMODE_SET_BITS(LPT_ECP_ECR_CHIPMODE_GET_BITS(ch));
234 break;
235 case 3:
236 break;
237 case 4:
238 break;
239 case 5:
240 break;
241 case 6:
242 break;
243 case 7:
244 break;
245 }
246 return VINF_SUCCESS;
247}
248
249static uint32_t parallel_ioport_read_ecp(void *opaque, uint32_t addr, int *pRC)
250{
251 PARALLELPORT *s = (PARALLELPORT *)opaque;
252 uint32_t ret = ~0U;
253
254 *pRC = VINF_SUCCESS;
255
256 addr &= 7;
257 switch (addr) {
258 default:
259 case 0:
260 if (LPT_ECP_ECR_CHIPMODE_GET_BITS(s->reg_ecp_ecr) == LPT_ECP_ECR_CHIPMODE_FIFO_TEST) {
261 ret = s->ecp_fifo[s->act_fifo_pos_read];
262 s->act_fifo_pos_read++;
263 if (s->act_fifo_pos_read == LPT_ECP_FIFO_DEPTH)
264 s->act_fifo_pos_read = 0; /* end of FIFO, start at beginning */
265 if (s->act_fifo_pos_read == s->act_fifo_pos_write) {
266 /* FIFO is empty */
267 /* Set FIFO empty bit */
268 s->reg_ecp_ecr |= LPT_ECP_ECR_FIFO_EMPTY;
269 /* Clear FIFO full bit */
270 s->reg_ecp_ecr &= ~LPT_ECP_ECR_FIFO_FULL;
271 } else {
272 /* FIFO has some data (clear all FIFO bits) */
273 s->reg_ecp_ecr &= ~(LPT_ECP_ECR_FIFO_EMPTY | LPT_ECP_ECR_FIFO_FULL);
274 }
275 } else {
276 ret = s->reg_ecp_base_plus_400h;
277 }
278 break;
279 case 1:
280 ret = s->reg_ecp_config_b;
281 break;
282 case 2:
283 ret = s->reg_ecp_ecr;
284 break;
285 case 3:
286 break;
287 case 4:
288 break;
289 case 5:
290 break;
291 case 6:
292 break;
293 case 7:
294 break;
295 }
296 LogFlow(("parallel: read ecp addr=0x%02x val=0x%02x\n", addr, ret));
297 return ret;
298}
299#endif
300
301#ifdef IN_RING3
302/**
303 * @interface_method_impl{PDMIHOSTPARALLELPORT,pfnNotifyInterrupt}
304 */
305static DECLCALLBACK(int) parallelR3NotifyInterrupt(PPDMIHOSTPARALLELPORT pInterface)
306{
307 PARALLELPORT *pThis = PDMIHOSTPARALLELPORT_2_PARALLELPORT(pInterface);
308
309 PDMCritSectEnter(pThis->pDevInsR3->pCritSectRoR3, VINF_SUCCESS);
310 parallelR3IrqSet(pThis);
311 PDMCritSectLeave(pThis->pDevInsR3->pCritSectRoR3);
312
313 return VINF_SUCCESS;
314}
315#endif /* IN_RING3 */
316
317
318/**
319 * @callback_method_impl{FNIOMIOPORTOUT}
320 */
321PDMBOTHCBDECL(int) parallelIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
322{
323 PARALLELPORT *pThis = PDMINS_2_DATA(pDevIns, PPARALLELPORT);
324 int rc = VINF_SUCCESS;
325 RT_NOREF_PV(pvUser);
326
327 if (cb == 1)
328 {
329 uint8_t u8 = u32;
330
331 Log2(("%s: port %#06x val %#04x\n", __FUNCTION__, uPort, u32));
332
333 uPort &= 7;
334 switch (uPort)
335 {
336 case 0:
337#ifndef IN_RING3
338 NOREF(u8);
339 rc = VINF_IOM_R3_IOPORT_WRITE;
340#else
341 pThis->regData = u8;
342 if (RT_LIKELY(pThis->pDrvHostParallelConnector))
343 {
344 LogFlowFunc(("Set data lines 0x%X\n", u8));
345 rc = pThis->pDrvHostParallelConnector->pfnWrite(pThis->pDrvHostParallelConnector, &u8, 1, PDM_PARALLEL_PORT_MODE_SPP);
346 AssertRC(rc);
347 }
348#endif
349 break;
350 case 1:
351 break;
352 case 2:
353 /* Set the reserved bits to one */
354 u8 |= (LPT_CONTROL_BIT6 | LPT_CONTROL_BIT7);
355 if (u8 != pThis->regControl)
356 {
357#ifndef IN_RING3
358 return VINF_IOM_R3_IOPORT_WRITE;
359#else
360 if (RT_LIKELY(pThis->pDrvHostParallelConnector))
361 {
362 /* Set data direction. */
363 if (u8 & LPT_CONTROL_ENABLE_BIDIRECT)
364 rc = pThis->pDrvHostParallelConnector->pfnSetPortDirection(pThis->pDrvHostParallelConnector, false /* fForward */);
365 else
366 rc = pThis->pDrvHostParallelConnector->pfnSetPortDirection(pThis->pDrvHostParallelConnector, true /* fForward */);
367 AssertRC(rc);
368
369 u8 &= ~LPT_CONTROL_ENABLE_BIDIRECT; /* Clear bit. */
370
371 rc = pThis->pDrvHostParallelConnector->pfnWriteControl(pThis->pDrvHostParallelConnector, u8);
372 AssertRC(rc);
373 }
374 else
375 u8 &= ~LPT_CONTROL_ENABLE_BIDIRECT; /* Clear bit. */
376
377 pThis->regControl = u8;
378#endif
379 }
380 break;
381 case 3:
382#ifndef IN_RING3
383 NOREF(u8);
384 rc = VINF_IOM_R3_IOPORT_WRITE;
385#else
386 pThis->regEppAddr = u8;
387 if (RT_LIKELY(pThis->pDrvHostParallelConnector))
388 {
389 LogFlowFunc(("Write EPP address 0x%X\n", u8));
390 rc = pThis->pDrvHostParallelConnector->pfnWrite(pThis->pDrvHostParallelConnector, &u8, 1, PDM_PARALLEL_PORT_MODE_EPP_ADDR);
391 AssertRC(rc);
392 }
393#endif
394 break;
395 case 4:
396#ifndef IN_RING3
397 NOREF(u8);
398 rc = VINF_IOM_R3_IOPORT_WRITE;
399#else
400 pThis->regEppData = u8;
401 if (RT_LIKELY(pThis->pDrvHostParallelConnector))
402 {
403 LogFlowFunc(("Write EPP data 0x%X\n", u8));
404 rc = pThis->pDrvHostParallelConnector->pfnWrite(pThis->pDrvHostParallelConnector, &u8, 1, PDM_PARALLEL_PORT_MODE_EPP_DATA);
405 AssertRC(rc);
406 }
407#endif
408 break;
409 case 5:
410 break;
411 case 6:
412 break;
413 case 7:
414 default:
415 break;
416 }
417 }
418 else
419 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", uPort, cb, u32));
420
421 return rc;
422}
423
424
425/**
426 * @callback_method_impl{FNIOMIOPORTIN}
427 */
428PDMBOTHCBDECL(int) parallelIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
429{
430 PARALLELPORT *pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT *);
431 int rc = VINF_SUCCESS;
432 RT_NOREF_PV(pvUser);
433
434 if (cb == 1)
435 {
436 uPort &= 7;
437 switch (uPort)
438 {
439 case 0:
440 if (!(pThis->regControl & LPT_CONTROL_ENABLE_BIDIRECT))
441 *pu32 = pThis->regData;
442 else
443 {
444#ifndef IN_RING3
445 rc = VINF_IOM_R3_IOPORT_READ;
446#else
447 if (RT_LIKELY(pThis->pDrvHostParallelConnector))
448 {
449 rc = pThis->pDrvHostParallelConnector->pfnRead(pThis->pDrvHostParallelConnector, &pThis->regData,
450 1, PDM_PARALLEL_PORT_MODE_SPP);
451 Log(("Read data lines 0x%X\n", pThis->regData));
452 AssertRC(rc);
453 }
454 *pu32 = pThis->regData;
455#endif
456 }
457 break;
458 case 1:
459#ifndef IN_RING3
460 rc = VINF_IOM_R3_IOPORT_READ;
461#else
462 if (RT_LIKELY(pThis->pDrvHostParallelConnector))
463 {
464 rc = pThis->pDrvHostParallelConnector->pfnReadStatus(pThis->pDrvHostParallelConnector, &pThis->regStatus);
465 AssertRC(rc);
466 }
467 *pu32 = pThis->regStatus;
468 parallelR3IrqClear(pThis);
469#endif
470 break;
471 case 2:
472#ifndef IN_RING3
473 rc = VINF_IOM_R3_IOPORT_READ;
474#else
475 if (RT_LIKELY(pThis->pDrvHostParallelConnector))
476 {
477 rc = pThis->pDrvHostParallelConnector->pfnReadControl(pThis->pDrvHostParallelConnector, &pThis->regControl);
478 AssertRC(rc);
479 pThis->regControl |= LPT_CONTROL_BIT6 | LPT_CONTROL_BIT7;
480 }
481
482 *pu32 = pThis->regControl;
483#endif
484 break;
485 case 3:
486#ifndef IN_RING3
487 rc = VINF_IOM_R3_IOPORT_READ;
488#else
489 if (RT_LIKELY(pThis->pDrvHostParallelConnector))
490 {
491 rc = pThis->pDrvHostParallelConnector->pfnRead(pThis->pDrvHostParallelConnector, &pThis->regEppAddr,
492 1, PDM_PARALLEL_PORT_MODE_EPP_ADDR);
493 Log(("Read EPP address 0x%X\n", pThis->regEppAddr));
494 AssertRC(rc);
495 }
496 *pu32 = pThis->regEppAddr;
497#endif
498 break;
499 case 4:
500#ifndef IN_RING3
501 rc = VINF_IOM_R3_IOPORT_READ;
502#else
503 if (RT_LIKELY(pThis->pDrvHostParallelConnector))
504 {
505 rc = pThis->pDrvHostParallelConnector->pfnRead(pThis->pDrvHostParallelConnector, &pThis->regEppData,
506 1, PDM_PARALLEL_PORT_MODE_EPP_DATA);
507 Log(("Read EPP data 0x%X\n", pThis->regEppData));
508 AssertRC(rc);
509 }
510 *pu32 = pThis->regEppData;
511#endif
512 break;
513 case 5:
514 break;
515 case 6:
516 break;
517 case 7:
518 break;
519 }
520 }
521 else
522 rc = VERR_IOM_IOPORT_UNUSED;
523
524 return rc;
525}
526
527#if 0
528/**
529 * @callback_method_impl{FNIOMIOPORTOUT, ECP registers.}
530 */
531PDMBOTHCBDECL(int) parallelIOPortWriteECP(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
532{
533 PARALLELPORT *pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT *);
534 int rc = VINF_SUCCESS;
535
536 if (cb == 1)
537 {
538 Log2(("%s: ecp port %#06x val %#04x\n", __FUNCTION__, Port, u32));
539 rc = parallel_ioport_write_ecp (pThis, Port, u32);
540 }
541 else
542 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
543
544 return rc;
545}
546
547/**
548 * @callback_method_impl{FNIOMIOPORTOUT, ECP registers.}
549 */
550PDMBOTHCBDECL(int) parallelIOPortReadECP(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
551{
552 PARALLELPORT *pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT *);
553 int rc = VINF_SUCCESS;
554
555 if (cb == 1)
556 {
557 *pu32 = parallel_ioport_read_ecp (pThis, Port, &rc);
558 Log2(("%s: ecp port %#06x val %#04x\n", __FUNCTION__, Port, *pu32));
559 }
560 else
561 rc = VERR_IOM_IOPORT_UNUSED;
562
563 return rc;
564}
565#endif
566
567#ifdef IN_RING3
568
569/**
570 * @callback_method_impl{FNSSMDEVLIVEEXEC}
571 */
572static DECLCALLBACK(int) parallelR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
573{
574 RT_NOREF(uPass);
575 PARALLELPORT *pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT *);
576
577 SSMR3PutS32(pSSM, pThis->iIrq);
578 SSMR3PutU32(pSSM, pThis->IOBase);
579 SSMR3PutU32(pSSM, UINT32_MAX); /* sanity/terminator */
580 return VINF_SSM_DONT_CALL_AGAIN;
581}
582
583
584/**
585 * @callback_method_impl{FNSSMDEVSAVEEXEC}
586 */
587static DECLCALLBACK(int) parallelR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
588{
589 PARALLELPORT *pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT *);
590
591 SSMR3PutU8(pSSM, pThis->regData);
592 SSMR3PutU8(pSSM, pThis->regStatus);
593 SSMR3PutU8(pSSM, pThis->regControl);
594
595 parallelR3LiveExec(pDevIns, pSSM, 0);
596 return VINF_SUCCESS;
597}
598
599
600/**
601 * @callback_method_impl{FNSSMDEVLOADEXEC}
602 */
603static DECLCALLBACK(int) parallelR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
604{
605 PARALLELPORT *pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT *);
606
607 AssertMsgReturn(uVersion == PARALLEL_SAVED_STATE_VERSION, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
608 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
609 if (uPass == SSM_PASS_FINAL)
610 {
611 SSMR3GetU8(pSSM, &pThis->regData);
612 SSMR3GetU8(pSSM, &pThis->regStatus);
613 SSMR3GetU8(pSSM, &pThis->regControl);
614 }
615
616 /* the config */
617 int32_t iIrq;
618 SSMR3GetS32(pSSM, &iIrq);
619 uint32_t uIoBase;
620 SSMR3GetU32(pSSM, &uIoBase);
621 uint32_t u32;
622 int rc = SSMR3GetU32(pSSM, &u32);
623 if (RT_FAILURE(rc))
624 return rc;
625 AssertMsgReturn(u32 == UINT32_MAX, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
626
627 if (pThis->iIrq != iIrq)
628 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("IRQ changed: config=%#x state=%#x"), pThis->iIrq, iIrq);
629
630 if (pThis->IOBase != uIoBase)
631 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("IOBase changed: config=%#x state=%#x"), pThis->IOBase, uIoBase);
632
633 /* not necessary... but it doesn't harm. */
634 pThis->pDevInsR3 = pDevIns;
635 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
636 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
637 return VINF_SUCCESS;
638}
639
640
641/**
642 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
643 */
644static DECLCALLBACK(void *) parallelR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
645{
646 PARALLELPORT *pThis = PDMIBASE_2_PARALLELPORT(pInterface);
647 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
648 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIHOSTPARALLELPORT, &pThis->IHostParallelPort);
649 return NULL;
650}
651
652
653/**
654 * @copydoc FNPDMDEVRELOCATE
655 */
656static DECLCALLBACK(void) parallelR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
657{
658 PARALLELPORT *pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT *);
659 pThis->pDevInsRC += offDelta;
660}
661
662
663/**
664 * @interface_method_impl{PDMDEVREG,pfnConstruct}
665 */
666static DECLCALLBACK(int) parallelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
667{
668 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
669 int rc;
670 PARALLELPORT *pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT*);
671
672 Assert(iInstance < 4);
673
674 /*
675 * Init the data.
676 */
677 pThis->pDevInsR3 = pDevIns;
678 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
679 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
680
681 /* IBase */
682 pThis->IBase.pfnQueryInterface = parallelR3QueryInterface;
683
684 /* IHostParallelPort */
685 pThis->IHostParallelPort.pfnNotifyInterrupt = parallelR3NotifyInterrupt;
686
687 /* Init parallel state */
688 pThis->regData = 0;
689#if 0 /* ECP implementation not complete. */
690 pThis->reg_ecp_ecr = LPT_ECP_ECR_CHIPMODE_COMPAT | LPT_ECP_ECR_FIFO_EMPTY;
691 pThis->act_fifo_pos_read = 0;
692 pThis->act_fifo_pos_write = 0;
693#endif
694
695 /*
696 * Validate and read the configuration.
697 */
698 if (!CFGMR3AreValuesValid(pCfg, "IRQ\0" "IOBase\0" "GCEnabled\0" "R0Enabled\0"))
699 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
700 N_("Configuration error: Unknown config key"));
701
702 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fGCEnabled, false);
703 if (RT_FAILURE(rc))
704 return PDMDEV_SET_ERROR(pDevIns, rc,
705 N_("Configuration error: Failed to get the \"GCEnabled\" value"));
706
707 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, false);
708 if (RT_FAILURE(rc))
709 return PDMDEV_SET_ERROR(pDevIns, rc,
710 N_("Configuration error: Failed to get the \"R0Enabled\" value"));
711 rc = CFGMR3QueryS32Def(pCfg, "IRQ", &pThis->iIrq, 7);
712 if (RT_FAILURE(rc))
713 return PDMDEV_SET_ERROR(pDevIns, rc,
714 N_("Configuration error: Failed to get the \"IRQ\" value"));
715 rc = CFGMR3QueryU16Def(pCfg, "IOBase", &pThis->IOBase, 0x378);
716 if (RT_FAILURE(rc))
717 return PDMDEV_SET_ERROR(pDevIns, rc,
718 N_("Configuration error: Failed to get the \"IOBase\" value"));
719
720 int port_count = (pThis->IOBase == 0x3BC) ? 4 : 8;
721 /*
722 * Register the I/O ports and saved state.
723 */
724 rc = PDMDevHlpIOPortRegister(pDevIns, pThis->IOBase, port_count, 0,
725 parallelIOPortWrite, parallelIOPortRead,
726 NULL, NULL, "Parallel");
727 if (RT_FAILURE(rc))
728 return rc;
729
730#if 0
731 /* register ecp registers */
732 rc = PDMDevHlpIOPortRegister(pDevIns, io_base+0x400, 8, 0,
733 parallelIOPortWriteECP, parallelIOPortReadECP,
734 NULL, NULL, "PARALLEL ECP");
735 if (RT_FAILURE(rc))
736 return rc;
737#endif
738
739 if (pThis->fGCEnabled)
740 {
741 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->IOBase, port_count, 0, "parallelIOPortWrite",
742 "parallelIOPortRead", NULL, NULL, "Parallel");
743 if (RT_FAILURE(rc))
744 return rc;
745
746#if 0
747 rc = PDMDevHlpIOPortRegisterGC(pDevIns, io_base+0x400, port_count, 0, "parallelIOPortWriteECP",
748 "parallelIOPortReadECP", NULL, NULL, "Parallel Ecp");
749 if (RT_FAILURE(rc))
750 return rc;
751#endif
752 }
753
754 if (pThis->fR0Enabled)
755 {
756 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->IOBase, port_count, 0, "parallelIOPortWrite",
757 "parallelIOPortRead", NULL, NULL, "Parallel");
758 if (RT_FAILURE(rc))
759 return rc;
760
761#if 0
762 rc = PDMDevHlpIOPortRegisterR0(pDevIns, io_base+0x400, 8, 0, "parallelIOPortWriteECP",
763 "parallelIOPortReadECP", NULL, NULL, "Parallel Ecp");
764 if (RT_FAILURE(rc))
765 return rc;
766#endif
767 }
768
769 rc = PDMDevHlpSSMRegister3(pDevIns, PARALLEL_SAVED_STATE_VERSION, sizeof(*pThis),
770 parallelR3LiveExec, parallelR3SaveExec, parallelR3LoadExec);
771 if (RT_FAILURE(rc))
772 return rc;
773
774
775 /*
776 * Attach the parallel port driver and get the interfaces.
777 * For now no run-time changes are supported.
778 */
779 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Parallel Host");
780 if (RT_SUCCESS(rc))
781 {
782 pThis->pDrvHostParallelConnector = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIHOSTPARALLELCONNECTOR);
783
784 /* Set compatibility mode */
785 //pThis->pDrvHostParallelConnector->pfnSetMode(pThis->pDrvHostParallelConnector, PDM_PARALLEL_PORT_MODE_COMPAT);
786 /* Get status of control register */
787 pThis->pDrvHostParallelConnector->pfnReadControl(pThis->pDrvHostParallelConnector, &pThis->regControl);
788
789 AssertMsgReturn(pThis->pDrvHostParallelConnector,
790 ("Configuration error: instance %d has no host parallel interface!\n", iInstance),
791 VERR_PDM_MISSING_INTERFACE);
792 }
793 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
794 {
795 pThis->pDrvBase = NULL;
796 pThis->pDrvHostParallelConnector = NULL;
797 LogRel(("Parallel%d: no unit\n", iInstance));
798 }
799 else
800 {
801 AssertMsgFailed(("Parallel%d: Failed to attach to host driver. rc=%Rrc\n", iInstance, rc));
802 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
803 N_("Parallel device %d cannot attach to host driver"), iInstance);
804 }
805
806 return VINF_SUCCESS;
807}
808
809/**
810 * The device registration structure.
811 */
812const PDMDEVREG g_DeviceParallelPort =
813{
814 /* u32Version */
815 PDM_DEVREG_VERSION,
816 /* szName */
817 "parallel",
818 /* szRCMod */
819 "VBoxDDRC.rc",
820 /* szR0Mod */
821 "VBoxDDR0.r0",
822 /* pszDescription */
823 "Parallel Communication Port",
824 /* fFlags */
825 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
826 /* fClass */
827 PDM_DEVREG_CLASS_PARALLEL,
828 /* cMaxInstances */
829 2,
830 /* cbInstance */
831 sizeof(PARALLELPORT),
832 /* pfnConstruct */
833 parallelR3Construct,
834 /* pfnDestruct */
835 NULL,
836 /* pfnRelocate */
837 parallelR3Relocate,
838 /* pfnMemSetup */
839 NULL,
840 /* pfnPowerOn */
841 NULL,
842 /* pfnReset */
843 NULL,
844 /* pfnSuspend */
845 NULL,
846 /* pfnResume */
847 NULL,
848 /* pfnAttach */
849 NULL,
850 /* pfnDetach */
851 NULL,
852 /* pfnQueryInterface. */
853 NULL,
854 /* pfnInitComplete */
855 NULL,
856 /* pfnPowerOff */
857 NULL,
858 /* pfnSoftReset */
859 NULL,
860 /* u32VersionEnd */
861 PDM_DEVREG_VERSION
862};
863#endif /* IN_RING3 */
864#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
865
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