DevParallel.cpp@ 48107

Last change on this file since 48107 was 45025, checked in by vboxsync, 12 years ago
Update PDMDEVREG initialization comment so they refer to pfnMemSetup instead of pfnIOCtl.
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1	/* $Id: DevParallel.cpp 45025 2013-03-13 16:45:15Z vboxsync $ */
2	/** @file
3	* DevParallel - Parallel (Port) Device Emulation.
4	*
5	* Contributed by: Alexander Eichner
6	* Based on DevSerial.cpp
7	*/
8
9	/*
10	* Copyright (C) 2006-2012 Oracle Corporation
11	*
12	* This file is part of VirtualBox Open Source Edition (OSE), as
13	* available from http://www.virtualbox.org. This file is free software;
14	* you can redistribute it and/or modify it under the terms of the GNU
15	* General Public License (GPL) as published by the Free Software
16	* Foundation, in version 2 as it comes in the "COPYING" file of the
17	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19	*/
20
21	/*******************************************************************************
22	* Header Files *
23	*******************************************************************************/
24	#define LOG_GROUP LOG_GROUP_DEV_PARALLEL
25	#include <VBox/vmm/pdmdev.h>
26	#include <iprt/assert.h>
27	#include <iprt/uuid.h>
28	#include <iprt/string.h>
29	#include <iprt/semaphore.h>
30
31	#include "VBoxDD.h"
32
33
34	/*******************************************************************************
35	* Defined Constants And Macros *
36	*******************************************************************************/
37	#define PARALLEL_SAVED_STATE_VERSION 1
38
39	/* defines for accessing the register bits */
40	#define LPT_STATUS_BUSY 0x80
41	#define LPT_STATUS_ACK 0x40
42	#define LPT_STATUS_PAPER_OUT 0x20
43	#define LPT_STATUS_SELECT_IN 0x10
44	#define LPT_STATUS_ERROR 0x08
45	#define LPT_STATUS_IRQ 0x04
46	#define LPT_STATUS_BIT1 0x02 /* reserved (only for completeness) */
47	#define LPT_STATUS_EPP_TIMEOUT 0x01
48
49	#define LPT_CONTROL_BIT7 0x80 /* reserved (only for completeness) */
50	#define LPT_CONTROL_BIT6 0x40 /* reserved (only for completeness) */
51	#define LPT_CONTROL_ENABLE_BIDIRECT 0x20
52	#define LPT_CONTROL_ENABLE_IRQ_VIA_ACK 0x10
53	#define LPT_CONTROL_SELECT_PRINTER 0x08
54	#define LPT_CONTROL_RESET 0x04
55	#define LPT_CONTROL_AUTO_LINEFEED 0x02
56	#define LPT_CONTROL_STROBE 0x01
57
58	/** mode defines for the extended control register */
59	#define LPT_ECP_ECR_CHIPMODE_MASK 0xe0
60	#define LPT_ECP_ECR_CHIPMODE_GET_BITS(reg) ((reg) >> 5)
61	#define LPT_ECP_ECR_CHIPMODE_SET_BITS(val) ((val) << 5)
62	#define LPT_ECP_ECR_CHIPMODE_CONFIGURATION 0x07
63	#define LPT_ECP_ECR_CHIPMODE_FIFO_TEST 0x06
64	#define LPT_ECP_ECR_CHIPMODE_RESERVED 0x05
65	#define LPT_ECP_ECR_CHIPMODE_EPP 0x04
66	#define LPT_ECP_ECR_CHIPMODE_ECP_FIFO 0x03
67	#define LPT_ECP_ECR_CHIPMODE_PP_FIFO 0x02
68	#define LPT_ECP_ECR_CHIPMODE_BYTE 0x01
69	#define LPT_ECP_ECR_CHIPMODE_COMPAT 0x00
70
71	/** FIFO status bits in extended control register */
72	#define LPT_ECP_ECR_FIFO_MASK 0x03
73	#define LPT_ECP_ECR_FIFO_SOME_DATA 0x00
74	#define LPT_ECP_ECR_FIFO_FULL 0x02
75	#define LPT_ECP_ECR_FIFO_EMPTY 0x01
76
77	#define LPT_ECP_CONFIGA_FIFO_WITDH_MASK 0x70
78	#define LPT_ECP_CONFIGA_FIFO_WIDTH_GET_BITS(reg) ((reg) >> 4)
79	#define LPT_ECP_CONFIGA_FIFO_WIDTH_SET_BITS(val) ((val) << 4)
80	#define LPT_ECP_CONFIGA_FIFO_WIDTH_16 0x00
81	#define LPT_ECP_CONFIGA_FIFO_WIDTH_32 0x20
82	#define LPT_ECP_CONFIGA_FIFO_WIDTH_8 0x10
83
84	#define LPT_ECP_FIFO_DEPTH 2
85
86
87	/*******************************************************************************
88	* Structures and Typedefs *
89	*******************************************************************************/
90	/**
91	* Parallel device state.
92	*
93	* @implements PDMIBASE
94	* @implements PDMIHOSTPARALLELPORT
95	*/
96	typedef struct PARALLELPORT
97	{
98	/** Pointer to the device instance - R3 Ptr */
99	PPDMDEVINSR3 pDevInsR3;
100	/** Pointer to the device instance - R0 Ptr */
101	PPDMDEVINSR0 pDevInsR0;
102	/** Pointer to the device instance - RC Ptr */
103	PPDMDEVINSRC pDevInsRC;
104	/** Alignment. */
105	RTRCPTR Alignment0;
106	/** LUN\#0: The base interface. */
107	PDMIBASE IBase;
108	/** LUN\#0: The host device port interface. */
109	PDMIHOSTPARALLELPORT IHostParallelPort;
110	/** Pointer to the attached base driver. */
111	R3PTRTYPE(PPDMIBASE) pDrvBase;
112	/** Pointer to the attached host device. */
113	R3PTRTYPE(PPDMIHOSTPARALLELCONNECTOR) pDrvHostParallelConnector;
114	/** Flag whether the device has its RC component enabled. */
115	bool fGCEnabled;
116	/** Flag whether the device has its R0 component enabled. */
117	bool fR0Enabled;
118	/** Flag whether an EPP timeout occurred (error handling). */
119	bool fEppTimeout;
120	/** Base I/O port of the parallel port. */
121	RTIOPORT IOBase;
122	/** IRQ number assigned ot the parallel port. */
123	int iIrq;
124	/** Data register. */
125	uint8_t regData;
126	/** Status register. */
127	uint8_t regStatus;
128	/** Control register. */
129	uint8_t regControl;
130	/** EPP address register. */
131	uint8_t regEppAddr;
132	/** EPP data register. */
133	uint8_t regEppData;
134	/** More alignment. */
135	uint32_t u32Alignment;
136
137	#if 0 /* Data for ECP implementation, currently unused. */
138	uint8_t reg_ecp_ecr;
139	uint8_t reg_ecp_base_plus_400h; /* has different meanings */
140	uint8_t reg_ecp_config_b;
141
142	/** The ECP FIFO implementation*/
143	uint8_t ecp_fifo[LPT_ECP_FIFO_DEPTH];
144	uint8_t abAlignemnt[2];
145	int act_fifo_pos_write;
146	int act_fifo_pos_read;
147	#endif
148	} PARALLELPORT, *PPARALLELPORT;
149
150	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
151
152	#define PDMIHOSTPARALLELPORT_2_PARALLELPORT(pInstance) ( (PARALLELPORT *)((uintptr_t)(pInterface) - RT_OFFSETOF(PARALLELPORT, IHostParallelPort)) )
153	#define PDMIHOSTDEVICEPORT_2_PARALLELPORT(pInstance) ( (PARALLELPORT *)((uintptr_t)(pInterface) - RT_OFFSETOF(PARALLELPORT, IHostDevicePort)) )
154	#define PDMIBASE_2_PARALLELPORT(pInstance) ( (PARALLELPORT *)((uintptr_t)(pInterface) - RT_OFFSETOF(PARALLELPORT, IBase)) )
155
156
157	/*******************************************************************************
158	* Internal Functions *
159	*******************************************************************************/
160	RT_C_DECLS_BEGIN
161	PDMBOTHCBDECL(int) parallelIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
162	PDMBOTHCBDECL(int) parallelIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
163	#if 0
164	PDMBOTHCBDECL(int) parallelIOPortReadECP(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
165	PDMBOTHCBDECL(int) parallelIOPortWriteECP(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
166	#endif
167	RT_C_DECLS_END
168
169
170	#ifdef IN_RING3
171	static void parallelR3IrqSet(PARALLELPORT *pThis)
172	{
173	if (pThis->regControl & LPT_CONTROL_ENABLE_IRQ_VIA_ACK)
174	{
175	LogFlowFunc(("%d 1\n", pThis->iIrq));
176	PDMDevHlpISASetIrqNoWait(pThis->CTX_SUFF(pDevIns), pThis->iIrq, 1);
177	}
178	}
179
180	static void parallelR3IrqClear(PARALLELPORT *pThis)
181	{
182	LogFlowFunc(("%d 0\n", pThis->iIrq));
183	PDMDevHlpISASetIrqNoWait(pThis->CTX_SUFF(pDevIns), pThis->iIrq, 0);
184	}
185	#endif
186
187	#if 0
188	static int parallel_ioport_write_ecp(void *opaque, uint32_t addr, uint32_t val)
189	{
190	PARALLELPORT s = (PARALLELPORT )opaque;
191	unsigned char ch;
192
193	addr &= 7;
194	LogFlow(("parallel: write ecp addr=0x%02x val=0x%02x\n", addr, val));
195	ch = val;
196	switch (addr) {
197	default:
198	case 0:
199	if (LPT_ECP_ECR_CHIPMODE_GET_BITS(s->reg_ecp_ecr) == LPT_ECP_ECR_CHIPMODE_FIFO_TEST) {
200	s->ecp_fifo[s->act_fifo_pos_write] = ch;
201	s->act_fifo_pos_write++;
202	if (s->act_fifo_pos_write < LPT_ECP_FIFO_DEPTH) {
203	/* FIFO has some data (clear both FIFO bits) */
204	s->reg_ecp_ecr &= ~(LPT_ECP_ECR_FIFO_EMPTY \| LPT_ECP_ECR_FIFO_FULL);
205	} else {
206	/* FIFO is full */
207	/* Clear FIFO empty bit */
208	s->reg_ecp_ecr &= ~LPT_ECP_ECR_FIFO_EMPTY;
209	/* Set FIFO full bit */
210	s->reg_ecp_ecr \|= LPT_ECP_ECR_FIFO_FULL;
211	s->act_fifo_pos_write = 0;
212	}
213	} else {
214	s->reg_ecp_base_plus_400h = ch;
215	}
216	break;
217	case 1:
218	s->reg_ecp_config_b = ch;
219	break;
220	case 2:
221	/* If we change the mode clear FIFO */
222	if ((ch & LPT_ECP_ECR_CHIPMODE_MASK) != (s->reg_ecp_ecr & LPT_ECP_ECR_CHIPMODE_MASK)) {
223	/* reset the fifo */
224	s->act_fifo_pos_write = 0;
225	s->act_fifo_pos_read = 0;
226	/* Set FIFO empty bit */
227	s->reg_ecp_ecr \|= LPT_ECP_ECR_FIFO_EMPTY;
228	/* Clear FIFO full bit */
229	s->reg_ecp_ecr &= ~LPT_ECP_ECR_FIFO_FULL;
230	}
231	/* Set new mode */
232	s->reg_ecp_ecr \|= LPT_ECP_ECR_CHIPMODE_SET_BITS(LPT_ECP_ECR_CHIPMODE_GET_BITS(ch));
233	break;
234	case 3:
235	break;
236	case 4:
237	break;
238	case 5:
239	break;
240	case 6:
241	break;
242	case 7:
243	break;
244	}
245	return VINF_SUCCESS;
246	}
247
248	static uint32_t parallel_ioport_read_ecp(void opaque, uint32_t addr, int pRC)
249	{
250	PARALLELPORT s = (PARALLELPORT )opaque;
251	uint32_t ret = ~0U;
252
253	*pRC = VINF_SUCCESS;
254
255	addr &= 7;
256	switch (addr) {
257	default:
258	case 0:
259	if (LPT_ECP_ECR_CHIPMODE_GET_BITS(s->reg_ecp_ecr) == LPT_ECP_ECR_CHIPMODE_FIFO_TEST) {
260	ret = s->ecp_fifo[s->act_fifo_pos_read];
261	s->act_fifo_pos_read++;
262	if (s->act_fifo_pos_read == LPT_ECP_FIFO_DEPTH)
263	s->act_fifo_pos_read = 0; /* end of FIFO, start at beginning */
264	if (s->act_fifo_pos_read == s->act_fifo_pos_write) {
265	/* FIFO is empty */
266	/* Set FIFO empty bit */
267	s->reg_ecp_ecr \|= LPT_ECP_ECR_FIFO_EMPTY;
268	/* Clear FIFO full bit */
269	s->reg_ecp_ecr &= ~LPT_ECP_ECR_FIFO_FULL;
270	} else {
271	/* FIFO has some data (clear all FIFO bits) */
272	s->reg_ecp_ecr &= ~(LPT_ECP_ECR_FIFO_EMPTY \| LPT_ECP_ECR_FIFO_FULL);
273	}
274	} else {
275	ret = s->reg_ecp_base_plus_400h;
276	}
277	break;
278	case 1:
279	ret = s->reg_ecp_config_b;
280	break;
281	case 2:
282	ret = s->reg_ecp_ecr;
283	break;
284	case 3:
285	break;
286	case 4:
287	break;
288	case 5:
289	break;
290	case 6:
291	break;
292	case 7:
293	break;
294	}
295	LogFlow(("parallel: read ecp addr=0x%02x val=0x%02x\n", addr, ret));
296	return ret;
297	}
298	#endif
299
300	#ifdef IN_RING3
301	/**
302	* @interface_methods_impl{PDMIHOSTPARALLELPORT,pfnNotifyInterrupt}
303	*/
304	static DECLCALLBACK(int) parallelR3NotifyInterrupt(PPDMIHOSTPARALLELPORT pInterface)
305	{
306	PARALLELPORT *pThis = PDMIHOSTPARALLELPORT_2_PARALLELPORT(pInterface);
307
308	PDMCritSectEnter(pThis->pDevInsR3->pCritSectRoR3, VINF_SUCCESS);
309	parallelR3IrqSet(pThis);
310	PDMCritSectLeave(pThis->pDevInsR3->pCritSectRoR3);
311
312	return VINF_SUCCESS;
313	}
314	#endif /* IN_RING3 */
315
316
317	/**
318	* @callback_method_impl{FNIOMIOPORTOUT}
319	*/
320	PDMBOTHCBDECL(int) parallelIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
321	{
322	PARALLELPORT *pThis = PDMINS_2_DATA(pDevIns, PPARALLELPORT);
323	int rc = VINF_SUCCESS;
324
325	if (cb == 1)
326	{
327	uint8_t u8 = u32;
328
329	Log2(("%s: port %#06x val %#04x\n", __FUNCTION__, Port, u32));
330
331	Port &= 7;
332	switch (Port)
333	{
334	case 0:
335	#ifndef IN_RING3
336	NOREF(u8);
337	rc = VINF_IOM_R3_IOPORT_WRITE;
338	#else
339	pThis->regData = u8;
340	if (RT_LIKELY(pThis->pDrvHostParallelConnector))
341	{
342	LogFlowFunc(("Set data lines 0x%X\n", u8));
343	rc = pThis->pDrvHostParallelConnector->pfnWrite(pThis->pDrvHostParallelConnector, &u8, 1, PDM_PARALLEL_PORT_MODE_SPP);
344	AssertRC(rc);
345	}
346	#endif
347	break;
348	case 1:
349	break;
350	case 2:
351	/* Set the reserved bits to one */
352	u8 \|= (LPT_CONTROL_BIT6 \| LPT_CONTROL_BIT7);
353	if (u8 != pThis->regControl)
354	{
355	#ifndef IN_RING3
356	return VINF_IOM_R3_IOPORT_WRITE;
357	#else
358	/* Set data direction. */
359	if (u8 & LPT_CONTROL_ENABLE_BIDIRECT)
360	rc = pThis->pDrvHostParallelConnector->pfnSetPortDirection(pThis->pDrvHostParallelConnector, false /* fForward */);
361	else
362	rc = pThis->pDrvHostParallelConnector->pfnSetPortDirection(pThis->pDrvHostParallelConnector, true /* fForward */);
363	AssertRC(rc);
364	u8 &= ~LPT_CONTROL_ENABLE_BIDIRECT; /* Clear bit. */
365
366	rc = pThis->pDrvHostParallelConnector->pfnWriteControl(pThis->pDrvHostParallelConnector, u8);
367	AssertRC(rc);
368	pThis->regControl = u8;
369	#endif
370	}
371	break;
372	case 3:
373	#ifndef IN_RING3
374	NOREF(u8);
375	rc = VINF_IOM_R3_IOPORT_WRITE;
376	#else
377	pThis->regEppAddr = u8;
378	if (RT_LIKELY(pThis->pDrvHostParallelConnector))
379	{
380	LogFlowFunc(("Write EPP address 0x%X\n", u8));
381	rc = pThis->pDrvHostParallelConnector->pfnWrite(pThis->pDrvHostParallelConnector, &u8, 1, PDM_PARALLEL_PORT_MODE_EPP_ADDR);
382	AssertRC(rc);
383	}
384	#endif
385	break;
386	case 4:
387	#ifndef IN_RING3
388	NOREF(u8);
389	rc = VINF_IOM_R3_IOPORT_WRITE;
390	#else
391	pThis->regEppData = u8;
392	if (RT_LIKELY(pThis->pDrvHostParallelConnector))
393	{
394	LogFlowFunc(("Write EPP data 0x%X\n", u8));
395	rc = pThis->pDrvHostParallelConnector->pfnWrite(pThis->pDrvHostParallelConnector, &u8, 1, PDM_PARALLEL_PORT_MODE_EPP_DATA);
396	AssertRC(rc);
397	}
398	#endif
399	break;
400	case 5:
401	break;
402	case 6:
403	break;
404	case 7:
405	default:
406	break;
407	}
408	}
409	else
410	AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
411
412	return rc;
413	}
414
415
416	/**
417	* @callback_method_impl{FNIOMIOPORTIN}
418	*/
419	PDMBOTHCBDECL(int) parallelIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
420	{
421	PARALLELPORT pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT );
422	int rc = VINF_SUCCESS;
423
424	if (cb == 1)
425	{
426	Port &= 7;
427	switch (Port)
428	{
429	case 0:
430	if (!(pThis->regControl & LPT_CONTROL_ENABLE_BIDIRECT))
431	*pu32 = pThis->regData;
432	else
433	{
434	#ifndef IN_RING3
435	rc = VINF_IOM_R3_IOPORT_READ;
436	#else
437	if (RT_LIKELY(pThis->pDrvHostParallelConnector))
438	{
439	rc = pThis->pDrvHostParallelConnector->pfnRead(pThis->pDrvHostParallelConnector, &pThis->regData,
440	1, PDM_PARALLEL_PORT_MODE_SPP);
441	Log(("Read data lines 0x%X\n", pThis->regData));
442	AssertRC(rc);
443	}
444	*pu32 = pThis->regData;
445	#endif
446	}
447	break;
448	case 1:
449	#ifndef IN_RING3
450	rc = VINF_IOM_R3_IOPORT_READ;
451	#else
452	if (RT_LIKELY(pThis->pDrvHostParallelConnector))
453	{
454	rc = pThis->pDrvHostParallelConnector->pfnReadStatus(pThis->pDrvHostParallelConnector, &pThis->regStatus);
455	AssertRC(rc);
456	}
457	*pu32 = pThis->regStatus;
458	parallelR3IrqClear(pThis);
459	#endif
460	break;
461	case 2:
462	#ifndef IN_RING3
463	rc = VINF_IOM_R3_IOPORT_READ;
464	#else
465	rc = pThis->pDrvHostParallelConnector->pfnReadControl(pThis->pDrvHostParallelConnector, &pThis->regControl);
466	AssertRC(rc);
467	pThis->regControl \|= LPT_CONTROL_BIT6 \| LPT_CONTROL_BIT7;
468	*pu32 = pThis->regControl;
469	#endif
470	break;
471	case 3:
472	#ifndef IN_RING3
473	rc = VINF_IOM_R3_IOPORT_READ;
474	#else
475	if (RT_LIKELY(pThis->pDrvHostParallelConnector))
476	{
477	rc = pThis->pDrvHostParallelConnector->pfnRead(pThis->pDrvHostParallelConnector, &pThis->regEppAddr,
478	1, PDM_PARALLEL_PORT_MODE_EPP_ADDR);
479	Log(("Read EPP address 0x%X\n", pThis->regEppAddr));
480	AssertRC(rc);
481	}
482	*pu32 = pThis->regEppAddr;
483	#endif
484	break;
485	case 4:
486	#ifndef IN_RING3
487	rc = VINF_IOM_R3_IOPORT_READ;
488	#else
489	if (RT_LIKELY(pThis->pDrvHostParallelConnector))
490	{
491	rc = pThis->pDrvHostParallelConnector->pfnRead(pThis->pDrvHostParallelConnector, &pThis->regEppData,
492	1, PDM_PARALLEL_PORT_MODE_EPP_DATA);
493	Log(("Read EPP data 0x%X\n", pThis->regEppData));
494	AssertRC(rc);
495	}
496	*pu32 = pThis->regEppData;
497	#endif
498	break;
499	case 5:
500	break;
501	case 6:
502	break;
503	case 7:
504	break;
505	}
506	}
507	else
508	rc = VERR_IOM_IOPORT_UNUSED;
509
510	return rc;
511	}
512
513	#if 0
514	/**
515	* @callback_method_impl{FNIOMIOPORTOUT, ECP registers.}
516	*/
517	PDMBOTHCBDECL(int) parallelIOPortWriteECP(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
518	{
519	PARALLELPORT pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT );
520	int rc = VINF_SUCCESS;
521
522	if (cb == 1)
523	{
524	Log2(("%s: ecp port %#06x val %#04x\n", __FUNCTION__, Port, u32));
525	rc = parallel_ioport_write_ecp (pThis, Port, u32);
526	}
527	else
528	AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
529
530	return rc;
531	}
532
533	/**
534	* @callback_method_impl{FNIOMIOPORTOUT, ECP registers.}
535	*/
536	PDMBOTHCBDECL(int) parallelIOPortReadECP(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
537	{
538	PARALLELPORT pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT );
539	int rc = VINF_SUCCESS;
540
541	if (cb == 1)
542	{
543	*pu32 = parallel_ioport_read_ecp (pThis, Port, &rc);
544	Log2(("%s: ecp port %#06x val %#04x\n", __FUNCTION__, Port, *pu32));
545	}
546	else
547	rc = VERR_IOM_IOPORT_UNUSED;
548
549	return rc;
550	}
551	#endif
552
553	#ifdef IN_RING3
554
555	/**
556	* @callback_method_impl{FNSSMDEVLIVEEXEC}
557	*/
558	static DECLCALLBACK(int) parallelR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
559	{
560	PARALLELPORT pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT );
561
562	SSMR3PutS32(pSSM, pThis->iIrq);
563	SSMR3PutU32(pSSM, pThis->IOBase);
564	SSMR3PutU32(pSSM, ~0); /* sanity/terminator */
565	return VINF_SSM_DONT_CALL_AGAIN;
566	}
567
568
569	/**
570	* @callback_method_impl{FNSSMDEVSAVEEXEC}
571	*/
572	static DECLCALLBACK(int) parallelR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
573	{
574	PARALLELPORT pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT );
575
576	SSMR3PutU8(pSSM, pThis->regData);
577	SSMR3PutU8(pSSM, pThis->regStatus);
578	SSMR3PutU8(pSSM, pThis->regControl);
579
580	parallelR3LiveExec(pDevIns, pSSM, 0);
581	return VINF_SUCCESS;
582	}
583
584
585	/**
586	* @callback_method_impl{FNSSMDEVLOADEXEC}
587	*/
588	static DECLCALLBACK(int) parallelR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
589	{
590	PARALLELPORT pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT );
591
592	AssertMsgReturn(uVersion == PARALLEL_SAVED_STATE_VERSION, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
593	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
594	if (uPass == SSM_PASS_FINAL)
595	{
596	SSMR3GetU8(pSSM, &pThis->regData);
597	SSMR3GetU8(pSSM, &pThis->regStatus);
598	SSMR3GetU8(pSSM, &pThis->regControl);
599	}
600
601	/* the config */
602	int32_t iIrq;
603	SSMR3GetS32(pSSM, &iIrq);
604	uint32_t uIoBase;
605	SSMR3GetU32(pSSM, &uIoBase);
606	uint32_t u32;
607	int rc = SSMR3GetU32(pSSM, &u32);
608	if (RT_FAILURE(rc))
609	return rc;
610	AssertMsgReturn(u32 == ~0U, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
611
612	if (pThis->iIrq != iIrq)
613	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("IRQ changed: config=%#x state=%#x"), pThis->iIrq, iIrq);
614
615	if (pThis->IOBase != uIoBase)
616	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("IOBase changed: config=%#x state=%#x"), pThis->IOBase, uIoBase);
617
618	/* not necessary... but it doesn't harm. */
619	pThis->pDevInsR3 = pDevIns;
620	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
621	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
622	return VINF_SUCCESS;
623	}
624
625
626	/**
627	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
628	*/
629	static DECLCALLBACK(void ) parallelR3QueryInterface(PPDMIBASE pInterface, const char pszIID)
630	{
631	PARALLELPORT *pThis = PDMIBASE_2_PARALLELPORT(pInterface);
632	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
633	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIHOSTPARALLELPORT, &pThis->IHostParallelPort);
634	return NULL;
635	}
636
637
638	/**
639	* @copydoc FNPDMDEVRELOCATE
640	*/
641	static DECLCALLBACK(void) parallelR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
642	{
643	PARALLELPORT pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT );
644	pThis->pDevInsRC += offDelta;
645	}
646
647
648	/**
649	* @interface_method_impl{PDMDEVREG,pfnConstruct}
650	*/
651	static DECLCALLBACK(int) parallelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
652	{
653	int rc;
654	PARALLELPORT pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT);
655
656	Assert(iInstance < 4);
657	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
658
659	/*
660	* Init the data.
661	*/
662	pThis->pDevInsR3 = pDevIns;
663	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
664	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
665
666	/* IBase */
667	pThis->IBase.pfnQueryInterface = parallelR3QueryInterface;
668
669	/* IHostParallelPort */
670	pThis->IHostParallelPort.pfnNotifyInterrupt = parallelR3NotifyInterrupt;
671
672	/* Init parallel state */
673	pThis->regData = 0;
674	#if 0 /* ECP implementation not complete. */
675	pThis->reg_ecp_ecr = LPT_ECP_ECR_CHIPMODE_COMPAT \| LPT_ECP_ECR_FIFO_EMPTY;
676	pThis->act_fifo_pos_read = 0;
677	pThis->act_fifo_pos_write = 0;
678	#endif
679
680	/*
681	* Validate and read the configuration.
682	*/
683	if (!CFGMR3AreValuesValid(pCfg, "IRQ\0" "IOBase\0" "GCEnabled\0" "R0Enabled\0"))
684	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
685	N_("Configuration error: Unknown config key"));
686
687	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fGCEnabled, false);
688	if (RT_FAILURE(rc))
689	return PDMDEV_SET_ERROR(pDevIns, rc,
690	N_("Configuration error: Failed to get the \"GCEnabled\" value"));
691
692	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, false);
693	if (RT_FAILURE(rc))
694	return PDMDEV_SET_ERROR(pDevIns, rc,
695	N_("Configuration error: Failed to get the \"R0Enabled\" value"));
696	rc = CFGMR3QueryS32Def(pCfg, "IRQ", &pThis->iIrq, 7);
697	if (RT_FAILURE(rc))
698	return PDMDEV_SET_ERROR(pDevIns, rc,
699	N_("Configuration error: Failed to get the \"IRQ\" value"));
700	rc = CFGMR3QueryU16Def(pCfg, "IOBase", &pThis->IOBase, 0x378);
701	if (RT_FAILURE(rc))
702	return PDMDEV_SET_ERROR(pDevIns, rc,
703	N_("Configuration error: Failed to get the \"IOBase\" value"));
704
705	/*
706	* Register the I/O ports and saved state.
707	*/
708	rc = PDMDevHlpIOPortRegister(pDevIns, pThis->IOBase, 8, 0,
709	parallelIOPortWrite, parallelIOPortRead,
710	NULL, NULL, "Parallel");
711	if (RT_FAILURE(rc))
712	return rc;
713
714	#if 0
715	/* register ecp registers */
716	rc = PDMDevHlpIOPortRegister(pDevIns, io_base+0x400, 8, 0,
717	parallelIOPortWriteECP, parallelIOPortReadECP,
718	NULL, NULL, "PARALLEL ECP");
719	if (RT_FAILURE(rc))
720	return rc;
721	#endif
722
723	if (pThis->fGCEnabled)
724	{
725	rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->IOBase, 8, 0, "parallelIOPortWrite",
726	"parallelIOPortRead", NULL, NULL, "Parallel");
727	if (RT_FAILURE(rc))
728	return rc;
729
730	#if 0
731	rc = PDMDevHlpIOPortRegisterGC(pDevIns, io_base+0x400, 8, 0, "parallelIOPortWriteECP",
732	"parallelIOPortReadECP", NULL, NULL, "Parallel Ecp");
733	if (RT_FAILURE(rc))
734	return rc;
735	#endif
736	}
737
738	if (pThis->fR0Enabled)
739	{
740	rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->IOBase, 8, 0, "parallelIOPortWrite",
741	"parallelIOPortRead", NULL, NULL, "Parallel");
742	if (RT_FAILURE(rc))
743	return rc;
744
745	#if 0
746	rc = PDMDevHlpIOPortRegisterR0(pDevIns, io_base+0x400, 8, 0, "parallelIOPortWriteECP",
747	"parallelIOPortReadECP", NULL, NULL, "Parallel Ecp");
748	if (RT_FAILURE(rc))
749	return rc;
750	#endif
751	}
752
753	rc = PDMDevHlpSSMRegister3(pDevIns, PARALLEL_SAVED_STATE_VERSION, sizeof(*pThis),
754	parallelR3LiveExec, parallelR3SaveExec, parallelR3LoadExec);
755	if (RT_FAILURE(rc))
756	return rc;
757
758
759	/*
760	* Attach the parallel port driver and get the interfaces.
761	* For now no run-time changes are supported.
762	*/
763	rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Parallel Host");
764	if (RT_SUCCESS(rc))
765	{
766	pThis->pDrvHostParallelConnector = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIHOSTPARALLELCONNECTOR);
767	AssertMsgReturn(pThis->pDrvHostParallelConnector,
768	("Configuration error: instance %d has no host parallel interface!\n", iInstance),
769	VERR_PDM_MISSING_INTERFACE);
770	}
771	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
772	{
773	pThis->pDrvBase = NULL;
774	pThis->pDrvHostParallelConnector = NULL;
775	LogRel(("Parallel%d: no unit\n", iInstance));
776	}
777	else
778	{
779	AssertMsgFailed(("Parallel%d: Failed to attach to host driver. rc=%Rrc\n", iInstance, rc));
780	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
781	N_("Parallel device %d cannot attach to host driver"), iInstance);
782	}
783
784	/* Set compatibility mode */
785	//pThis->pDrvHostParallelConnector->pfnSetMode(pThis->pDrvHostParallelConnector, PDM_PARALLEL_PORT_MODE_COMPAT);
786	/* Get status of control register */
787	pThis->pDrvHostParallelConnector->pfnReadControl(pThis->pDrvHostParallelConnector, &pThis->regControl);
788
789	return VINF_SUCCESS;
790	}
791
792	/**
793	* The device registration structure.
794	*/
795	const PDMDEVREG g_DeviceParallelPort =
796	{
797	/* u32Version */
798	PDM_DEVREG_VERSION,
799	/* szName */
800	"parallel",
801	/* szRCMod */
802	"VBoxDDGC.gc",
803	/* szR0Mod */
804	"VBoxDDR0.r0",
805	/* pszDescription */
806	"Parallel Communication Port",
807	/* fFlags */
808	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
809	/* fClass */
810	PDM_DEVREG_CLASS_PARALLEL,
811	/* cMaxInstances */
812	1,
813	/* cbInstance */
814	sizeof(PARALLELPORT),
815	/* pfnConstruct */
816	parallelR3Construct,
817	/* pfnDestruct */
818	NULL,
819	/* pfnRelocate */
820	parallelR3Relocate,
821	/* pfnMemSetup */
822	NULL,
823	/* pfnPowerOn */
824	NULL,
825	/* pfnReset */
826	NULL,
827	/* pfnSuspend */
828	NULL,
829	/* pfnResume */
830	NULL,
831	/* pfnAttach */
832	NULL,
833	/* pfnDetach */
834	NULL,
835	/* pfnQueryInterface. */
836	NULL,
837	/* pfnInitComplete */
838	NULL,
839	/* pfnPowerOff */
840	NULL,
841	/* pfnSoftReset */
842	NULL,
843	/* u32VersionEnd */
844	PDM_DEVREG_VERSION
845	};
846	#endif /* IN_RING3 */
847
848
849	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Parallel/DevParallel.cpp@ 48107

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