DevParallel.cpp@ 57925

Last change on this file since 57925 was 57358, checked in by vboxsync, 10 years ago
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1	/* $Id: DevParallel.cpp 57358 2015-08-14 15:16:38Z vboxsync $ */
2	/** @file
3	* DevParallel - Parallel (Port) Device Emulation.
4	*
5	* Contributed by: Alexander Eichner
6	* Based on DevSerial.cpp
7	*/
8
9	/*
10	* Copyright (C) 2006-2015 Oracle Corporation
11	*
12	* This file is part of VirtualBox Open Source Edition (OSE), as
13	* available from http://www.virtualbox.org. This file is free software;
14	* you can redistribute it and/or modify it under the terms of the GNU
15	* General Public License (GPL) as published by the Free Software
16	* Foundation, in version 2 as it comes in the "COPYING" file of the
17	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19	*/
20
21
22	/*********************************************************************************************************************************
23	* Header Files *
24	*********************************************************************************************************************************/
25	#define LOG_GROUP LOG_GROUP_DEV_PARALLEL
26	#include <VBox/vmm/pdmdev.h>
27	#include <iprt/assert.h>
28	#include <iprt/uuid.h>
29	#include <iprt/string.h>
30	#include <iprt/semaphore.h>
31
32	#include "VBoxDD.h"
33
34
35	/*********************************************************************************************************************************
36	* Defined Constants And Macros *
37	*********************************************************************************************************************************/
38	#define PARALLEL_SAVED_STATE_VERSION 1
39
40	/* defines for accessing the register bits */
41	#define LPT_STATUS_BUSY 0x80
42	#define LPT_STATUS_ACK 0x40
43	#define LPT_STATUS_PAPER_OUT 0x20
44	#define LPT_STATUS_SELECT_IN 0x10
45	#define LPT_STATUS_ERROR 0x08
46	#define LPT_STATUS_IRQ 0x04
47	#define LPT_STATUS_BIT1 0x02 /* reserved (only for completeness) */
48	#define LPT_STATUS_EPP_TIMEOUT 0x01
49
50	#define LPT_CONTROL_BIT7 0x80 /* reserved (only for completeness) */
51	#define LPT_CONTROL_BIT6 0x40 /* reserved (only for completeness) */
52	#define LPT_CONTROL_ENABLE_BIDIRECT 0x20
53	#define LPT_CONTROL_ENABLE_IRQ_VIA_ACK 0x10
54	#define LPT_CONTROL_SELECT_PRINTER 0x08
55	#define LPT_CONTROL_RESET 0x04
56	#define LPT_CONTROL_AUTO_LINEFEED 0x02
57	#define LPT_CONTROL_STROBE 0x01
58
59	/** mode defines for the extended control register */
60	#define LPT_ECP_ECR_CHIPMODE_MASK 0xe0
61	#define LPT_ECP_ECR_CHIPMODE_GET_BITS(reg) ((reg) >> 5)
62	#define LPT_ECP_ECR_CHIPMODE_SET_BITS(val) ((val) << 5)
63	#define LPT_ECP_ECR_CHIPMODE_CONFIGURATION 0x07
64	#define LPT_ECP_ECR_CHIPMODE_FIFO_TEST 0x06
65	#define LPT_ECP_ECR_CHIPMODE_RESERVED 0x05
66	#define LPT_ECP_ECR_CHIPMODE_EPP 0x04
67	#define LPT_ECP_ECR_CHIPMODE_ECP_FIFO 0x03
68	#define LPT_ECP_ECR_CHIPMODE_PP_FIFO 0x02
69	#define LPT_ECP_ECR_CHIPMODE_BYTE 0x01
70	#define LPT_ECP_ECR_CHIPMODE_COMPAT 0x00
71
72	/** FIFO status bits in extended control register */
73	#define LPT_ECP_ECR_FIFO_MASK 0x03
74	#define LPT_ECP_ECR_FIFO_SOME_DATA 0x00
75	#define LPT_ECP_ECR_FIFO_FULL 0x02
76	#define LPT_ECP_ECR_FIFO_EMPTY 0x01
77
78	#define LPT_ECP_CONFIGA_FIFO_WITDH_MASK 0x70
79	#define LPT_ECP_CONFIGA_FIFO_WIDTH_GET_BITS(reg) ((reg) >> 4)
80	#define LPT_ECP_CONFIGA_FIFO_WIDTH_SET_BITS(val) ((val) << 4)
81	#define LPT_ECP_CONFIGA_FIFO_WIDTH_16 0x00
82	#define LPT_ECP_CONFIGA_FIFO_WIDTH_32 0x20
83	#define LPT_ECP_CONFIGA_FIFO_WIDTH_8 0x10
84
85	#define LPT_ECP_FIFO_DEPTH 2
86
87
88	/*********************************************************************************************************************************
89	* Structures and Typedefs *
90	*********************************************************************************************************************************/
91	/**
92	* Parallel device state.
93	*
94	* @implements PDMIBASE
95	* @implements PDMIHOSTPARALLELPORT
96	*/
97	typedef struct PARALLELPORT
98	{
99	/** Pointer to the device instance - R3 Ptr */
100	PPDMDEVINSR3 pDevInsR3;
101	/** Pointer to the device instance - R0 Ptr */
102	PPDMDEVINSR0 pDevInsR0;
103	/** Pointer to the device instance - RC Ptr */
104	PPDMDEVINSRC pDevInsRC;
105	/** Alignment. */
106	RTRCPTR Alignment0;
107	/** LUN\#0: The base interface. */
108	PDMIBASE IBase;
109	/** LUN\#0: The host device port interface. */
110	PDMIHOSTPARALLELPORT IHostParallelPort;
111	/** Pointer to the attached base driver. */
112	R3PTRTYPE(PPDMIBASE) pDrvBase;
113	/** Pointer to the attached host device. */
114	R3PTRTYPE(PPDMIHOSTPARALLELCONNECTOR) pDrvHostParallelConnector;
115	/** Flag whether the device has its RC component enabled. */
116	bool fGCEnabled;
117	/** Flag whether the device has its R0 component enabled. */
118	bool fR0Enabled;
119	/** Flag whether an EPP timeout occurred (error handling). */
120	bool fEppTimeout;
121	/** Base I/O port of the parallel port. */
122	RTIOPORT IOBase;
123	/** IRQ number assigned ot the parallel port. */
124	int iIrq;
125	/** Data register. */
126	uint8_t regData;
127	/** Status register. */
128	uint8_t regStatus;
129	/** Control register. */
130	uint8_t regControl;
131	/** EPP address register. */
132	uint8_t regEppAddr;
133	/** EPP data register. */
134	uint8_t regEppData;
135	/** More alignment. */
136	uint32_t u32Alignment;
137
138	#if 0 /* Data for ECP implementation, currently unused. */
139	uint8_t reg_ecp_ecr;
140	uint8_t reg_ecp_base_plus_400h; /* has different meanings */
141	uint8_t reg_ecp_config_b;
142
143	/** The ECP FIFO implementation*/
144	uint8_t ecp_fifo[LPT_ECP_FIFO_DEPTH];
145	uint8_t abAlignemnt[2];
146	int act_fifo_pos_write;
147	int act_fifo_pos_read;
148	#endif
149	} PARALLELPORT, *PPARALLELPORT;
150
151	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
152
153	#define PDMIHOSTPARALLELPORT_2_PARALLELPORT(pInstance) ( (PARALLELPORT *)((uintptr_t)(pInterface) - RT_OFFSETOF(PARALLELPORT, IHostParallelPort)) )
154	#define PDMIHOSTDEVICEPORT_2_PARALLELPORT(pInstance) ( (PARALLELPORT *)((uintptr_t)(pInterface) - RT_OFFSETOF(PARALLELPORT, IHostDevicePort)) )
155	#define PDMIBASE_2_PARALLELPORT(pInstance) ( (PARALLELPORT *)((uintptr_t)(pInterface) - RT_OFFSETOF(PARALLELPORT, IBase)) )
156
157
158	/*********************************************************************************************************************************
159	* Internal Functions *
160	*********************************************************************************************************************************/
161	RT_C_DECLS_BEGIN
162	PDMBOTHCBDECL(int) parallelIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
163	PDMBOTHCBDECL(int) parallelIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
164	#if 0
165	PDMBOTHCBDECL(int) parallelIOPortReadECP(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
166	PDMBOTHCBDECL(int) parallelIOPortWriteECP(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
167	#endif
168	RT_C_DECLS_END
169
170
171	#ifdef IN_RING3
172	static void parallelR3IrqSet(PARALLELPORT *pThis)
173	{
174	if (pThis->regControl & LPT_CONTROL_ENABLE_IRQ_VIA_ACK)
175	{
176	LogFlowFunc(("%d 1\n", pThis->iIrq));
177	PDMDevHlpISASetIrqNoWait(pThis->CTX_SUFF(pDevIns), pThis->iIrq, 1);
178	}
179	}
180
181	static void parallelR3IrqClear(PARALLELPORT *pThis)
182	{
183	LogFlowFunc(("%d 0\n", pThis->iIrq));
184	PDMDevHlpISASetIrqNoWait(pThis->CTX_SUFF(pDevIns), pThis->iIrq, 0);
185	}
186	#endif
187
188	#if 0
189	static int parallel_ioport_write_ecp(void *opaque, uint32_t addr, uint32_t val)
190	{
191	PARALLELPORT s = (PARALLELPORT )opaque;
192	unsigned char ch;
193
194	addr &= 7;
195	LogFlow(("parallel: write ecp addr=0x%02x val=0x%02x\n", addr, val));
196	ch = val;
197	switch (addr) {
198	default:
199	case 0:
200	if (LPT_ECP_ECR_CHIPMODE_GET_BITS(s->reg_ecp_ecr) == LPT_ECP_ECR_CHIPMODE_FIFO_TEST) {
201	s->ecp_fifo[s->act_fifo_pos_write] = ch;
202	s->act_fifo_pos_write++;
203	if (s->act_fifo_pos_write < LPT_ECP_FIFO_DEPTH) {
204	/* FIFO has some data (clear both FIFO bits) */
205	s->reg_ecp_ecr &= ~(LPT_ECP_ECR_FIFO_EMPTY \| LPT_ECP_ECR_FIFO_FULL);
206	} else {
207	/* FIFO is full */
208	/* Clear FIFO empty bit */
209	s->reg_ecp_ecr &= ~LPT_ECP_ECR_FIFO_EMPTY;
210	/* Set FIFO full bit */
211	s->reg_ecp_ecr \|= LPT_ECP_ECR_FIFO_FULL;
212	s->act_fifo_pos_write = 0;
213	}
214	} else {
215	s->reg_ecp_base_plus_400h = ch;
216	}
217	break;
218	case 1:
219	s->reg_ecp_config_b = ch;
220	break;
221	case 2:
222	/* If we change the mode clear FIFO */
223	if ((ch & LPT_ECP_ECR_CHIPMODE_MASK) != (s->reg_ecp_ecr & LPT_ECP_ECR_CHIPMODE_MASK)) {
224	/* reset the fifo */
225	s->act_fifo_pos_write = 0;
226	s->act_fifo_pos_read = 0;
227	/* Set FIFO empty bit */
228	s->reg_ecp_ecr \|= LPT_ECP_ECR_FIFO_EMPTY;
229	/* Clear FIFO full bit */
230	s->reg_ecp_ecr &= ~LPT_ECP_ECR_FIFO_FULL;
231	}
232	/* Set new mode */
233	s->reg_ecp_ecr \|= LPT_ECP_ECR_CHIPMODE_SET_BITS(LPT_ECP_ECR_CHIPMODE_GET_BITS(ch));
234	break;
235	case 3:
236	break;
237	case 4:
238	break;
239	case 5:
240	break;
241	case 6:
242	break;
243	case 7:
244	break;
245	}
246	return VINF_SUCCESS;
247	}
248
249	static uint32_t parallel_ioport_read_ecp(void opaque, uint32_t addr, int pRC)
250	{
251	PARALLELPORT s = (PARALLELPORT )opaque;
252	uint32_t ret = ~0U;
253
254	*pRC = VINF_SUCCESS;
255
256	addr &= 7;
257	switch (addr) {
258	default:
259	case 0:
260	if (LPT_ECP_ECR_CHIPMODE_GET_BITS(s->reg_ecp_ecr) == LPT_ECP_ECR_CHIPMODE_FIFO_TEST) {
261	ret = s->ecp_fifo[s->act_fifo_pos_read];
262	s->act_fifo_pos_read++;
263	if (s->act_fifo_pos_read == LPT_ECP_FIFO_DEPTH)
264	s->act_fifo_pos_read = 0; /* end of FIFO, start at beginning */
265	if (s->act_fifo_pos_read == s->act_fifo_pos_write) {
266	/* FIFO is empty */
267	/* Set FIFO empty bit */
268	s->reg_ecp_ecr \|= LPT_ECP_ECR_FIFO_EMPTY;
269	/* Clear FIFO full bit */
270	s->reg_ecp_ecr &= ~LPT_ECP_ECR_FIFO_FULL;
271	} else {
272	/* FIFO has some data (clear all FIFO bits) */
273	s->reg_ecp_ecr &= ~(LPT_ECP_ECR_FIFO_EMPTY \| LPT_ECP_ECR_FIFO_FULL);
274	}
275	} else {
276	ret = s->reg_ecp_base_plus_400h;
277	}
278	break;
279	case 1:
280	ret = s->reg_ecp_config_b;
281	break;
282	case 2:
283	ret = s->reg_ecp_ecr;
284	break;
285	case 3:
286	break;
287	case 4:
288	break;
289	case 5:
290	break;
291	case 6:
292	break;
293	case 7:
294	break;
295	}
296	LogFlow(("parallel: read ecp addr=0x%02x val=0x%02x\n", addr, ret));
297	return ret;
298	}
299	#endif
300
301	#ifdef IN_RING3
302	/**
303	* @interface_methods_impl{PDMIHOSTPARALLELPORT,pfnNotifyInterrupt}
304	*/
305	static DECLCALLBACK(int) parallelR3NotifyInterrupt(PPDMIHOSTPARALLELPORT pInterface)
306	{
307	PARALLELPORT *pThis = PDMIHOSTPARALLELPORT_2_PARALLELPORT(pInterface);
308
309	PDMCritSectEnter(pThis->pDevInsR3->pCritSectRoR3, VINF_SUCCESS);
310	parallelR3IrqSet(pThis);
311	PDMCritSectLeave(pThis->pDevInsR3->pCritSectRoR3);
312
313	return VINF_SUCCESS;
314	}
315	#endif /* IN_RING3 */
316
317
318	/**
319	* @callback_method_impl{FNIOMIOPORTOUT}
320	*/
321	PDMBOTHCBDECL(int) parallelIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
322	{
323	PARALLELPORT *pThis = PDMINS_2_DATA(pDevIns, PPARALLELPORT);
324	int rc = VINF_SUCCESS;
325
326	if (cb == 1)
327	{
328	uint8_t u8 = u32;
329
330	Log2(("%s: port %#06x val %#04x\n", __FUNCTION__, Port, u32));
331
332	Port &= 7;
333	switch (Port)
334	{
335	case 0:
336	#ifndef IN_RING3
337	NOREF(u8);
338	rc = VINF_IOM_R3_IOPORT_WRITE;
339	#else
340	pThis->regData = u8;
341	if (RT_LIKELY(pThis->pDrvHostParallelConnector))
342	{
343	LogFlowFunc(("Set data lines 0x%X\n", u8));
344	rc = pThis->pDrvHostParallelConnector->pfnWrite(pThis->pDrvHostParallelConnector, &u8, 1, PDM_PARALLEL_PORT_MODE_SPP);
345	AssertRC(rc);
346	}
347	#endif
348	break;
349	case 1:
350	break;
351	case 2:
352	/* Set the reserved bits to one */
353	u8 \|= (LPT_CONTROL_BIT6 \| LPT_CONTROL_BIT7);
354	if (u8 != pThis->regControl)
355	{
356	#ifndef IN_RING3
357	return VINF_IOM_R3_IOPORT_WRITE;
358	#else
359	/* Set data direction. */
360	if (u8 & LPT_CONTROL_ENABLE_BIDIRECT)
361	rc = pThis->pDrvHostParallelConnector->pfnSetPortDirection(pThis->pDrvHostParallelConnector, false /* fForward */);
362	else
363	rc = pThis->pDrvHostParallelConnector->pfnSetPortDirection(pThis->pDrvHostParallelConnector, true /* fForward */);
364	AssertRC(rc);
365	u8 &= ~LPT_CONTROL_ENABLE_BIDIRECT; /* Clear bit. */
366
367	rc = pThis->pDrvHostParallelConnector->pfnWriteControl(pThis->pDrvHostParallelConnector, u8);
368	AssertRC(rc);
369	pThis->regControl = u8;
370	#endif
371	}
372	break;
373	case 3:
374	#ifndef IN_RING3
375	NOREF(u8);
376	rc = VINF_IOM_R3_IOPORT_WRITE;
377	#else
378	pThis->regEppAddr = u8;
379	if (RT_LIKELY(pThis->pDrvHostParallelConnector))
380	{
381	LogFlowFunc(("Write EPP address 0x%X\n", u8));
382	rc = pThis->pDrvHostParallelConnector->pfnWrite(pThis->pDrvHostParallelConnector, &u8, 1, PDM_PARALLEL_PORT_MODE_EPP_ADDR);
383	AssertRC(rc);
384	}
385	#endif
386	break;
387	case 4:
388	#ifndef IN_RING3
389	NOREF(u8);
390	rc = VINF_IOM_R3_IOPORT_WRITE;
391	#else
392	pThis->regEppData = u8;
393	if (RT_LIKELY(pThis->pDrvHostParallelConnector))
394	{
395	LogFlowFunc(("Write EPP data 0x%X\n", u8));
396	rc = pThis->pDrvHostParallelConnector->pfnWrite(pThis->pDrvHostParallelConnector, &u8, 1, PDM_PARALLEL_PORT_MODE_EPP_DATA);
397	AssertRC(rc);
398	}
399	#endif
400	break;
401	case 5:
402	break;
403	case 6:
404	break;
405	case 7:
406	default:
407	break;
408	}
409	}
410	else
411	AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
412
413	return rc;
414	}
415
416
417	/**
418	* @callback_method_impl{FNIOMIOPORTIN}
419	*/
420	PDMBOTHCBDECL(int) parallelIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
421	{
422	PARALLELPORT pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT );
423	int rc = VINF_SUCCESS;
424
425	if (cb == 1)
426	{
427	Port &= 7;
428	switch (Port)
429	{
430	case 0:
431	if (!(pThis->regControl & LPT_CONTROL_ENABLE_BIDIRECT))
432	*pu32 = pThis->regData;
433	else
434	{
435	#ifndef IN_RING3
436	rc = VINF_IOM_R3_IOPORT_READ;
437	#else
438	if (RT_LIKELY(pThis->pDrvHostParallelConnector))
439	{
440	rc = pThis->pDrvHostParallelConnector->pfnRead(pThis->pDrvHostParallelConnector, &pThis->regData,
441	1, PDM_PARALLEL_PORT_MODE_SPP);
442	Log(("Read data lines 0x%X\n", pThis->regData));
443	AssertRC(rc);
444	}
445	*pu32 = pThis->regData;
446	#endif
447	}
448	break;
449	case 1:
450	#ifndef IN_RING3
451	rc = VINF_IOM_R3_IOPORT_READ;
452	#else
453	if (RT_LIKELY(pThis->pDrvHostParallelConnector))
454	{
455	rc = pThis->pDrvHostParallelConnector->pfnReadStatus(pThis->pDrvHostParallelConnector, &pThis->regStatus);
456	AssertRC(rc);
457	}
458	*pu32 = pThis->regStatus;
459	parallelR3IrqClear(pThis);
460	#endif
461	break;
462	case 2:
463	#ifndef IN_RING3
464	rc = VINF_IOM_R3_IOPORT_READ;
465	#else
466	rc = pThis->pDrvHostParallelConnector->pfnReadControl(pThis->pDrvHostParallelConnector, &pThis->regControl);
467	AssertRC(rc);
468	pThis->regControl \|= LPT_CONTROL_BIT6 \| LPT_CONTROL_BIT7;
469	*pu32 = pThis->regControl;
470	#endif
471	break;
472	case 3:
473	#ifndef IN_RING3
474	rc = VINF_IOM_R3_IOPORT_READ;
475	#else
476	if (RT_LIKELY(pThis->pDrvHostParallelConnector))
477	{
478	rc = pThis->pDrvHostParallelConnector->pfnRead(pThis->pDrvHostParallelConnector, &pThis->regEppAddr,
479	1, PDM_PARALLEL_PORT_MODE_EPP_ADDR);
480	Log(("Read EPP address 0x%X\n", pThis->regEppAddr));
481	AssertRC(rc);
482	}
483	*pu32 = pThis->regEppAddr;
484	#endif
485	break;
486	case 4:
487	#ifndef IN_RING3
488	rc = VINF_IOM_R3_IOPORT_READ;
489	#else
490	if (RT_LIKELY(pThis->pDrvHostParallelConnector))
491	{
492	rc = pThis->pDrvHostParallelConnector->pfnRead(pThis->pDrvHostParallelConnector, &pThis->regEppData,
493	1, PDM_PARALLEL_PORT_MODE_EPP_DATA);
494	Log(("Read EPP data 0x%X\n", pThis->regEppData));
495	AssertRC(rc);
496	}
497	*pu32 = pThis->regEppData;
498	#endif
499	break;
500	case 5:
501	break;
502	case 6:
503	break;
504	case 7:
505	break;
506	}
507	}
508	else
509	rc = VERR_IOM_IOPORT_UNUSED;
510
511	return rc;
512	}
513
514	#if 0
515	/**
516	* @callback_method_impl{FNIOMIOPORTOUT, ECP registers.}
517	*/
518	PDMBOTHCBDECL(int) parallelIOPortWriteECP(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
519	{
520	PARALLELPORT pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT );
521	int rc = VINF_SUCCESS;
522
523	if (cb == 1)
524	{
525	Log2(("%s: ecp port %#06x val %#04x\n", __FUNCTION__, Port, u32));
526	rc = parallel_ioport_write_ecp (pThis, Port, u32);
527	}
528	else
529	AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
530
531	return rc;
532	}
533
534	/**
535	* @callback_method_impl{FNIOMIOPORTOUT, ECP registers.}
536	*/
537	PDMBOTHCBDECL(int) parallelIOPortReadECP(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
538	{
539	PARALLELPORT pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT );
540	int rc = VINF_SUCCESS;
541
542	if (cb == 1)
543	{
544	*pu32 = parallel_ioport_read_ecp (pThis, Port, &rc);
545	Log2(("%s: ecp port %#06x val %#04x\n", __FUNCTION__, Port, *pu32));
546	}
547	else
548	rc = VERR_IOM_IOPORT_UNUSED;
549
550	return rc;
551	}
552	#endif
553
554	#ifdef IN_RING3
555
556	/**
557	* @callback_method_impl{FNSSMDEVLIVEEXEC}
558	*/
559	static DECLCALLBACK(int) parallelR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
560	{
561	PARALLELPORT pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT );
562
563	SSMR3PutS32(pSSM, pThis->iIrq);
564	SSMR3PutU32(pSSM, pThis->IOBase);
565	SSMR3PutU32(pSSM, ~0); /* sanity/terminator */
566	return VINF_SSM_DONT_CALL_AGAIN;
567	}
568
569
570	/**
571	* @callback_method_impl{FNSSMDEVSAVEEXEC}
572	*/
573	static DECLCALLBACK(int) parallelR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
574	{
575	PARALLELPORT pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT );
576
577	SSMR3PutU8(pSSM, pThis->regData);
578	SSMR3PutU8(pSSM, pThis->regStatus);
579	SSMR3PutU8(pSSM, pThis->regControl);
580
581	parallelR3LiveExec(pDevIns, pSSM, 0);
582	return VINF_SUCCESS;
583	}
584
585
586	/**
587	* @callback_method_impl{FNSSMDEVLOADEXEC}
588	*/
589	static DECLCALLBACK(int) parallelR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
590	{
591	PARALLELPORT pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT );
592
593	AssertMsgReturn(uVersion == PARALLEL_SAVED_STATE_VERSION, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
594	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
595	if (uPass == SSM_PASS_FINAL)
596	{
597	SSMR3GetU8(pSSM, &pThis->regData);
598	SSMR3GetU8(pSSM, &pThis->regStatus);
599	SSMR3GetU8(pSSM, &pThis->regControl);
600	}
601
602	/* the config */
603	int32_t iIrq;
604	SSMR3GetS32(pSSM, &iIrq);
605	uint32_t uIoBase;
606	SSMR3GetU32(pSSM, &uIoBase);
607	uint32_t u32;
608	int rc = SSMR3GetU32(pSSM, &u32);
609	if (RT_FAILURE(rc))
610	return rc;
611	AssertMsgReturn(u32 == ~0U, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
612
613	if (pThis->iIrq != iIrq)
614	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("IRQ changed: config=%#x state=%#x"), pThis->iIrq, iIrq);
615
616	if (pThis->IOBase != uIoBase)
617	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("IOBase changed: config=%#x state=%#x"), pThis->IOBase, uIoBase);
618
619	/* not necessary... but it doesn't harm. */
620	pThis->pDevInsR3 = pDevIns;
621	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
622	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
623	return VINF_SUCCESS;
624	}
625
626
627	/**
628	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
629	*/
630	static DECLCALLBACK(void ) parallelR3QueryInterface(PPDMIBASE pInterface, const char pszIID)
631	{
632	PARALLELPORT *pThis = PDMIBASE_2_PARALLELPORT(pInterface);
633	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
634	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIHOSTPARALLELPORT, &pThis->IHostParallelPort);
635	return NULL;
636	}
637
638
639	/**
640	* @copydoc FNPDMDEVRELOCATE
641	*/
642	static DECLCALLBACK(void) parallelR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
643	{
644	PARALLELPORT pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT );
645	pThis->pDevInsRC += offDelta;
646	}
647
648
649	/**
650	* @interface_method_impl{PDMDEVREG,pfnConstruct}
651	*/
652	static DECLCALLBACK(int) parallelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
653	{
654	int rc;
655	PARALLELPORT pThis = PDMINS_2_DATA(pDevIns, PARALLELPORT);
656
657	Assert(iInstance < 4);
658	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
659
660	/*
661	* Init the data.
662	*/
663	pThis->pDevInsR3 = pDevIns;
664	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
665	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
666
667	/* IBase */
668	pThis->IBase.pfnQueryInterface = parallelR3QueryInterface;
669
670	/* IHostParallelPort */
671	pThis->IHostParallelPort.pfnNotifyInterrupt = parallelR3NotifyInterrupt;
672
673	/* Init parallel state */
674	pThis->regData = 0;
675	#if 0 /* ECP implementation not complete. */
676	pThis->reg_ecp_ecr = LPT_ECP_ECR_CHIPMODE_COMPAT \| LPT_ECP_ECR_FIFO_EMPTY;
677	pThis->act_fifo_pos_read = 0;
678	pThis->act_fifo_pos_write = 0;
679	#endif
680
681	/*
682	* Validate and read the configuration.
683	*/
684	if (!CFGMR3AreValuesValid(pCfg, "IRQ\0" "IOBase\0" "GCEnabled\0" "R0Enabled\0"))
685	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
686	N_("Configuration error: Unknown config key"));
687
688	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fGCEnabled, false);
689	if (RT_FAILURE(rc))
690	return PDMDEV_SET_ERROR(pDevIns, rc,
691	N_("Configuration error: Failed to get the \"GCEnabled\" value"));
692
693	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, false);
694	if (RT_FAILURE(rc))
695	return PDMDEV_SET_ERROR(pDevIns, rc,
696	N_("Configuration error: Failed to get the \"R0Enabled\" value"));
697	rc = CFGMR3QueryS32Def(pCfg, "IRQ", &pThis->iIrq, 7);
698	if (RT_FAILURE(rc))
699	return PDMDEV_SET_ERROR(pDevIns, rc,
700	N_("Configuration error: Failed to get the \"IRQ\" value"));
701	rc = CFGMR3QueryU16Def(pCfg, "IOBase", &pThis->IOBase, 0x378);
702	if (RT_FAILURE(rc))
703	return PDMDEV_SET_ERROR(pDevIns, rc,
704	N_("Configuration error: Failed to get the \"IOBase\" value"));
705
706	/*
707	* Register the I/O ports and saved state.
708	*/
709	rc = PDMDevHlpIOPortRegister(pDevIns, pThis->IOBase, 8, 0,
710	parallelIOPortWrite, parallelIOPortRead,
711	NULL, NULL, "Parallel");
712	if (RT_FAILURE(rc))
713	return rc;
714
715	#if 0
716	/* register ecp registers */
717	rc = PDMDevHlpIOPortRegister(pDevIns, io_base+0x400, 8, 0,
718	parallelIOPortWriteECP, parallelIOPortReadECP,
719	NULL, NULL, "PARALLEL ECP");
720	if (RT_FAILURE(rc))
721	return rc;
722	#endif
723
724	if (pThis->fGCEnabled)
725	{
726	rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->IOBase, 8, 0, "parallelIOPortWrite",
727	"parallelIOPortRead", NULL, NULL, "Parallel");
728	if (RT_FAILURE(rc))
729	return rc;
730
731	#if 0
732	rc = PDMDevHlpIOPortRegisterGC(pDevIns, io_base+0x400, 8, 0, "parallelIOPortWriteECP",
733	"parallelIOPortReadECP", NULL, NULL, "Parallel Ecp");
734	if (RT_FAILURE(rc))
735	return rc;
736	#endif
737	}
738
739	if (pThis->fR0Enabled)
740	{
741	rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->IOBase, 8, 0, "parallelIOPortWrite",
742	"parallelIOPortRead", NULL, NULL, "Parallel");
743	if (RT_FAILURE(rc))
744	return rc;
745
746	#if 0
747	rc = PDMDevHlpIOPortRegisterR0(pDevIns, io_base+0x400, 8, 0, "parallelIOPortWriteECP",
748	"parallelIOPortReadECP", NULL, NULL, "Parallel Ecp");
749	if (RT_FAILURE(rc))
750	return rc;
751	#endif
752	}
753
754	rc = PDMDevHlpSSMRegister3(pDevIns, PARALLEL_SAVED_STATE_VERSION, sizeof(*pThis),
755	parallelR3LiveExec, parallelR3SaveExec, parallelR3LoadExec);
756	if (RT_FAILURE(rc))
757	return rc;
758
759
760	/*
761	* Attach the parallel port driver and get the interfaces.
762	* For now no run-time changes are supported.
763	*/
764	rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Parallel Host");
765	if (RT_SUCCESS(rc))
766	{
767	pThis->pDrvHostParallelConnector = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIHOSTPARALLELCONNECTOR);
768	AssertMsgReturn(pThis->pDrvHostParallelConnector,
769	("Configuration error: instance %d has no host parallel interface!\n", iInstance),
770	VERR_PDM_MISSING_INTERFACE);
771	}
772	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
773	{
774	pThis->pDrvBase = NULL;
775	pThis->pDrvHostParallelConnector = NULL;
776	LogRel(("Parallel%d: no unit\n", iInstance));
777	}
778	else
779	{
780	AssertMsgFailed(("Parallel%d: Failed to attach to host driver. rc=%Rrc\n", iInstance, rc));
781	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
782	N_("Parallel device %d cannot attach to host driver"), iInstance);
783	}
784
785	/* Set compatibility mode */
786	//pThis->pDrvHostParallelConnector->pfnSetMode(pThis->pDrvHostParallelConnector, PDM_PARALLEL_PORT_MODE_COMPAT);
787	/* Get status of control register */
788	pThis->pDrvHostParallelConnector->pfnReadControl(pThis->pDrvHostParallelConnector, &pThis->regControl);
789
790	return VINF_SUCCESS;
791	}
792
793	/**
794	* The device registration structure.
795	*/
796	const PDMDEVREG g_DeviceParallelPort =
797	{
798	/* u32Version */
799	PDM_DEVREG_VERSION,
800	/* szName */
801	"parallel",
802	/* szRCMod */
803	"VBoxDDRC.rc",
804	/* szR0Mod */
805	"VBoxDDR0.r0",
806	/* pszDescription */
807	"Parallel Communication Port",
808	/* fFlags */
809	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
810	/* fClass */
811	PDM_DEVREG_CLASS_PARALLEL,
812	/* cMaxInstances */
813	1,
814	/* cbInstance */
815	sizeof(PARALLELPORT),
816	/* pfnConstruct */
817	parallelR3Construct,
818	/* pfnDestruct */
819	NULL,
820	/* pfnRelocate */
821	parallelR3Relocate,
822	/* pfnMemSetup */
823	NULL,
824	/* pfnPowerOn */
825	NULL,
826	/* pfnReset */
827	NULL,
828	/* pfnSuspend */
829	NULL,
830	/* pfnResume */
831	NULL,
832	/* pfnAttach */
833	NULL,
834	/* pfnDetach */
835	NULL,
836	/* pfnQueryInterface. */
837	NULL,
838	/* pfnInitComplete */
839	NULL,
840	/* pfnPowerOff */
841	NULL,
842	/* pfnSoftReset */
843	NULL,
844	/* u32VersionEnd */
845	PDM_DEVREG_VERSION
846	};
847	#endif /* IN_RING3 */
848
849
850	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Parallel/DevParallel.cpp@ 57925

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