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source: vbox/trunk/src/VBox/Devices/PC/Etherboot-src/drivers/net/forcedeth.c@ 895

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1/**************************************************************************
2* forcedeth.c -- Etherboot device driver for the NVIDIA nForce
3* media access controllers.
4*
5* Note: This driver is based on the Linux driver that was based on
6* a cleanroom reimplementation which was based on reverse
7* engineered documentation written by Carl-Daniel Hailfinger
8* and Andrew de Quincey. It's neither supported nor endorsed
9* by NVIDIA Corp. Use at your own risk.
10*
11* Written 2004 by Timothy Legge <tlegge@rogers.com>
12*
13* This program is free software; you can redistribute it and/or modify
14* it under the terms of the GNU General Public License as published by
15* the Free Software Foundation; either version 2 of the License, or
16* (at your option) any later version.
17*
18* This program is distributed in the hope that it will be useful,
19* but WITHOUT ANY WARRANTY; without even the implied warranty of
20* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21* GNU General Public License for more details.
22*
23* You should have received a copy of the GNU General Public License
24* along with this program; if not, write to the Free Software
25* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26*
27* Portions of this code based on:
28* forcedeth: Ethernet driver for NVIDIA nForce media access controllers:
29*
30* (C) 2003 Manfred Spraul
31* See Linux Driver for full information
32*
33* Linux Driver Version 0.30, 25 Sep 2004
34* Linux Kernel 2.6.10
35*
36*
37* REVISION HISTORY:
38* ================
39* v1.0 01-31-2004 timlegge Initial port of Linux driver
40* v1.1 02-03-2004 timlegge Large Clean up, first release
41* v1.2 05-14-2005 timlegge Add Linux 0.22 to .030 features
42*
43* Indent Options: indent -kr -i8
44***************************************************************************/
45
46/* to get some global routines like printf */
47#include "etherboot.h"
48/* to get the interface to the body of the program */
49#include "nic.h"
50/* to get the PCI support functions, if this is a PCI NIC */
51#include "pci.h"
52/* Include timer support functions */
53#include "timer.h"
54#include "mii.h"
55
56#define drv_version "v1.2"
57#define drv_date "05-14-2005"
58
59//#define TFTM_DEBUG
60#ifdef TFTM_DEBUG
61#define dprintf(x) printf x
62#else
63#define dprintf(x)
64#endif
65
66#define ETH_DATA_LEN 1500
67
68/* Condensed operations for readability. */
69#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
70#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
71
72unsigned long BASE;
73/* NIC specific static variables go here */
74#define PCI_DEVICE_ID_NVIDIA_NVENET_1 0x01c3
75#define PCI_DEVICE_ID_NVIDIA_NVENET_2 0x0066
76#define PCI_DEVICE_ID_NVIDIA_NVENET_4 0x0086
77#define PCI_DEVICE_ID_NVIDIA_NVENET_5 0x008c
78#define PCI_DEVICE_ID_NVIDIA_NVENET_3 0x00d6
79#define PCI_DEVICE_ID_NVIDIA_NVENET_7 0x00df
80#define PCI_DEVICE_ID_NVIDIA_NVENET_6 0x00e6
81#define PCI_DEVICE_ID_NVIDIA_NVENET_8 0x0056
82#define PCI_DEVICE_ID_NVIDIA_NVENET_9 0x0057
83#define PCI_DEVICE_ID_NVIDIA_NVENET_10 0x0037
84#define PCI_DEVICE_ID_NVIDIA_NVENET_11 0x0038
85
86
87/*
88 * Hardware access:
89 */
90
91#define DEV_NEED_LASTPACKET1 0x0001 /* set LASTPACKET1 in tx flags */
92#define DEV_IRQMASK_1 0x0002 /* use NVREG_IRQMASK_WANTED_1 for irq mask */
93#define DEV_IRQMASK_2 0x0004 /* use NVREG_IRQMASK_WANTED_2 for irq mask */
94#define DEV_NEED_TIMERIRQ 0x0008 /* set the timer irq flag in the irq mask */
95#define DEV_NEED_LINKTIMER 0x0010 /* poll link settings. Relies on the timer irq */
96
97enum {
98 NvRegIrqStatus = 0x000,
99#define NVREG_IRQSTAT_MIIEVENT 0040
100#define NVREG_IRQSTAT_MASK 0x1ff
101 NvRegIrqMask = 0x004,
102#define NVREG_IRQ_RX_ERROR 0x0001
103#define NVREG_IRQ_RX 0x0002
104#define NVREG_IRQ_RX_NOBUF 0x0004
105#define NVREG_IRQ_TX_ERR 0x0008
106#define NVREG_IRQ_TX2 0x0010
107#define NVREG_IRQ_TIMER 0x0020
108#define NVREG_IRQ_LINK 0x0040
109#define NVREG_IRQ_TX1 0x0100
110#define NVREG_IRQMASK_WANTED_1 0x005f
111#define NVREG_IRQMASK_WANTED_2 0x0147
112#define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1))
113
114 NvRegUnknownSetupReg6 = 0x008,
115#define NVREG_UNKSETUP6_VAL 3
116
117/*
118 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
119 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
120 */
121 NvRegPollingInterval = 0x00c,
122#define NVREG_POLL_DEFAULT 970
123 NvRegMisc1 = 0x080,
124#define NVREG_MISC1_HD 0x02
125#define NVREG_MISC1_FORCE 0x3b0f3c
126
127 NvRegTransmitterControl = 0x084,
128#define NVREG_XMITCTL_START 0x01
129 NvRegTransmitterStatus = 0x088,
130#define NVREG_XMITSTAT_BUSY 0x01
131
132 NvRegPacketFilterFlags = 0x8c,
133#define NVREG_PFF_ALWAYS 0x7F0008
134#define NVREG_PFF_PROMISC 0x80
135#define NVREG_PFF_MYADDR 0x20
136
137 NvRegOffloadConfig = 0x90,
138#define NVREG_OFFLOAD_HOMEPHY 0x601
139#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
140 NvRegReceiverControl = 0x094,
141#define NVREG_RCVCTL_START 0x01
142 NvRegReceiverStatus = 0x98,
143#define NVREG_RCVSTAT_BUSY 0x01
144
145 NvRegRandomSeed = 0x9c,
146#define NVREG_RNDSEED_MASK 0x00ff
147#define NVREG_RNDSEED_FORCE 0x7f00
148#define NVREG_RNDSEED_FORCE2 0x2d00
149#define NVREG_RNDSEED_FORCE3 0x7400
150
151 NvRegUnknownSetupReg1 = 0xA0,
152#define NVREG_UNKSETUP1_VAL 0x16070f
153 NvRegUnknownSetupReg2 = 0xA4,
154#define NVREG_UNKSETUP2_VAL 0x16
155 NvRegMacAddrA = 0xA8,
156 NvRegMacAddrB = 0xAC,
157 NvRegMulticastAddrA = 0xB0,
158#define NVREG_MCASTADDRA_FORCE 0x01
159 NvRegMulticastAddrB = 0xB4,
160 NvRegMulticastMaskA = 0xB8,
161 NvRegMulticastMaskB = 0xBC,
162
163 NvRegPhyInterface = 0xC0,
164#define PHY_RGMII 0x10000000
165
166 NvRegTxRingPhysAddr = 0x100,
167 NvRegRxRingPhysAddr = 0x104,
168 NvRegRingSizes = 0x108,
169#define NVREG_RINGSZ_TXSHIFT 0
170#define NVREG_RINGSZ_RXSHIFT 16
171 NvRegUnknownTransmitterReg = 0x10c,
172 NvRegLinkSpeed = 0x110,
173#define NVREG_LINKSPEED_FORCE 0x10000
174#define NVREG_LINKSPEED_10 1000
175#define NVREG_LINKSPEED_100 100
176#define NVREG_LINKSPEED_1000 50
177 NvRegUnknownSetupReg5 = 0x130,
178#define NVREG_UNKSETUP5_BIT31 (1<<31)
179 NvRegUnknownSetupReg3 = 0x13c,
180#define NVREG_UNKSETUP3_VAL1 0x200010
181 NvRegTxRxControl = 0x144,
182#define NVREG_TXRXCTL_KICK 0x0001
183#define NVREG_TXRXCTL_BIT1 0x0002
184#define NVREG_TXRXCTL_BIT2 0x0004
185#define NVREG_TXRXCTL_IDLE 0x0008
186#define NVREG_TXRXCTL_RESET 0x0010
187#define NVREG_TXRXCTL_RXCHECK 0x0400
188 NvRegMIIStatus = 0x180,
189#define NVREG_MIISTAT_ERROR 0x0001
190#define NVREG_MIISTAT_LINKCHANGE 0x0008
191#define NVREG_MIISTAT_MASK 0x000f
192#define NVREG_MIISTAT_MASK2 0x000f
193 NvRegUnknownSetupReg4 = 0x184,
194#define NVREG_UNKSETUP4_VAL 8
195
196 NvRegAdapterControl = 0x188,
197#define NVREG_ADAPTCTL_START 0x02
198#define NVREG_ADAPTCTL_LINKUP 0x04
199#define NVREG_ADAPTCTL_PHYVALID 0x40000
200#define NVREG_ADAPTCTL_RUNNING 0x100000
201#define NVREG_ADAPTCTL_PHYSHIFT 24
202 NvRegMIISpeed = 0x18c,
203#define NVREG_MIISPEED_BIT8 (1<<8)
204#define NVREG_MIIDELAY 5
205 NvRegMIIControl = 0x190,
206#define NVREG_MIICTL_INUSE 0x08000
207#define NVREG_MIICTL_WRITE 0x00400
208#define NVREG_MIICTL_ADDRSHIFT 5
209 NvRegMIIData = 0x194,
210 NvRegWakeUpFlags = 0x200,
211#define NVREG_WAKEUPFLAGS_VAL 0x7770
212#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
213#define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
214#define NVREG_WAKEUPFLAGS_D3SHIFT 12
215#define NVREG_WAKEUPFLAGS_D2SHIFT 8
216#define NVREG_WAKEUPFLAGS_D1SHIFT 4
217#define NVREG_WAKEUPFLAGS_D0SHIFT 0
218#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
219#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
220#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
221#define NVREG_WAKEUPFLAGS_ENABLE 0x1111
222
223 NvRegPatternCRC = 0x204,
224 NvRegPatternMask = 0x208,
225 NvRegPowerCap = 0x268,
226#define NVREG_POWERCAP_D3SUPP (1<<30)
227#define NVREG_POWERCAP_D2SUPP (1<<26)
228#define NVREG_POWERCAP_D1SUPP (1<<25)
229 NvRegPowerState = 0x26c,
230#define NVREG_POWERSTATE_POWEREDUP 0x8000
231#define NVREG_POWERSTATE_VALID 0x0100
232#define NVREG_POWERSTATE_MASK 0x0003
233#define NVREG_POWERSTATE_D0 0x0000
234#define NVREG_POWERSTATE_D1 0x0001
235#define NVREG_POWERSTATE_D2 0x0002
236#define NVREG_POWERSTATE_D3 0x0003
237};
238
239#define FLAG_MASK_V1 0xffff0000
240#define FLAG_MASK_V2 0xffffc000
241#define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
242#define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
243
244#define NV_TX_LASTPACKET (1<<16)
245#define NV_TX_RETRYERROR (1<<19)
246#define NV_TX_LASTPACKET1 (1<<24)
247#define NV_TX_DEFERRED (1<<26)
248#define NV_TX_CARRIERLOST (1<<27)
249#define NV_TX_LATECOLLISION (1<<28)
250#define NV_TX_UNDERFLOW (1<<29)
251#define NV_TX_ERROR (1<<30)
252#define NV_TX_VALID (1<<31)
253
254#define NV_TX2_LASTPACKET (1<<29)
255#define NV_TX2_RETRYERROR (1<<18)
256#define NV_TX2_LASTPACKET1 (1<<23)
257#define NV_TX2_DEFERRED (1<<25)
258#define NV_TX2_CARRIERLOST (1<<26)
259#define NV_TX2_LATECOLLISION (1<<27)
260#define NV_TX2_UNDERFLOW (1<<28)
261/* error and valid are the same for both */
262#define NV_TX2_ERROR (1<<30)
263#define NV_TX2_VALID (1<<31)
264
265#define NV_RX_DESCRIPTORVALID (1<<16)
266#define NV_RX_MISSEDFRAME (1<<17)
267#define NV_RX_SUBSTRACT1 (1<<18)
268#define NV_RX_ERROR1 (1<<23)
269#define NV_RX_ERROR2 (1<<24)
270#define NV_RX_ERROR3 (1<<25)
271#define NV_RX_ERROR4 (1<<26)
272#define NV_RX_CRCERR (1<<27)
273#define NV_RX_OVERFLOW (1<<28)
274#define NV_RX_FRAMINGERR (1<<29)
275#define NV_RX_ERROR (1<<30)
276#define NV_RX_AVAIL (1<<31)
277
278#define NV_RX2_CHECKSUMMASK (0x1C000000)
279#define NV_RX2_CHECKSUMOK1 (0x10000000)
280#define NV_RX2_CHECKSUMOK2 (0x14000000)
281#define NV_RX2_CHECKSUMOK3 (0x18000000)
282#define NV_RX2_DESCRIPTORVALID (1<<29)
283#define NV_RX2_SUBSTRACT1 (1<<25)
284#define NV_RX2_ERROR1 (1<<18)
285#define NV_RX2_ERROR2 (1<<19)
286#define NV_RX2_ERROR3 (1<<20)
287#define NV_RX2_ERROR4 (1<<21)
288#define NV_RX2_CRCERR (1<<22)
289#define NV_RX2_OVERFLOW (1<<23)
290#define NV_RX2_FRAMINGERR (1<<24)
291/* error and avail are the same for both */
292#define NV_RX2_ERROR (1<<30)
293#define NV_RX2_AVAIL (1<<31)
294
295/* Miscelaneous hardware related defines: */
296#define NV_PCI_REGSZ 0x270
297
298/* various timeout delays: all in usec */
299#define NV_TXRX_RESET_DELAY 4
300#define NV_TXSTOP_DELAY1 10
301#define NV_TXSTOP_DELAY1MAX 500000
302#define NV_TXSTOP_DELAY2 100
303#define NV_RXSTOP_DELAY1 10
304#define NV_RXSTOP_DELAY1MAX 500000
305#define NV_RXSTOP_DELAY2 100
306#define NV_SETUP5_DELAY 5
307#define NV_SETUP5_DELAYMAX 50000
308#define NV_POWERUP_DELAY 5
309#define NV_POWERUP_DELAYMAX 5000
310#define NV_MIIBUSY_DELAY 50
311#define NV_MIIPHY_DELAY 10
312#define NV_MIIPHY_DELAYMAX 10000
313
314#define NV_WAKEUPPATTERNS 5
315#define NV_WAKEUPMASKENTRIES 4
316
317/* General driver defaults */
318#define NV_WATCHDOG_TIMEO (5*HZ)
319
320#define RX_RING 4
321#define TX_RING 2
322
323/*
324 * If your nic mysteriously hangs then try to reduce the limits
325 * to 1/0: It might be required to set NV_TX_LASTPACKET in the
326 * last valid ring entry. But this would be impossible to
327 * implement - probably a disassembly error.
328 */
329#define TX_LIMIT_STOP 63
330#define TX_LIMIT_START 62
331
332/* rx/tx mac addr + type + vlan + align + slack*/
333#define RX_NIC_BUFSIZE (ETH_DATA_LEN + 64)
334/* even more slack */
335#define RX_ALLOC_BUFSIZE (ETH_DATA_LEN + 128)
336
337#define OOM_REFILL (1+HZ/20)
338#define POLL_WAIT (1+HZ/100)
339#define LINK_TIMEOUT (3*HZ)
340
341/*
342 * desc_ver values:
343 * This field has two purposes:
344 * - Newer nics uses a different ring layout. The layout is selected by
345 * comparing np->desc_ver with DESC_VER_xy.
346 * - It contains bits that are forced on when writing to NvRegTxRxControl.
347 */
348#define DESC_VER_1 0x0
349#define DESC_VER_2 (0x02100|NVREG_TXRXCTL_RXCHECK)
350
351/* PHY defines */
352#define PHY_OUI_MARVELL 0x5043
353#define PHY_OUI_CICADA 0x03f1
354#define PHYID1_OUI_MASK 0x03ff
355#define PHYID1_OUI_SHFT 6
356#define PHYID2_OUI_MASK 0xfc00
357#define PHYID2_OUI_SHFT 10
358#define PHY_INIT1 0x0f000
359#define PHY_INIT2 0x0e00
360#define PHY_INIT3 0x01000
361#define PHY_INIT4 0x0200
362#define PHY_INIT5 0x0004
363#define PHY_INIT6 0x02000
364#define PHY_GIGABIT 0x0100
365
366#define PHY_TIMEOUT 0x1
367#define PHY_ERROR 0x2
368
369#define PHY_100 0x1
370#define PHY_1000 0x2
371#define PHY_HALF 0x100
372
373/* FIXME: MII defines that should be added to <linux/mii.h> */
374#define MII_1000BT_CR 0x09
375#define MII_1000BT_SR 0x0a
376#define ADVERTISE_1000FULL 0x0200
377#define ADVERTISE_1000HALF 0x0100
378#define LPA_1000FULL 0x0800
379#define LPA_1000HALF 0x0400
380
381/* Big endian: should work, but is untested */
382struct ring_desc {
383 u32 PacketBuffer;
384 u32 FlagLen;
385};
386
387
388/* Define the TX Descriptor */
389static struct ring_desc tx_ring[TX_RING];
390
391/* Create a static buffer of size RX_BUF_SZ for each
392TX Descriptor. All descriptors point to a
393part of this buffer */
394static unsigned char txb[TX_RING * RX_NIC_BUFSIZE];
395
396/* Define the TX Descriptor */
397static struct ring_desc rx_ring[RX_RING];
398
399/* Create a static buffer of size RX_BUF_SZ for each
400RX Descriptor All descriptors point to a
401part of this buffer */
402static unsigned char rxb[RX_RING * RX_NIC_BUFSIZE];
403
404/* Private Storage for the NIC */
405struct forcedeth_private {
406 /* General data:
407 * Locking: spin_lock(&np->lock); */
408 int in_shutdown;
409 u32 linkspeed;
410 int duplex;
411 int phyaddr;
412 int wolenabled;
413 unsigned int phy_oui;
414 u16 gigabit;
415
416 /* General data: RO fields */
417 u8 *ring_addr;
418 u32 orig_mac[2];
419 u32 irqmask;
420 u32 desc_ver;
421 /* rx specific fields.
422 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
423 */
424//yhlu struct ring_desc *rx_ring;
425 unsigned int cur_rx, refill_rx;
426//yhlu struct sk_buff *rx_skbuff[RX_RING];
427//yhlu u32 rx_dma[RX_RING];
428//yhlu unsigned int rx_buf_sz;
429
430 /*
431 * tx specific fields.
432 */
433//yhlu struct ring_desc *tx_ring;
434 unsigned int next_tx, nic_tx;
435//yhlu struct sk_buff *tx_skbuff[TX_RING];
436//yhlu u32 tx_dma[TX_RING];
437 u32 tx_flags;
438} npx;
439
440static struct forcedeth_private *np;
441
442static void drop_rx(void);
443static void nv_udelay(unsigned long delay)
444{
445 if (!np->in_shutdown) {
446 udelay(delay);
447 } else while(delay) {
448 /* Don't allow an rx_ring overflow to happen
449 * while shutting down the NIC it will
450 * kill the receive function.
451 */
452 unsigned long sleep;
453 drop_rx();
454 sleep = 3;
455 if (sleep > delay)
456 sleep = delay;
457 udelay(sleep);
458 delay -= sleep;
459 }
460}
461
462static inline void pci_push(u8 * base)
463{
464 /* force out pending posted writes */
465 readl(base);
466}
467
468static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
469{
470 return le32_to_cpu(prd->FlagLen)
471 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
472}
473
474static int reg_delay(int offset, u32 mask,
475 u32 target, int delay, int delaymax, const char *msg)
476{
477 u8 *base = (u8 *) BASE;
478
479 pci_push(base);
480 do {
481 nv_udelay(delay);
482 delaymax -= delay;
483 if (delaymax < 0) {
484 if (msg)
485 printf(msg);
486 return 1;
487 }
488 } while ((readl(base + offset) & mask) != target);
489 return 0;
490}
491
492#define MII_READ (-1)
493#define MII_PHYSID1 0x02 /* PHYS ID 1 */
494#define MII_PHYSID2 0x03 /* PHYS ID 2 */
495#define MII_BMCR 0x00 /* Basic mode control register */
496#define MII_BMSR 0x01 /* Basic mode status register */
497#define MII_ADVERTISE 0x04 /* Advertisement control reg */
498#define MII_LPA 0x05 /* Link partner ability reg */
499
500#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
501
502/* Link partner ability register. */
503#define LPA_SLCT 0x001f /* Same as advertise selector */
504#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
505#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
506#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
507#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
508#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
509#define LPA_RESV 0x1c00 /* Unused... */
510#define LPA_RFAULT 0x2000 /* Link partner faulted */
511#define LPA_LPACK 0x4000 /* Link partner acked us */
512#define LPA_NPAGE 0x8000 /* Next page bit */
513
514/* mii_rw: read/write a register on the PHY.
515 *
516 * Caller must guarantee serialization
517 */
518static int mii_rw(struct nic *nic __unused, int addr, int miireg,
519 int value)
520{
521 u8 *base = (u8 *) BASE;
522 u32 reg;
523 int retval;
524
525 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
526
527 reg = readl(base + NvRegMIIControl);
528 if (reg & NVREG_MIICTL_INUSE) {
529 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
530 nv_udelay(NV_MIIBUSY_DELAY);
531 }
532
533 reg =
534 (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
535 if (value != MII_READ) {
536 writel(value, base + NvRegMIIData);
537 reg |= NVREG_MIICTL_WRITE;
538 }
539 writel(reg, base + NvRegMIIControl);
540
541 if (reg_delay(NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
542 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
543 dprintf(("mii_rw of reg %d at PHY %d timed out.\n",
544 miireg, addr));
545 retval = -1;
546 } else if (value != MII_READ) {
547 /* it was a write operation - fewer failures are detectable */
548 dprintf(("mii_rw wrote 0x%x to reg %d at PHY %d\n",
549 value, miireg, addr));
550 retval = 0;
551 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
552 dprintf(("mii_rw of reg %d at PHY %d failed.\n",
553 miireg, addr));
554 retval = -1;
555 } else {
556 retval = readl(base + NvRegMIIData);
557 dprintf(("mii_rw read from reg %d at PHY %d: 0x%x.\n",
558 miireg, addr, retval));
559 }
560 return retval;
561}
562
563static int phy_reset(struct nic *nic)
564{
565
566 u32 miicontrol;
567 unsigned int tries = 0;
568
569 miicontrol = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ);
570 miicontrol |= BMCR_RESET;
571 if (mii_rw(nic, np->phyaddr, MII_BMCR, miicontrol)) {
572 return -1;
573 }
574
575 /* wait for 500ms */
576 mdelay(500);
577
578 /* must wait till reset is deasserted */
579 while (miicontrol & BMCR_RESET) {
580 mdelay(10);
581 miicontrol = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ);
582 /* FIXME: 100 tries seem excessive */
583 if (tries++ > 100)
584 return -1;
585 }
586 return 0;
587}
588
589static int phy_init(struct nic *nic)
590{
591 u8 *base = (u8 *) BASE;
592 u32 phyinterface, phy_reserved, mii_status, mii_control,
593 mii_control_1000, reg;
594
595 /* set advertise register */
596 reg = mii_rw(nic, np->phyaddr, MII_ADVERTISE, MII_READ);
597 reg |=
598 (ADVERTISE_10HALF | ADVERTISE_10FULL | ADVERTISE_100HALF |
599 ADVERTISE_100FULL | 0x800 | 0x400);
600 if (mii_rw(nic, np->phyaddr, MII_ADVERTISE, reg)) {
601 printf("phy write to advertise failed.\n");
602 return PHY_ERROR;
603 }
604
605 /* get phy interface type */
606 phyinterface = readl(base + NvRegPhyInterface);
607
608 /* see if gigabit phy */
609 mii_status = mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ);
610
611 if (mii_status & PHY_GIGABIT) {
612 np->gigabit = PHY_GIGABIT;
613 mii_control_1000 =
614 mii_rw(nic, np->phyaddr, MII_1000BT_CR, MII_READ);
615 mii_control_1000 &= ~ADVERTISE_1000HALF;
616 if (phyinterface & PHY_RGMII)
617 mii_control_1000 |= ADVERTISE_1000FULL;
618 else
619 mii_control_1000 &= ~ADVERTISE_1000FULL;
620
621 if (mii_rw
622 (nic, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
623 printf("phy init failed.\n");
624 return PHY_ERROR;
625 }
626 } else
627 np->gigabit = 0;
628
629 /* reset the phy */
630 if (phy_reset(nic)) {
631 printf("phy reset failed\n");
632 return PHY_ERROR;
633 }
634
635 /* phy vendor specific configuration */
636 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII)) {
637 phy_reserved =
638 mii_rw(nic, np->phyaddr, MII_RESV1, MII_READ);
639 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
640 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
641 if (mii_rw(nic, np->phyaddr, MII_RESV1, phy_reserved)) {
642 printf("phy init failed.\n");
643 return PHY_ERROR;
644 }
645 phy_reserved =
646 mii_rw(nic, np->phyaddr, MII_NCONFIG, MII_READ);
647 phy_reserved |= PHY_INIT5;
648 if (mii_rw(nic, np->phyaddr, MII_NCONFIG, phy_reserved)) {
649 printf("phy init failed.\n");
650 return PHY_ERROR;
651 }
652 }
653 if (np->phy_oui == PHY_OUI_CICADA) {
654 phy_reserved =
655 mii_rw(nic, np->phyaddr, MII_SREVISION, MII_READ);
656 phy_reserved |= PHY_INIT6;
657 if (mii_rw(nic, np->phyaddr, MII_SREVISION, phy_reserved)) {
658 printf("phy init failed.\n");
659 return PHY_ERROR;
660 }
661 }
662
663 /* restart auto negotiation */
664 mii_control = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ);
665 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
666 if (mii_rw(nic, np->phyaddr, MII_BMCR, mii_control)) {
667 return PHY_ERROR;
668 }
669
670 return 0;
671}
672
673static void start_rx(struct nic *nic __unused)
674{
675 u8 *base = (u8 *) BASE;
676
677 dprintf(("start_rx\n"));
678 /* Already running? Stop it. */
679 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
680 writel(0, base + NvRegReceiverControl);
681 pci_push(base);
682 }
683 writel(np->linkspeed, base + NvRegLinkSpeed);
684 pci_push(base);
685 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
686 pci_push(base);
687}
688
689static void stop_rx(void)
690{
691 u8 *base = (u8 *) BASE;
692
693 dprintf(("stop_rx\n"));
694 writel(0, base + NvRegReceiverControl);
695 reg_delay(NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
696 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
697 "stop_rx: ReceiverStatus remained busy");
698
699 nv_udelay(NV_RXSTOP_DELAY2);
700 writel(0, base + NvRegLinkSpeed);
701}
702
703static void start_tx(struct nic *nic __unused)
704{
705 u8 *base = (u8 *) BASE;
706
707 dprintf(("start_tx\n"));
708 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
709 pci_push(base);
710}
711
712static void stop_tx(void)
713{
714 u8 *base = (u8 *) BASE;
715
716 dprintf(("stop_tx\n"));
717 writel(0, base + NvRegTransmitterControl);
718 reg_delay(NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
719 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
720 "stop_tx: TransmitterStatus remained busy");
721
722 nv_udelay(NV_TXSTOP_DELAY2);
723 writel(0, base + NvRegUnknownTransmitterReg);
724}
725
726
727static void txrx_reset(struct nic *nic __unused)
728{
729 u8 *base = (u8 *) BASE;
730
731 dprintf(("txrx_reset\n"));
732 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->desc_ver,
733 base + NvRegTxRxControl);
734
735 pci_push(base);
736 nv_udelay(NV_TXRX_RESET_DELAY);
737 writel(NVREG_TXRXCTL_BIT2 | np->desc_ver, base + NvRegTxRxControl);
738 pci_push(base);
739}
740
741/*
742 * alloc_rx: fill rx ring entries.
743 * Return 1 if the allocations for the skbs failed and the
744 * rx engine is without Available descriptors
745 */
746static void alloc_rx(struct nic *nic __unused)
747{
748 unsigned int refill_rx = np->refill_rx;
749 while (np->cur_rx != refill_rx) {
750 int nr = refill_rx % RX_RING;
751 rx_ring[nr].PacketBuffer =
752 virt_to_le32desc(&rxb[nr * RX_NIC_BUFSIZE]);
753 wmb();
754 rx_ring[nr].FlagLen =
755 cpu_to_le32(RX_NIC_BUFSIZE | NV_RX_AVAIL);
756 /* printf("alloc_rx: Packet %d marked as Available\n",
757 refill_rx); */
758 refill_rx++;
759 }
760 np->refill_rx = refill_rx;
761}
762
763static void drop_rx(void)
764{
765 u32 events;
766 u8 *base = (u8 *)BASE;
767
768 events = readl(base + NvRegIrqStatus);
769 if (events)
770 writel(events, base + NvRegIrqStatus);
771 if (!(events & (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF)))
772 return;
773 for (;;) {
774 int i, len;
775 u32 Flags;
776 i = np->cur_rx % RX_RING;
777
778 Flags = le32_to_cpu(rx_ring[i].FlagLen);
779 len = nv_descr_getlength(&rx_ring[i], np->desc_ver);
780
781 if (Flags & NV_RX_AVAIL)
782 break; /* still owned by hardware, */
783 wmb();
784 np->cur_rx++;
785 alloc_rx(NULL);
786 }
787}
788
789static int update_linkspeed(struct nic *nic)
790{
791 int adv, lpa;
792 u32 newls;
793 int newdup = np->duplex;
794 u32 mii_status;
795 int retval = 0;
796 u32 control_1000, status_1000, phyreg;
797 u8 *base = (u8 *) BASE;
798 int i;
799
800 /* BMSR_LSTATUS is latched, read it twice:
801 * we want the current value.
802 */
803 mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ);
804 mii_status = mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ);
805
806#if 1
807 //yhlu
808 for(i=0;i<30;i++) {
809 mii_status = mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ);
810 if((mii_status & BMSR_LSTATUS) && (mii_status & BMSR_ANEGCOMPLETE)) break;
811 mdelay(100);
812 }
813#endif
814
815 if (!(mii_status & BMSR_LSTATUS)) {
816 printf
817 ("no link detected by phy - falling back to 10HD.\n");
818 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
819 newdup = 0;
820 retval = 0;
821 goto set_speed;
822 }
823
824 /* check auto negotiation is complete */
825 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
826 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
827 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
828 newdup = 0;
829 retval = 0;
830 printf("autoneg not completed - falling back to 10HD.\n");
831 goto set_speed;
832 }
833
834 retval = 1;
835 if (np->gigabit == PHY_GIGABIT) {
836 control_1000 =
837 mii_rw(nic, np->phyaddr, MII_1000BT_CR, MII_READ);
838 status_1000 =
839 mii_rw(nic, np->phyaddr, MII_1000BT_SR, MII_READ);
840
841 if ((control_1000 & ADVERTISE_1000FULL) &&
842 (status_1000 & LPA_1000FULL)) {
843 printf
844 ("update_linkspeed: GBit ethernet detected.\n");
845 newls =
846 NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_1000;
847 newdup = 1;
848 goto set_speed;
849 }
850 }
851
852 adv = mii_rw(nic, np->phyaddr, MII_ADVERTISE, MII_READ);
853 lpa = mii_rw(nic, np->phyaddr, MII_LPA, MII_READ);
854 dprintf(("update_linkspeed: PHY advertises 0x%hX, lpa 0x%hX.\n",
855 adv, lpa));
856
857 /* FIXME: handle parallel detection properly, handle gigabit ethernet */
858 lpa = lpa & adv;
859 if (lpa & LPA_100FULL) {
860 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_100;
861 newdup = 1;
862 } else if (lpa & LPA_100HALF) {
863 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_100;
864 newdup = 0;
865 } else if (lpa & LPA_10FULL) {
866 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
867 newdup = 1;
868 } else if (lpa & LPA_10HALF) {
869 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
870 newdup = 0;
871 } else {
872 printf("bad ability %hX - falling back to 10HD.\n", lpa);
873 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
874 newdup = 0;
875 }
876
877 set_speed:
878 if (np->duplex == newdup && np->linkspeed == newls)
879 return retval;
880
881 dprintf(("changing link setting from %d/%s to %d/%s.\n",
882 np->linkspeed, np->duplex ? "Full-Duplex": "Half-Duplex", newls, newdup ? "Full-Duplex": "Half-Duplex"));
883
884 np->duplex = newdup;
885 np->linkspeed = newls;
886
887 if (np->gigabit == PHY_GIGABIT) {
888 phyreg = readl(base + NvRegRandomSeed);
889 phyreg &= ~(0x3FF00);
890 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
891 phyreg |= NVREG_RNDSEED_FORCE3;
892 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
893 phyreg |= NVREG_RNDSEED_FORCE2;
894 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
895 phyreg |= NVREG_RNDSEED_FORCE;
896 writel(phyreg, base + NvRegRandomSeed);
897 }
898
899 phyreg = readl(base + NvRegPhyInterface);
900 phyreg &= ~(PHY_HALF | PHY_100 | PHY_1000);
901 if (np->duplex == 0)
902 phyreg |= PHY_HALF;
903 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
904 phyreg |= PHY_100;
905 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
906 phyreg |= PHY_1000;
907 writel(phyreg, base + NvRegPhyInterface);
908
909 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
910 base + NvRegMisc1);
911 pci_push(base);
912 writel(np->linkspeed, base + NvRegLinkSpeed);
913 pci_push(base);
914
915 return retval;
916}
917
918static void nv_linkchange(struct nic *nic)
919{
920 if (update_linkspeed(nic)) {
921// if (netif_carrier_ok(nic)) {
922 stop_rx();
923//= } else {
924 // netif_carrier_on(dev);
925 // printk(KERN_INFO "%s: link up.\n", dev->name);
926 // }
927 start_rx(nic);
928 } else {
929 // if (netif_carrier_ok(dev)) {
930 // netif_carrier_off(dev);
931 // printk(KERN_INFO "%s: link down.\n", dev->name);
932 stop_rx();
933 // }
934 }
935}
936
937
938static void init_ring(struct nic *nic)
939{
940 int i;
941
942 np->next_tx = np->nic_tx = 0;
943 for (i = 0; i < TX_RING; i++)
944 tx_ring[i].FlagLen = 0;
945
946 np->cur_rx = RX_RING;
947 np->refill_rx = 0;
948 for (i = 0; i < RX_RING; i++)
949 rx_ring[i].FlagLen = 0;
950 alloc_rx(nic);
951}
952
953static void set_multicast(struct nic *nic)
954{
955
956 u8 *base = (u8 *) BASE;
957 u32 addr[2];
958 u32 mask[2];
959 u32 pff;
960 u32 alwaysOff[2];
961 u32 alwaysOn[2];
962
963 memset(addr, 0, sizeof(addr));
964 memset(mask, 0, sizeof(mask));
965
966 pff = NVREG_PFF_MYADDR;
967
968 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
969
970 addr[0] = alwaysOn[0];
971 addr[1] = alwaysOn[1];
972 mask[0] = alwaysOn[0] | alwaysOff[0];
973 mask[1] = alwaysOn[1] | alwaysOff[1];
974
975 addr[0] |= NVREG_MCASTADDRA_FORCE;
976 pff |= NVREG_PFF_ALWAYS;
977 stop_rx();
978 writel(addr[0], base + NvRegMulticastAddrA);
979 writel(addr[1], base + NvRegMulticastAddrB);
980 writel(mask[0], base + NvRegMulticastMaskA);
981 writel(mask[1], base + NvRegMulticastMaskB);
982 writel(pff, base + NvRegPacketFilterFlags);
983 start_rx(nic);
984}
985
986/**************************************************************************
987RESET - Reset the NIC to prepare for use
988***************************************************************************/
989static int forcedeth_reset(struct nic *nic)
990{
991 u8 *base = (u8 *) BASE;
992 int ret, i;
993 ret = 0;
994 dprintf(("forcedeth: open\n"));
995
996 /* 1) erase previous misconfiguration */
997 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
998 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
999 writel(0, base + NvRegMulticastAddrB);
1000 writel(0, base + NvRegMulticastMaskA);
1001 writel(0, base + NvRegMulticastMaskB);
1002 writel(0, base + NvRegPacketFilterFlags);
1003
1004 writel(0, base + NvRegTransmitterControl);
1005 writel(0, base + NvRegReceiverControl);
1006
1007 writel(0, base + NvRegAdapterControl);
1008
1009 /* 2) initialize descriptor rings */
1010 init_ring(nic);
1011
1012 writel(0, base + NvRegLinkSpeed);
1013 writel(0, base + NvRegUnknownTransmitterReg);
1014 txrx_reset(nic);
1015 writel(0, base + NvRegUnknownSetupReg6);
1016
1017 np->in_shutdown = 0;
1018
1019 /* 3) set mac address */
1020 {
1021 u32 mac[2];
1022
1023 mac[0] =
1024 (nic->node_addr[0] << 0) + (nic->node_addr[1] << 8) +
1025 (nic->node_addr[2] << 16) + (nic->node_addr[3] << 24);
1026 mac[1] =
1027 (nic->node_addr[4] << 0) + (nic->node_addr[5] << 8);
1028
1029 writel(mac[0], base + NvRegMacAddrA);
1030 writel(mac[1], base + NvRegMacAddrB);
1031 }
1032
1033 /* 4) give hw rings */
1034 writel((u32) virt_to_le32desc(&rx_ring[0]),
1035 base + NvRegRxRingPhysAddr);
1036 writel((u32) virt_to_le32desc(&tx_ring[0]),
1037 base + NvRegTxRingPhysAddr);
1038
1039 writel(((RX_RING - 1) << NVREG_RINGSZ_RXSHIFT) +
1040 ((TX_RING - 1) << NVREG_RINGSZ_TXSHIFT),
1041 base + NvRegRingSizes);
1042
1043 /* 5) continue setup */
1044 np->linkspeed = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
1045 np->duplex = 0;
1046 writel(np->linkspeed, base + NvRegLinkSpeed);
1047 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
1048 writel(np->desc_ver, base + NvRegTxRxControl);
1049 pci_push(base);
1050 writel(NVREG_TXRXCTL_BIT1 | np->desc_ver, base + NvRegTxRxControl);
1051 reg_delay(NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31,
1052 NVREG_UNKSETUP5_BIT31, NV_SETUP5_DELAY,
1053 NV_SETUP5_DELAYMAX,
1054 "open: SetupReg5, Bit 31 remained off\n");
1055
1056 writel(0, base + NvRegUnknownSetupReg4);
1057// writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1058 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1059#if 0
1060 printf("%d-Mbs Link, %s-Duplex\n",
1061 np->linkspeed & NVREG_LINKSPEED_10 ? 10 : 100,
1062 np->duplex ? "Full" : "Half");
1063#endif
1064
1065 /* 6) continue setup */
1066 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
1067 writel(readl(base + NvRegTransmitterStatus),
1068 base + NvRegTransmitterStatus);
1069 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
1070 writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig);
1071
1072 writel(readl(base + NvRegReceiverStatus),
1073 base + NvRegReceiverStatus);
1074
1075 /* Get a random number */
1076 i = random();
1077 writel(NVREG_RNDSEED_FORCE | (i & NVREG_RNDSEED_MASK),
1078 base + NvRegRandomSeed);
1079 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
1080 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
1081 writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
1082 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
1083 writel((np->
1084 phyaddr << NVREG_ADAPTCTL_PHYSHIFT) |
1085 NVREG_ADAPTCTL_PHYVALID | NVREG_ADAPTCTL_RUNNING,
1086 base + NvRegAdapterControl);
1087 writel(NVREG_MIISPEED_BIT8 | NVREG_MIIDELAY, base + NvRegMIISpeed);
1088 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
1089 writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
1090
1091 i = readl(base + NvRegPowerState);
1092 if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
1093 writel(NVREG_POWERSTATE_POWEREDUP | i,
1094 base + NvRegPowerState);
1095
1096 pci_push(base);
1097 nv_udelay(10);
1098 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID,
1099 base + NvRegPowerState);
1100
1101 writel(0, base + NvRegIrqMask);
1102 pci_push(base);
1103 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1104 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1105 pci_push(base);
1106/*
1107 writel(np->irqmask, base + NvRegIrqMask);
1108*/
1109 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1110 writel(0, base + NvRegMulticastAddrB);
1111 writel(0, base + NvRegMulticastMaskA);
1112 writel(0, base + NvRegMulticastMaskB);
1113 writel(NVREG_PFF_ALWAYS | NVREG_PFF_MYADDR,
1114 base + NvRegPacketFilterFlags);
1115
1116 set_multicast(nic);
1117 /* One manual link speed update: Interrupts are enabled, future link
1118 * speed changes cause interrupts and are handled by nv_link_irq().
1119 */
1120 {
1121 u32 miistat;
1122 miistat = readl(base + NvRegMIIStatus);
1123 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1124 dprintf(("startup: got 0x%hX.\n", miistat));
1125 }
1126 ret = update_linkspeed(nic);
1127
1128 //start_rx(nic);
1129 start_tx(nic);
1130
1131 if (ret) {
1132 //Start Connection netif_carrier_on(dev);
1133 } else {
1134 printf("no link during initialization.\n");
1135 }
1136
1137 out_drain:
1138 return ret;
1139}
1140
1141/*
1142 * extern void hex_dump(const char *data, const unsigned int len);
1143*/
1144/**************************************************************************
1145POLL - Wait for a frame
1146***************************************************************************/
1147static int forcedeth_poll(struct nic *nic, int retrieve)
1148{
1149 /* return true if there's an ethernet packet ready to read */
1150 /* nic->packet should contain data on return */
1151 /* nic->packetlen should contain length of data */
1152
1153 int len;
1154 int i;
1155 u32 Flags;
1156 u32 valid;
1157
1158top:
1159 i = np->cur_rx % RX_RING;
1160
1161 Flags = le32_to_cpu(rx_ring[i].FlagLen);
1162 len = nv_descr_getlength(&rx_ring[i], np->desc_ver);
1163
1164 if (Flags & NV_RX_AVAIL)
1165 return 0; /* still owned by hardware, */
1166
1167 if (np->desc_ver == DESC_VER_1) {
1168 if (!(Flags & NV_RX_DESCRIPTORVALID))
1169 return 0;
1170 } else {
1171 if (!(Flags & NV_RX2_DESCRIPTORVALID))
1172 return 0;
1173 }
1174
1175 valid = 1;
1176 if (!retrieve)
1177 return 1;
1178
1179 /* got a valid packet - forward it to the network core */
1180 nic->packetlen = len;
1181 memcpy(nic->packet, rxb + (i * RX_NIC_BUFSIZE), nic->packetlen);
1182/*
1183 * hex_dump(rxb + (i * RX_NIC_BUFSIZE), len);
1184*/
1185 wmb();
1186 np->cur_rx++;
1187 if (!valid)
1188 goto top;
1189 alloc_rx(nic);
1190 return 1;
1191}
1192
1193
1194/**************************************************************************
1195TRANSMIT - Transmit a frame
1196***************************************************************************/
1197static void forcedeth_transmit(struct nic *nic, const char *d, /* Destination */
1198 unsigned int t, /* Type */
1199 unsigned int s, /* size */
1200 const char *p)
1201{ /* Packet */
1202 /* send the packet to destination */
1203 u8 *ptxb;
1204 u16 nstype;
1205 u8 *base = (u8 *) BASE;
1206 int nr = np->next_tx % TX_RING;
1207
1208 /* point to the current txb incase multiple tx_rings are used */
1209 ptxb = txb + (nr * RX_NIC_BUFSIZE);
1210 //np->tx_skbuff[nr] = ptxb;
1211
1212 /* copy the packet to ring buffer */
1213 memcpy(ptxb, d, ETH_ALEN); /* dst */
1214 memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN); /* src */
1215 nstype = htons((u16) t); /* type */
1216 memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2); /* type */
1217 memcpy(ptxb + ETH_HLEN, p, s);
1218
1219 s += ETH_HLEN;
1220 while (s < ETH_ZLEN) /* pad to min length */
1221 ptxb[s++] = '\0';
1222
1223 tx_ring[nr].PacketBuffer = (u32) virt_to_le32desc(ptxb);
1224
1225 wmb();
1226 tx_ring[nr].FlagLen = cpu_to_le32((s - 1) | np->tx_flags);
1227
1228 writel(NVREG_TXRXCTL_KICK | np->desc_ver, base + NvRegTxRxControl);
1229 pci_push(base);
1230 np->next_tx++;
1231}
1232
1233/**************************************************************************
1234DISABLE - Turn off ethernet interface
1235***************************************************************************/
1236static void forcedeth_disable(struct dev *dev __unused)
1237{
1238 /* put the card in its initial state */
1239 /* This function serves 3 purposes.
1240 * This disables DMA and interrupts so we don't receive
1241 * unexpected packets or interrupts from the card after
1242 * etherboot has finished.
1243 * This frees resources so etherboot may use
1244 * this driver on another interface
1245 * This allows etherboot to reinitialize the interface
1246 * if something is something goes wrong.
1247 */
1248 u8 *base = (u8 *) BASE;
1249 np->in_shutdown = 1;
1250 stop_tx();
1251 stop_rx();
1252
1253 /* disable interrupts on the nic or we will lock up */
1254 writel(0, base + NvRegIrqMask);
1255 pci_push(base);
1256 dprintf(("Irqmask is zero again\n"));
1257
1258 /* specia op:o write back the misordered MAC address - otherwise
1259 * the next probe_nic would see a wrong address.
1260 */
1261 writel(np->orig_mac[0], base + NvRegMacAddrA);
1262 writel(np->orig_mac[1], base + NvRegMacAddrB);
1263}
1264
1265/**************************************************************************
1266IRQ - Enable, Disable, or Force interrupts
1267***************************************************************************/
1268static void forcedeth_irq(struct nic *nic __unused,
1269 irq_action_t action __unused)
1270{
1271 switch (action) {
1272 case DISABLE:
1273 break;
1274 case ENABLE:
1275 break;
1276 case FORCE:
1277 break;
1278 }
1279}
1280
1281/**************************************************************************
1282PROBE - Look for an adapter, this routine's visible to the outside
1283***************************************************************************/
1284#define IORESOURCE_MEM 0x00000200
1285#define board_found 1
1286#define valid_link 0
1287static int forcedeth_probe(struct dev *dev, struct pci_device *pci)
1288{
1289 struct nic *nic = (struct nic *) dev;
1290 unsigned long addr;
1291 int sz;
1292 u8 *base;
1293 int i;
1294
1295 if (pci->ioaddr == 0)
1296 return 0;
1297
1298 dprintf(("forcedeth.c: Found %s, vendor=0x%hX, device=0x%hX\n",
1299 pci->name, pci->vendor, pci->dev_id));
1300
1301 nic->irqno = 0;
1302 nic->ioaddr = pci->ioaddr & ~3;
1303
1304 /* point to private storage */
1305 np = &npx;
1306
1307 adjust_pci_device(pci);
1308
1309 addr = pci_bar_start(pci, PCI_BASE_ADDRESS_0);
1310 sz = pci_bar_size(pci, PCI_BASE_ADDRESS_0);
1311
1312 /* BASE is used throughout to address the card */
1313 BASE = (unsigned long) ioremap(addr, sz);
1314 if (!BASE)
1315 return 0;
1316
1317 /* handle different descriptor versions */
1318 if (pci->dev_id == PCI_DEVICE_ID_NVIDIA_NVENET_1 ||
1319 pci->dev_id == PCI_DEVICE_ID_NVIDIA_NVENET_2 ||
1320 pci->dev_id == PCI_DEVICE_ID_NVIDIA_NVENET_3)
1321 np->desc_ver = DESC_VER_1;
1322 else
1323 np->desc_ver = DESC_VER_2;
1324
1325 //rx_ring[0] = rx_ring;
1326 //tx_ring[0] = tx_ring;
1327
1328 /* read the mac address */
1329 base = (u8 *) BASE;
1330 np->orig_mac[0] = readl(base + NvRegMacAddrA);
1331 np->orig_mac[1] = readl(base + NvRegMacAddrB);
1332
1333 nic->node_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
1334 nic->node_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
1335 nic->node_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
1336 nic->node_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
1337 nic->node_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
1338 nic->node_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
1339#ifdef LINUX
1340 if (!is_valid_ether_addr(dev->dev_addr)) {
1341 /*
1342 * Bad mac address. At least one bios sets the mac address
1343 * to 01:23:45:67:89:ab
1344 */
1345 printk(KERN_ERR
1346 "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
1347 pci_name(pci_dev), dev->dev_addr[0],
1348 dev->dev_addr[1], dev->dev_addr[2],
1349 dev->dev_addr[3], dev->dev_addr[4],
1350 dev->dev_addr[5]);
1351 printk(KERN_ERR
1352 "Please complain to your hardware vendor. Switching to a random MAC.\n");
1353 dev->dev_addr[0] = 0x00;
1354 dev->dev_addr[1] = 0x00;
1355 dev->dev_addr[2] = 0x6c;
1356 get_random_bytes(&dev->dev_addr[3], 3);
1357 }
1358#endif
1359 printf("%s: MAC Address %!, ", pci->name, nic->node_addr);
1360 /* disable WOL */
1361 writel(0, base + NvRegWakeUpFlags);
1362 np->wolenabled = 0;
1363
1364 if (np->desc_ver == DESC_VER_1) {
1365 np->tx_flags = NV_TX_LASTPACKET | NV_TX_VALID;
1366 } else {
1367 np->tx_flags = NV_TX2_LASTPACKET | NV_TX2_VALID;
1368 }
1369
1370 switch (pci->dev_id) {
1371 case 0x01C3: // nforce
1372 // DEV_IRQMASK_1|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
1373 np->irqmask = NVREG_IRQMASK_WANTED_2 | NVREG_IRQ_TIMER;
1374// np->need_linktimer = 1;
1375// np->link_timeout = jiffies + LINK_TIMEOUT;
1376 break;
1377 case 0x0066:
1378 /* Fall Through */
1379 case 0x00D6:
1380 // DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER
1381 np->irqmask = NVREG_IRQMASK_WANTED_2;
1382 np->irqmask |= NVREG_IRQ_TIMER;
1383// np->need_linktimer = 1;
1384// np->link_timeout = jiffies + LINK_TIMEOUT;
1385 if (np->desc_ver == DESC_VER_1)
1386 np->tx_flags |= NV_TX_LASTPACKET1;
1387 else
1388 np->tx_flags |= NV_TX2_LASTPACKET1;
1389 break;
1390 case 0x0086:
1391 /* Fall Through */
1392 case 0x008c:
1393 /* Fall Through */
1394 case 0x00e6:
1395 /* Fall Through */
1396 case 0x00df:
1397 /* Fall Through */
1398 case 0x0056:
1399 /* Fall Through */
1400 case 0x0057:
1401 /* Fall Through */
1402 case 0x0037:
1403 /* Fall Through */
1404 case 0x0038:
1405 //DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ
1406 np->irqmask = NVREG_IRQMASK_WANTED_2;
1407 np->irqmask |= NVREG_IRQ_TIMER;
1408// np->need_linktimer = 1;
1409// np->link_timeout = jiffies + LINK_TIMEOUT;
1410 if (np->desc_ver == DESC_VER_1)
1411 np->tx_flags |= NV_TX_LASTPACKET1;
1412 else
1413 np->tx_flags |= NV_TX2_LASTPACKET1;
1414 break;
1415 default:
1416 printf
1417 ("Your card was undefined in this driver. Review driver_data in Linux driver and send a patch\n");
1418 }
1419
1420 /* find a suitable phy */
1421 for (i = 1; i < 32; i++) {
1422 int id1, id2;
1423 id1 = mii_rw(nic, i, MII_PHYSID1, MII_READ);
1424 if (id1 < 0 || id1 == 0xffff)
1425 continue;
1426 id2 = mii_rw(nic, i, MII_PHYSID2, MII_READ);
1427 if (id2 < 0 || id2 == 0xffff)
1428 continue;
1429 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
1430 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
1431 dprintf
1432 (("%s: open: Found PHY %hX:%hX at address %d.\n",
1433 pci->name, id1, id2, i));
1434 np->phyaddr = i;
1435 np->phy_oui = id1 | id2;
1436 break;
1437 }
1438 if (i == 32) {
1439 /* PHY in isolate mode? No phy attached and user wants to
1440 * test loopback? Very odd, but can be correct.
1441 */
1442 printf
1443 ("%s: open: Could not find a valid PHY.\n", pci->name);
1444 }
1445
1446 if (i != 32) {
1447 /* reset it */
1448 phy_init(nic);
1449 }
1450 dprintf(("%s: forcedeth.c: subsystem: %hX:%hX bound to %s\n",
1451 pci->name, pci->vendor, pci->dev_id, pci->name));
1452 if(!forcedeth_reset(nic)) return 0; // no valid link
1453// if (board_found && valid_link)
1454 /* point to NIC specific routines */
1455 dev->disable = forcedeth_disable;
1456 nic->poll = forcedeth_poll;
1457 nic->transmit = forcedeth_transmit;
1458 nic->irq = forcedeth_irq;
1459 return 1;
1460// }
1461 /* else */
1462}
1463
1464static struct pci_id forcedeth_nics[] = {
1465 PCI_ROM(0x10de, 0x01C3, "nforce", "nForce NVENET_1 Ethernet Controller"),
1466 PCI_ROM(0x10de, 0x0066, "nforce2", "nForce NVENET_2 Ethernet Controller"),
1467 PCI_ROM(0x10de, 0x00D6, "nforce3", "nForce NVENET_3 Ethernet Controller"),
1468 PCI_ROM(0x10de, 0x0086, "nforce4", "nForce NVENET_4 Ethernet Controller"),
1469 PCI_ROM(0x10de, 0x008c, "nforce5", "nForce NVENET_5 Ethernet Controller"),
1470 PCI_ROM(0x10de, 0x00e6, "nforce6", "nForce NVENET_6 Ethernet Controller"),
1471 PCI_ROM(0x10de, 0x00df, "nforce7", "nForce NVENET_7 Ethernet Controller"),
1472 PCI_ROM(0x10de, 0x0056, "nforce8", "nForce NVENET_8 Ethernet Controller"),
1473 PCI_ROM(0x10de, 0x0057, "nforce9", "nForce NVENET_9 Ethernet Controller"),
1474 PCI_ROM(0x10de, 0x0037, "nforce10", "nForce NVENET_10 Ethernet Controller"),
1475 PCI_ROM(0x10de, 0x0038, "nforce11", "nForce NVENET_11 Ethernet Controller"),
1476};
1477static struct pci_driver forcedeth_driver __pci_driver = {
1478 .type = NIC_DRIVER,.name = "forcedeth",.probe =
1479 forcedeth_probe,.ids =
1480 forcedeth_nics,.id_count =
1481 sizeof(forcedeth_nics) / sizeof(forcedeth_nics[0]),.class = 0,
1482};
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