| 1 | /*
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| 2 | *
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| 3 | * modified
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| 4 | * by Steve M. Gehlbach <steve@kesa.com>
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| 5 | *
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| 6 | * Originally from linux/drivers/video/vga16.c by
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| 7 | * Ben Pfaff <pfaffben@debian.org> and Petr Vandrovec <VANDROVE@vc.cvut.cz>
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| 8 | * Copyright 1999 Ben Pfaff <pfaffben@debian.org> and Petr Vandrovec <VANDROVE@vc.cvut.cz>
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| 9 | * Based on VGA info at http://www.goodnet.com/~tinara/FreeVGA/home.htm
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| 10 | * Based on VESA framebuffer (c) 1998 Gerd Knorr <kraxel@goldbach.in-berlin.de>
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| 11 | *
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| 12 | */
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| 13 |
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| 14 | #ifndef VGA_H_INCL
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| 15 | #define VGA_H_INCL 1
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| 16 |
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| 17 | //#include <cpu/p5/io.h>
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| 18 |
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| 19 | #define u8 unsigned char
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| 20 | #define u16 unsigned short
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| 21 | #define u32 unsigned int
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| 22 | #define __u32 u32
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| 23 |
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| 24 | #define VERROR -1
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| 25 | #define CHAR_HEIGHT 16
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| 26 | #define LINES 25
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| 27 | #define COLS 80
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| 28 |
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| 29 | // macros for writing to vga regs
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| 30 | #define write_crtc(data,addr) outb(addr,CRT_IC); outb(data,CRT_DC)
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| 31 | #define write_att(data,addr) inb(IS1_RC); inb(0x80); outb(addr,ATT_IW); inb(0x80); outb(data,ATT_IW); inb(0x80)
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| 32 | #define write_seq(data,addr) outb(addr,SEQ_I); outb(data,SEQ_D)
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| 33 | #define write_gra(data,addr) outb(addr,GRA_I); outb(data,GRA_D)
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| 34 | u8 read_seq_b(u16 addr);
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| 35 | u8 read_gra_b(u16 addr);
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| 36 | u8 read_crtc_b(u16 addr);
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| 37 | u8 read_att_b(u16 addr);
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| 38 |
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| 39 |
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| 40 | #ifdef VGA_HARDWARE_FIXUP
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| 41 | void vga_hardware_fixup(void);
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| 42 | #else
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| 43 | #define vga_hardware_fixup() do{} while(0)
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| 44 | #endif
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| 45 |
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| 46 | #define SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */
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| 47 | #define SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
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| 48 | #define SYNC_EXT 4 /* external sync */
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| 49 | #define SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
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| 50 | #define SYNC_BROADCAST 16 /* broadcast video timings */
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| 51 | /* vtotal = 144d/288n/576i => PAL */
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| 52 | /* vtotal = 121d/242n/484i => NTSC */
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| 53 |
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| 54 | #define SYNC_ON_GREEN 32 /* sync on green */
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| 55 |
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| 56 | #define VMODE_NONINTERLACED 0 /* non interlaced */
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| 57 | #define VMODE_INTERLACED 1 /* interlaced */
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| 58 | #define VMODE_DOUBLE 2 /* double scan */
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| 59 | #define VMODE_MASK 255
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| 60 |
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| 61 | #define VMODE_YWRAP 256 /* ywrap instead of panning */
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| 62 | #define VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */
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| 63 | #define VMODE_CONUPDATE 512 /* don't update x/yoffset */
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| 64 |
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| 65 | /* VGA data register ports */
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| 66 | #define CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */
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| 67 | #define CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */
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| 68 | #define ATT_R 0x3C1 /* Attribute Controller Data Read Register */
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| 69 | #define GRA_D 0x3CF /* Graphics Controller Data Register */
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| 70 | #define SEQ_D 0x3C5 /* Sequencer Data Register */
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| 71 |
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| 72 | #define MIS_R 0x3CC // Misc Output Read Register
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| 73 | #define MIS_W 0x3C2 // Misc Output Write Register
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| 74 |
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| 75 | #define IS1_RC 0x3DA /* Input Status Register 1 - color emulation */
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| 76 | #define IS1_RM 0x3BA /* Input Status Register 1 - mono emulation */
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| 77 | #define PEL_D 0x3C9 /* PEL Data Register */
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| 78 | #define PEL_MSK 0x3C6 /* PEL mask register */
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| 79 |
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| 80 | /* EGA-specific registers */
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| 81 | #define GRA_E0 0x3CC /* Graphics enable processor 0 */
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| 82 | #define GRA_E1 0x3CA /* Graphics enable processor 1 */
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| 83 |
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| 84 |
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| 85 | /* VGA index register ports */
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| 86 | #define CRT_IC 0x3D4 /* CRT Controller Index - color emulation */
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| 87 | #define CRT_IM 0x3B4 /* CRT Controller Index - mono emulation */
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| 88 | #define ATT_IW 0x3C0 /* Attribute Controller Index & Data Write Register */
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| 89 | #define GRA_I 0x3CE /* Graphics Controller Index */
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| 90 | #define SEQ_I 0x3C4 /* Sequencer Index */
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| 91 | #define PEL_IW 0x3C8 /* PEL Write Index */
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| 92 | #define PEL_IR 0x3C7 /* PEL Read Index */
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| 93 |
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| 94 | /* standard VGA indexes max counts */
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| 95 | #define CRTC_C 25 /* 25 CRT Controller Registers sequentially set*/
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| 96 | // the remainder are not in the par array
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| 97 | #define ATT_C 21 /* 21 Attribute Controller Registers */
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| 98 | #define GRA_C 9 /* 9 Graphics Controller Registers */
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| 99 | #define SEQ_C 5 /* 5 Sequencer Registers */
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| 100 | #define MIS_C 1 /* 1 Misc Output Register */
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| 101 |
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| 102 | #define CRTC_H_TOTAL 0
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| 103 | #define CRTC_H_DISP 1
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| 104 | #define CRTC_H_BLANK_START 2
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| 105 | #define CRTC_H_BLANK_END 3
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| 106 | #define CRTC_H_SYNC_START 4
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| 107 | #define CRTC_H_SYNC_END 5
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| 108 | #define CRTC_V_TOTAL 6
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| 109 | #define CRTC_OVERFLOW 7
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| 110 | #define CRTC_PRESET_ROW 8
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| 111 | #define CRTC_MAX_SCAN 9
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| 112 | #define CRTC_CURSOR_START 0x0A
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| 113 | #define CRTC_CURSOR_END 0x0B
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| 114 | #define CRTC_START_HI 0x0C
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| 115 | #define CRTC_START_LO 0x0D
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| 116 | #define CRTC_CURSOR_HI 0x0E
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| 117 | #define CRTC_CURSOR_LO 0x0F
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| 118 | #define CRTC_V_SYNC_START 0x10
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| 119 | #define CRTC_V_SYNC_END 0x11
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| 120 | #define CRTC_V_DISP_END 0x12
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| 121 | #define CRTC_OFFSET 0x13
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| 122 | #define CRTC_UNDERLINE 0x14
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| 123 | #define CRTC_V_BLANK_START 0x15
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| 124 | #define CRTC_V_BLANK_END 0x16
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| 125 | #define CRTC_MODE 0x17
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| 126 | #define CRTC_LINE_COMPARE 0x18
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| 127 |
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| 128 | #define ATC_MODE 0x10
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| 129 | #define ATC_OVERSCAN 0x11
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| 130 | #define ATC_PLANE_ENABLE 0x12
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| 131 | #define ATC_PEL 0x13
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| 132 | #define ATC_COLOR_PAGE 0x14
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| 133 |
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| 134 | #define SEQ_CLOCK_MODE 0x01
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| 135 | #define SEQ_PLANE_WRITE 0x02
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| 136 | #define SEQ_CHARACTER_MAP 0x03
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| 137 | #define SEQ_MEMORY_MODE 0x04
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| 138 |
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| 139 | #define GDC_SR_VALUE 0x00
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| 140 | #define GDC_SR_ENABLE 0x01
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| 141 | #define GDC_COMPARE_VALUE 0x02
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| 142 | #define GDC_DATA_ROTATE 0x03
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| 143 | #define GDC_PLANE_READ 0x04
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| 144 | #define GDC_MODE 0x05
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| 145 | #define GDC_MISC 0x06
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| 146 | #define GDC_COMPARE_MASK 0x07
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| 147 | #define GDC_BIT_MASK 0x08
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| 148 |
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| 149 | // text attributes
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| 150 | #define VGA_ATTR_CLR_RED 0x4
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| 151 | #define VGA_ATTR_CLR_GRN 0x2
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| 152 | #define VGA_ATTR_CLR_BLU 0x1
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| 153 | #define VGA_ATTR_CLR_YEL (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN)
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| 154 | #define VGA_ATTR_CLR_CYN (VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU)
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| 155 | #define VGA_ATTR_CLR_MAG (VGA_ATTR_CLR_BLU | VGA_ATTR_CLR_RED)
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| 156 | #define VGA_ATTR_CLR_BLK 0
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| 157 | #define VGA_ATTR_CLR_WHT (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU)
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| 158 | #define VGA_ATTR_BNK 0x80
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| 159 | #define VGA_ATTR_ITN 0x08
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| 160 |
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| 161 | /*
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| 162 | * vga register parameters
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| 163 | * these are copied to the
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| 164 | * registers.
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| 165 | *
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| 166 | */
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| 167 | struct vga_par {
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| 168 | u8 crtc[CRTC_C];
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| 169 | u8 atc[ATT_C];
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| 170 | u8 gdc[GRA_C];
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| 171 | u8 seq[SEQ_C];
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| 172 | u8 misc; // the misc register, MIS_W
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| 173 | u8 vss;
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| 174 | };
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| 175 |
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| 176 |
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| 177 | /* Interpretation of offset for color fields: All offsets are from the right,
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| 178 | * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you
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| 179 | * can use the offset as right argument to <<). A pixel afterwards is a bit
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| 180 | * stream and is written to video memory as that unmodified. This implies
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| 181 | * big-endian byte order if bits_per_pixel is greater than 8.
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| 182 | */
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| 183 | struct fb_bitfield {
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| 184 | __u32 offset; /* beginning of bitfield */
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| 185 | __u32 length; /* length of bitfield */
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| 186 | __u32 msb_right; /* != 0 : Most significant bit is */
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| 187 | /* right */
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| 188 | };
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| 189 |
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| 190 | struct screeninfo {
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| 191 | __u32 xres; /* visible resolution */
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| 192 | __u32 yres;
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| 193 | __u32 xres_virtual; /* virtual resolution */
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| 194 | __u32 yres_virtual;
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| 195 | __u32 xoffset; /* offset from virtual to visible */
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| 196 | __u32 yoffset; /* resolution */
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| 197 |
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| 198 | __u32 bits_per_pixel; /* guess what */
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| 199 | __u32 grayscale; /* != 0 Graylevels instead of colors */
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| 200 |
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| 201 | struct fb_bitfield red; /* bitfield in fb mem if true color, */
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| 202 | struct fb_bitfield green; /* else only length is significant */
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| 203 | struct fb_bitfield blue;
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| 204 | struct fb_bitfield transp; /* transparency */
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| 205 |
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| 206 | __u32 nonstd; /* != 0 Non standard pixel format */
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| 207 |
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| 208 | __u32 activate; /* see FB_ACTIVATE_* */
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| 209 |
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| 210 | __u32 height; /* height of picture in mm */
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| 211 | __u32 width; /* width of picture in mm */
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| 212 |
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| 213 | __u32 accel_flags; /* acceleration flags (hints) */
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| 214 |
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| 215 | /* Timing: All values in pixclocks, except pixclock (of course) */
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| 216 | __u32 pixclock; /* pixel clock in ps (pico seconds) */
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| 217 | __u32 left_margin; /* time from sync to picture */
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| 218 | __u32 right_margin; /* time from picture to sync */
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| 219 | __u32 upper_margin; /* time from sync to picture */
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| 220 | __u32 lower_margin;
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| 221 | __u32 hsync_len; /* length of horizontal sync */
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| 222 | __u32 vsync_len; /* length of vertical sync */
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| 223 | __u32 sync; /* sync polarity */
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| 224 | __u32 vmode; /* interlaced etc */
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| 225 | __u32 reserved[6]; /* Reserved for future compatibility */
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| 226 | };
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| 227 |
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| 228 | #endif
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