VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevRTC.cpp@ 3257

Last change on this file since 3257 was 3257, checked in by vboxsync, 17 years ago

rtc_timer_update is called on every timer tick, so don't attempt LogRel unless something actually changed.
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1/* $Id: DevRTC.cpp 3257 2007-06-24 06:41:16Z vboxsync $ */
2/** @file
3 * Motorola MC146818 RTC/CMOS Device.
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * If you received this file as part of a commercial VirtualBox
18 * distribution, then only the terms of your commercial VirtualBox
19 * license agreement apply instead of the previous paragraph.
20 *
21 * --------------------------------------------------------------------
22 *
23 * This code is based on:
24 *
25 * QEMU MC146818 RTC emulation
26 *
27 * Copyright (c) 2003-2004 Fabrice Bellard
28 *
29 * Permission is hereby granted, free of charge, to any person obtaining a copy
30 * of this software and associated documentation files (the "Software"), to deal
31 * in the Software without restriction, including without limitation the rights
32 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
33 * copies of the Software, and to permit persons to whom the Software is
34 * furnished to do so, subject to the following conditions:
35 *
36 * The above copyright notice and this permission notice shall be included in
37 * all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
40 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
41 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
42 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
43 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
44 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
45 * THE SOFTWARE.
46 */
47
48/*******************************************************************************
49* Header Files *
50*******************************************************************************/
51#define LOG_GROUP LOG_GROUP_DEV_RTC
52#include <VBox/pdm.h>
53#include <VBox/log.h>
54#include <iprt/asm.h>
55#include <iprt/assert.h>
56
57#include "vl_vbox.h"
58
59/** @todo Replace struct tm with RTTIME. */
60#include <time.h>
61
62struct RTCState;
63typedef struct RTCState RTCState;
64
65#define RTC_CRC_START 0x10
66#define RTC_CRC_LAST 0x2d
67#define RTC_CRC_HIGH 0x2e
68#define RTC_CRC_LOW 0x2f
69
70#ifndef VBOX_DEVICE_STRUCT_TESTCASE
71/*******************************************************************************
72* Internal Functions *
73*******************************************************************************/
74__BEGIN_DECLS
75PDMBOTHCBDECL(int) rtcIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
76PDMBOTHCBDECL(int) rtcIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
77PDMBOTHCBDECL(void) rtcTimerPeriodic(PPDMDEVINS pDevIns, PTMTIMER pTimer);
78PDMBOTHCBDECL(void) rtcTimerSecond(PPDMDEVINS pDevIns, PTMTIMER pTimer);
79PDMBOTHCBDECL(void) rtcTimerSecond2(PPDMDEVINS pDevIns, PTMTIMER pTimer);
80__END_DECLS
81#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
82
83/*#define DEBUG_CMOS*/
84
85#define RTC_SECONDS 0
86#define RTC_SECONDS_ALARM 1
87#define RTC_MINUTES 2
88#define RTC_MINUTES_ALARM 3
89#define RTC_HOURS 4
90#define RTC_HOURS_ALARM 5
91#define RTC_ALARM_DONT_CARE 0xC0
92
93#define RTC_DAY_OF_WEEK 6
94#define RTC_DAY_OF_MONTH 7
95#define RTC_MONTH 8
96#define RTC_YEAR 9
97
98#define RTC_REG_A 10
99#define RTC_REG_B 11
100#define RTC_REG_C 12
101#define RTC_REG_D 13
102
103#define REG_A_UIP 0x80
104
105#define REG_B_SET 0x80
106#define REG_B_PIE 0x40
107#define REG_B_AIE 0x20
108#define REG_B_UIE 0x10
109
110struct RTCState {
111 uint8_t cmos_data[128];
112 uint8_t cmos_index;
113 uint8_t Alignment0[7];
114 struct tm current_tm;
115#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32 && IN_GC
116# if !defined(__WIN__)
117 uint32_t Alignment1[3];
118# endif
119#endif
120 int32_t irq;
121 /* periodic timer */
122 PTMTIMERGC pPeriodicTimerGC;
123 PTMTIMERHC pPeriodicTimerHC;
124 int64_t next_periodic_time;
125 /* second update */
126 int64_t next_second_time;
127 PTMTIMERHC pSecondTimerHC;
128 PTMTIMERGC pSecondTimerGC;
129 PTMTIMERGC pSecondTimer2GC;
130 PTMTIMERHC pSecondTimer2HC;
131 /** Pointer to the device instance - HC Ptr. */
132 PPDMDEVINSHC pDevInsHC;
133 /** Pointer to the device instance - GC Ptr. */
134 PPDMDEVINSGC pDevInsGC;
135 /** Use UTC or local time initially. */
136 bool fUTC;
137 /** The RTC registration structure. */
138 PDMRTCREG RtcReg;
139 /** The RTC device helpers. */
140 HCPTRTYPE(PCPDMRTCHLP) pRtcHlpHC;
141 /** Number of release log entries. Used to prevent flooding. */
142 uint32_t cRelLogEntries;
143 /** The current/previous timer period. Used to prevent flooding changes. */
144 uint32_t CurPeriod;
145};
146
147#ifndef VBOX_DEVICE_STRUCT_TESTCASE
148static void rtc_set_time(RTCState *s);
149static void rtc_copy_date(RTCState *s);
150
151static void rtc_timer_update(RTCState *s, int64_t current_time)
152{
153 int period_code, period;
154 uint64_t cur_clock, next_irq_clock;
155 uint32_t freq;
156
157 period_code = s->cmos_data[RTC_REG_A] & 0x0f;
158 if (period_code != 0 &&
159 (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
160 if (period_code <= 2)
161 period_code += 7;
162 /* period in 32 kHz cycles */
163 period = 1 << (period_code - 1);
164 /* compute 32 kHz clock */
165 freq = TMTimerGetFreq(s->CTXSUFF(pPeriodicTimer));
166
167 cur_clock = ASMMultU64ByU32DivByU32(current_time, 32768, freq);
168 next_irq_clock = (cur_clock & ~(uint64_t)(period - 1)) + period;
169 s->next_periodic_time = ASMMultU64ByU32DivByU32(next_irq_clock, freq, 32768) + 1;
170 TMTimerSet(s->CTXSUFF(pPeriodicTimer), s->next_periodic_time);
171
172 if (period != s->CurPeriod)
173 {
174 if (s->cRelLogEntries++ < 64)
175 LogRel(("RTC: period=%#x (%d) %u Hz\n", period, period, _32K / period));
176 s->CurPeriod = period;
177 }
178 } else {
179 if (TMTimerIsActive(s->CTXSUFF(pPeriodicTimer)) && s->cRelLogEntries++ < 64)
180 LogRel(("RTC: stopped the periodic timer\n"));
181 TMTimerStop(s->CTXSUFF(pPeriodicTimer));
182 }
183}
184
185static void rtc_periodic_timer(void *opaque)
186{
187 RTCState *s = (RTCState*)opaque;
188
189 rtc_timer_update(s, s->next_periodic_time);
190 s->cmos_data[RTC_REG_C] |= 0xc0;
191 PDMDevHlpISASetIrq(s->CTXSUFF(pDevIns), s->irq, 1);
192}
193
194static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
195{
196 RTCState *s = (RTCState*)opaque;
197
198 if ((addr & 1) == 0) {
199 s->cmos_index = data & 0x7f;
200 } else {
201 Log(("CMOS: Write idx %#04x: %#04x (old %#04x)\n", s->cmos_index, data, s->cmos_data[s->cmos_index]));
202 switch(s->cmos_index) {
203 case RTC_SECONDS_ALARM:
204 case RTC_MINUTES_ALARM:
205 case RTC_HOURS_ALARM:
206 s->cmos_data[s->cmos_index] = data;
207 break;
208 case RTC_SECONDS:
209 case RTC_MINUTES:
210 case RTC_HOURS:
211 case RTC_DAY_OF_WEEK:
212 case RTC_DAY_OF_MONTH:
213 case RTC_MONTH:
214 case RTC_YEAR:
215 s->cmos_data[s->cmos_index] = data;
216 /* if in set mode, do not update the time */
217 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
218 rtc_set_time(s);
219 }
220 break;
221 case RTC_REG_A:
222 /* UIP bit is read only */
223 s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
224 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
225 rtc_timer_update(s, TMTimerGet(s->CTXSUFF(pPeriodicTimer)));
226 break;
227 case RTC_REG_B:
228 if (data & REG_B_SET) {
229 /* set mode: reset UIP mode */
230 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
231 data &= ~REG_B_UIE;
232 } else {
233 /* if disabling set mode, update the time */
234 if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
235 rtc_set_time(s);
236 }
237 }
238 s->cmos_data[RTC_REG_B] = data;
239 rtc_timer_update(s, TMTimerGet(s->CTXSUFF(pPeriodicTimer)));
240 break;
241 case RTC_REG_C:
242 case RTC_REG_D:
243 /* cannot write to them */
244 break;
245 default:
246 s->cmos_data[s->cmos_index] = data;
247 break;
248 }
249 }
250}
251
252static inline int to_bcd(RTCState *s, int a)
253{
254 if (s->cmos_data[RTC_REG_B] & 0x04) {
255 return a;
256 } else {
257 return ((a / 10) << 4) | (a % 10);
258 }
259}
260
261static inline int from_bcd(RTCState *s, int a)
262{
263 if (s->cmos_data[RTC_REG_B] & 0x04) {
264 return a;
265 } else {
266 return ((a >> 4) * 10) + (a & 0x0f);
267 }
268}
269
270static void rtc_set_time(RTCState *s)
271{
272 struct tm *tm = &s->current_tm;
273
274 tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]);
275 tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]);
276 tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
277 if (!(s->cmos_data[RTC_REG_B] & 0x02) &&
278 (s->cmos_data[RTC_HOURS] & 0x80)) {
279 tm->tm_hour += 12;
280 }
281 tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]);
282 tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
283 tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
284 tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + 100;
285}
286
287static void rtc_copy_date(RTCState *s)
288{
289 const struct tm *tm = &s->current_tm;
290
291 s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
292 s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
293 if (s->cmos_data[RTC_REG_B] & 0x02) {
294 /* 24 hour format */
295 s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour);
296 } else {
297 /* 12 hour format */
298 s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
299 if (tm->tm_hour >= 12)
300 s->cmos_data[RTC_HOURS] |= 0x80;
301 }
302 s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday);
303 s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
304 s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
305 s->cmos_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100);
306}
307
308/* month is between 0 and 11. */
309static int get_days_in_month(int month, int year)
310{
311 static const int days_tab[12] = {
312 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
313 };
314 int d;
315 if ((unsigned )month >= 12)
316 return 31;
317 d = days_tab[month];
318 if (month == 1) {
319 if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
320 d++;
321 }
322 return d;
323}
324
325/* update 'tm' to the next second */
326static void rtc_next_second(struct tm *tm)
327{
328 int days_in_month;
329
330 tm->tm_sec++;
331 if ((unsigned)tm->tm_sec >= 60) {
332 tm->tm_sec = 0;
333 tm->tm_min++;
334 if ((unsigned)tm->tm_min >= 60) {
335 tm->tm_min = 0;
336 tm->tm_hour++;
337 if ((unsigned)tm->tm_hour >= 24) {
338 tm->tm_hour = 0;
339 /* next day */
340 tm->tm_wday++;
341 if ((unsigned)tm->tm_wday >= 7)
342 tm->tm_wday = 0;
343 days_in_month = get_days_in_month(tm->tm_mon,
344 tm->tm_year + 1900);
345 tm->tm_mday++;
346 if (tm->tm_mday < 1) {
347 tm->tm_mday = 1;
348 } else if (tm->tm_mday > days_in_month) {
349 tm->tm_mday = 1;
350 tm->tm_mon++;
351 if (tm->tm_mon >= 12) {
352 tm->tm_mon = 0;
353 tm->tm_year++;
354 }
355 }
356 }
357 }
358 }
359}
360
361
362static void rtc_update_second(void *opaque)
363{
364 RTCState *s = (RTCState*)opaque;
365 int64_t delay;
366
367 /* if the oscillator is not in normal operation, we do not update */
368 if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
369 s->next_second_time += TMTimerGetFreq(s->CTXSUFF(pSecondTimer));
370 TMTimerSet(s->CTXSUFF(pSecondTimer), s->next_second_time);
371 } else {
372 rtc_next_second(&s->current_tm);
373
374 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
375 /* update in progress bit */
376 s->cmos_data[RTC_REG_A] |= REG_A_UIP;
377 }
378 /* should be 244 us = 8 / 32768 seconds, but currently the
379 timers do not have the necessary resolution. */
380 delay = (TMTimerGetFreq(s->CTXSUFF(pSecondTimer2)) * 1) / 100;
381 if (delay < 1)
382 delay = 1;
383 TMTimerSet(s->CTXSUFF(pSecondTimer2), s->next_second_time + delay);
384 }
385}
386
387static void rtc_update_second2(void *opaque)
388{
389 RTCState *s = (RTCState*)opaque;
390
391 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
392 rtc_copy_date(s);
393 }
394
395 /* check alarm */
396 if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
397 if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
398 from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]) == s->current_tm.tm_sec) &&
399 ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
400 from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]) == s->current_tm.tm_min) &&
401 ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
402 from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]) == s->current_tm.tm_hour)) {
403
404 s->cmos_data[RTC_REG_C] |= 0xa0;
405 PDMDevHlpISASetIrq(s->CTXSUFF(pDevIns), s->irq, 1);
406 }
407 }
408
409 /* update ended interrupt */
410 if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
411 s->cmos_data[RTC_REG_C] |= 0x90;
412 PDMDevHlpISASetIrq(s->CTXSUFF(pDevIns), s->irq, 1);
413 }
414
415 /* clear update in progress bit */
416 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
417
418 s->next_second_time += TMTimerGetFreq(s->CTXSUFF(pSecondTimer));
419 TMTimerSet(s->CTXSUFF(pSecondTimer), s->next_second_time);
420}
421
422static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
423{
424 RTCState *s = (RTCState*)opaque;
425 int ret;
426 if ((addr & 1) == 0) {
427 return 0xff;
428 } else {
429 switch(s->cmos_index) {
430 case RTC_SECONDS:
431 case RTC_MINUTES:
432 case RTC_HOURS:
433 case RTC_DAY_OF_WEEK:
434 case RTC_DAY_OF_MONTH:
435 case RTC_MONTH:
436 case RTC_YEAR:
437 ret = s->cmos_data[s->cmos_index];
438 break;
439 case RTC_REG_A:
440 ret = s->cmos_data[s->cmos_index];
441 break;
442 case RTC_REG_C:
443 ret = s->cmos_data[s->cmos_index];
444 PDMDevHlpISASetIrq(s->CTXSUFF(pDevIns), s->irq, 0);
445 s->cmos_data[RTC_REG_C] = 0x00;
446 break;
447 default:
448 ret = s->cmos_data[s->cmos_index];
449 break;
450 }
451 Log(("CMOS: Read idx %#04x: %#04x\n", s->cmos_index, ret));
452 return ret;
453 }
454}
455
456#ifdef IN_RING3
457static void rtc_set_memory(RTCState *s, int addr, int val)
458{
459 if (addr >= 0 && addr <= 127)
460 s->cmos_data[addr] = val;
461}
462
463static void rtc_set_date(RTCState *s, const struct tm *tm)
464{
465 s->current_tm = *tm;
466 rtc_copy_date(s);
467}
468
469static void rtc_save(QEMUFile *f, void *opaque)
470{
471 RTCState *s = (RTCState*)opaque;
472
473 qemu_put_buffer(f, s->cmos_data, 128);
474 qemu_put_8s(f, &s->cmos_index);
475
476 qemu_put_be32s(f, &s->current_tm.tm_sec);
477 qemu_put_be32s(f, &s->current_tm.tm_min);
478 qemu_put_be32s(f, &s->current_tm.tm_hour);
479 qemu_put_be32s(f, &s->current_tm.tm_wday);
480 qemu_put_be32s(f, &s->current_tm.tm_mday);
481 qemu_put_be32s(f, &s->current_tm.tm_mon);
482 qemu_put_be32s(f, &s->current_tm.tm_year);
483
484 qemu_put_timer(f, s->CTXSUFF(pPeriodicTimer));
485 qemu_put_be64s(f, &s->next_periodic_time);
486
487 qemu_put_be64s(f, &s->next_second_time);
488 qemu_put_timer(f, s->CTXSUFF(pSecondTimer));
489 qemu_put_timer(f, s->CTXSUFF(pSecondTimer2));
490
491}
492
493static int rtc_load(QEMUFile *f, void *opaque, int version_id)
494{
495 RTCState *s = (RTCState*)opaque;
496
497 if (version_id != 1)
498 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
499
500 qemu_get_buffer(f, s->cmos_data, 128);
501 qemu_get_8s(f, &s->cmos_index);
502
503 qemu_get_be32s(f, (uint32_t *)&s->current_tm.tm_sec);
504 qemu_get_be32s(f, (uint32_t *)&s->current_tm.tm_min);
505 qemu_get_be32s(f, (uint32_t *)&s->current_tm.tm_hour);
506 qemu_get_be32s(f, (uint32_t *)&s->current_tm.tm_wday);
507 qemu_get_be32s(f, (uint32_t *)&s->current_tm.tm_mday);
508 qemu_get_be32s(f, (uint32_t *)&s->current_tm.tm_mon);
509 qemu_get_be32s(f, (uint32_t *)&s->current_tm.tm_year);
510
511 qemu_get_timer(f, s->CTXSUFF(pPeriodicTimer));
512
513 qemu_get_be64s(f, (uint64_t *)&s->next_periodic_time);
514
515 qemu_get_be64s(f, (uint64_t *)&s->next_second_time);
516 qemu_get_timer(f, s->CTXSUFF(pSecondTimer));
517 qemu_get_timer(f, s->CTXSUFF(pSecondTimer2));
518
519 int period_code = s->cmos_data[RTC_REG_A] & 0x0f;
520 if ( period_code != 0
521 && (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
522 if (period_code <= 2)
523 period_code += 7;
524 int period = 1 << (period_code - 1);
525 LogRel(("RTC: period=%#x (%d) %u Hz (restore)\n", period, period, _32K / period));
526 s->CurPeriod = period;
527 } else {
528 LogRel(("RTC: stopped the periodic timer (restore)\n"));
529 s->CurPeriod = 0;
530 }
531 s->cRelLogEntries = 0;
532 return 0;
533}
534#endif /* IN_RING3 */
535
536/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
537
538/**
539 * Port I/O Handler for IN operations.
540 *
541 * @returns VBox status code.
542 *
543 * @param pDevIns The device instance.
544 * @param pvUser User argument - ignored.
545 * @param uPort Port number used for the IN operation.
546 * @param pu32 Where to store the result.
547 * @param cb Number of bytes read.
548 */
549PDMBOTHCBDECL(int) rtcIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
550{
551 NOREF(pvUser);
552 if (cb == 1)
553 {
554 *pu32 = cmos_ioport_read(PDMINS2DATA(pDevIns, RTCState *), Port);
555 return VINF_SUCCESS;
556 }
557 return VERR_IOM_IOPORT_UNUSED;
558}
559
560
561/**
562 * Port I/O Handler for OUT operations.
563 *
564 * @returns VBox status code.
565 *
566 * @param pDevIns The device instance.
567 * @param pvUser User argument - ignored.
568 * @param uPort Port number used for the IN operation.
569 * @param u32 The value to output.
570 * @param cb The value size in bytes.
571 */
572PDMBOTHCBDECL(int) rtcIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
573{
574 NOREF(pvUser);
575 if (cb == 1)
576 cmos_ioport_write(PDMINS2DATA(pDevIns, RTCState *), Port, u32);
577 return VINF_SUCCESS;
578}
579
580
581/**
582 * Device timer callback function, periodic.
583 *
584 * @param pDevIns Device instance of the device which registered the timer.
585 * @param pTimer The timer handle.
586 */
587PDMBOTHCBDECL(void) rtcTimerPeriodic(PPDMDEVINS pDevIns, PTMTIMER pTimer)
588{
589 rtc_periodic_timer(PDMINS2DATA(pDevIns, RTCState *));
590}
591
592
593/**
594 * Device timer callback function, second.
595 *
596 * @param pDevIns Device instance of the device which registered the timer.
597 * @param pTimer The timer handle.
598 */
599PDMBOTHCBDECL(void) rtcTimerSecond(PPDMDEVINS pDevIns, PTMTIMER pTimer)
600{
601 rtc_update_second(PDMINS2DATA(pDevIns, RTCState *));
602}
603
604
605/**
606 * Device timer callback function, second2.
607 *
608 * @param pDevIns Device instance of the device which registered the timer.
609 * @param pTimer The timer handle.
610 */
611PDMBOTHCBDECL(void) rtcTimerSecond2(PPDMDEVINS pDevIns, PTMTIMER pTimer)
612{
613 rtc_update_second2(PDMINS2DATA(pDevIns, RTCState *));
614}
615
616
617#ifdef IN_RING3
618/**
619 * Saves a state of the programmable interval timer device.
620 *
621 * @returns VBox status code.
622 * @param pDevIns The device instance.
623 * @param pSSMHandle The handle to save the state to.
624 */
625static DECLCALLBACK(int) rtcSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
626{
627 RTCState *pData = PDMINS2DATA(pDevIns, RTCState *);
628 rtc_save(pSSMHandle, pData);
629 return VINF_SUCCESS;
630}
631
632
633/**
634 * Loads a saved programmable interval timer device state.
635 *
636 * @returns VBox status code.
637 * @param pDevIns The device instance.
638 * @param pSSMHandle The handle to the saved state.
639 * @param u32Version The data unit version number.
640 */
641static DECLCALLBACK(int) rtcLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
642{
643 RTCState *pData = PDMINS2DATA(pDevIns, RTCState *);
644 return rtc_load(pSSMHandle, pData, u32Version);
645}
646
647
648/* -=-=-=-=-=- PDM Interface provided by the RTC device -=-=-=-=-=- */
649
650/**
651 * Calculate and update the standard CMOS checksum.
652 *
653 * @param pData Pointer to the RTC state data.
654 */
655static void rtcCalcCRC(RTCState *pData)
656{
657 uint16_t u16;
658 unsigned i;
659
660 for (i = RTC_CRC_START, u16 = 0; i <= RTC_CRC_LAST; i++)
661 u16 += pData->cmos_data[i];
662 pData->cmos_data[RTC_CRC_LOW] = u16 & 0xff;
663 pData->cmos_data[RTC_CRC_HIGH] = (u16 >> 8) & 0xff;
664}
665
666
667/**
668 * Write to a CMOS register and update the checksum if necessary.
669 *
670 * @returns VBox status code.
671 * @param pDevIns Device instance of the RTC.
672 * @param iReg The CMOS register index.
673 * @param u8Value The CMOS register value.
674 */
675static DECLCALLBACK(int) rtcCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
676{
677 RTCState *pData = PDMINS2DATA(pDevIns, RTCState *);
678 if (iReg < ELEMENTS(pData->cmos_data))
679 {
680 pData->cmos_data[iReg] = u8Value;
681
682 /* does it require checksum update? */
683 if ( iReg >= RTC_CRC_START
684 && iReg <= RTC_CRC_LAST)
685 rtcCalcCRC(pData);
686
687 return VINF_SUCCESS;
688 }
689 AssertMsgFailed(("iReg=%d\n", iReg));
690 return VERR_INVALID_PARAMETER;
691}
692
693
694/**
695 * Read a CMOS register.
696 *
697 * @returns VBox status code.
698 * @param pDevIns Device instance of the RTC.
699 * @param iReg The CMOS register index.
700 * @param pu8Value Where to store the CMOS register value.
701 */
702static DECLCALLBACK(int) rtcCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
703{
704 RTCState *pData = PDMINS2DATA(pDevIns, RTCState *);
705 if (iReg < ELEMENTS(pData->cmos_data))
706 {
707 *pu8Value = pData->cmos_data[iReg];
708 return VINF_SUCCESS;
709 }
710 AssertMsgFailed(("iReg=%d\n", iReg));
711 return VERR_INVALID_PARAMETER;
712}
713
714
715/* -=-=-=-=-=- based on bits from pc.c -=-=-=-=-=- */
716
717/** @copydoc FNPDMDEVINITCOMPLETE */
718static DECLCALLBACK(int) rtcInitComplete(PPDMDEVINS pDevIns)
719{
720 /** @todo this should be (re)done at power on if we didn't load a state... */
721 RTCState *pData = PDMINS2DATA(pDevIns, RTCState *);
722 struct tm Tm;
723 struct tm *pTm;
724
725 /*
726 * Set the CMOS date/time.
727 */
728 RTTIMESPEC Now;
729 PDMDevHlpUTCNow(pDevIns, &Now);
730 RTTIME Time;
731 if (pData->fUTC)
732 RTTimeExplode(&Time, &Now);
733 else
734 RTTimeLocalExplode(&Time, &Now);
735
736 memset(&Tm, 0, sizeof(Tm));
737 Tm.tm_year = Time.i32Year - 1900;
738 Tm.tm_mon = Time.u8Month - 1;
739 Tm.tm_mday = Time.u8MonthDay;
740 Tm.tm_wday = (Time.u8WeekDay - 1 + 7) % 7; /* 0 = monday -> sunday */
741 Tm.tm_yday = Time.u16YearDay - 1;
742 Tm.tm_hour = Time.u8Hour;
743 Tm.tm_min = Time.u8Minute;
744 Tm.tm_sec = Time.u8Second;
745 Tm.tm_isdst = -1;
746 pTm = &Tm;
747
748 rtc_set_date(pData, pTm);
749
750 int iYear = to_bcd(pData, (Tm.tm_year / 100) + 19); /* tm_year is 1900 based */
751 rtc_set_memory(pData, 0x32, iYear); /* 32h - Century Byte (BCD value for the century */
752 rtc_set_memory(pData, 0x37, iYear); /* 37h - (IBM PS/2) Date Century Byte */
753
754 /*
755 * Recalculate the checksum just in case.
756 */
757 rtcCalcCRC(pData);
758
759 Log(("CMOS: \n%16.128Vhxd\n", pData->cmos_data));
760 return VINF_SUCCESS;
761}
762
763
764/* -=-=-=-=-=- real code -=-=-=-=-=- */
765
766/**
767 * @copydoc
768 */
769static DECLCALLBACK(void) rtcRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
770{
771 RTCState *pThis = PDMINS2DATA(pDevIns, RTCState *);
772
773 pThis->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
774 pThis->pPeriodicTimerGC = TMTimerGCPtr(pThis->pPeriodicTimerHC);
775 pThis->pSecondTimerGC = TMTimerGCPtr(pThis->pSecondTimerHC);
776 pThis->pSecondTimer2GC = TMTimerGCPtr(pThis->pSecondTimer2HC);
777}
778
779
780/**
781 * Construct a device instance for a VM.
782 *
783 * @returns VBox status.
784 * @param pDevIns The device instance data.
785 * If the registration structure is needed, pDevIns->pDevReg points to it.
786 * @param iInstance Instance number. Use this to figure out which registers and such to use.
787 * The device number is also found in pDevIns->iInstance, but since it's
788 * likely to be freqently used PDM passes it as parameter.
789 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
790 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
791 * iInstance it's expected to be used a bit in this function.
792 */
793static DECLCALLBACK(int) rtcConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
794{
795 RTCState *pData = PDMINS2DATA(pDevIns, RTCState *);
796 int rc;
797 uint8_t u8Irq;
798 uint16_t u16Base;
799 bool fGCEnabled;
800 bool fR0Enabled;
801 Assert(iInstance == 0);
802
803 /*
804 * Validate configuration.
805 */
806 if (!CFGMR3AreValuesValid(pCfgHandle, "Irq\0Base\0GCEnabled\0fR0Enabled\0"))
807 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
808
809 /*
810 * Init the data.
811 */
812 rc = CFGMR3QueryU8(pCfgHandle, "Irq", &u8Irq);
813 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
814 u8Irq = 8;
815 else if (VBOX_FAILURE(rc))
816 return PDMDEV_SET_ERROR(pDevIns, rc,
817 N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
818
819 rc = CFGMR3QueryU16(pCfgHandle, "Base", &u16Base);
820 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
821 u16Base = 0x70;
822 else if (VBOX_FAILURE(rc))
823 return PDMDEV_SET_ERROR(pDevIns, rc,
824 N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
825
826 rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
827 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
828 fGCEnabled = false/*true*/; /** @todo later when we've got more than 15-30 switches to save. */
829 else if (VBOX_FAILURE(rc))
830 return PDMDEV_SET_ERROR(pDevIns, rc,
831 N_("Configuration error: failed to read GCEnabled as boolean"));
832
833 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
834 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
835 fR0Enabled = true;
836 else if (VBOX_FAILURE(rc))
837 return PDMDEV_SET_ERROR(pDevIns, rc,
838 N_("Configuration error: failed to read R0Enabled as boolean"));
839
840 Log(("CMOS: fGCEnabled=%d fR0Enabled=%d\n", fGCEnabled, fR0Enabled));
841
842
843 pData->pDevInsHC = pDevIns;
844 pData->irq = u8Irq;
845 pData->cmos_data[RTC_REG_A] = 0x26;
846 pData->cmos_data[RTC_REG_B] = 0x02;
847 pData->cmos_data[RTC_REG_C] = 0x00;
848 pData->cmos_data[RTC_REG_D] = 0x80;
849 pData->RtcReg.u32Version = PDM_RTCREG_VERSION;
850 pData->RtcReg.pfnRead = rtcCMOSRead;
851 pData->RtcReg.pfnWrite = rtcCMOSWrite;
852
853 /*
854 * Create timers, arm them, register I/O Ports and save state.
855 */
856 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, rtcTimerPeriodic, "MC146818 RTC/CMOS - Periodic", &pData->pPeriodicTimerHC);
857 if (VBOX_FAILURE(rc))
858 {
859 AssertMsgFailed(("pfnTMTimerCreate -> %Vrc\n", rc));
860 return rc;
861 }
862 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, rtcTimerSecond, "MC146818 RTC/CMOS - Second", &pData->pSecondTimerHC);
863 if (VBOX_FAILURE(rc))
864 {
865 AssertMsgFailed(("pfnTMTimerCreate -> %Vrc\n", rc));
866 return rc;
867 }
868 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, rtcTimerSecond2, "MC146818 RTC/CMOS - Second2", &pData->pSecondTimer2HC);
869 if (VBOX_FAILURE(rc))
870 {
871 AssertMsgFailed(("pfnTMTimerCreate -> %Vrc\n", rc));
872 return rc;
873 }
874 pData->next_second_time = TMTimerGet(pData->CTXSUFF(pSecondTimer2)) + (TMTimerGetFreq(pData->CTXSUFF(pSecondTimer2)) * 99) / 100;
875 TMTimerSet(pData->CTXSUFF(pSecondTimer2), pData->next_second_time);
876
877 rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 2, NULL, rtcIOPortWrite, rtcIOPortRead, NULL, NULL, "MC146818 RTC/CMOS");
878 if (VBOX_FAILURE(rc))
879 return rc;
880 if (fGCEnabled)
881 {
882 rc = PDMDevHlpIOPortRegisterGC(pDevIns, u16Base, 2, 0, "rtcIOPortWrite", "rtcIOPortRead", NULL, NULL, "MC146818 RTC/CMOS");
883 if (VBOX_FAILURE(rc))
884 return rc;
885 }
886 if (fR0Enabled)
887 {
888 rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 2, 0, "rtcIOPortWrite", "rtcIOPortRead", NULL, NULL, "MC146818 RTC/CMOS");
889 if (VBOX_FAILURE(rc))
890 return rc;
891 }
892
893 rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version */, sizeof(*pData),
894 NULL, rtcSaveExec, NULL,
895 NULL, rtcLoadExec, NULL);
896 if (VBOX_FAILURE(rc))
897 return rc;
898
899 /*
900 * Register ourselves as the RTC with PDM.
901 */
902 rc = pDevIns->pDevHlp->pfnRTCRegister(pDevIns, &pData->RtcReg, &pData->pRtcHlpHC);
903 if (VBOX_FAILURE(rc))
904 return rc;
905
906 return VINF_SUCCESS;
907}
908
909
910/**
911 * The device registration structure.
912 */
913const PDMDEVREG g_DeviceMC146818 =
914{
915 /* u32Version */
916 PDM_DEVREG_VERSION,
917 /* szDeviceName */
918 "mc146818",
919 /* szGCMod */
920 "VBoxDDGC.gc",
921 /* szR0Mod */
922 "VBoxDDR0.r0",
923 /* pszDescription */
924 "Motorola MC146818 RTC/CMOS Device.",
925 /* fFlags */
926 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36 | PDM_DEVREG_FLAGS_GC | PDM_DEVREG_FLAGS_R0,
927 /* fClass */
928 PDM_DEVREG_CLASS_RTC,
929 /* cMaxInstances */
930 1,
931 /* cbInstance */
932 sizeof(RTCState),
933 /* pfnConstruct */
934 rtcConstruct,
935 /* pfnDestruct */
936 NULL,
937 /* pfnRelocate */
938 rtcRelocate,
939 /* pfnIOCtl */
940 NULL,
941 /* pfnPowerOn */
942 NULL,
943 /* pfnReset */
944 NULL,
945 /* pfnSuspend */
946 NULL,
947 /* pfnResume */
948 NULL,
949 /* pfnAttach */
950 NULL,
951 /* pfnDetach */
952 NULL,
953 /* pfnQueryInterface */
954 NULL,
955 /* pfnInitComplete */
956 rtcInitComplete
957};
958#endif /* IN_RING3 */
959#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
960
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