DevRTC.cpp@ 11280

Last change on this file since 11280 was 11269, checked in by vboxsync, 16 years ago
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1	/* $Id: DevRTC.cpp 11269 2008-08-08 16:24:48Z vboxsync $ */
2	/** @file
3	* Motorola MC146818 RTC/CMOS Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	* --------------------------------------------------------------------
21	*
22	* This code is based on:
23	*
24	* QEMU MC146818 RTC emulation
25	*
26	* Copyright (c) 2003-2004 Fabrice Bellard
27	*
28	* Permission is hereby granted, free of charge, to any person obtaining a copy
29	* of this software and associated documentation files (the "Software"), to deal
30	* in the Software without restriction, including without limitation the rights
31	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
32	* copies of the Software, and to permit persons to whom the Software is
33	* furnished to do so, subject to the following conditions:
34	*
35	* The above copyright notice and this permission notice shall be included in
36	* all copies or substantial portions of the Software.
37	*
38	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
39	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
40	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
41	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
42	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
43	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
44	* THE SOFTWARE.
45	*/
46
47	/*******************************************************************************
48	* Header Files *
49	*******************************************************************************/
50	#define LOG_GROUP LOG_GROUP_DEV_RTC
51	#include <VBox/pdmdev.h>
52	#include <VBox/log.h>
53	#include <iprt/asm.h>
54	#include <iprt/assert.h>
55	#include <iprt/string.h>
56
57	#include "../Builtins.h"
58
59	struct RTCState;
60	typedef struct RTCState RTCState;
61
62	#define RTC_CRC_START 0x10
63	#define RTC_CRC_LAST 0x2d
64	#define RTC_CRC_HIGH 0x2e
65	#define RTC_CRC_LOW 0x2f
66
67
68	/*******************************************************************************
69	* Internal Functions *
70	*******************************************************************************/
71	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
72	__BEGIN_DECLS
73	PDMBOTHCBDECL(int) rtcIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
74	PDMBOTHCBDECL(int) rtcIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
75	PDMBOTHCBDECL(void) rtcTimerPeriodic(PPDMDEVINS pDevIns, PTMTIMER pTimer);
76	PDMBOTHCBDECL(void) rtcTimerSecond(PPDMDEVINS pDevIns, PTMTIMER pTimer);
77	PDMBOTHCBDECL(void) rtcTimerSecond2(PPDMDEVINS pDevIns, PTMTIMER pTimer);
78	__END_DECLS
79	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
80
81
82	/*******************************************************************************
83	* Defined Constants And Macros *
84	*******************************************************************************/
85	/#define DEBUG_CMOS/
86
87	#define RTC_SECONDS 0
88	#define RTC_SECONDS_ALARM 1
89	#define RTC_MINUTES 2
90	#define RTC_MINUTES_ALARM 3
91	#define RTC_HOURS 4
92	#define RTC_HOURS_ALARM 5
93	#define RTC_ALARM_DONT_CARE 0xC0
94
95	#define RTC_DAY_OF_WEEK 6
96	#define RTC_DAY_OF_MONTH 7
97	#define RTC_MONTH 8
98	#define RTC_YEAR 9
99
100	#define RTC_REG_A 10
101	#define RTC_REG_B 11
102	#define RTC_REG_C 12
103	#define RTC_REG_D 13
104
105	#define REG_A_UIP 0x80
106
107	#define REG_B_SET 0x80
108	#define REG_B_PIE 0x40
109	#define REG_B_AIE 0x20
110	#define REG_B_UIE 0x10
111
112
113	/*******************************************************************************
114	* Structures and Typedefs *
115	*******************************************************************************/
116	/** @todo Replace struct my_tm with RTTIME. */
117	struct my_tm
118	{
119	int32_t tm_sec;
120	int32_t tm_min;
121	int32_t tm_hour;
122	int32_t tm_mday;
123	int32_t tm_mon;
124	int32_t tm_year;
125	int32_t tm_wday;
126	int32_t tm_yday;
127	};
128
129
130	struct RTCState {
131	uint8_t cmos_data[128];
132	uint8_t cmos_index;
133	uint8_t Alignment0[7];
134	struct my_tm current_tm;
135	int32_t irq;
136	/** Use UTC or local time initially. */
137	bool fUTC;
138	/* periodic timer */
139	int64_t next_periodic_time;
140	/* second update */
141	int64_t next_second_time;
142
143	/** Pointer to the device instance - R3 Ptr. */
144	PPDMDEVINSR3 pDevInsR3;
145	/** The periodic timer (rtcTimerPeriodic) - R3 Ptr. */
146	PTMTIMERR3 pPeriodicTimerR3;
147	/** The second timer (rtcTimerSecond) - R3 Ptr. */
148	PTMTIMERR3 pSecondTimerR3;
149	/** The second second timer (rtcTimerSecond2) - R3 Ptr. */
150	PTMTIMERR3 pSecondTimer2R3;
151
152	/** Pointer to the device instance - R0 Ptr. */
153	PPDMDEVINSR0 pDevInsR0;
154	/** The periodic timer (rtcTimerPeriodic) - R0 Ptr. */
155	PTMTIMERR0 pPeriodicTimerR0;
156	/** The second timer (rtcTimerSecond) - R0 Ptr. */
157	PTMTIMERR0 pSecondTimerR0;
158	/** The second second timer (rtcTimerSecond2) - R0 Ptr. */
159	PTMTIMERR0 pSecondTimer2R0;
160
161	/** Pointer to the device instance - RC Ptr. */
162	PPDMDEVINSRC pDevInsRC;
163	/** The periodic timer (rtcTimerPeriodic) - RC Ptr. */
164	PTMTIMERRC pPeriodicTimerRC;
165	/** The second timer (rtcTimerSecond) - RC Ptr. */
166	PTMTIMERRC pSecondTimerRC;
167	/** The second second timer (rtcTimerSecond2) - RC Ptr. */
168	PTMTIMERRC pSecondTimer2RC;
169
170	/** The RTC registration structure. */
171	PDMRTCREG RtcReg;
172	/** The RTC device helpers. */
173	R3PTRTYPE(PCPDMRTCHLP) pRtcHlpR3;
174	/** Number of release log entries. Used to prevent flooding. */
175	uint32_t cRelLogEntries;
176	/** The current/previous timer period. Used to prevent flooding changes. */
177	int32_t CurPeriod;
178	};
179
180	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
181	static void rtc_set_time(RTCState *s);
182	static void rtc_copy_date(RTCState *s);
183
184	static void rtc_timer_update(RTCState *s, int64_t current_time)
185	{
186	int period_code, period;
187	uint64_t cur_clock, next_irq_clock;
188	uint32_t freq;
189
190	period_code = s->cmos_data[RTC_REG_A] & 0x0f;
191	if (period_code != 0 &&
192	(s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
193	if (period_code <= 2)
194	period_code += 7;
195	/* period in 32 kHz cycles */
196	period = 1 << (period_code - 1);
197	/* compute 32 kHz clock */
198	freq = TMTimerGetFreq(s->CTX_SUFF(pPeriodicTimer));
199
200	cur_clock = ASMMultU64ByU32DivByU32(current_time, 32768, freq);
201	next_irq_clock = (cur_clock & ~(uint64_t)(period - 1)) + period;
202	s->next_periodic_time = ASMMultU64ByU32DivByU32(next_irq_clock, freq, 32768) + 1;
203	TMTimerSet(s->CTX_SUFF(pPeriodicTimer), s->next_periodic_time);
204
205	if (period != s->CurPeriod)
206	{
207	if (s->cRelLogEntries++ < 64)
208	LogRel(("RTC: period=%#x (%d) %u Hz\n", period, period, _32K / period));
209	s->CurPeriod = period;
210	}
211	} else {
212	if (TMTimerIsActive(s->CTX_SUFF(pPeriodicTimer)) && s->cRelLogEntries++ < 64)
213	LogRel(("RTC: stopped the periodic timer\n"));
214	TMTimerStop(s->CTX_SUFF(pPeriodicTimer));
215	}
216	}
217
218	static void rtc_periodic_timer(void *opaque)
219	{
220	RTCState s = (RTCState)opaque;
221
222	rtc_timer_update(s, s->next_periodic_time);
223	s->cmos_data[RTC_REG_C] \|= 0xc0;
224	PDMDevHlpISASetIrq(s->CTX_SUFF(pDevIns), s->irq, 1);
225	}
226
227	static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
228	{
229	RTCState s = (RTCState)opaque;
230
231	if ((addr & 1) == 0) {
232	s->cmos_index = data & 0x7f;
233	} else {
234	Log(("CMOS: Write idx %#04x: %#04x (old %#04x)\n", s->cmos_index, data, s->cmos_data[s->cmos_index]));
235	switch(s->cmos_index) {
236	case RTC_SECONDS_ALARM:
237	case RTC_MINUTES_ALARM:
238	case RTC_HOURS_ALARM:
239	s->cmos_data[s->cmos_index] = data;
240	break;
241	case RTC_SECONDS:
242	case RTC_MINUTES:
243	case RTC_HOURS:
244	case RTC_DAY_OF_WEEK:
245	case RTC_DAY_OF_MONTH:
246	case RTC_MONTH:
247	case RTC_YEAR:
248	s->cmos_data[s->cmos_index] = data;
249	/* if in set mode, do not update the time */
250	if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
251	rtc_set_time(s);
252	}
253	break;
254	case RTC_REG_A:
255	/* UIP bit is read only */
256	s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) \|
257	(s->cmos_data[RTC_REG_A] & REG_A_UIP);
258	rtc_timer_update(s, TMTimerGet(s->CTX_SUFF(pPeriodicTimer)));
259	break;
260	case RTC_REG_B:
261	if (data & REG_B_SET) {
262	/* set mode: reset UIP mode */
263	s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
264	#if 0 /* This is probably wrong as it breaks changing the time/date in OS/2. */
265	data &= ~REG_B_UIE;
266	#endif
267	} else {
268	/* if disabling set mode, update the time */
269	if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
270	rtc_set_time(s);
271	}
272	}
273	s->cmos_data[RTC_REG_B] = data;
274	rtc_timer_update(s, TMTimerGet(s->CTX_SUFF(pPeriodicTimer)));
275	break;
276	case RTC_REG_C:
277	case RTC_REG_D:
278	/* cannot write to them */
279	break;
280	default:
281	s->cmos_data[s->cmos_index] = data;
282	break;
283	}
284	}
285	}
286
287	static inline int to_bcd(RTCState *s, int a)
288	{
289	if (s->cmos_data[RTC_REG_B] & 0x04) {
290	return a;
291	} else {
292	return ((a / 10) << 4) \| (a % 10);
293	}
294	}
295
296	static inline int from_bcd(RTCState *s, int a)
297	{
298	if (s->cmos_data[RTC_REG_B] & 0x04) {
299	return a;
300	} else {
301	return ((a >> 4) * 10) + (a & 0x0f);
302	}
303	}
304
305	static void rtc_set_time(RTCState *s)
306	{
307	struct my_tm *tm = &s->current_tm;
308
309	tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]);
310	tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]);
311	tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
312	if (!(s->cmos_data[RTC_REG_B] & 0x02) &&
313	(s->cmos_data[RTC_HOURS] & 0x80)) {
314	tm->tm_hour += 12;
315	}
316	tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]);
317	tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
318	tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
319	tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + 100;
320	}
321
322	static void rtc_copy_date(RTCState *s)
323	{
324	const struct my_tm *tm = &s->current_tm;
325
326	s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
327	s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
328	if (s->cmos_data[RTC_REG_B] & 0x02) {
329	/* 24 hour format */
330	s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour);
331	} else {
332	/* 12 hour format */
333	s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
334	if (tm->tm_hour >= 12)
335	s->cmos_data[RTC_HOURS] \|= 0x80;
336	}
337	s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday);
338	s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
339	s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
340	s->cmos_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100);
341	}
342
343	/* month is between 0 and 11. */
344	static int get_days_in_month(int month, int year)
345	{
346	static const int days_tab[12] = {
347	31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
348	};
349	int d;
350	if ((unsigned )month >= 12)
351	return 31;
352	d = days_tab[month];
353	if (month == 1) {
354	if ((year % 4) == 0 && ((year % 100) != 0 \|\| (year % 400) == 0))
355	d++;
356	}
357	return d;
358	}
359
360	/* update 'tm' to the next second */
361	static void rtc_next_second(struct my_tm *tm)
362	{
363	int days_in_month;
364
365	tm->tm_sec++;
366	if ((unsigned)tm->tm_sec >= 60) {
367	tm->tm_sec = 0;
368	tm->tm_min++;
369	if ((unsigned)tm->tm_min >= 60) {
370	tm->tm_min = 0;
371	tm->tm_hour++;
372	if ((unsigned)tm->tm_hour >= 24) {
373	tm->tm_hour = 0;
374	/* next day */
375	tm->tm_wday++;
376	if ((unsigned)tm->tm_wday >= 7)
377	tm->tm_wday = 0;
378	days_in_month = get_days_in_month(tm->tm_mon,
379	tm->tm_year + 1900);
380	tm->tm_mday++;
381	if (tm->tm_mday < 1) {
382	tm->tm_mday = 1;
383	} else if (tm->tm_mday > days_in_month) {
384	tm->tm_mday = 1;
385	tm->tm_mon++;
386	if (tm->tm_mon >= 12) {
387	tm->tm_mon = 0;
388	tm->tm_year++;
389	}
390	}
391	}
392	}
393	}
394	}
395
396
397	static void rtc_update_second(void *opaque)
398	{
399	RTCState s = (RTCState)opaque;
400
401	/* if the oscillator is not in normal operation, we do not update */
402	if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
403	s->next_second_time += TMTimerGetFreq(s->CTX_SUFF(pSecondTimer));
404	TMTimerSet(s->CTX_SUFF(pSecondTimer), s->next_second_time);
405	} else {
406	rtc_next_second(&s->current_tm);
407
408	if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
409	/* update in progress bit */
410	s->cmos_data[RTC_REG_A] \|= REG_A_UIP;
411	}
412
413	/* 244140 ns = 8 / 32768 seconds */
414	uint64_t delay = TMTimerFromNano(s->CTX_SUFF(pSecondTimer2), 244140);
415	TMTimerSet(s->CTX_SUFF(pSecondTimer2), s->next_second_time + delay);
416	}
417	}
418
419	static void rtc_update_second2(void *opaque)
420	{
421	RTCState s = (RTCState)opaque;
422
423	if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
424	rtc_copy_date(s);
425	}
426
427	/* check alarm */
428	if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
429	if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 \|\|
430	from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]) == s->current_tm.tm_sec) &&
431	((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 \|\|
432	from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]) == s->current_tm.tm_min) &&
433	((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 \|\|
434	from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]) == s->current_tm.tm_hour)) {
435
436	s->cmos_data[RTC_REG_C] \|= 0xa0;
437	PDMDevHlpISASetIrq(s->CTX_SUFF(pDevIns), s->irq, 1);
438	}
439	}
440
441	/* update ended interrupt */
442	if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
443	s->cmos_data[RTC_REG_C] \|= 0x90;
444	PDMDevHlpISASetIrq(s->CTX_SUFF(pDevIns), s->irq, 1);
445	}
446
447	/* clear update in progress bit */
448	s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
449
450	s->next_second_time += TMTimerGetFreq(s->CTX_SUFF(pSecondTimer));
451	TMTimerSet(s->CTX_SUFF(pSecondTimer), s->next_second_time);
452	}
453
454	static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
455	{
456	RTCState s = (RTCState)opaque;
457	int ret;
458	if ((addr & 1) == 0) {
459	return 0xff;
460	} else {
461	switch(s->cmos_index) {
462	case RTC_SECONDS:
463	case RTC_MINUTES:
464	case RTC_HOURS:
465	case RTC_DAY_OF_WEEK:
466	case RTC_DAY_OF_MONTH:
467	case RTC_MONTH:
468	case RTC_YEAR:
469	ret = s->cmos_data[s->cmos_index];
470	break;
471	case RTC_REG_A:
472	ret = s->cmos_data[s->cmos_index];
473	break;
474	case RTC_REG_C:
475	ret = s->cmos_data[s->cmos_index];
476	PDMDevHlpISASetIrq(s->CTX_SUFF(pDevIns), s->irq, 0);
477	s->cmos_data[RTC_REG_C] = 0x00;
478	break;
479	default:
480	ret = s->cmos_data[s->cmos_index];
481	break;
482	}
483	Log(("CMOS: Read idx %#04x: %#04x\n", s->cmos_index, ret));
484	return ret;
485	}
486	}
487
488	#ifdef IN_RING3
489	static void rtc_set_memory(RTCState *s, int addr, int val)
490	{
491	if (addr >= 0 && addr <= 127)
492	s->cmos_data[addr] = val;
493	}
494
495	static void rtc_set_date(RTCState s, const struct my_tm tm)
496	{
497	s->current_tm = *tm;
498	rtc_copy_date(s);
499	}
500
501	#endif /* IN_RING3 */
502
503	/* -=-=-=-=-=- wrappers / stuff -=-=-=-=-=- */
504
505	/**
506	* Port I/O Handler for IN operations.
507	*
508	* @returns VBox status code.
509	*
510	* @param pDevIns The device instance.
511	* @param pvUser User argument - ignored.
512	* @param uPort Port number used for the IN operation.
513	* @param pu32 Where to store the result.
514	* @param cb Number of bytes read.
515	*/
516	PDMBOTHCBDECL(int) rtcIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
517	{
518	NOREF(pvUser);
519	if (cb == 1)
520	{
521	pu32 = cmos_ioport_read(PDMINS_2_DATA(pDevIns, RTCState ), Port);
522	return VINF_SUCCESS;
523	}
524	return VERR_IOM_IOPORT_UNUSED;
525	}
526
527
528	/**
529	* Port I/O Handler for OUT operations.
530	*
531	* @returns VBox status code.
532	*
533	* @param pDevIns The device instance.
534	* @param pvUser User argument - ignored.
535	* @param uPort Port number used for the IN operation.
536	* @param u32 The value to output.
537	* @param cb The value size in bytes.
538	*/
539	PDMBOTHCBDECL(int) rtcIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
540	{
541	NOREF(pvUser);
542	if (cb == 1)
543	cmos_ioport_write(PDMINS_2_DATA(pDevIns, RTCState *), Port, u32);
544	return VINF_SUCCESS;
545	}
546
547
548	/**
549	* Device timer callback function, periodic.
550	*
551	* @param pDevIns Device instance of the device which registered the timer.
552	* @param pTimer The timer handle.
553	*/
554	PDMBOTHCBDECL(void) rtcTimerPeriodic(PPDMDEVINS pDevIns, PTMTIMER pTimer)
555	{
556	rtc_periodic_timer(PDMINS_2_DATA(pDevIns, RTCState *));
557	}
558
559
560	/**
561	* Device timer callback function, second.
562	*
563	* @param pDevIns Device instance of the device which registered the timer.
564	* @param pTimer The timer handle.
565	*/
566	PDMBOTHCBDECL(void) rtcTimerSecond(PPDMDEVINS pDevIns, PTMTIMER pTimer)
567	{
568	rtc_update_second(PDMINS_2_DATA(pDevIns, RTCState *));
569	}
570
571
572	/**
573	* Device timer callback function, second2.
574	*
575	* @param pDevIns Device instance of the device which registered the timer.
576	* @param pTimer The timer handle.
577	*/
578	PDMBOTHCBDECL(void) rtcTimerSecond2(PPDMDEVINS pDevIns, PTMTIMER pTimer)
579	{
580	rtc_update_second2(PDMINS_2_DATA(pDevIns, RTCState *));
581	}
582
583
584	#ifdef IN_RING3
585	/**
586	* Saves a state of the programmable interval timer device.
587	*
588	* @returns VBox status code.
589	* @param pDevIns The device instance.
590	* @param pSSMHandle The handle to save the state to.
591	*/
592	static DECLCALLBACK(int) rtcSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
593	{
594	RTCState pThis = PDMINS_2_DATA(pDevIns, RTCState );
595
596	SSMR3PutMem(pSSMHandle, pThis->cmos_data, 128);
597	SSMR3PutU8(pSSMHandle, pThis->cmos_index);
598
599	SSMR3PutS32(pSSMHandle, pThis->current_tm.tm_sec);
600	SSMR3PutS32(pSSMHandle, pThis->current_tm.tm_min);
601	SSMR3PutS32(pSSMHandle, pThis->current_tm.tm_hour);
602	SSMR3PutS32(pSSMHandle, pThis->current_tm.tm_wday);
603	SSMR3PutS32(pSSMHandle, pThis->current_tm.tm_mday);
604	SSMR3PutS32(pSSMHandle, pThis->current_tm.tm_mon);
605	SSMR3PutS32(pSSMHandle, pThis->current_tm.tm_year);
606
607	TMR3TimerSave(pThis->CTX_SUFF(pPeriodicTimer), pSSMHandle);
608
609	SSMR3PutS64(pSSMHandle, pThis->next_periodic_time);
610
611	SSMR3PutS64(pSSMHandle, pThis->next_second_time);
612	TMR3TimerSave(pThis->CTX_SUFF(pSecondTimer), pSSMHandle);
613	TMR3TimerSave(pThis->CTX_SUFF(pSecondTimer2), pSSMHandle);
614
615	return VINF_SUCCESS;
616	}
617
618
619	/**
620	* Loads a saved programmable interval timer device state.
621	*
622	* @returns VBox status code.
623	* @param pDevIns The device instance.
624	* @param pSSMHandle The handle to the saved state.
625	* @param u32Version The data unit version number.
626	*/
627	static DECLCALLBACK(int) rtcLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
628	{
629	RTCState pThis = PDMINS_2_DATA(pDevIns, RTCState );
630
631	if (u32Version != 1)
632	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
633
634	SSMR3GetMem(pSSMHandle, pThis->cmos_data, 128);
635	SSMR3GetU8(pSSMHandle, &pThis->cmos_index);
636
637	SSMR3GetS32(pSSMHandle, &pThis->current_tm.tm_sec);
638	SSMR3GetS32(pSSMHandle, &pThis->current_tm.tm_min);
639	SSMR3GetS32(pSSMHandle, &pThis->current_tm.tm_hour);
640	SSMR3GetS32(pSSMHandle, &pThis->current_tm.tm_wday);
641	SSMR3GetS32(pSSMHandle, &pThis->current_tm.tm_mday);
642	SSMR3GetS32(pSSMHandle, &pThis->current_tm.tm_mon);
643	SSMR3GetS32(pSSMHandle, &pThis->current_tm.tm_year);
644
645	TMR3TimerLoad(pThis->CTX_SUFF(pPeriodicTimer), pSSMHandle);
646
647	SSMR3GetS64(pSSMHandle, &pThis->next_periodic_time);
648
649	SSMR3GetS64(pSSMHandle, &pThis->next_second_time);
650	TMR3TimerLoad(pThis->CTX_SUFF(pSecondTimer), pSSMHandle);
651	TMR3TimerLoad(pThis->CTX_SUFF(pSecondTimer2), pSSMHandle);
652
653	int period_code = pThis->cmos_data[RTC_REG_A] & 0x0f;
654	if ( period_code != 0
655	&& (pThis->cmos_data[RTC_REG_B] & REG_B_PIE)) {
656	if (period_code <= 2)
657	period_code += 7;
658	int period = 1 << (period_code - 1);
659	LogRel(("RTC: period=%#x (%d) %u Hz (restore)\n", period, period, _32K / period));
660	pThis->CurPeriod = period;
661	} else {
662	LogRel(("RTC: stopped the periodic timer (restore)\n"));
663	pThis->CurPeriod = 0;
664	}
665	pThis->cRelLogEntries = 0;
666	return VINF_SUCCESS;
667	}
668
669
670	/* -=-=-=-=-=- PDM Interface provided by the RTC device -=-=-=-=-=- */
671
672	/**
673	* Calculate and update the standard CMOS checksum.
674	*
675	* @param pThis Pointer to the RTC state data.
676	*/
677	static void rtcCalcCRC(RTCState *pThis)
678	{
679	uint16_t u16;
680	unsigned i;
681
682	for (i = RTC_CRC_START, u16 = 0; i <= RTC_CRC_LAST; i++)
683	u16 += pThis->cmos_data[i];
684	pThis->cmos_data[RTC_CRC_LOW] = u16 & 0xff;
685	pThis->cmos_data[RTC_CRC_HIGH] = (u16 >> 8) & 0xff;
686	}
687
688
689	/**
690	* Write to a CMOS register and update the checksum if necessary.
691	*
692	* @returns VBox status code.
693	* @param pDevIns Device instance of the RTC.
694	* @param iReg The CMOS register index.
695	* @param u8Value The CMOS register value.
696	*/
697	static DECLCALLBACK(int) rtcCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
698	{
699	RTCState pThis = PDMINS_2_DATA(pDevIns, RTCState );
700	if (iReg < RT_ELEMENTS(pThis->cmos_data))
701	{
702	pThis->cmos_data[iReg] = u8Value;
703
704	/* does it require checksum update? */
705	if ( iReg >= RTC_CRC_START
706	&& iReg <= RTC_CRC_LAST)
707	rtcCalcCRC(pThis);
708
709	return VINF_SUCCESS;
710	}
711	AssertMsgFailed(("iReg=%d\n", iReg));
712	return VERR_INVALID_PARAMETER;
713	}
714
715
716	/**
717	* Read a CMOS register.
718	*
719	* @returns VBox status code.
720	* @param pDevIns Device instance of the RTC.
721	* @param iReg The CMOS register index.
722	* @param pu8Value Where to store the CMOS register value.
723	*/
724	static DECLCALLBACK(int) rtcCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
725	{
726	RTCState pThis = PDMINS_2_DATA(pDevIns, RTCState );
727	if (iReg < RT_ELEMENTS(pThis->cmos_data))
728	{
729	*pu8Value = pThis->cmos_data[iReg];
730	return VINF_SUCCESS;
731	}
732	AssertMsgFailed(("iReg=%d\n", iReg));
733	return VERR_INVALID_PARAMETER;
734	}
735
736
737	/* -=-=-=-=-=- based on bits from pc.c -=-=-=-=-=- */
738
739	/** @copydoc FNPDMDEVINITCOMPLETE */
740	static DECLCALLBACK(int) rtcInitComplete(PPDMDEVINS pDevIns)
741	{
742	/** @todo this should be (re)done at power on if we didn't load a state... */
743	RTCState pThis = PDMINS_2_DATA(pDevIns, RTCState );
744
745	/*
746	* Set the CMOS date/time.
747	*/
748	RTTIMESPEC Now;
749	PDMDevHlpUTCNow(pDevIns, &Now);
750	RTTIME Time;
751	if (pThis->fUTC)
752	RTTimeExplode(&Time, &Now);
753	else
754	RTTimeLocalExplode(&Time, &Now);
755
756	struct my_tm Tm;
757	memset(&Tm, 0, sizeof(Tm));
758	Tm.tm_year = Time.i32Year - 1900;
759	Tm.tm_mon = Time.u8Month - 1;
760	Tm.tm_mday = Time.u8MonthDay;
761	Tm.tm_wday = (Time.u8WeekDay - 1 + 7) % 7; /* 0 = monday -> sunday */
762	Tm.tm_yday = Time.u16YearDay - 1;
763	Tm.tm_hour = Time.u8Hour;
764	Tm.tm_min = Time.u8Minute;
765	Tm.tm_sec = Time.u8Second;
766
767	rtc_set_date(pThis, &Tm);
768
769	int iYear = to_bcd(pThis, (Tm.tm_year / 100) + 19); /* tm_year is 1900 based */
770	rtc_set_memory(pThis, 0x32, iYear); /* 32h - Century Byte (BCD value for the century */
771	rtc_set_memory(pThis, 0x37, iYear); /* 37h - (IBM PS/2) Date Century Byte */
772
773	/*
774	* Recalculate the checksum just in case.
775	*/
776	rtcCalcCRC(pThis);
777
778	Log(("CMOS: \n%16.128Vhxd\n", pThis->cmos_data));
779	return VINF_SUCCESS;
780	}
781
782
783	/* -=-=-=-=-=- real code -=-=-=-=-=- */
784
785	/**
786	* @copydoc
787	*/
788	static DECLCALLBACK(void) rtcRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
789	{
790	RTCState pThis = PDMINS_2_DATA(pDevIns, RTCState );
791
792	pThis->pDevInsRC = PDMDEVINS_2_GCPTR(pDevIns);
793	pThis->pPeriodicTimerRC = TMTimerRCPtr(pThis->pPeriodicTimerR3);
794	pThis->pSecondTimerRC = TMTimerRCPtr(pThis->pSecondTimerR3);
795	pThis->pSecondTimer2RC = TMTimerRCPtr(pThis->pSecondTimer2R3);
796	}
797
798
799	/**
800	* Construct a device instance for a VM.
801	*
802	* @returns VBox status.
803	* @param pDevIns The device instance data.
804	* If the registration structure is needed, pDevIns->pDevReg points to it.
805	* @param iInstance Instance number. Use this to figure out which registers and such to use.
806	* The device number is also found in pDevIns->iInstance, but since it's
807	* likely to be freqently used PDM passes it as parameter.
808	* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
809	* of the device instance. It's also found in pDevIns->pCfgHandle, but like
810	* iInstance it's expected to be used a bit in this function.
811	*/
812	static DECLCALLBACK(int) rtcConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
813	{
814	RTCState pThis = PDMINS_2_DATA(pDevIns, RTCState );
815	int rc;
816	uint8_t u8Irq;
817	uint16_t u16Base;
818	bool fGCEnabled;
819	bool fR0Enabled;
820	Assert(iInstance == 0);
821
822	/*
823	* Validate configuration.
824	*/
825	if (!CFGMR3AreValuesValid(pCfgHandle, "Irq\0" "Base\0" "GCEnabled\0" "R0Enabled\0"))
826	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
827
828	/*
829	* Init the data.
830	*/
831	rc = CFGMR3QueryU8Def(pCfgHandle, "Irq", &u8Irq, 8);
832	if (RT_FAILURE(rc))
833	return PDMDEV_SET_ERROR(pDevIns, rc,
834	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
835
836	rc = CFGMR3QueryU16Def(pCfgHandle, "Base", &u16Base, 0x70);
837	if (RT_FAILURE(rc))
838	return PDMDEV_SET_ERROR(pDevIns, rc,
839	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
840
841	rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
842	if (RT_FAILURE(rc))
843	return PDMDEV_SET_ERROR(pDevIns, rc,
844	N_("Configuration error: failed to read GCEnabled as boolean"));
845
846	rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
847	if (RT_FAILURE(rc))
848	return PDMDEV_SET_ERROR(pDevIns, rc,
849	N_("Configuration error: failed to read R0Enabled as boolean"));
850
851	Log(("RTC: Irq=%#x Base=%#x fGCEnabled=%RTbool fR0Enabled=%RTbool\n", u8Irq, u16Base, fGCEnabled, fR0Enabled));
852
853
854	pThis->pDevInsR3 = pDevIns;
855	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
856	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
857	pThis->irq = u8Irq;
858	pThis->cmos_data[RTC_REG_A] = 0x26;
859	pThis->cmos_data[RTC_REG_B] = 0x02;
860	pThis->cmos_data[RTC_REG_C] = 0x00;
861	pThis->cmos_data[RTC_REG_D] = 0x80;
862	pThis->RtcReg.u32Version = PDM_RTCREG_VERSION;
863	pThis->RtcReg.pfnRead = rtcCMOSRead;
864	pThis->RtcReg.pfnWrite = rtcCMOSWrite;
865
866	/*
867	* Create timers, arm them, register I/O Ports and save state.
868	*/
869	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, rtcTimerPeriodic, "MC146818 RTC/CMOS - Periodic", &pThis->pPeriodicTimerR3);
870	if (RT_FAILURE(rc))
871	return rc;
872	pThis->pPeriodicTimerR0 = TMTimerR0Ptr(pThis->pPeriodicTimerR3);
873	pThis->pPeriodicTimerRC = TMTimerRCPtr(pThis->pPeriodicTimerR3);
874
875	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, rtcTimerSecond, "MC146818 RTC/CMOS - Second", &pThis->pSecondTimerR3);
876	if (RT_FAILURE(rc))
877	return rc;
878	pThis->pSecondTimerR0 = TMTimerR0Ptr(pThis->pSecondTimerR3);
879	pThis->pSecondTimerRC = TMTimerRCPtr(pThis->pSecondTimerR3);
880
881	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, rtcTimerSecond2, "MC146818 RTC/CMOS - Second2", &pThis->pSecondTimer2R3);
882	if (RT_FAILURE(rc))
883	return rc;
884	pThis->pSecondTimer2R0 = TMTimerR0Ptr(pThis->pSecondTimer2R3);
885	pThis->pSecondTimer2RC = TMTimerRCPtr(pThis->pSecondTimer2R3);
886	pThis->next_second_time = TMTimerGet(pThis->CTX_SUFF(pSecondTimer2)) + (TMTimerGetFreq(pThis->CTX_SUFF(pSecondTimer2)) * 99) / 100;
887	rc = TMTimerSet(pThis->CTX_SUFF(pSecondTimer2), pThis->next_second_time);
888	if (RT_FAILURE(rc))
889	return rc;
890
891	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 2, NULL, rtcIOPortWrite, rtcIOPortRead, NULL, NULL, "MC146818 RTC/CMOS");
892	if (RT_FAILURE(rc))
893	return rc;
894	if (fGCEnabled)
895	{
896	rc = PDMDevHlpIOPortRegisterGC(pDevIns, u16Base, 2, 0, "rtcIOPortWrite", "rtcIOPortRead", NULL, NULL, "MC146818 RTC/CMOS");
897	if (RT_FAILURE(rc))
898	return rc;
899	}
900	if (fR0Enabled)
901	{
902	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 2, 0, "rtcIOPortWrite", "rtcIOPortRead", NULL, NULL, "MC146818 RTC/CMOS");
903	if (RT_FAILURE(rc))
904	return rc;
905	}
906
907	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version /, sizeof(pThis),
908	NULL, rtcSaveExec, NULL,
909	NULL, rtcLoadExec, NULL);
910	if (RT_FAILURE(rc))
911	return rc;
912
913	/*
914	* Register ourselves as the RTC/CMOS with PDM.
915	*/
916	rc = pDevIns->pDevHlp->pfnRTCRegister(pDevIns, &pThis->RtcReg, &pThis->pRtcHlpR3);
917	if (RT_FAILURE(rc))
918	return rc;
919
920	return VINF_SUCCESS;
921	}
922
923
924	/**
925	* The device registration structure.
926	*/
927	const PDMDEVREG g_DeviceMC146818 =
928	{
929	/* u32Version */
930	PDM_DEVREG_VERSION,
931	/* szDeviceName */
932	"mc146818",
933	/* szGCMod */
934	"VBoxDDGC.gc",
935	/* szR0Mod */
936	"VBoxDDR0.r0",
937	/* pszDescription */
938	"Motorola MC146818 RTC/CMOS Device.",
939	/* fFlags */
940	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
941	/* fClass */
942	PDM_DEVREG_CLASS_RTC,
943	/* cMaxInstances */
944	1,
945	/* cbInstance */
946	sizeof(RTCState),
947	/* pfnConstruct */
948	rtcConstruct,
949	/* pfnDestruct */
950	NULL,
951	/* pfnRelocate */
952	rtcRelocate,
953	/* pfnIOCtl */
954	NULL,
955	/* pfnPowerOn */
956	NULL,
957	/* pfnReset */
958	NULL,
959	/* pfnSuspend */
960	NULL,
961	/* pfnResume */
962	NULL,
963	/* pfnAttach */
964	NULL,
965	/* pfnDetach */
966	NULL,
967	/* pfnQueryInterface */
968	NULL,
969	/* pfnInitComplete */
970	rtcInitComplete
971	};
972	#endif /* IN_RING3 */
973	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
974

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source: vbox/trunk/src/VBox/Devices/PC/DevRTC.cpp@ 11280

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