DevPit-i8254.cpp@ 93115

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1	/* $Id: DevPit-i8254.cpp 93115 2022-01-01 11:31:46Z vboxsync $ */
2	/** @file
3	* DevPIT-i8254 - Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU 8253/8254 interval timer emulation
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Header Files *
46	*********************************************************************************************************************************/
47	#define LOG_GROUP LOG_GROUP_DEV_PIT
48	#include <VBox/vmm/pdmdev.h>
49	#include <VBox/log.h>
50	#include <VBox/vmm/stam.h>
51	#include <iprt/assert.h>
52	#include <iprt/asm-math.h>
53
54	#ifdef IN_RING3
55	# ifdef RT_OS_LINUX
56	# include <fcntl.h>
57	# include <errno.h>
58	# include <unistd.h>
59	# include <stdio.h>
60	# include <linux/kd.h>
61	# include <linux/input.h>
62	# include <sys/ioctl.h>
63	# endif
64	# include <iprt/alloc.h>
65	# include <iprt/string.h>
66	# include <iprt/uuid.h>
67	#endif /* IN_RING3 */
68
69	#include "VBoxDD.h"
70
71
72	/*********************************************************************************************************************************
73	* Defined Constants And Macros *
74	*********************************************************************************************************************************/
75	/** The PIT frequency. */
76	#define PIT_FREQ 1193182
77
78	#define RW_STATE_LSB 1
79	#define RW_STATE_MSB 2
80	#define RW_STATE_WORD0 3
81	#define RW_STATE_WORD1 4
82
83	/** The current saved state version. */
84	#define PIT_SAVED_STATE_VERSION 4
85	/** The saved state version used by VirtualBox 3.1 and earlier.
86	* This did not include disable by HPET flag. */
87	#define PIT_SAVED_STATE_VERSION_VBOX_31 3
88	/** The saved state version used by VirtualBox 3.0 and earlier.
89	* This did not include the config part. */
90	#define PIT_SAVED_STATE_VERSION_VBOX_30 2
91
92	/** @def FAKE_REFRESH_CLOCK
93	* Define this to flip the 15usec refresh bit on every read.
94	* If not defined, it will be flipped correctly. */
95	/* #define FAKE_REFRESH_CLOCK */
96	#ifdef DOXYGEN_RUNNING
97	# define FAKE_REFRESH_CLOCK
98	#endif
99
100	/** The effective counter mode - if bit 1 is set, bit 2 is ignored. */
101	#define EFFECTIVE_MODE(x) ((x) & ~(((x) & 2) << 1))
102
103
104	/**
105	* Acquires the PIT lock or returns.
106	*/
107	#define DEVPIT_LOCK_RETURN(a_pDevIns, a_pThis, a_rcBusy) \
108	do { \
109	int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (a_rcBusy)); \
110	if (rcLock == VINF_SUCCESS) { /* likely */ } \
111	else return rcLock; \
112	} while (0)
113
114	/**
115	* Releases the PIT lock.
116	*/
117	#define DEVPIT_UNLOCK(a_pDevIns, a_pThis) \
118	do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
119
120
121	/**
122	* Acquires the TM lock and PIT lock, returns on failure.
123	*/
124	#define DEVPIT_LOCK_BOTH_RETURN(a_pDevIns, a_pThis, a_rcBusy) \
125	do { \
126	VBOXSTRICTRC rcLock = PDMDevHlpTimerLockClock2((a_pDevIns), (a_pThis)->channels[0].hTimer, \
127	&(a_pThis)->CritSect, (a_rcBusy)); \
128	if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
129	{ /* likely */ } \
130	else \
131	return rcLock; \
132	} while (0)
133
134	#ifdef IN_RING3
135	/**
136	* Acquires the TM lock and PIT lock, ignores failures.
137	*/
138	# define DEVPIT_R3_LOCK_BOTH(a_pDevIns, a_pThis) \
139	PDMDevHlpTimerLockClock2((a_pDevIns), (a_pThis)->channels[0].hTimer, &(a_pThis)->CritSect, VERR_IGNORED)
140	#endif /* IN_RING3 */
141
142	/**
143	* Releases the PIT lock and TM lock.
144	*/
145	#define DEVPIT_UNLOCK_BOTH(a_pDevIns, a_pThis) \
146	PDMDevHlpTimerUnlockClock2((a_pDevIns), (a_pThis)->channels[0].hTimer, &(a_pThis)->CritSect)
147
148
149
150	/*********************************************************************************************************************************
151	* Structures and Typedefs *
152	*********************************************************************************************************************************/
153	/**
154	* The state of one PIT channel.
155	*/
156	typedef struct PITCHANNEL
157	{
158	/** The timer.
159	* @note Only channel 0 has a timer. */
160	TMTIMERHANDLE hTimer;
161	/** The virtual time stamp at the last reload (only used in mode 2 for now). */
162	uint64_t u64ReloadTS;
163	/** The actual time of the next tick.
164	* As apposed to the next_transition_time which contains the correct time of the next tick. */
165	uint64_t u64NextTS;
166
167	/** (count_load_time is only set by PDMDevHlpTimerGet() which returns uint64_t) */
168	uint64_t count_load_time;
169	/* irq handling */
170	int64_t next_transition_time;
171	int32_t irq;
172	/** Number of release log entries. Used to prevent flooding. */
173	uint8_t cRelLogEntries;
174	/** The channel number. */
175	uint8_t iChan;
176	uint8_t abAlignment[2];
177
178	uint32_t count; /* can be 65536 */
179	uint16_t latched_count;
180	uint8_t count_latched;
181	uint8_t status_latched;
182
183	uint8_t status;
184	uint8_t read_state;
185	uint8_t write_state;
186	uint8_t write_latch;
187
188	uint8_t rw_mode;
189	uint8_t mode;
190	uint8_t bcd; /* not supported */
191	uint8_t gate; /* timer start */
192
193	} PITCHANNEL;
194	/** Pointer to the state of one PIT channel. */
195	typedef PITCHANNEL *PPITCHANNEL;
196
197	/** Speaker emulation state. */
198	typedef enum PITSPEAKEREMU
199	{
200	PIT_SPEAKER_EMU_NONE = 0,
201	PIT_SPEAKER_EMU_CONSOLE,
202	PIT_SPEAKER_EMU_EVDEV,
203	PIT_SPEAKER_EMU_TTY
204	} PITSPEAKEREMU;
205
206	/**
207	* The shared PIT state.
208	*/
209	typedef struct PITSTATE
210	{
211	/** Channel state. Must come first? */
212	PITCHANNEL channels[3];
213	/** Speaker data. */
214	int32_t speaker_data_on;
215	#ifdef FAKE_REFRESH_CLOCK
216	/** Refresh dummy. */
217	int32_t dummy_refresh_clock;
218	#else
219	uint32_t Alignment1;
220	#endif
221	/** Config: I/O port base. */
222	RTIOPORT IOPortBaseCfg;
223	/** Config: Speaker enabled. */
224	bool fSpeakerCfg;
225	/** Disconnect PIT from the interrupt controllers if requested by HPET. */
226	bool fDisabledByHpet;
227	/** Config: What to do with speaker activity. */
228	PITSPEAKEREMU enmSpeakerEmu;
229	#ifdef RT_OS_LINUX
230	/** File handle for host speaker functionality. */
231	int hHostSpeaker;
232	int afAlignment2;
233	#endif
234	/** Number of IRQs that's been raised. */
235	STAMCOUNTER StatPITIrq;
236	/** Profiling the timer callback handler. */
237	STAMPROFILEADV StatPITHandler;
238	/** Critical section protecting the state. */
239	PDMCRITSECT CritSect;
240	/** The primary I/O port range (0x40-0x43). */
241	IOMIOPORTHANDLE hIoPorts;
242	/** The speaker I/O port range (0x40-0x43). */
243	IOMIOPORTHANDLE hIoPortSpeaker;
244	} PITSTATE;
245	/** Pointer to the shared PIT device state. */
246	typedef PITSTATE *PPITSTATE;
247
248
249	/**
250	* The ring-3 PIT state.
251	*/
252	typedef struct PITSTATER3
253	{
254	/** PIT port interface. */
255	PDMIHPETLEGACYNOTIFY IHpetLegacyNotify;
256	/** Pointer to the device instance. */
257	PPDMDEVINSR3 pDevIns;
258	} PITSTATER3;
259	/** Pointer to the ring-3 PIT device state. */
260	typedef PITSTATER3 *PPITSTATER3;
261
262
263	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
264
265
266
267	static int pit_get_count(PPDMDEVINS pDevIns, PPITSTATE pThis, PPITCHANNEL pChan)
268	{
269	uint64_t d;
270	TMTIMERHANDLE hTimer = pThis->channels[0].hTimer;
271	Assert(PDMDevHlpTimerIsLockOwner(pDevIns, hTimer));
272
273	if (EFFECTIVE_MODE(pChan->mode) == 2)
274	{
275	if (pChan->u64NextTS == UINT64_MAX)
276	{
277	d = ASMMultU64ByU32DivByU32(PDMDevHlpTimerGet(pDevIns, hTimer) - pChan->count_load_time,
278	PIT_FREQ, PDMDevHlpTimerGetFreq(pDevIns, hTimer));
279	return pChan->count - (d % pChan->count); /** @todo check this value. */
280	}
281	uint64_t Interval = pChan->u64NextTS - pChan->u64ReloadTS;
282	if (!Interval)
283	return pChan->count - 1; /** @todo This is WRONG! But I'm too tired to fix it properly and just want to shut up a DIV/0 trap now. */
284	d = PDMDevHlpTimerGet(pDevIns, hTimer);
285	d = ASMMultU64ByU32DivByU32(d - pChan->u64ReloadTS, pChan->count, Interval);
286	if (d >= pChan->count)
287	return 1;
288	return pChan->count - d;
289	}
290
291	d = ASMMultU64ByU32DivByU32(PDMDevHlpTimerGet(pDevIns, hTimer) - pChan->count_load_time,
292	PIT_FREQ, PDMDevHlpTimerGetFreq(pDevIns, hTimer));
293	int counter;
294	switch (EFFECTIVE_MODE(pChan->mode))
295	{
296	case 0:
297	case 1:
298	case 4:
299	case 5:
300	counter = (pChan->count - d) & 0xffff;
301	break;
302	case 3:
303	/* XXX: may be incorrect for odd counts */
304	counter = pChan->count - ((2 * d) % pChan->count);
305	break;
306	default:
307	counter = pChan->count - (d % pChan->count);
308	break;
309	}
310	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
311	return counter;
312	}
313
314
315	/* get pit output bit */
316	static int pit_get_out1(PPDMDEVINS pDevIns, PPITSTATE pThis, PPITCHANNEL pChan, int64_t current_time)
317	{
318	TMTIMERHANDLE hTimer = pThis->channels[0].hTimer;
319	uint64_t d;
320	int out;
321
322	d = ASMMultU64ByU32DivByU32(current_time - pChan->count_load_time, PIT_FREQ, PDMDevHlpTimerGetFreq(pDevIns, hTimer));
323	switch (EFFECTIVE_MODE(pChan->mode))
324	{
325	default:
326	case 0:
327	out = (d >= pChan->count);
328	break;
329	case 1:
330	out = (d < pChan->count);
331	break;
332	case 2:
333	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, pChan->count, (unsigned)(d % pChan->count)));
334	if ((d % pChan->count) == 0 && d != 0)
335	out = 1;
336	else
337	out = 0;
338	break;
339	case 3:
340	out = (d % pChan->count) < ((pChan->count + 1) >> 1);
341	break;
342	case 4:
343	case 5:
344	out = (d != pChan->count);
345	break;
346	}
347	return out;
348	}
349
350
351	static int pit_get_out(PPDMDEVINS pDevIns, PPITSTATE pThis, int channel, int64_t current_time)
352	{
353	PPITCHANNEL pChan = &pThis->channels[channel];
354	return pit_get_out1(pDevIns, pThis, pChan, current_time);
355	}
356
357
358	static int pit_get_gate(PPITSTATE pThis, int channel)
359	{
360	PPITCHANNEL pChan = &pThis->channels[channel];
361	return pChan->gate;
362	}
363
364
365	/* if already latched, do not latch again */
366	static void pit_latch_count(PPDMDEVINS pDevIns, PPITSTATE pThis, PPITCHANNEL pChan)
367	{
368	if (!pChan->count_latched)
369	{
370	pChan->latched_count = pit_get_count(pDevIns, pThis, pChan);
371	pChan->count_latched = pChan->rw_mode;
372	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
373	pChan->latched_count, ASMMultU64ByU32DivByU32(pChan->count - pChan->latched_count, 1000000000, PIT_FREQ),
374	pChan->count, pChan->mode));
375	}
376	}
377
378	#ifdef IN_RING3
379
380	/* return -1 if no transition will occur. */
381	static int64_t pitR3GetNextTransitionTime(PPDMDEVINS pDevIns, PPITSTATE pThis, PPITCHANNEL pChan, uint64_t current_time)
382	{
383	TMTIMERHANDLE hTimer = pThis->channels[0].hTimer;
384	uint64_t d, next_time, base;
385	uint32_t period2;
386
387	d = ASMMultU64ByU32DivByU32(current_time - pChan->count_load_time, PIT_FREQ, PDMDevHlpTimerGetFreq(pDevIns, hTimer));
388	switch (EFFECTIVE_MODE(pChan->mode))
389	{
390	default:
391	case 0:
392	case 1:
393	if (d < pChan->count)
394	next_time = pChan->count;
395	else
396	return -1;
397	break;
398
399	/*
400	* Mode 2: The period is 'count' PIT ticks.
401	* When the counter reaches 1 we set the output low (for channel 0 that
402	* means lowering IRQ0). On the next tick, where we should be decrementing
403	* from 1 to 0, the count is loaded and the output goes high (channel 0
404	* means raising IRQ0 again and triggering timer interrupt).
405	*
406	* In VirtualBox we compress the pulse and flip-flop the IRQ line at the
407	* end of the period, which signals an interrupt at the exact same time.
408	*/
409	case 2:
410	base = (d / pChan->count) * pChan->count;
411	# ifndef VBOX /* see above */
412	if ((d - base) == 0 && d != 0)
413	next_time = base + pChan->count - 1;
414	else
415	# endif
416	next_time = base + pChan->count;
417	break;
418	case 3:
419	base = (d / pChan->count) * pChan->count;
420	period2 = ((pChan->count + 1) >> 1);
421	if ((d - base) < period2)
422	next_time = base + period2;
423	else
424	next_time = base + pChan->count;
425	break;
426
427	/* Modes 4 and 5 generate a short pulse at the end of the time delay. This
428	* is similar to mode 2, except modes 4/5 aren't periodic. We use the same
429	* optimization - only use one timer callback and pulse the IRQ.
430	* Note: Tickless Linux kernels use PIT mode 4 with 'nolapic'.
431	*/
432	case 4:
433	case 5:
434	# ifdef VBOX
435	if (d <= pChan->count)
436	next_time = pChan->count;
437	# else
438	if (d < pChan->count)
439	next_time = pChan->count;
440	else if (d == pChan->count)
441	next_time = pChan->count + 1;
442	# endif
443	else
444	return -1;
445	break;
446	}
447
448	/* convert to timer units */
449	LogFlow(("PIT: next_time=%'14RU64 %'20RU64 mode=%#x count=%#06x\n", next_time,
450	ASMMultU64ByU32DivByU32(next_time, PDMDevHlpTimerGetFreq(pDevIns, hTimer), PIT_FREQ), pChan->mode, pChan->count));
451	next_time = pChan->count_load_time + ASMMultU64ByU32DivByU32(next_time, PDMDevHlpTimerGetFreq(pDevIns, hTimer), PIT_FREQ);
452
453	/* fix potential rounding problems */
454	if (next_time <= current_time)
455	next_time = current_time;
456
457	/* Add one to next_time; if we don't, integer truncation will cause
458	* the algorithm to think that at the end of each period, it'pChan still
459	* within the first one instead of at the beginning of the next one.
460	*/
461	return next_time + 1;
462	}
463
464
465	static void pitR3IrqTimerUpdate(PPDMDEVINS pDevIns, PPITSTATE pThis, PPITCHANNEL pChan,
466	uint64_t current_time, uint64_t now, bool in_timer)
467	{
468	int64_t expire_time;
469	int irq_level;
470	Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->channels[0].hTimer));
471
472	if (pChan->hTimer == NIL_TMTIMERHANDLE)
473	return;
474	expire_time = pitR3GetNextTransitionTime(pDevIns, pThis, pChan, current_time);
475	irq_level = pit_get_out1(pDevIns, pThis, pChan, current_time) ? PDM_IRQ_LEVEL_HIGH : PDM_IRQ_LEVEL_LOW;
476
477	/* If PIT is disabled by HPET - simply disconnect ticks from interrupt controllers,
478	* but do not modify other aspects of device operation.
479	*/
480	if (!pThis->fDisabledByHpet)
481	{
482	switch (EFFECTIVE_MODE(pChan->mode))
483	{
484	case 2:
485	case 4:
486	case 5:
487	/* We just flip-flop the IRQ line to save an extra timer call,
488	* which isn't generally required. However, the pulse is only
489	* generated when running on the timer callback (and thus on
490	* the trailing edge of the output signal pulse).
491	*/
492	if (in_timer)
493	{
494	PDMDevHlpISASetIrq(pDevIns, pChan->irq, PDM_IRQ_LEVEL_FLIP_FLOP);
495	break;
496	}
497	RT_FALL_THRU();
498	default:
499	PDMDevHlpISASetIrq(pDevIns, pChan->irq, irq_level);
500	break;
501	}
502	}
503
504	if (irq_level)
505	{
506	pChan->u64ReloadTS = now;
507	STAM_COUNTER_INC(&pThis->StatPITIrq);
508	}
509
510	if (expire_time != -1)
511	{
512	Log3(("pitR3IrqTimerUpdate: next=%'RU64 now=%'RU64\n", expire_time, now));
513	pChan->u64NextTS = expire_time;
514	PDMDevHlpTimerSet(pDevIns, pChan->hTimer, pChan->u64NextTS);
515	}
516	else
517	{
518	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", pChan->mode, pChan->count, irq_level));
519	PDMDevHlpTimerStop(pDevIns, pChan->hTimer);
520	pChan->u64NextTS = UINT64_MAX;
521	}
522	pChan->next_transition_time = expire_time;
523	}
524
525
526	/* val must be 0 or 1 */
527	static void pitR3SetGate(PPDMDEVINS pDevIns, PPITSTATE pThis, int channel, int val)
528	{
529	PPITCHANNEL pChan = &pThis->channels[channel];
530	TMTIMERHANDLE hTimer = pThis->channels[0].hTimer;
531
532	Assert((val & 1) == val);
533	Assert(PDMDevHlpTimerIsLockOwner(pDevIns, hTimer));
534
535	switch (EFFECTIVE_MODE(pChan->mode))
536	{
537	default:
538	case 0:
539	case 4:
540	/* XXX: just disable/enable counting */
541	break;
542	case 1:
543	case 5:
544	if (pChan->gate < val)
545	{
546	/* restart counting on rising edge */
547	Log(("pitR3SetGate: restarting mode %d\n", pChan->mode));
548	pChan->count_load_time = PDMDevHlpTimerGet(pDevIns, hTimer);
549	pitR3IrqTimerUpdate(pDevIns, pThis, pChan, pChan->count_load_time, pChan->count_load_time, false);
550	}
551	break;
552	case 2:
553	case 3:
554	if (pChan->gate < val)
555	{
556	/* restart counting on rising edge */
557	Log(("pitR3SetGate: restarting mode %d\n", pChan->mode));
558	pChan->count_load_time = pChan->u64ReloadTS = PDMDevHlpTimerGet(pDevIns, hTimer);
559	pitR3IrqTimerUpdate(pDevIns, pThis, pChan, pChan->count_load_time, pChan->count_load_time, false);
560	}
561	/* XXX: disable/enable counting */
562	break;
563	}
564	pChan->gate = val;
565	}
566
567
568	static void pitR3LoadCount(PPDMDEVINS pDevIns, PPITSTATE pThis, PPITCHANNEL pChan, int val)
569	{
570	TMTIMERHANDLE hTimer = pThis->channels[0].hTimer;
571	Assert(PDMDevHlpTimerIsLockOwner(pDevIns, hTimer));
572
573	if (val == 0)
574	val = 0x10000;
575	pChan->count_load_time = pChan->u64ReloadTS = PDMDevHlpTimerGet(pDevIns, hTimer);
576	pChan->count = val;
577	pitR3IrqTimerUpdate(pDevIns, pThis, pChan, pChan->count_load_time, pChan->count_load_time, false);
578
579	/* log the new rate (ch 0 only). */
580	if (pChan->hTimer != NIL_TMTIMERHANDLE /* ch 0 */)
581	{
582	if (pChan->cRelLogEntries < 32)
583	{
584	pChan->cRelLogEntries++;
585	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
586	pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100));
587	}
588	else
589	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
590	pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100));
591	PDMDevHlpTimerSetFrequencyHint(pDevIns, hTimer, PIT_FREQ / pChan->count);
592	}
593	else
594	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d)\n",
595	pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100,
596	pChan - &pThis->channels[0]));
597	}
598
599	#endif /* IN_RING3 */
600
601	/**
602	* @callback_method_impl{FNIOMIOPORTNEWIN}
603	*/
604	static DECLCALLBACK(VBOXSTRICTRC) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
605	{
606	Log2(("pitIOPortRead: offPort=%#x cb=%x\n", offPort, cb));
607	NOREF(pvUser);
608	Assert(offPort < 4);
609	if (cb != 1 \|\| offPort == 3)
610	{
611	Log(("pitIOPortRead: offPort=%#x cb=%x *pu32=unused!\n", offPort, cb));
612	return VERR_IOM_IOPORT_UNUSED;
613	}
614	RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
615
616	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
617	PPITCHANNEL pChan = &pThis->channels[offPort];
618	int ret;
619
620	DEVPIT_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
621	if (pChan->status_latched)
622	{
623	pChan->status_latched = 0;
624	ret = pChan->status;
625	DEVPIT_UNLOCK(pDevIns, pThis);
626	}
627	else if (pChan->count_latched)
628	{
629	switch (pChan->count_latched)
630	{
631	default:
632	case RW_STATE_LSB:
633	ret = pChan->latched_count & 0xff;
634	pChan->count_latched = 0;
635	break;
636	case RW_STATE_MSB:
637	ret = pChan->latched_count >> 8;
638	pChan->count_latched = 0;
639	break;
640	case RW_STATE_WORD0:
641	ret = pChan->latched_count & 0xff;
642	pChan->count_latched = RW_STATE_MSB;
643	break;
644	}
645	DEVPIT_UNLOCK(pDevIns, pThis);
646	}
647	else
648	{
649	DEVPIT_UNLOCK(pDevIns, pThis);
650	DEVPIT_LOCK_BOTH_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
651	int count;
652	switch (pChan->read_state)
653	{
654	default:
655	case RW_STATE_LSB:
656	count = pit_get_count(pDevIns, pThis, pChan);
657	ret = count & 0xff;
658	break;
659	case RW_STATE_MSB:
660	count = pit_get_count(pDevIns, pThis, pChan);
661	ret = (count >> 8) & 0xff;
662	break;
663	case RW_STATE_WORD0:
664	count = pit_get_count(pDevIns, pThis, pChan);
665	ret = count & 0xff;
666	pChan->read_state = RW_STATE_WORD1;
667	break;
668	case RW_STATE_WORD1:
669	count = pit_get_count(pDevIns, pThis, pChan);
670	ret = (count >> 8) & 0xff;
671	pChan->read_state = RW_STATE_WORD0;
672	break;
673	}
674	DEVPIT_UNLOCK_BOTH(pDevIns, pThis);
675	}
676
677	*pu32 = ret;
678	Log2(("pitIOPortRead: offPort=%#x cb=%x pu32=%#04x\n", offPort, cb, pu32));
679	return VINF_SUCCESS;
680	}
681
682
683	/**
684	* @callback_method_impl{FNIOMIOPORTNEWOUT}
685	*/
686	static DECLCALLBACK(VBOXSTRICTRC) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
687	{
688	Log2(("pitIOPortWrite: offPort=%#x cb=%x u32=%#04x\n", offPort, cb, u32));
689	NOREF(pvUser);
690	Assert(offPort < 4);
691
692	if (cb != 1)
693	return VINF_SUCCESS;
694
695	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
696	if (offPort == 3)
697	{
698	/*
699	* Port 43h - Mode/Command Register.
700	* 7 6 5 4 3 2 1 0
701	* * * . . . . . . Select channel: 0 0 = Channel 0
702	* 0 1 = Channel 1
703	* 1 0 = Channel 2
704	* 1 1 = Read-back command (8254 only)
705	* (Illegal on 8253)
706	* (Illegal on PS/2 {JAM})
707	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
708	* 0 1 = Access mode: lobyte only
709	* 1 0 = Access mode: hibyte only
710	* 1 1 = Access mode: lobyte/hibyte
711	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
712	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
713	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
714	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
715	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
716	*/
717	unsigned channel = (u32 >> 6) & 0x3;
718	RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
719	if (channel == 3)
720	{
721	/* read-back command */
722	DEVPIT_LOCK_BOTH_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
723	for (channel = 0; channel < RT_ELEMENTS(pThis->channels); channel++)
724	{
725	PPITCHANNEL pChan = &pThis->channels[channel];
726	if (u32 & (2 << channel))
727	{
728	if (!(u32 & 0x20))
729	pit_latch_count(pDevIns, pThis, pChan);
730	if (!(u32 & 0x10) && !pChan->status_latched)
731	{
732	/* status latch */
733	/* XXX: add BCD and null count */
734	pChan->status = (pit_get_out1(pDevIns, pThis, pChan,
735	PDMDevHlpTimerGet(pDevIns, pThis->channels[0].hTimer)) << 7)
736	\| (pChan->rw_mode << 4)
737	\| (pChan->mode << 1)
738	\| pChan->bcd;
739	pChan->status_latched = 1;
740	}
741	}
742	}
743	DEVPIT_UNLOCK_BOTH(pDevIns, pThis);
744	}
745	else
746	{
747	PPITCHANNEL pChan = &pThis->channels[channel];
748	unsigned access = (u32 >> 4) & 3;
749	if (access == 0)
750	{
751	DEVPIT_LOCK_BOTH_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
752	pit_latch_count(pDevIns, pThis, pChan);
753	DEVPIT_UNLOCK_BOTH(pDevIns, pThis);
754	}
755	else
756	{
757	DEVPIT_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
758	pChan->rw_mode = access;
759	pChan->read_state = access;
760	pChan->write_state = access;
761
762	pChan->mode = (u32 >> 1) & 7;
763	pChan->bcd = u32 & 1;
764	/* XXX: update irq timer ? */
765	DEVPIT_UNLOCK(pDevIns, pThis);
766	}
767	}
768	}
769	else
770	{
771	#ifndef IN_RING3
772	/** @todo There is no reason not to do this in all contexts these
773	* days... */
774	return VINF_IOM_R3_IOPORT_WRITE;
775	#else /* IN_RING3 */
776	/*
777	* Port 40-42h - Channel Data Ports.
778	*/
779	RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
780	PPITCHANNEL pChan = &pThis->channels[offPort];
781	DEVPIT_LOCK_BOTH_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_WRITE);
782	switch (pChan->write_state)
783	{
784	default:
785	case RW_STATE_LSB:
786	pitR3LoadCount(pDevIns, pThis, pChan, u32);
787	break;
788	case RW_STATE_MSB:
789	pitR3LoadCount(pDevIns, pThis, pChan, u32 << 8);
790	break;
791	case RW_STATE_WORD0:
792	pChan->write_latch = u32;
793	pChan->write_state = RW_STATE_WORD1;
794	break;
795	case RW_STATE_WORD1:
796	pitR3LoadCount(pDevIns, pThis, pChan, pChan->write_latch \| (u32 << 8));
797	pChan->write_state = RW_STATE_WORD0;
798	break;
799	}
800	DEVPIT_UNLOCK_BOTH(pDevIns, pThis);
801	#endif /* !IN_RING3 */
802	}
803	return VINF_SUCCESS;
804	}
805
806
807	/**
808	* @callback_method_impl{FNIOMIOPORTNEWIN, Speaker}
809	*/
810	static DECLCALLBACK(VBOXSTRICTRC)
811	pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
812	{
813	RT_NOREF(pvUser, offPort);
814	if (cb == 1)
815	{
816	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
817	DEVPIT_LOCK_BOTH_RETURN(pDevIns, pThis, VINF_IOM_R3_IOPORT_READ);
818
819	const uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->channels[0].hTimer);
820	Assert(PDMDevHlpTimerGetFreq(pDevIns, pThis->channels[0].hTimer) == 1000000000); /* lazy bird. */
821
822	/* bit 6,7 Parity error stuff. */
823	/* bit 5 - mirrors timer 2 output condition. */
824	const int fOut = pit_get_out(pDevIns, pThis, 2, u64Now);
825	/* bit 4 - toggled with each (DRAM?) refresh request, every 15.085 u-op Chan.
826	ASSUMES ns timer freq, see assertion above. */
827	#ifndef FAKE_REFRESH_CLOCK
828	const int fRefresh = (u64Now / 15085) & 1;
829	#else
830	pThis->dummy_refresh_clock ^= 1;
831	const int fRefresh = pThis->dummy_refresh_clock;
832	#endif
833	/* bit 2,3 NMI / parity status stuff. */
834	/* bit 1 - speaker data status */
835	const int fSpeakerStatus = pThis->speaker_data_on;
836	/* bit 0 - timer 2 clock gate to speaker status. */
837	const int fTimer2GateStatus = pit_get_gate(pThis, 2);
838
839	DEVPIT_UNLOCK_BOTH(pDevIns, pThis);
840
841	*pu32 = fTimer2GateStatus
842	\| (fSpeakerStatus << 1)
843	\| (fRefresh << 4)
844	\| (fOut << 5);
845	Log(("pitIOPortSpeakerRead: offPort=%#x cb=%x pu32=%#x\n", offPort, cb, pu32));
846	return VINF_SUCCESS;
847	}
848	Log(("pitIOPortSpeakerRead: offPort=%#x cb=%x *pu32=unused!\n", offPort, cb));
849	return VERR_IOM_IOPORT_UNUSED;
850	}
851
852	#ifdef IN_RING3
853
854	/**
855	* @callback_method_impl{FNIOMIOPORTNEWOUT, Speaker}
856	*/
857	static DECLCALLBACK(VBOXSTRICTRC)
858	pitR3IOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
859	{
860	RT_NOREF(pvUser, offPort);
861	if (cb == 1)
862	{
863	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
864	DEVPIT_LOCK_BOTH_RETURN(pDevIns, pThis, VERR_IGNORED);
865
866	pThis->speaker_data_on = (u32 >> 1) & 1;
867	pitR3SetGate(pDevIns, pThis, 2, u32 & 1);
868
869	/** @todo r=klaus move this to a (system-specific) driver, which can
870	* abstract the details, and if necessary create a thread to minimize
871	* impact on VM execution. */
872	# ifdef RT_OS_LINUX
873	if (pThis->enmSpeakerEmu != PIT_SPEAKER_EMU_NONE)
874	{
875	PPITCHANNEL pChan = &pThis->channels[2];
876	if (pThis->speaker_data_on)
877	{
878	Log2Func(("starting beep freq=%d\n", PIT_FREQ / pChan->count));
879	switch (pThis->enmSpeakerEmu)
880	{
881	case PIT_SPEAKER_EMU_CONSOLE:
882	{
883	int res;
884	res = ioctl(pThis->hHostSpeaker, KIOCSOUND, pChan->count);
885	if (res == -1)
886	{
887	LogRel(("PIT: speaker: ioctl failed errno=%d, disabling emulation\n", errno));
888	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
889	}
890	break;
891	}
892	case PIT_SPEAKER_EMU_EVDEV:
893	{
894	struct input_event e;
895	e.type = EV_SND;
896	e.code = SND_TONE;
897	e.value = PIT_FREQ / pChan->count;
898	int res = write(pThis->hHostSpeaker, &e, sizeof(struct input_event));
899	NOREF(res);
900	break;
901	}
902	case PIT_SPEAKER_EMU_TTY:
903	{
904	int res = write(pThis->hHostSpeaker, "\a", 1);
905	NOREF(res);
906	break;
907	}
908	case PIT_SPEAKER_EMU_NONE:
909	break;
910	default:
911	Log2Func(("unknown speaker emulation %d, disabling emulation\n", pThis->enmSpeakerEmu));
912	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
913	}
914	}
915	else
916	{
917	Log2Func(("stopping beep\n"));
918	switch (pThis->enmSpeakerEmu)
919	{
920	case PIT_SPEAKER_EMU_CONSOLE:
921	/* No error checking here. The Linux device driver
922	* implementation considers it an error (errno=22,
923	* EINVAL) to stop sound if it hasn't been started.
924	* Of course we could detect this by checking only
925	* for enabled->disabled transitions and ignoring
926	* disabled->disabled ones, but it's not worth the
927	* effort. */
928	ioctl(pThis->hHostSpeaker, KIOCSOUND, 0);
929	break;
930	case PIT_SPEAKER_EMU_EVDEV:
931	{
932	struct input_event e;
933	e.type = EV_SND;
934	e.code = SND_TONE;
935	e.value = 0;
936	int res = write(pThis->hHostSpeaker, &e, sizeof(struct input_event));
937	NOREF(res);
938	break;
939	}
940	case PIT_SPEAKER_EMU_TTY:
941	break;
942	case PIT_SPEAKER_EMU_NONE:
943	break;
944	default:
945	Log2Func(("unknown speaker emulation %d, disabling emulation\n", pThis->enmSpeakerEmu));
946	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
947	}
948	}
949	}
950	# endif /* RT_OS_LINUX */
951
952	DEVPIT_UNLOCK_BOTH(pDevIns, pThis);
953	}
954	Log(("pitR3IOPortSpeakerWrite: offPort=%#x cb=%x u32=%#x\n", offPort, cb, u32));
955	return VINF_SUCCESS;
956	}
957
958
959	/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
960
961	/**
962	* @callback_method_impl{FNSSMDEVLIVEEXEC}
963	*/
964	static DECLCALLBACK(int) pitR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
965	{
966	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
967	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
968	RT_NOREF(uPass);
969	pHlp->pfnSSMPutIOPort(pSSM, pThis->IOPortBaseCfg);
970	pHlp->pfnSSMPutU8( pSSM, pThis->channels[0].irq);
971	pHlp->pfnSSMPutBool( pSSM, pThis->fSpeakerCfg);
972	return VINF_SSM_DONT_CALL_AGAIN;
973	}
974
975
976	/**
977	* @callback_method_impl{FNSSMDEVSAVEEXEC}
978	*/
979	static DECLCALLBACK(int) pitR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
980	{
981	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
982	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
983	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
984	AssertRCReturn(rc, rc);
985
986	/* The config. */
987	pitR3LiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
988
989	/* The state. */
990	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
991	{
992	PPITCHANNEL pChan = &pThis->channels[i];
993	pHlp->pfnSSMPutU32(pSSM, pChan->count);
994	pHlp->pfnSSMPutU16(pSSM, pChan->latched_count);
995	pHlp->pfnSSMPutU8(pSSM, pChan->count_latched);
996	pHlp->pfnSSMPutU8(pSSM, pChan->status_latched);
997	pHlp->pfnSSMPutU8(pSSM, pChan->status);
998	pHlp->pfnSSMPutU8(pSSM, pChan->read_state);
999	pHlp->pfnSSMPutU8(pSSM, pChan->write_state);
1000	pHlp->pfnSSMPutU8(pSSM, pChan->write_latch);
1001	pHlp->pfnSSMPutU8(pSSM, pChan->rw_mode);
1002	pHlp->pfnSSMPutU8(pSSM, pChan->mode);
1003	pHlp->pfnSSMPutU8(pSSM, pChan->bcd);
1004	pHlp->pfnSSMPutU8(pSSM, pChan->gate);
1005	pHlp->pfnSSMPutU64(pSSM, pChan->count_load_time);
1006	pHlp->pfnSSMPutU64(pSSM, pChan->u64NextTS);
1007	pHlp->pfnSSMPutU64(pSSM, pChan->u64ReloadTS);
1008	pHlp->pfnSSMPutS64(pSSM, pChan->next_transition_time);
1009	if (pChan->hTimer != NIL_TMTIMERHANDLE)
1010	PDMDevHlpTimerSave(pDevIns, pChan->hTimer, pSSM);
1011	}
1012
1013	pHlp->pfnSSMPutS32(pSSM, pThis->speaker_data_on);
1014	# ifdef FAKE_REFRESH_CLOCK
1015	pHlp->pfnSSMPutS32(pSSM, pThis->dummy_refresh_clock);
1016	# else
1017	pHlp->pfnSSMPutS32(pSSM, 0);
1018	# endif
1019
1020	pHlp->pfnSSMPutBool(pSSM, pThis->fDisabledByHpet);
1021
1022	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1023	return VINF_SUCCESS;
1024	}
1025
1026
1027	/**
1028	* @callback_method_impl{FNSSMDEVLOADEXEC}
1029	*/
1030	static DECLCALLBACK(int) pitR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1031	{
1032	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
1033	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1034	int rc;
1035
1036	if ( uVersion != PIT_SAVED_STATE_VERSION
1037	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_30
1038	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_31)
1039	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1040
1041	/* The config. */
1042	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_30)
1043	{
1044	RTIOPORT IOPortBaseCfg;
1045	rc = pHlp->pfnSSMGetIOPort(pSSM, &IOPortBaseCfg); AssertRCReturn(rc, rc);
1046	if (IOPortBaseCfg != pThis->IOPortBaseCfg)
1047	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - IOPortBaseCfg: saved=%RTiop config=%RTiop"),
1048	IOPortBaseCfg, pThis->IOPortBaseCfg);
1049
1050	uint8_t u8Irq;
1051	rc = pHlp->pfnSSMGetU8(pSSM, &u8Irq); AssertRCReturn(rc, rc);
1052	if (u8Irq != pThis->channels[0].irq)
1053	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - u8Irq: saved=%#x config=%#x"),
1054	u8Irq, pThis->channels[0].irq);
1055
1056	bool fSpeakerCfg;
1057	rc = pHlp->pfnSSMGetBool(pSSM, &fSpeakerCfg); AssertRCReturn(rc, rc);
1058	if (fSpeakerCfg != pThis->fSpeakerCfg)
1059	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fSpeakerCfg: saved=%RTbool config=%RTbool"),
1060	fSpeakerCfg, pThis->fSpeakerCfg);
1061	}
1062
1063	if (uPass != SSM_PASS_FINAL)
1064	return VINF_SUCCESS;
1065
1066	/* The state. */
1067	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1068	{
1069	PPITCHANNEL pChan = &pThis->channels[i];
1070	pHlp->pfnSSMGetU32(pSSM, &pChan->count);
1071	pHlp->pfnSSMGetU16(pSSM, &pChan->latched_count);
1072	pHlp->pfnSSMGetU8(pSSM, &pChan->count_latched);
1073	pHlp->pfnSSMGetU8(pSSM, &pChan->status_latched);
1074	pHlp->pfnSSMGetU8(pSSM, &pChan->status);
1075	pHlp->pfnSSMGetU8(pSSM, &pChan->read_state);
1076	pHlp->pfnSSMGetU8(pSSM, &pChan->write_state);
1077	pHlp->pfnSSMGetU8(pSSM, &pChan->write_latch);
1078	pHlp->pfnSSMGetU8(pSSM, &pChan->rw_mode);
1079	pHlp->pfnSSMGetU8(pSSM, &pChan->mode);
1080	pHlp->pfnSSMGetU8(pSSM, &pChan->bcd);
1081	pHlp->pfnSSMGetU8(pSSM, &pChan->gate);
1082	pHlp->pfnSSMGetU64(pSSM, &pChan->count_load_time);
1083	pHlp->pfnSSMGetU64(pSSM, &pChan->u64NextTS);
1084	pHlp->pfnSSMGetU64(pSSM, &pChan->u64ReloadTS);
1085	pHlp->pfnSSMGetS64(pSSM, &pChan->next_transition_time);
1086	if (pChan->hTimer != NIL_TMTIMERHANDLE)
1087	{
1088	rc = PDMDevHlpTimerLoad(pDevIns, pChan->hTimer, pSSM);
1089	AssertRCReturn(rc, rc);
1090	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
1091	pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100, i));
1092	rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1093	AssertRCReturn(rc, rc);
1094	PDMDevHlpTimerSetFrequencyHint(pDevIns, pChan->hTimer, PIT_FREQ / pChan->count);
1095	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1096	}
1097	pThis->channels[i].cRelLogEntries = 0;
1098	}
1099
1100	pHlp->pfnSSMGetS32(pSSM, &pThis->speaker_data_on);
1101	# ifdef FAKE_REFRESH_CLOCK
1102	pHlp->pfnSSMGetS32(pSSM, &pThis->dummy_refresh_clock);
1103	# else
1104	int32_t u32Dummy;
1105	pHlp->pfnSSMGetS32(pSSM, &u32Dummy);
1106	# endif
1107	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_31)
1108	rc = pHlp->pfnSSMGetBool(pSSM, &pThis->fDisabledByHpet);
1109
1110	return VINF_SUCCESS;
1111	}
1112
1113
1114	/* -=-=-=-=-=- Timer -=-=-=-=-=- */
1115
1116	/**
1117	* @callback_method_impl{FNTMTIMERDEV, User argument points to the PIT channel state.}
1118	*/
1119	static DECLCALLBACK(void) pitR3Timer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
1120	{
1121	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
1122	PPITCHANNEL pChan = (PPITCHANNEL)pvUser;
1123	STAM_PROFILE_ADV_START(&pThis->StatPITHandler, a);
1124	Assert(hTimer == pChan->hTimer);
1125
1126	Log(("pitR3Timer\n"));
1127	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
1128	Assert(PDMDevHlpTimerIsLockOwner(pDevIns, hTimer));
1129
1130	pitR3IrqTimerUpdate(pDevIns, pThis, pChan, pChan->next_transition_time, PDMDevHlpTimerGet(pDevIns, hTimer), true);
1131
1132	STAM_PROFILE_ADV_STOP(&pThis->StatPITHandler, a);
1133	}
1134
1135
1136	/* -=-=-=-=-=- Debug Info -=-=-=-=-=- */
1137
1138	/**
1139	* @callback_method_impl{FNDBGFHANDLERDEV}
1140	*/
1141	static DECLCALLBACK(void) pitR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1142	{
1143	RT_NOREF(pszArgs);
1144	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
1145	unsigned i;
1146	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1147	{
1148	const PITCHANNEL *pChan = &pThis->channels[i];
1149
1150	pHlp->pfnPrintf(pHlp,
1151	"PIT (i8254) channel %d status: irq=%#x\n"
1152	" count=%08x" " latched_count=%04x count_latched=%02x\n"
1153	" status=%02x status_latched=%02x read_state=%02x\n"
1154	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
1155	" mode=%02x bcd=%02x gate=%02x\n"
1156	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
1157	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
1158	,
1159	i, pChan->irq,
1160	pChan->count, pChan->latched_count, pChan->count_latched,
1161	pChan->status, pChan->status_latched, pChan->read_state,
1162	pChan->write_state, pChan->write_latch, pChan->rw_mode,
1163	pChan->mode, pChan->bcd, pChan->gate,
1164	pChan->count_load_time, pChan->next_transition_time,
1165	pChan->u64ReloadTS, pChan->u64NextTS);
1166	}
1167	# ifdef FAKE_REFRESH_CLOCK
1168	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
1169	pThis->speaker_data_on, pThis->dummy_refresh_clock);
1170	# else
1171	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x\n", pThis->speaker_data_on);
1172	# endif
1173	if (pThis->fDisabledByHpet)
1174	pHlp->pfnPrintf(pHlp, "Disabled by HPET\n");
1175	}
1176
1177
1178	/* -=-=-=-=-=- IHpetLegacyNotify -=-=-=-=-=- */
1179
1180	/**
1181	* @interface_method_impl{PDMIHPETLEGACYNOTIFY,pfnModeChanged}
1182	*/
1183	static DECLCALLBACK(void) pitR3NotifyHpetLegacyNotify_ModeChanged(PPDMIHPETLEGACYNOTIFY pInterface, bool fActivated)
1184	{
1185	PPITSTATER3 pThisCC = RT_FROM_MEMBER(pInterface, PITSTATER3, IHpetLegacyNotify);
1186	PPDMDEVINS pDevIns = pThisCC->pDevIns;
1187	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
1188	int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1189	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
1190
1191	pThis->fDisabledByHpet = fActivated;
1192
1193	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1194	}
1195
1196
1197	/* -=-=-=-=-=- PDMDEVINS::IBase -=-=-=-=-=- */
1198
1199	/**
1200	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
1201	*/
1202	static DECLCALLBACK(void ) pitR3QueryInterface(PPDMIBASE pInterface, const char pszIID)
1203	{
1204	PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase);
1205	PPITSTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PPITSTATER3);
1206	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase);
1207	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIHPETLEGACYNOTIFY, &pThisCC->IHpetLegacyNotify);
1208	return NULL;
1209	}
1210
1211
1212	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
1213
1214	/**
1215	* @interface_method_impl{PDMDEVREG,pfnReset}
1216	*/
1217	static DECLCALLBACK(void) pitR3Reset(PPDMDEVINS pDevIns)
1218	{
1219	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
1220	LogFlow(("pitR3Reset: \n"));
1221
1222	DEVPIT_R3_LOCK_BOTH(pDevIns, pThis);
1223
1224	pThis->fDisabledByHpet = false;
1225
1226	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1227	{
1228	PPITCHANNEL pChan = &pThis->channels[i];
1229
1230	# if 1 /* Set everything back to virgin state. (might not be strictly correct) */
1231	pChan->latched_count = 0;
1232	pChan->count_latched = 0;
1233	pChan->status_latched = 0;
1234	pChan->status = 0;
1235	pChan->read_state = 0;
1236	pChan->write_state = 0;
1237	pChan->write_latch = 0;
1238	pChan->rw_mode = 0;
1239	pChan->bcd = 0;
1240	# endif
1241	pChan->u64NextTS = UINT64_MAX;
1242	pChan->cRelLogEntries = 0;
1243	pChan->mode = 3;
1244	pChan->gate = (i != 2);
1245	pitR3LoadCount(pDevIns, pThis, pChan, 0);
1246	}
1247
1248	DEVPIT_UNLOCK_BOTH(pDevIns, pThis);
1249	}
1250
1251	# ifdef RT_OS_LINUX
1252
1253	static int pitR3TryDeviceOpen(const char *pszPath, int flags)
1254	{
1255	int fd = open(pszPath, flags);
1256	if (fd == -1)
1257	LogRel(("PIT: speaker: cannot open \"%s\", errno=%d\n", pszPath, errno));
1258	else
1259	LogRel(("PIT: speaker: opened \"%s\"\n", pszPath));
1260	return fd;
1261	}
1262
1263
1264	static int pitR3TryDeviceOpenSanitizeIoctl(const char *pszPath, int flags)
1265	{
1266	int fd = open(pszPath, flags);
1267	if (fd == -1)
1268	LogRel(("PIT: speaker: cannot open \"%s\", errno=%d\n", pszPath, errno));
1269	else
1270	{
1271	int errno_eviocgsnd0 = 0;
1272	int errno_kiocsound = 0;
1273	if (ioctl(fd, EVIOCGSND(0)) == -1)
1274	{
1275	errno_eviocgsnd0 = errno;
1276	if (ioctl(fd, KIOCSOUND, 1) == -1)
1277	errno_kiocsound = errno;
1278	else
1279	ioctl(fd, KIOCSOUND, 0);
1280	}
1281	if (errno_eviocgsnd0 && errno_kiocsound)
1282	{
1283	LogRel(("PIT: speaker: cannot use \"%s\", ioctl failed errno=%d/errno=%d\n", pszPath, errno_eviocgsnd0, errno_kiocsound));
1284	close(fd);
1285	fd = -1;
1286	}
1287	else
1288	LogRel(("PIT: speaker: opened \"%s\"\n", pszPath));
1289	}
1290	return fd;
1291	}
1292
1293	# endif /* RT_OS_LINUX */
1294
1295	/**
1296	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1297	*/
1298	static DECLCALLBACK(int) pitR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1299	{
1300	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1301	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
1302	PPITSTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PPITSTATER3);
1303	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1304	int rc;
1305	uint8_t u8Irq;
1306	uint16_t u16Base;
1307	bool fSpeaker;
1308	unsigned i;
1309	Assert(iInstance == 0);
1310
1311	/*
1312	* Validate and read the configuration.
1313	*/
1314	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "Irq\|Base\|SpeakerEnabled\|PassthroughSpeaker\|PassthroughSpeakerDevice", "");
1315
1316	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Irq", &u8Irq, 0);
1317	if (RT_FAILURE(rc))
1318	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
1319
1320	rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Base", &u16Base, 0x40);
1321	if (RT_FAILURE(rc))
1322	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
1323
1324	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "SpeakerEnabled", &fSpeaker, true);
1325	if (RT_FAILURE(rc))
1326	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
1327
1328	uint8_t uPassthroughSpeaker;
1329	char *pszPassthroughSpeakerDevice = NULL;
1330	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "PassthroughSpeaker", &uPassthroughSpeaker, 0);
1331	if (RT_FAILURE(rc))
1332	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: failed to read PassthroughSpeaker as uint8_t"));
1333	if (uPassthroughSpeaker)
1334	{
1335	rc = pHlp->pfnCFGMQueryStringAllocDef(pCfg, "PassthroughSpeakerDevice", &pszPassthroughSpeakerDevice, NULL);
1336	if (RT_FAILURE(rc))
1337	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: failed to read PassthroughSpeakerDevice as string"));
1338	}
1339
1340	/*
1341	* Init the data.
1342	*/
1343	pThis->IOPortBaseCfg = u16Base;
1344	pThis->channels[0].irq = u8Irq;
1345	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1346	{
1347	pThis->channels[i].hTimer = NIL_TMTIMERHANDLE;
1348	pThis->channels[i].iChan = i;
1349	}
1350	pThis->fSpeakerCfg = fSpeaker;
1351	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
1352	if (uPassthroughSpeaker)
1353	{
1354	/** @todo r=klaus move this to a (system-specific) driver */
1355	#ifdef RT_OS_LINUX
1356	int fd = -1;
1357	if ((uPassthroughSpeaker == 1 \|\| uPassthroughSpeaker == 100) && fd == -1)
1358	fd = pitR3TryDeviceOpenSanitizeIoctl("/dev/input/by-path/platform-pcspkr-event-spkr", O_WRONLY);
1359	if ((uPassthroughSpeaker == 2 \|\| uPassthroughSpeaker == 100) && fd == -1)
1360	fd = pitR3TryDeviceOpenSanitizeIoctl("/dev/tty", O_WRONLY);
1361	if ((uPassthroughSpeaker == 3 \|\| uPassthroughSpeaker == 100) && fd == -1)
1362	{
1363	fd = pitR3TryDeviceOpenSanitizeIoctl("/dev/tty0", O_WRONLY);
1364	if (fd == -1)
1365	fd = pitR3TryDeviceOpenSanitizeIoctl("/dev/vc/0", O_WRONLY);
1366	}
1367	if ((uPassthroughSpeaker == 9 \|\| uPassthroughSpeaker == 100) && pszPassthroughSpeakerDevice && fd == -1)
1368	fd = pitR3TryDeviceOpenSanitizeIoctl(pszPassthroughSpeakerDevice, O_WRONLY);
1369	if (pThis->enmSpeakerEmu == PIT_SPEAKER_EMU_NONE && fd != -1)
1370	{
1371	pThis->hHostSpeaker = fd;
1372	if (ioctl(fd, EVIOCGSND(0)) != -1)
1373	{
1374	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_EVDEV;
1375	LogRel(("PIT: speaker: emulation mode evdev\n"));
1376	}
1377	else
1378	{
1379	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_CONSOLE;
1380	LogRel(("PIT: speaker: emulation mode console\n"));
1381	}
1382	}
1383	if ((uPassthroughSpeaker == 70 \|\| uPassthroughSpeaker == 100) && fd == -1)
1384	fd = pitR3TryDeviceOpen("/dev/tty", O_WRONLY);
1385	if ((uPassthroughSpeaker == 79 \|\| uPassthroughSpeaker == 100) && pszPassthroughSpeakerDevice && fd == -1)
1386	fd = pitR3TryDeviceOpen(pszPassthroughSpeakerDevice, O_WRONLY);
1387	if (pThis->enmSpeakerEmu == PIT_SPEAKER_EMU_NONE && fd != -1)
1388	{
1389	pThis->hHostSpeaker = fd;
1390	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_TTY;
1391	LogRel(("PIT: speaker: emulation mode tty\n"));
1392	}
1393	if (pThis->enmSpeakerEmu == PIT_SPEAKER_EMU_NONE)
1394	{
1395	Assert(fd == -1);
1396	LogRel(("PIT: speaker: no emulation possible\n"));
1397	}
1398	#else
1399	LogRel(("PIT: speaker: emulation deactivated\n"));
1400	#endif
1401	if (pszPassthroughSpeakerDevice)
1402	{
1403	PDMDevHlpMMHeapFree(pDevIns, pszPassthroughSpeakerDevice);
1404	pszPassthroughSpeakerDevice = NULL;
1405	}
1406	}
1407
1408	/*
1409	* Interfaces
1410	*/
1411	/* IBase */
1412	pDevIns->IBase.pfnQueryInterface = pitR3QueryInterface;
1413	/* IHpetLegacyNotify */
1414	pThisCC->IHpetLegacyNotify.pfnModeChanged = pitR3NotifyHpetLegacyNotify_ModeChanged;
1415	pThisCC->pDevIns = pDevIns;
1416
1417	/*
1418	* We do our own locking. This must be done before creating timers.
1419	*/
1420	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "pit#%u", iInstance);
1421	AssertRCReturn(rc, rc);
1422
1423	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1424	AssertRCReturn(rc, rc);
1425
1426	/*
1427	* Create the timer, make it take our critsect.
1428	*/
1429	rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitR3Timer, &pThis->channels[0],
1430	TMTIMER_FLAGS_NO_CRIT_SECT \| TMTIMER_FLAGS_RING0, "i8254 PIT", &pThis->channels[0].hTimer);
1431	AssertRCReturn(rc, rc);
1432	rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->channels[0].hTimer, &pThis->CritSect);
1433	AssertRCReturn(rc, rc);
1434
1435	/*
1436	* Register I/O ports.
1437	*/
1438	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, u16Base, 4 /cPorts/, pitIOPortWrite, pitIOPortRead,
1439	"i8254 Programmable Interval Timer", NULL /paExtDescs/, &pThis->hIoPorts);
1440	AssertRCReturn(rc, rc);
1441
1442	if (fSpeaker)
1443	{
1444	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, 0x61, 1 /cPorts/, pitR3IOPortSpeakerWrite, pitIOPortSpeakerRead,
1445	"PC Speaker", NULL /paExtDescs/, &pThis->hIoPortSpeaker);
1446	AssertRCReturn(rc, rc);
1447	}
1448
1449	/*
1450	* Saved state.
1451	*/
1452	rc = PDMDevHlpSSMRegister3(pDevIns, PIT_SAVED_STATE_VERSION, sizeof(*pThis), pitR3LiveExec, pitR3SaveExec, pitR3LoadExec);
1453	if (RT_FAILURE(rc))
1454	return rc;
1455
1456	/*
1457	* Initialize the device state.
1458	*/
1459	pitR3Reset(pDevIns);
1460
1461	/*
1462	* Register statistics and debug info.
1463	*/
1464	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1465	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1466
1467	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitR3Info);
1468
1469	return VINF_SUCCESS;
1470	}
1471
1472	#else /* !IN_RING3 */
1473
1474	/**
1475	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1476	*/
1477	static DECLCALLBACK(int) picRZConstruct(PPDMDEVINS pDevIns)
1478	{
1479	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1480	PPITSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPITSTATE);
1481
1482	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1483	AssertRCReturn(rc, rc);
1484
1485	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPorts, pitIOPortWrite, pitIOPortRead, NULL /pvUser/);
1486	AssertRCReturn(rc, rc);
1487
1488	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortSpeaker, NULL /pfnWrite/, pitIOPortSpeakerRead, NULL /pvUser/);
1489	AssertRCReturn(rc, rc);
1490
1491	return VINF_SUCCESS;
1492	}
1493
1494	#endif /* !IN_RING3 */
1495
1496	/**
1497	* The device registration structure.
1498	*/
1499	const PDMDEVREG g_DeviceI8254 =
1500	{
1501	/* .u32Version = */ PDM_DEVREG_VERSION,
1502	/* .uReserved0 = */ 0,
1503	/* .szName = */ "i8254",
1504	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1505	/* .fClass = */ PDM_DEVREG_CLASS_PIT,
1506	/* .cMaxInstances = */ 1,
1507	/* .uSharedVersion = */ 42,
1508	/* .cbInstanceShared = */ sizeof(PITSTATE),
1509	/* .cbInstanceCC = */ CTX_EXPR(sizeof(PITSTATER3), 0, 0),
1510	/* .cbInstanceRC = */ 0,
1511	/* .cMaxPciDevices = */ 0,
1512	/* .cMaxMsixVectors = */ 0,
1513	/* .pszDescription = */ "Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1514	#if defined(IN_RING3)
1515	/* .pszRCMod = */ "VBoxDDRC.rc",
1516	/* .pszR0Mod = */ "VBoxDDR0.r0",
1517	/* .pfnConstruct = */ pitR3Construct,
1518	/* .pfnDestruct = */ NULL,
1519	/* .pfnRelocate = */ NULL,
1520	/* .pfnMemSetup = */ NULL,
1521	/* .pfnPowerOn = */ NULL,
1522	/* .pfnReset = */ pitR3Reset,
1523	/* .pfnSuspend = */ NULL,
1524	/* .pfnResume = */ NULL,
1525	/* .pfnAttach = */ NULL,
1526	/* .pfnDetach = */ NULL,
1527	/* .pfnQueryInterface = */ NULL,
1528	/* .pfnInitComplete = */ NULL,
1529	/* .pfnPowerOff = */ NULL,
1530	/* .pfnSoftReset = */ NULL,
1531	/* .pfnReserved0 = */ NULL,
1532	/* .pfnReserved1 = */ NULL,
1533	/* .pfnReserved2 = */ NULL,
1534	/* .pfnReserved3 = */ NULL,
1535	/* .pfnReserved4 = */ NULL,
1536	/* .pfnReserved5 = */ NULL,
1537	/* .pfnReserved6 = */ NULL,
1538	/* .pfnReserved7 = */ NULL,
1539	#elif defined(IN_RING0)
1540	/* .pfnEarlyConstruct = */ NULL,
1541	/* .pfnConstruct = */ picRZConstruct,
1542	/* .pfnDestruct = */ NULL,
1543	/* .pfnFinalDestruct = */ NULL,
1544	/* .pfnRequest = */ NULL,
1545	/* .pfnReserved0 = */ NULL,
1546	/* .pfnReserved1 = */ NULL,
1547	/* .pfnReserved2 = */ NULL,
1548	/* .pfnReserved3 = */ NULL,
1549	/* .pfnReserved4 = */ NULL,
1550	/* .pfnReserved5 = */ NULL,
1551	/* .pfnReserved6 = */ NULL,
1552	/* .pfnReserved7 = */ NULL,
1553	#elif defined(IN_RC)
1554	/* .pfnConstruct = */ picRZConstruct,
1555	/* .pfnReserved0 = */ NULL,
1556	/* .pfnReserved1 = */ NULL,
1557	/* .pfnReserved2 = */ NULL,
1558	/* .pfnReserved3 = */ NULL,
1559	/* .pfnReserved4 = */ NULL,
1560	/* .pfnReserved5 = */ NULL,
1561	/* .pfnReserved6 = */ NULL,
1562	/* .pfnReserved7 = */ NULL,
1563	#else
1564	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1565	#endif
1566	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1567	};
1568
1569	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 93115

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