DevPit-i8254.cpp@ 73494

Last change on this file since 73494 was 71821, checked in by vboxsync, 7 years ago
DevPit: Increased paranoia level a little.
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1	/* $Id: DevPit-i8254.cpp 71821 2018-04-11 12:06:34Z vboxsync $ */
2	/** @file
3	* DevPIT-i8254 - Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU 8253/8254 interval timer emulation
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Header Files *
46	*********************************************************************************************************************************/
47	#define LOG_GROUP LOG_GROUP_DEV_PIT
48	#include <VBox/vmm/pdmdev.h>
49	#include <VBox/log.h>
50	#include <VBox/vmm/stam.h>
51	#include <iprt/assert.h>
52	#include <iprt/asm-math.h>
53
54	#ifdef IN_RING3
55	# ifdef RT_OS_LINUX
56	# include <fcntl.h>
57	# include <errno.h>
58	# include <unistd.h>
59	# include <stdio.h>
60	# include <linux/kd.h>
61	# include <linux/input.h>
62	# include <sys/ioctl.h>
63	# endif
64	# include <iprt/alloc.h>
65	# include <iprt/string.h>
66	# include <iprt/uuid.h>
67	#endif /* IN_RING3 */
68
69	#include "VBoxDD.h"
70
71
72	/*********************************************************************************************************************************
73	* Defined Constants And Macros *
74	*********************************************************************************************************************************/
75	/** The PIT frequency. */
76	#define PIT_FREQ 1193182
77
78	#define RW_STATE_LSB 1
79	#define RW_STATE_MSB 2
80	#define RW_STATE_WORD0 3
81	#define RW_STATE_WORD1 4
82
83	/** The current saved state version. */
84	#define PIT_SAVED_STATE_VERSION 4
85	/** The saved state version used by VirtualBox 3.1 and earlier.
86	* This did not include disable by HPET flag. */
87	#define PIT_SAVED_STATE_VERSION_VBOX_31 3
88	/** The saved state version used by VirtualBox 3.0 and earlier.
89	* This did not include the config part. */
90	#define PIT_SAVED_STATE_VERSION_VBOX_30 2
91
92	/** @def FAKE_REFRESH_CLOCK
93	* Define this to flip the 15usec refresh bit on every read.
94	* If not defined, it will be flipped correctly. */
95	/* #define FAKE_REFRESH_CLOCK */
96	#ifdef DOXYGEN_RUNNING
97	# define FAKE_REFRESH_CLOCK
98	#endif
99
100	/** The effective counter mode - if bit 1 is set, bit 2 is ignored. */
101	#define EFFECTIVE_MODE(x) ((x) & ~(((x) & 2) << 1))
102
103
104	/**
105	* Acquires the PIT lock or returns.
106	*/
107	#define DEVPIT_LOCK_RETURN(a_pThis, a_rcBusy) \
108	do { \
109	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
110	if (rcLock != VINF_SUCCESS) \
111	return rcLock; \
112	} while (0)
113
114	/**
115	* Releases the PIT lock.
116	*/
117	#define DEVPIT_UNLOCK(a_pThis) \
118	do { PDMCritSectLeave(&(a_pThis)->CritSect); } while (0)
119
120
121	/**
122	* Acquires the TM lock and PIT lock, returns on failure.
123	*/
124	#define DEVPIT_LOCK_BOTH_RETURN(a_pThis, a_rcBusy) \
125	do { \
126	int rcLock = TMTimerLock((a_pThis)->channels[0].CTX_SUFF(pTimer), (a_rcBusy)); \
127	if (rcLock != VINF_SUCCESS) \
128	return rcLock; \
129	rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
130	if (rcLock != VINF_SUCCESS) \
131	{ \
132	TMTimerUnlock((a_pThis)->channels[0].CTX_SUFF(pTimer)); \
133	return rcLock; \
134	} \
135	} while (0)
136
137	#ifdef IN_RING3
138	/**
139	* Acquires the TM lock and PIT lock, ignores failures.
140	*/
141	# define DEVPIT_R3_LOCK_BOTH(a_pThis) \
142	do { \
143	TMTimerLock((a_pThis)->channels[0].CTX_SUFF(pTimer), VERR_IGNORED); \
144	PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
145	} while (0)
146	#endif /* IN_RING3 */
147
148	/**
149	* Releases the PIT lock and TM lock.
150	*/
151	#define DEVPIT_UNLOCK_BOTH(a_pThis) \
152	do { \
153	PDMCritSectLeave(&(a_pThis)->CritSect); \
154	TMTimerUnlock((a_pThis)->channels[0].CTX_SUFF(pTimer)); \
155	} while (0)
156
157
158
159	/*********************************************************************************************************************************
160	* Structures and Typedefs *
161	*********************************************************************************************************************************/
162	/**
163	* The state of one PIT channel.
164	*/
165	typedef struct PITCHANNEL
166	{
167	/** Pointer to the instance data - R3 Ptr. */
168	R3PTRTYPE(struct PITSTATE *) pPitR3;
169	/** The timer - R3 Ptr.
170	* @note Only channel 0 has a timer. */
171	PTMTIMERR3 pTimerR3;
172	/** Pointer to the instance data - R0 Ptr. */
173	R0PTRTYPE(struct PITSTATE *) pPitR0;
174	/** The timer - R0 Ptr.
175	* @note Only channel 0 has a timer. */
176	PTMTIMERR0 pTimerR0;
177	/** Pointer to the instance data - RC Ptr. */
178	RCPTRTYPE(struct PITSTATE *) pPitRC;
179	/** The timer - RC Ptr.
180	* @note Only channel 0 has a timer. */
181	PTMTIMERRC pTimerRC;
182	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
183	uint64_t u64ReloadTS;
184	/** The actual time of the next tick.
185	* As apposed to the next_transition_time which contains the correct time of the next tick. */
186	uint64_t u64NextTS;
187
188	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
189	uint64_t count_load_time;
190	/* irq handling */
191	int64_t next_transition_time;
192	int32_t irq;
193	/** Number of release log entries. Used to prevent flooding. */
194	uint32_t cRelLogEntries;
195
196	uint32_t count; /* can be 65536 */
197	uint16_t latched_count;
198	uint8_t count_latched;
199	uint8_t status_latched;
200
201	uint8_t status;
202	uint8_t read_state;
203	uint8_t write_state;
204	uint8_t write_latch;
205
206	uint8_t rw_mode;
207	uint8_t mode;
208	uint8_t bcd; /* not supported */
209	uint8_t gate; /* timer start */
210
211	} PITCHANNEL;
212	/** Pointer to the state of one PIT channel. */
213	typedef PITCHANNEL *PPITCHANNEL;
214
215	/** Speaker emulation state. */
216	typedef enum PITSPEAKEREMU
217	{
218	PIT_SPEAKER_EMU_NONE = 0,
219	PIT_SPEAKER_EMU_CONSOLE,
220	PIT_SPEAKER_EMU_EVDEV,
221	PIT_SPEAKER_EMU_TTY
222	} PITSPEAKEREMU;
223
224	/**
225	* The whole PIT state.
226	*/
227	typedef struct PITSTATE
228	{
229	/** Channel state. Must come first? */
230	PITCHANNEL channels[3];
231	/** Speaker data. */
232	int32_t speaker_data_on;
233	#ifdef FAKE_REFRESH_CLOCK
234	/** Refresh dummy. */
235	int32_t dummy_refresh_clock;
236	#else
237	uint32_t Alignment1;
238	#endif
239	/** Config: I/O port base. */
240	RTIOPORT IOPortBaseCfg;
241	/** Config: Speaker enabled. */
242	bool fSpeakerCfg;
243	/** Disconnect PIT from the interrupt controllers if requested by HPET. */
244	bool fDisabledByHpet;
245	/** Config: What to do with speaker activity. */
246	PITSPEAKEREMU enmSpeakerEmu;
247	#ifdef RT_OS_LINUX
248	/** File handle for host speaker functionality. */
249	int hHostSpeaker;
250	int afAlignment2;
251	#endif
252	/** PIT port interface. */
253	PDMIHPETLEGACYNOTIFY IHpetLegacyNotify;
254	/** Pointer to the device instance. */
255	PPDMDEVINSR3 pDevIns;
256	/** Number of IRQs that's been raised. */
257	STAMCOUNTER StatPITIrq;
258	/** Profiling the timer callback handler. */
259	STAMPROFILEADV StatPITHandler;
260	/** Critical section protecting the state. */
261	PDMCRITSECT CritSect;
262	} PITSTATE;
263	/** Pointer to the PIT device state. */
264	typedef PITSTATE *PPITSTATE;
265
266
267	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
268
269
270	/*********************************************************************************************************************************
271	* Internal Functions *
272	*********************************************************************************************************************************/
273	#ifdef IN_RING3
274	static void pit_irq_timer_update(PPITCHANNEL pChan, uint64_t current_time, uint64_t now, bool in_timer);
275	#endif
276
277
278	#ifdef IN_RING3
279	# ifdef RT_OS_LINUX
280	static int pitTryDeviceOpen(const char *pszPath, int flags)
281	{
282	int fd = open(pszPath, flags);
283	if (fd == -1)
284	LogRel(("PIT: speaker: cannot open \"%s\", errno=%d\n", pszPath, errno));
285	else
286	LogRel(("PIT: speaker: opened \"%s\"\n", pszPath));
287	return fd;
288	}
289
290	static int pitTryDeviceOpenSanitizeIoctl(const char *pszPath, int flags)
291	{
292	int fd = open(pszPath, flags);
293	if (fd == -1)
294	LogRel(("PIT: speaker: cannot open \"%s\", errno=%d\n", pszPath, errno));
295	else
296	{
297	int errno_eviocgsnd0 = 0;
298	int errno_kiocsound = 0;
299	if (ioctl(fd, EVIOCGSND(0)) == -1)
300	{
301	errno_eviocgsnd0 = errno;
302	if (ioctl(fd, KIOCSOUND, 1) == -1)
303	errno_kiocsound = errno;
304	else
305	ioctl(fd, KIOCSOUND, 0);
306	}
307	if (errno_eviocgsnd0 && errno_kiocsound)
308	{
309	LogRel(("PIT: speaker: cannot use \"%s\", ioctl failed errno=%d/errno=%d\n", pszPath, errno_eviocgsnd0, errno_kiocsound));
310	close(fd);
311	fd = -1;
312	}
313	else
314	LogRel(("PIT: speaker: opened \"%s\"\n", pszPath));
315	}
316	return fd;
317	}
318	# endif /* RT_OS_LINUX */
319	#endif /* IN_RING3 */
320
321	static int pit_get_count(PPITCHANNEL pChan)
322	{
323	uint64_t d;
324	PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
325	Assert(TMTimerIsLockOwner(pTimer));
326
327	if (EFFECTIVE_MODE(pChan->mode) == 2)
328	{
329	if (pChan->u64NextTS == UINT64_MAX)
330	{
331	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - pChan->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
332	return pChan->count - (d % pChan->count); /** @todo check this value. */
333	}
334	uint64_t Interval = pChan->u64NextTS - pChan->u64ReloadTS;
335	if (!Interval)
336	return pChan->count - 1; /** @todo This is WRONG! But I'm too tired to fix it properly and just want to shut up a DIV/0 trap now. */
337	d = TMTimerGet(pTimer);
338	d = ASMMultU64ByU32DivByU32(d - pChan->u64ReloadTS, pChan->count, Interval);
339	if (d >= pChan->count)
340	return 1;
341	return pChan->count - d;
342	}
343
344	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - pChan->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
345	int counter;
346	switch (EFFECTIVE_MODE(pChan->mode))
347	{
348	case 0:
349	case 1:
350	case 4:
351	case 5:
352	counter = (pChan->count - d) & 0xffff;
353	break;
354	case 3:
355	/* XXX: may be incorrect for odd counts */
356	counter = pChan->count - ((2 * d) % pChan->count);
357	break;
358	default:
359	counter = pChan->count - (d % pChan->count);
360	break;
361	}
362	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
363	return counter;
364	}
365
366	/* get pit output bit */
367	static int pit_get_out1(PPITCHANNEL pChan, int64_t current_time)
368	{
369	PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
370	uint64_t d;
371	int out;
372
373	d = ASMMultU64ByU32DivByU32(current_time - pChan->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
374	switch (EFFECTIVE_MODE(pChan->mode))
375	{
376	default:
377	case 0:
378	out = (d >= pChan->count);
379	break;
380	case 1:
381	out = (d < pChan->count);
382	break;
383	case 2:
384	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, pChan->count, (unsigned)(d % pChan->count)));
385	if ((d % pChan->count) == 0 && d != 0)
386	out = 1;
387	else
388	out = 0;
389	break;
390	case 3:
391	out = (d % pChan->count) < ((pChan->count + 1) >> 1);
392	break;
393	case 4:
394	case 5:
395	out = (d != pChan->count);
396	break;
397	}
398	return out;
399	}
400
401
402	static int pit_get_out(PPITSTATE pThis, int channel, int64_t current_time)
403	{
404	PPITCHANNEL pChan = &pThis->channels[channel];
405	return pit_get_out1(pChan, current_time);
406	}
407
408
409	static int pit_get_gate(PPITSTATE pThis, int channel)
410	{
411	PPITCHANNEL pChan = &pThis->channels[channel];
412	return pChan->gate;
413	}
414
415
416	/* if already latched, do not latch again */
417	static void pit_latch_count(PPITCHANNEL pChan)
418	{
419	if (!pChan->count_latched)
420	{
421	pChan->latched_count = pit_get_count(pChan);
422	pChan->count_latched = pChan->rw_mode;
423	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
424	pChan->latched_count, ASMMultU64ByU32DivByU32(pChan->count - pChan->latched_count, 1000000000, PIT_FREQ),
425	pChan->count, pChan->mode));
426	}
427	}
428
429	#ifdef IN_RING3
430
431	/* val must be 0 or 1 */
432	static void pit_set_gate(PPITSTATE pThis, int channel, int val)
433	{
434	PPITCHANNEL pChan = &pThis->channels[channel];
435	PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
436
437	Assert((val & 1) == val);
438	Assert(TMTimerIsLockOwner(pTimer));
439
440	switch (EFFECTIVE_MODE(pChan->mode))
441	{
442	default:
443	case 0:
444	case 4:
445	/* XXX: just disable/enable counting */
446	break;
447	case 1:
448	case 5:
449	if (pChan->gate < val)
450	{
451	/* restart counting on rising edge */
452	Log(("pit_set_gate: restarting mode %d\n", pChan->mode));
453	pChan->count_load_time = TMTimerGet(pTimer);
454	pit_irq_timer_update(pChan, pChan->count_load_time, pChan->count_load_time, false);
455	}
456	break;
457	case 2:
458	case 3:
459	if (pChan->gate < val)
460	{
461	/* restart counting on rising edge */
462	Log(("pit_set_gate: restarting mode %d\n", pChan->mode));
463	pChan->count_load_time = pChan->u64ReloadTS = TMTimerGet(pTimer);
464	pit_irq_timer_update(pChan, pChan->count_load_time, pChan->count_load_time, false);
465	}
466	/* XXX: disable/enable counting */
467	break;
468	}
469	pChan->gate = val;
470	}
471
472	static void pit_load_count(PPITCHANNEL pChan, int val)
473	{
474	PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
475	Assert(TMTimerIsLockOwner(pTimer));
476
477	if (val == 0)
478	val = 0x10000;
479	pChan->count_load_time = pChan->u64ReloadTS = TMTimerGet(pTimer);
480	pChan->count = val;
481	pit_irq_timer_update(pChan, pChan->count_load_time, pChan->count_load_time, false);
482
483	/* log the new rate (ch 0 only). */
484	if (pChan->pTimerR3 /* ch 0 */)
485	{
486	if (pChan->cRelLogEntries++ < 32)
487	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
488	pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100));
489	else
490	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
491	pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100));
492	TMTimerSetFrequencyHint(pChan->CTX_SUFF(pTimer), PIT_FREQ / pChan->count);
493	}
494	else
495	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d)\n",
496	pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100,
497	pChan - &pChan->CTX_SUFF(pPit)->channels[0]));
498	}
499
500	/* return -1 if no transition will occur. */
501	static int64_t pit_get_next_transition_time(PPITCHANNEL pChan, uint64_t current_time)
502	{
503	PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
504	uint64_t d, next_time, base;
505	uint32_t period2;
506
507	d = ASMMultU64ByU32DivByU32(current_time - pChan->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
508	switch(EFFECTIVE_MODE(pChan->mode))
509	{
510	default:
511	case 0:
512	case 1:
513	if (d < pChan->count)
514	next_time = pChan->count;
515	else
516	return -1;
517	break;
518
519	/*
520	* Mode 2: The period is 'count' PIT ticks.
521	* When the counter reaches 1 we set the output low (for channel 0 that
522	* means lowering IRQ0). On the next tick, where we should be decrementing
523	* from 1 to 0, the count is loaded and the output goes high (channel 0
524	* means raising IRQ0 again and triggering timer interrupt).
525	*
526	* In VirtualBox we compress the pulse and flip-flop the IRQ line at the
527	* end of the period, which signals an interrupt at the exact same time.
528	*/
529	case 2:
530	base = (d / pChan->count) * pChan->count;
531	#ifndef VBOX /* see above */
532	if ((d - base) == 0 && d != 0)
533	next_time = base + pChan->count - 1;
534	else
535	#endif
536	next_time = base + pChan->count;
537	break;
538	case 3:
539	base = (d / pChan->count) * pChan->count;
540	period2 = ((pChan->count + 1) >> 1);
541	if ((d - base) < period2)
542	next_time = base + period2;
543	else
544	next_time = base + pChan->count;
545	break;
546
547	/* Modes 4 and 5 generate a short pulse at the end of the time delay. This
548	* is similar to mode 2, except modes 4/5 aren't periodic. We use the same
549	* optimization - only use one timer callback and pulse the IRQ.
550	* Note: Tickless Linux kernels use PIT mode 4 with 'nolapic'.
551	*/
552	case 4:
553	case 5:
554	#ifdef VBOX
555	if (d <= pChan->count)
556	next_time = pChan->count;
557	#else
558	if (d < pChan->count)
559	next_time = pChan->count;
560	else if (d == pChan->count)
561	next_time = pChan->count + 1;
562	#endif
563	else
564	return -1;
565	break;
566	}
567
568	/* convert to timer units */
569	LogFlow(("PIT: next_time=%'14RU64 %'20RU64 mode=%#x count=%#06x\n", next_time,
570	ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), pChan->mode, pChan->count));
571	next_time = pChan->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
572
573	/* fix potential rounding problems */
574	if (next_time <= current_time)
575	next_time = current_time;
576
577	/* Add one to next_time; if we don't, integer truncation will cause
578	* the algorithm to think that at the end of each period, it'pChan still
579	* within the first one instead of at the beginning of the next one.
580	*/
581	return next_time + 1;
582	}
583
584	static void pit_irq_timer_update(PPITCHANNEL pChan, uint64_t current_time, uint64_t now, bool in_timer)
585	{
586	int64_t expire_time;
587	int irq_level;
588	Assert(TMTimerIsLockOwner(pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer)));
589
590	if (!pChan->CTX_SUFF(pTimer))
591	return;
592	expire_time = pit_get_next_transition_time(pChan, current_time);
593	irq_level = pit_get_out1(pChan, current_time) ? PDM_IRQ_LEVEL_HIGH : PDM_IRQ_LEVEL_LOW;
594
595	/* If PIT is disabled by HPET - simply disconnect ticks from interrupt controllers,
596	* but do not modify other aspects of device operation.
597	*/
598	if (!pChan->pPitR3->fDisabledByHpet)
599	{
600	PPDMDEVINS pDevIns = pChan->CTX_SUFF(pPit)->pDevIns;
601
602	switch (EFFECTIVE_MODE(pChan->mode))
603	{
604	case 2:
605	case 4:
606	case 5:
607	/* We just flip-flop the IRQ line to save an extra timer call,
608	* which isn't generally required. However, the pulse is only
609	* generated when running on the timer callback (and thus on
610	* the trailing edge of the output signal pulse).
611	*/
612	if (in_timer)
613	{
614	PDMDevHlpISASetIrq(pDevIns, pChan->irq, PDM_IRQ_LEVEL_FLIP_FLOP);
615	break;
616	}
617	RT_FALL_THRU();
618	default:
619	PDMDevHlpISASetIrq(pDevIns, pChan->irq, irq_level);
620	break;
621	}
622	}
623
624	if (irq_level)
625	{
626	pChan->u64ReloadTS = now;
627	STAM_COUNTER_INC(&pChan->CTX_SUFF(pPit)->StatPITIrq);
628	}
629
630	if (expire_time != -1)
631	{
632	Log3(("pit_irq_timer_update: next=%'RU64 now=%'RU64\n", expire_time, now));
633	pChan->u64NextTS = expire_time;
634	TMTimerSet(pChan->CTX_SUFF(pTimer), pChan->u64NextTS);
635	}
636	else
637	{
638	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", pChan->mode, pChan->count, irq_level));
639	TMTimerStop(pChan->CTX_SUFF(pTimer));
640	pChan->u64NextTS = UINT64_MAX;
641	}
642	pChan->next_transition_time = expire_time;
643	}
644
645	#endif /* IN_RING3 */
646
647
648	/**
649	* @callback_method_impl{FNIOMIOPORTIN}
650	*/
651	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
652	{
653	Log2(("pitIOPortRead: uPort=%#x cb=%x\n", uPort, cb));
654	NOREF(pvUser);
655	uPort &= 3;
656	if (cb != 1 \|\| uPort == 3)
657	{
658	Log(("pitIOPortRead: uPort=%#x cb=%x *pu32=unused!\n", uPort, cb));
659	return VERR_IOM_IOPORT_UNUSED;
660	}
661	RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
662
663	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
664	PPITCHANNEL pChan = &pThis->channels[uPort];
665	int ret;
666
667	DEVPIT_LOCK_RETURN(pThis, VINF_IOM_R3_IOPORT_READ);
668	if (pChan->status_latched)
669	{
670	pChan->status_latched = 0;
671	ret = pChan->status;
672	DEVPIT_UNLOCK(pThis);
673	}
674	else if (pChan->count_latched)
675	{
676	switch (pChan->count_latched)
677	{
678	default:
679	case RW_STATE_LSB:
680	ret = pChan->latched_count & 0xff;
681	pChan->count_latched = 0;
682	break;
683	case RW_STATE_MSB:
684	ret = pChan->latched_count >> 8;
685	pChan->count_latched = 0;
686	break;
687	case RW_STATE_WORD0:
688	ret = pChan->latched_count & 0xff;
689	pChan->count_latched = RW_STATE_MSB;
690	break;
691	}
692	DEVPIT_UNLOCK(pThis);
693	}
694	else
695	{
696	DEVPIT_UNLOCK(pThis);
697	DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_READ);
698	int count;
699	switch (pChan->read_state)
700	{
701	default:
702	case RW_STATE_LSB:
703	count = pit_get_count(pChan);
704	ret = count & 0xff;
705	break;
706	case RW_STATE_MSB:
707	count = pit_get_count(pChan);
708	ret = (count >> 8) & 0xff;
709	break;
710	case RW_STATE_WORD0:
711	count = pit_get_count(pChan);
712	ret = count & 0xff;
713	pChan->read_state = RW_STATE_WORD1;
714	break;
715	case RW_STATE_WORD1:
716	count = pit_get_count(pChan);
717	ret = (count >> 8) & 0xff;
718	pChan->read_state = RW_STATE_WORD0;
719	break;
720	}
721	DEVPIT_UNLOCK_BOTH(pThis);
722	}
723
724	*pu32 = ret;
725	Log2(("pitIOPortRead: uPort=%#x cb=%x pu32=%#04x\n", uPort, cb, pu32));
726	return VINF_SUCCESS;
727	}
728
729
730	/**
731	* @callback_method_impl{FNIOMIOPORTOUT}
732	*/
733	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
734	{
735	Log2(("pitIOPortWrite: uPort=%#x cb=%x u32=%#04x\n", uPort, cb, u32));
736	NOREF(pvUser);
737	if (cb != 1)
738	return VINF_SUCCESS;
739
740	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
741	uPort &= 3;
742	if (uPort == 3)
743	{
744	/*
745	* Port 43h - Mode/Command Register.
746	* 7 6 5 4 3 2 1 0
747	* * * . . . . . . Select channel: 0 0 = Channel 0
748	* 0 1 = Channel 1
749	* 1 0 = Channel 2
750	* 1 1 = Read-back command (8254 only)
751	* (Illegal on 8253)
752	* (Illegal on PS/2 {JAM})
753	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
754	* 0 1 = Access mode: lobyte only
755	* 1 0 = Access mode: hibyte only
756	* 1 1 = Access mode: lobyte/hibyte
757	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
758	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
759	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
760	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
761	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
762	*/
763	unsigned channel = (u32 >> 6) & 0x3;
764	RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
765	if (channel == 3)
766	{
767	/* read-back command */
768	DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_WRITE);
769	for (channel = 0; channel < RT_ELEMENTS(pThis->channels); channel++)
770	{
771	PPITCHANNEL pChan = &pThis->channels[channel];
772	if (u32 & (2 << channel))
773	{
774	if (!(u32 & 0x20))
775	pit_latch_count(pChan);
776	if (!(u32 & 0x10) && !pChan->status_latched)
777	{
778	/* status latch */
779	/* XXX: add BCD and null count */
780	PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
781	pChan->status = (pit_get_out1(pChan, TMTimerGet(pTimer)) << 7)
782	\| (pChan->rw_mode << 4)
783	\| (pChan->mode << 1)
784	\| pChan->bcd;
785	pChan->status_latched = 1;
786	}
787	}
788	}
789	DEVPIT_UNLOCK_BOTH(pThis);
790	}
791	else
792	{
793	PPITCHANNEL pChan = &pThis->channels[channel];
794	unsigned access = (u32 >> 4) & 3;
795	if (access == 0)
796	{
797	DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_WRITE);
798	pit_latch_count(pChan);
799	DEVPIT_UNLOCK_BOTH(pThis);
800	}
801	else
802	{
803	DEVPIT_LOCK_RETURN(pThis, VINF_IOM_R3_IOPORT_WRITE);
804	pChan->rw_mode = access;
805	pChan->read_state = access;
806	pChan->write_state = access;
807
808	pChan->mode = (u32 >> 1) & 7;
809	pChan->bcd = u32 & 1;
810	/* XXX: update irq timer ? */
811	DEVPIT_UNLOCK(pThis);
812	}
813	}
814	}
815	else
816	{
817	#ifndef IN_RING3
818	/** @todo There is no reason not to do this in all contexts these
819	* days... */
820	return VINF_IOM_R3_IOPORT_WRITE;
821	#else /* IN_RING3 */
822	/*
823	* Port 40-42h - Channel Data Ports.
824	*/
825	RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia */
826	PPITCHANNEL pChan = &pThis->channels[uPort];
827	DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_WRITE);
828	switch (pChan->write_state)
829	{
830	default:
831	case RW_STATE_LSB:
832	pit_load_count(pChan, u32);
833	break;
834	case RW_STATE_MSB:
835	pit_load_count(pChan, u32 << 8);
836	break;
837	case RW_STATE_WORD0:
838	pChan->write_latch = u32;
839	pChan->write_state = RW_STATE_WORD1;
840	break;
841	case RW_STATE_WORD1:
842	pit_load_count(pChan, pChan->write_latch \| (u32 << 8));
843	pChan->write_state = RW_STATE_WORD0;
844	break;
845	}
846	DEVPIT_UNLOCK_BOTH(pThis);
847	#endif /* !IN_RING3 */
848	}
849	return VINF_SUCCESS;
850	}
851
852
853	/**
854	* @callback_method_impl{FNIOMIOPORTIN, Speaker}
855	*/
856	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT uPort, uint32_t pu32, unsigned cb)
857	{
858	RT_NOREF2(pvUser, uPort);
859	if (cb == 1)
860	{
861	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
862	DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_READ);
863
864	const uint64_t u64Now = TMTimerGet(pThis->channels[0].CTX_SUFF(pTimer));
865	Assert(TMTimerGetFreq(pThis->channels[0].CTX_SUFF(pTimer)) == 1000000000); /* lazy bird. */
866
867	/* bit 6,7 Parity error stuff. */
868	/* bit 5 - mirrors timer 2 output condition. */
869	const int fOut = pit_get_out(pThis, 2, u64Now);
870	/* bit 4 - toggled with each (DRAM?) refresh request, every 15.085 u-op Chan.
871	ASSUMES ns timer freq, see assertion above. */
872	#ifndef FAKE_REFRESH_CLOCK
873	const int fRefresh = (u64Now / 15085) & 1;
874	#else
875	pThis->dummy_refresh_clock ^= 1;
876	const int fRefresh = pThis->dummy_refresh_clock;
877	#endif
878	/* bit 2,3 NMI / parity status stuff. */
879	/* bit 1 - speaker data status */
880	const int fSpeakerStatus = pThis->speaker_data_on;
881	/* bit 0 - timer 2 clock gate to speaker status. */
882	const int fTimer2GateStatus = pit_get_gate(pThis, 2);
883
884	DEVPIT_UNLOCK_BOTH(pThis);
885
886	*pu32 = fTimer2GateStatus
887	\| (fSpeakerStatus << 1)
888	\| (fRefresh << 4)
889	\| (fOut << 5);
890	Log(("pitIOPortSpeakerRead: uPort=%#x cb=%x pu32=%#x\n", uPort, cb, pu32));
891	return VINF_SUCCESS;
892	}
893	Log(("pitIOPortSpeakerRead: uPort=%#x cb=%x *pu32=unused!\n", uPort, cb));
894	return VERR_IOM_IOPORT_UNUSED;
895	}
896
897	#ifdef IN_RING3
898
899	/**
900	* @callback_method_impl{FNIOMIOPORTOUT, Speaker}
901	*/
902	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
903	{
904	RT_NOREF2(pvUser, uPort);
905	if (cb == 1)
906	{
907	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
908	DEVPIT_LOCK_BOTH_RETURN(pThis, VERR_IGNORED);
909
910	pThis->speaker_data_on = (u32 >> 1) & 1;
911	pit_set_gate(pThis, 2, u32 & 1);
912
913	/** @todo r=klaus move this to a (system-specific) driver, which can
914	* abstract the details, and if necessary create a thread to minimize
915	* impact on VM execution. */
916	#ifdef RT_OS_LINUX
917	if (pThis->enmSpeakerEmu != PIT_SPEAKER_EMU_NONE)
918	{
919	PPITCHANNEL pChan = &pThis->channels[2];
920	if (pThis->speaker_data_on)
921	{
922	Log2Func(("starting beep freq=%d\n", PIT_FREQ / pChan->count));
923	switch (pThis->enmSpeakerEmu)
924	{
925	case PIT_SPEAKER_EMU_CONSOLE:
926	{
927	int res;
928	res = ioctl(pThis->hHostSpeaker, KIOCSOUND, pChan->count);
929	if (res == -1)
930	{
931	LogRel(("PIT: speaker: ioctl failed errno=%d, disabling emulation\n", errno));
932	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
933	}
934	break;
935	}
936	case PIT_SPEAKER_EMU_EVDEV:
937	{
938	struct input_event e;
939	e.type = EV_SND;
940	e.code = SND_TONE;
941	e.value = PIT_FREQ / pChan->count;
942	int res = write(pThis->hHostSpeaker, &e, sizeof(struct input_event));
943	NOREF(res);
944	break;
945	}
946	case PIT_SPEAKER_EMU_TTY:
947	{
948	int res = write(pThis->hHostSpeaker, "\a", 1);
949	NOREF(res);
950	break;
951	}
952	case PIT_SPEAKER_EMU_NONE:
953	break;
954	default:
955	Log2Func(("unknown speaker emulation %d, disabling emulation\n", pThis->enmSpeakerEmu));
956	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
957	}
958	}
959	else
960	{
961	Log2Func(("stopping beep\n"));
962	switch (pThis->enmSpeakerEmu)
963	{
964	case PIT_SPEAKER_EMU_CONSOLE:
965	/* No error checking here. The Linux device driver
966	* implementation considers it an error (errno=22,
967	* EINVAL) to stop sound if it hasn't been started.
968	* Of course we could detect this by checking only
969	* for enabled->disabled transitions and ignoring
970	* disabled->disabled ones, but it's not worth the
971	* effort. */
972	ioctl(pThis->hHostSpeaker, KIOCSOUND, 0);
973	break;
974	case PIT_SPEAKER_EMU_EVDEV:
975	{
976	struct input_event e;
977	e.type = EV_SND;
978	e.code = SND_TONE;
979	e.value = 0;
980	int res = write(pThis->hHostSpeaker, &e, sizeof(struct input_event));
981	NOREF(res);
982	break;
983	}
984	case PIT_SPEAKER_EMU_TTY:
985	break;
986	case PIT_SPEAKER_EMU_NONE:
987	break;
988	default:
989	Log2Func(("unknown speaker emulation %d, disabling emulation\n", pThis->enmSpeakerEmu));
990	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
991	}
992	}
993	}
994	#endif
995
996	DEVPIT_UNLOCK_BOTH(pThis);
997	}
998	Log(("pitIOPortSpeakerWrite: uPort=%#x cb=%x u32=%#x\n", uPort, cb, u32));
999	return VINF_SUCCESS;
1000	}
1001
1002
1003	/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
1004
1005	/**
1006	* @callback_method_impl{FNSSMDEVLIVEEXEC}
1007	*/
1008	static DECLCALLBACK(int) pitLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
1009	{
1010	RT_NOREF1(uPass);
1011	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1012	SSMR3PutIOPort(pSSM, pThis->IOPortBaseCfg);
1013	SSMR3PutU8( pSSM, pThis->channels[0].irq);
1014	SSMR3PutBool( pSSM, pThis->fSpeakerCfg);
1015	return VINF_SSM_DONT_CALL_AGAIN;
1016	}
1017
1018
1019	/**
1020	* @callback_method_impl{FNSSMDEVSAVEEXEC}
1021	*/
1022	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1023	{
1024	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1025	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1026
1027	/* The config. */
1028	pitLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
1029
1030	/* The state. */
1031	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1032	{
1033	PPITCHANNEL pChan = &pThis->channels[i];
1034	SSMR3PutU32(pSSM, pChan->count);
1035	SSMR3PutU16(pSSM, pChan->latched_count);
1036	SSMR3PutU8(pSSM, pChan->count_latched);
1037	SSMR3PutU8(pSSM, pChan->status_latched);
1038	SSMR3PutU8(pSSM, pChan->status);
1039	SSMR3PutU8(pSSM, pChan->read_state);
1040	SSMR3PutU8(pSSM, pChan->write_state);
1041	SSMR3PutU8(pSSM, pChan->write_latch);
1042	SSMR3PutU8(pSSM, pChan->rw_mode);
1043	SSMR3PutU8(pSSM, pChan->mode);
1044	SSMR3PutU8(pSSM, pChan->bcd);
1045	SSMR3PutU8(pSSM, pChan->gate);
1046	SSMR3PutU64(pSSM, pChan->count_load_time);
1047	SSMR3PutU64(pSSM, pChan->u64NextTS);
1048	SSMR3PutU64(pSSM, pChan->u64ReloadTS);
1049	SSMR3PutS64(pSSM, pChan->next_transition_time);
1050	if (pChan->CTX_SUFF(pTimer))
1051	TMR3TimerSave(pChan->CTX_SUFF(pTimer), pSSM);
1052	}
1053
1054	SSMR3PutS32(pSSM, pThis->speaker_data_on);
1055	#ifdef FAKE_REFRESH_CLOCK
1056	SSMR3PutS32(pSSM, pThis->dummy_refresh_clock);
1057	#else
1058	SSMR3PutS32(pSSM, 0);
1059	#endif
1060
1061	SSMR3PutBool(pSSM, pThis->fDisabledByHpet);
1062
1063	PDMCritSectLeave(&pThis->CritSect);
1064	return VINF_SUCCESS;
1065	}
1066
1067
1068	/**
1069	* @callback_method_impl{FNSSMDEVLOADEXEC}
1070	*/
1071	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1072	{
1073	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1074	int rc;
1075
1076	if ( uVersion != PIT_SAVED_STATE_VERSION
1077	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_30
1078	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_31)
1079	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1080
1081	/* The config. */
1082	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_30)
1083	{
1084	RTIOPORT IOPortBaseCfg;
1085	rc = SSMR3GetIOPort(pSSM, &IOPortBaseCfg); AssertRCReturn(rc, rc);
1086	if (IOPortBaseCfg != pThis->IOPortBaseCfg)
1087	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - IOPortBaseCfg: saved=%RTiop config=%RTiop"),
1088	IOPortBaseCfg, pThis->IOPortBaseCfg);
1089
1090	uint8_t u8Irq;
1091	rc = SSMR3GetU8(pSSM, &u8Irq); AssertRCReturn(rc, rc);
1092	if (u8Irq != pThis->channels[0].irq)
1093	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - u8Irq: saved=%#x config=%#x"),
1094	u8Irq, pThis->channels[0].irq);
1095
1096	bool fSpeakerCfg;
1097	rc = SSMR3GetBool(pSSM, &fSpeakerCfg); AssertRCReturn(rc, rc);
1098	if (fSpeakerCfg != pThis->fSpeakerCfg)
1099	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fSpeakerCfg: saved=%RTbool config=%RTbool"),
1100	fSpeakerCfg, pThis->fSpeakerCfg);
1101	}
1102
1103	if (uPass != SSM_PASS_FINAL)
1104	return VINF_SUCCESS;
1105
1106	/* The state. */
1107	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1108	{
1109	PPITCHANNEL pChan = &pThis->channels[i];
1110	SSMR3GetU32(pSSM, &pChan->count);
1111	SSMR3GetU16(pSSM, &pChan->latched_count);
1112	SSMR3GetU8(pSSM, &pChan->count_latched);
1113	SSMR3GetU8(pSSM, &pChan->status_latched);
1114	SSMR3GetU8(pSSM, &pChan->status);
1115	SSMR3GetU8(pSSM, &pChan->read_state);
1116	SSMR3GetU8(pSSM, &pChan->write_state);
1117	SSMR3GetU8(pSSM, &pChan->write_latch);
1118	SSMR3GetU8(pSSM, &pChan->rw_mode);
1119	SSMR3GetU8(pSSM, &pChan->mode);
1120	SSMR3GetU8(pSSM, &pChan->bcd);
1121	SSMR3GetU8(pSSM, &pChan->gate);
1122	SSMR3GetU64(pSSM, &pChan->count_load_time);
1123	SSMR3GetU64(pSSM, &pChan->u64NextTS);
1124	SSMR3GetU64(pSSM, &pChan->u64ReloadTS);
1125	SSMR3GetS64(pSSM, &pChan->next_transition_time);
1126	if (pChan->CTX_SUFF(pTimer))
1127	{
1128	TMR3TimerLoad(pChan->CTX_SUFF(pTimer), pSSM);
1129	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
1130	pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100, i));
1131	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1132	TMTimerSetFrequencyHint(pChan->CTX_SUFF(pTimer), PIT_FREQ / pChan->count);
1133	PDMCritSectLeave(&pThis->CritSect);
1134	}
1135	pThis->channels[i].cRelLogEntries = 0;
1136	}
1137
1138	SSMR3GetS32(pSSM, &pThis->speaker_data_on);
1139	#ifdef FAKE_REFRESH_CLOCK
1140	SSMR3GetS32(pSSM, &pThis->dummy_refresh_clock);
1141	#else
1142	int32_t u32Dummy;
1143	SSMR3GetS32(pSSM, &u32Dummy);
1144	#endif
1145	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_31)
1146	SSMR3GetBool(pSSM, &pThis->fDisabledByHpet);
1147
1148	return VINF_SUCCESS;
1149	}
1150
1151
1152	/* -=-=-=-=-=- Timer -=-=-=-=-=- */
1153
1154	/**
1155	* @callback_method_impl{FNTMTIMERDEV}
1156	* @param pvUser Pointer to the PIT channel state.
1157	*/
1158	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1159	{
1160	RT_NOREF1(pDevIns);
1161	PPITCHANNEL pChan = (PPITCHANNEL)pvUser;
1162	STAM_PROFILE_ADV_START(&pChan->CTX_SUFF(pPit)->StatPITHandler, a);
1163
1164	Log(("pitTimer\n"));
1165	Assert(PDMCritSectIsOwner(&PDMINS_2_DATA(pDevIns, PPITSTATE)->CritSect));
1166	Assert(TMTimerIsLockOwner(pTimer));
1167
1168	pit_irq_timer_update(pChan, pChan->next_transition_time, TMTimerGet(pTimer), true);
1169
1170	STAM_PROFILE_ADV_STOP(&pChan->CTX_SUFF(pPit)->StatPITHandler, a);
1171	}
1172
1173
1174	/* -=-=-=-=-=- Debug Info -=-=-=-=-=- */
1175
1176	/**
1177	* @callback_method_impl{FNDBGFHANDLERDEV}
1178	*/
1179	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1180	{
1181	RT_NOREF1(pszArgs);
1182	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1183	unsigned i;
1184	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1185	{
1186	const PITCHANNEL *pChan = &pThis->channels[i];
1187
1188	pHlp->pfnPrintf(pHlp,
1189	"PIT (i8254) channel %d status: irq=%#x\n"
1190	" count=%08x" " latched_count=%04x count_latched=%02x\n"
1191	" status=%02x status_latched=%02x read_state=%02x\n"
1192	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
1193	" mode=%02x bcd=%02x gate=%02x\n"
1194	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
1195	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
1196	,
1197	i, pChan->irq,
1198	pChan->count, pChan->latched_count, pChan->count_latched,
1199	pChan->status, pChan->status_latched, pChan->read_state,
1200	pChan->write_state, pChan->write_latch, pChan->rw_mode,
1201	pChan->mode, pChan->bcd, pChan->gate,
1202	pChan->count_load_time, pChan->next_transition_time,
1203	pChan->u64ReloadTS, pChan->u64NextTS);
1204	}
1205	#ifdef FAKE_REFRESH_CLOCK
1206	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
1207	pThis->speaker_data_on, pThis->dummy_refresh_clock);
1208	#else
1209	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x\n", pThis->speaker_data_on);
1210	#endif
1211	if (pThis->fDisabledByHpet)
1212	pHlp->pfnPrintf(pHlp, "Disabled by HPET\n");
1213	}
1214
1215
1216	/* -=-=-=-=-=- IHpetLegacyNotify -=-=-=-=-=- */
1217
1218	/**
1219	* @interface_method_impl{PDMIHPETLEGACYNOTIFY,pfnModeChanged}
1220	*/
1221	static DECLCALLBACK(void) pitNotifyHpetLegacyNotify_ModeChanged(PPDMIHPETLEGACYNOTIFY pInterface, bool fActivated)
1222	{
1223	PPITSTATE pThis = RT_FROM_MEMBER(pInterface, PITSTATE, IHpetLegacyNotify);
1224	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1225
1226	pThis->fDisabledByHpet = fActivated;
1227
1228	PDMCritSectLeave(&pThis->CritSect);
1229	}
1230
1231
1232	/* -=-=-=-=-=- PDMDEVINS::IBase -=-=-=-=-=- */
1233
1234	/**
1235	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
1236	*/
1237	static DECLCALLBACK(void ) pitQueryInterface(PPDMIBASE pInterface, const char pszIID)
1238	{
1239	PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase);
1240	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1241	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase);
1242	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIHPETLEGACYNOTIFY, &pThis->IHpetLegacyNotify);
1243	return NULL;
1244	}
1245
1246
1247	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
1248
1249	/**
1250	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1251	*/
1252	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1253	{
1254	RT_NOREF1(offDelta);
1255	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1256	LogFlow(("pitRelocate: \n"));
1257
1258	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1259	{
1260	PPITCHANNEL pChan = &pThis->channels[i];
1261	if (pChan->pTimerR3)
1262	pChan->pTimerRC = TMTimerRCPtr(pChan->pTimerR3);
1263	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
1264	}
1265	}
1266
1267
1268	/**
1269	* @interface_method_impl{PDMDEVREG,pfnReset}
1270	*/
1271	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
1272	{
1273	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1274	LogFlow(("pitReset: \n"));
1275
1276	DEVPIT_R3_LOCK_BOTH(pThis);
1277
1278	pThis->fDisabledByHpet = false;
1279
1280	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1281	{
1282	PPITCHANNEL pChan = &pThis->channels[i];
1283
1284	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
1285	pChan->latched_count = 0;
1286	pChan->count_latched = 0;
1287	pChan->status_latched = 0;
1288	pChan->status = 0;
1289	pChan->read_state = 0;
1290	pChan->write_state = 0;
1291	pChan->write_latch = 0;
1292	pChan->rw_mode = 0;
1293	pChan->bcd = 0;
1294	#endif
1295	pChan->u64NextTS = UINT64_MAX;
1296	pChan->cRelLogEntries = 0;
1297	pChan->mode = 3;
1298	pChan->gate = (i != 2);
1299	pit_load_count(pChan, 0);
1300	}
1301
1302	DEVPIT_UNLOCK_BOTH(pThis);
1303	}
1304
1305
1306	/**
1307	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1308	*/
1309	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1310	{
1311	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1312	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1313	int rc;
1314	uint8_t u8Irq;
1315	uint16_t u16Base;
1316	bool fSpeaker;
1317	bool fGCEnabled;
1318	bool fR0Enabled;
1319	unsigned i;
1320	Assert(iInstance == 0);
1321
1322	/*
1323	* Validate configuration.
1324	*/
1325	if (!CFGMR3AreValuesValid(pCfg, "Irq\0" "Base\0"
1326	"SpeakerEnabled\0" "PassthroughSpeaker\0" "PassthroughSpeakerDevice\0"
1327	"R0Enabled\0" "GCEnabled\0"))
1328	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1329
1330	/*
1331	* Init the data.
1332	*/
1333	rc = CFGMR3QueryU8Def(pCfg, "Irq", &u8Irq, 0);
1334	if (RT_FAILURE(rc))
1335	return PDMDEV_SET_ERROR(pDevIns, rc,
1336	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
1337
1338	rc = CFGMR3QueryU16Def(pCfg, "Base", &u16Base, 0x40);
1339	if (RT_FAILURE(rc))
1340	return PDMDEV_SET_ERROR(pDevIns, rc,
1341	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
1342
1343	rc = CFGMR3QueryBoolDef(pCfg, "SpeakerEnabled", &fSpeaker, true);
1344	if (RT_FAILURE(rc))
1345	return PDMDEV_SET_ERROR(pDevIns, rc,
1346	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
1347
1348	uint8_t uPassthroughSpeaker;
1349	char *pszPassthroughSpeakerDevice = NULL;
1350	rc = CFGMR3QueryU8Def(pCfg, "PassthroughSpeaker", &uPassthroughSpeaker, 0);
1351	if (RT_FAILURE(rc))
1352	return PDMDEV_SET_ERROR(pDevIns, rc,
1353	N_("Configuration error: failed to read PassthroughSpeaker as uint8_t"));
1354	if (uPassthroughSpeaker)
1355	{
1356	rc = CFGMR3QueryStringAllocDef(pCfg, "PassthroughSpeakerDevice", &pszPassthroughSpeakerDevice, NULL);
1357	if (RT_FAILURE(rc))
1358	return PDMDEV_SET_ERROR(pDevIns, rc,
1359	N_("Configuration error: failed to read PassthroughSpeakerDevice as string"));
1360	}
1361
1362	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1363	if (RT_FAILURE(rc))
1364	return PDMDEV_SET_ERROR(pDevIns, rc,
1365	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
1366
1367	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1368	if (RT_FAILURE(rc))
1369	return PDMDEV_SET_ERROR(pDevIns, rc,
1370	N_("Configuration error: failed to read R0Enabled as boolean"));
1371
1372	pThis->pDevIns = pDevIns;
1373	pThis->IOPortBaseCfg = u16Base;
1374	pThis->fSpeakerCfg = fSpeaker;
1375	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
1376	if (uPassthroughSpeaker)
1377	{
1378	/** @todo r=klaus move this to a (system-specific) driver */
1379	#ifdef RT_OS_LINUX
1380	int fd = -1;
1381	if ((uPassthroughSpeaker == 1 \|\| uPassthroughSpeaker == 100) && fd == -1)
1382	fd = pitTryDeviceOpenSanitizeIoctl("/dev/input/by-path/platform-pcspkr-event-spkr", O_WRONLY);
1383	if ((uPassthroughSpeaker == 2 \|\| uPassthroughSpeaker == 100) && fd == -1)
1384	fd = pitTryDeviceOpenSanitizeIoctl("/dev/tty", O_WRONLY);
1385	if ((uPassthroughSpeaker == 3 \|\| uPassthroughSpeaker == 100) && fd == -1)
1386	{
1387	fd = pitTryDeviceOpenSanitizeIoctl("/dev/tty0", O_WRONLY);
1388	if (fd == -1)
1389	fd = pitTryDeviceOpenSanitizeIoctl("/dev/vc/0", O_WRONLY);
1390	}
1391	if ((uPassthroughSpeaker == 9 \|\| uPassthroughSpeaker == 100) && pszPassthroughSpeakerDevice && fd == -1)
1392	fd = pitTryDeviceOpenSanitizeIoctl(pszPassthroughSpeakerDevice, O_WRONLY);
1393	if (pThis->enmSpeakerEmu == PIT_SPEAKER_EMU_NONE && fd != -1)
1394	{
1395	pThis->hHostSpeaker = fd;
1396	if (ioctl(fd, EVIOCGSND(0)) != -1)
1397	{
1398	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_EVDEV;
1399	LogRel(("PIT: speaker: emulation mode evdev\n"));
1400	}
1401	else
1402	{
1403	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_CONSOLE;
1404	LogRel(("PIT: speaker: emulation mode console\n"));
1405	}
1406	}
1407	if ((uPassthroughSpeaker == 70 \|\| uPassthroughSpeaker == 100) && fd == -1)
1408	fd = pitTryDeviceOpen("/dev/tty", O_WRONLY);
1409	if ((uPassthroughSpeaker == 79 \|\| uPassthroughSpeaker == 100) && pszPassthroughSpeakerDevice && fd == -1)
1410	fd = pitTryDeviceOpen(pszPassthroughSpeakerDevice, O_WRONLY);
1411	if (pThis->enmSpeakerEmu == PIT_SPEAKER_EMU_NONE && fd != -1)
1412	{
1413	pThis->hHostSpeaker = fd;
1414	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_TTY;
1415	LogRel(("PIT: speaker: emulation mode tty\n"));
1416	}
1417	if (pThis->enmSpeakerEmu == PIT_SPEAKER_EMU_NONE)
1418	{
1419	Assert(fd == -1);
1420	LogRel(("PIT: speaker: no emulation possible\n"));
1421	}
1422	#else
1423	LogRel(("PIT: speaker: emulation deactivated\n"));
1424	#endif
1425	if (pszPassthroughSpeakerDevice)
1426	{
1427	MMR3HeapFree(pszPassthroughSpeakerDevice);
1428	pszPassthroughSpeakerDevice = NULL;
1429	}
1430	}
1431	pThis->channels[0].irq = u8Irq;
1432	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1433	{
1434	pThis->channels[i].pPitR3 = pThis;
1435	pThis->channels[i].pPitR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1436	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
1437	}
1438
1439	/*
1440	* Interfaces
1441	*/
1442	/* IBase */
1443	pDevIns->IBase.pfnQueryInterface = pitQueryInterface;
1444	/* IHpetLegacyNotify */
1445	pThis->IHpetLegacyNotify.pfnModeChanged = pitNotifyHpetLegacyNotify_ModeChanged;
1446
1447	/*
1448	* We do our own locking. This must be done before creating timers.
1449	*/
1450	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "pit#%u", iInstance);
1451	AssertRCReturn(rc, rc);
1452
1453	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1454	AssertRCReturn(rc, rc);
1455
1456	/*
1457	* Create the timer, make it take our critsect.
1458	*/
1459	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, &pThis->channels[0],
1460	TMTIMER_FLAGS_NO_CRIT_SECT, "i8254 Programmable Interval Timer",
1461	&pThis->channels[0].pTimerR3);
1462	if (RT_FAILURE(rc))
1463	return rc;
1464	pThis->channels[0].pTimerRC = TMTimerRCPtr(pThis->channels[0].pTimerR3);
1465	pThis->channels[0].pTimerR0 = TMTimerR0Ptr(pThis->channels[0].pTimerR3);
1466	rc = TMR3TimerSetCritSect(pThis->channels[0].pTimerR3, &pThis->CritSect);
1467	AssertRCReturn(rc, rc);
1468
1469	/*
1470	* Register I/O ports.
1471	*/
1472	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
1473	if (RT_FAILURE(rc))
1474	return rc;
1475	if (fGCEnabled)
1476	{
1477	rc = PDMDevHlpIOPortRegisterRC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1478	if (RT_FAILURE(rc))
1479	return rc;
1480	}
1481	if (fR0Enabled)
1482	{
1483	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1484	if (RT_FAILURE(rc))
1485	return rc;
1486	}
1487
1488	if (fSpeaker)
1489	{
1490	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1491	if (RT_FAILURE(rc))
1492	return rc;
1493	if (fGCEnabled)
1494	{
1495	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1496	if (RT_FAILURE(rc))
1497	return rc;
1498	}
1499	}
1500
1501	/*
1502	* Saved state.
1503	*/
1504	rc = PDMDevHlpSSMRegister3(pDevIns, PIT_SAVED_STATE_VERSION, sizeof(*pThis), pitLiveExec, pitSaveExec, pitLoadExec);
1505	if (RT_FAILURE(rc))
1506	return rc;
1507
1508	/*
1509	* Initialize the device state.
1510	*/
1511	pitReset(pDevIns);
1512
1513	/*
1514	* Register statistics and debug info.
1515	*/
1516	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1517	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1518
1519	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1520
1521	return VINF_SUCCESS;
1522	}
1523
1524
1525	/**
1526	* The device registration structure.
1527	*/
1528	const PDMDEVREG g_DeviceI8254 =
1529	{
1530	/* u32Version */
1531	PDM_DEVREG_VERSION,
1532	/* szName */
1533	"i8254",
1534	/* szRCMod */
1535	"VBoxDDRC.rc",
1536	/* szR0Mod */
1537	"VBoxDDR0.r0",
1538	/* pszDescription */
1539	"Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1540	/* fFlags */
1541	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1542	/* fClass */
1543	PDM_DEVREG_CLASS_PIT,
1544	/* cMaxInstances */
1545	1,
1546	/* cbInstance */
1547	sizeof(PITSTATE),
1548	/* pfnConstruct */
1549	pitConstruct,
1550	/* pfnDestruct */
1551	NULL,
1552	/* pfnRelocate */
1553	pitRelocate,
1554	/* pfnMemSetup */
1555	NULL,
1556	/* pfnPowerOn */
1557	NULL,
1558	/* pfnReset */
1559	pitReset,
1560	/* pfnSuspend */
1561	NULL,
1562	/* pfnResume */
1563	NULL,
1564	/* pfnAttach */
1565	NULL,
1566	/* pfnDetach */
1567	NULL,
1568	/* pfnQueryInterface */
1569	NULL,
1570	/* pfnInitComplete */
1571	NULL,
1572	/* pfnPowerOff */
1573	NULL,
1574	/* pfnSoftReset */
1575	NULL,
1576	/* u32VersionEnd */
1577	PDM_DEVREG_VERSION
1578	};
1579
1580	#endif /* IN_RING3 */
1581	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 73494

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