DevPit-i8254.cpp@ 5999

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1	/** $Id: DevPit-i8254.cpp 5999 2007-12-07 15:05:06Z vboxsync $ */
2	/** @file
3	* Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU 8253/8254 interval timer emulation
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43
44	/*******************************************************************************
45	* Header Files *
46	*******************************************************************************/
47	#define LOG_GROUP LOG_GROUP_DEV_PIT
48	#include <VBox/pdmdev.h>
49	#include <VBox/log.h>
50	#include <VBox/stam.h>
51	#include <iprt/assert.h>
52	#include <iprt/asm.h>
53
54	#include "Builtins.h"
55
56	/*******************************************************************************
57	* Defined Constants And Macros *
58	*******************************************************************************/
59	/** The PIT frequency. */
60	#define PIT_FREQ 1193182
61
62	#define RW_STATE_LSB 1
63	#define RW_STATE_MSB 2
64	#define RW_STATE_WORD0 3
65	#define RW_STATE_WORD1 4
66
67	/** The version of the saved state. */
68	#define PIT_SAVED_STATE_VERSION 2
69
70	/** @def FAKE_REFRESH_CLOCK
71	* Define this to flip the 15usec refresh bit on every read.
72	* If not defined, it will be flipped correctly. */
73	//#define FAKE_REFRESH_CLOCK
74
75	/*******************************************************************************
76	* Structures and Typedefs *
77	*******************************************************************************/
78	typedef struct PITChannelState
79	{
80	/** Pointer to the instance data - HCPtr. */
81	R3R0PTRTYPE(struct PITState *) pPitHC;
82	/** The timer - HCPtr. */
83	R3R0PTRTYPE(PTMTIMER) pTimerHC;
84	/** Pointer to the instance data - GCPtr. */
85	GCPTRTYPE(struct PITState *) pPitGC;
86	/** The timer - HCPtr. */
87	PTMTIMERGC pTimerGC;
88	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
89	uint64_t u64ReloadTS;
90	/** The actual time of the next tick.
91	* As apposed to the next_transition_time which contains the correct time of the next tick. */
92	uint64_t u64NextTS;
93
94	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
95	uint64_t count_load_time;
96	/* irq handling */
97	int64_t next_transition_time;
98	int32_t irq;
99	/** Number of release log entries. Used to prevent floading. */
100	uint32_t cRelLogEntries;
101
102	uint32_t count; /* can be 65536 */
103	uint16_t latched_count;
104	uint8_t count_latched;
105	uint8_t status_latched;
106
107	uint8_t status;
108	uint8_t read_state;
109	uint8_t write_state;
110	uint8_t write_latch;
111
112	uint8_t rw_mode;
113	uint8_t mode;
114	uint8_t bcd; /* not supported */
115	uint8_t gate; /* timer start */
116
117	} PITChannelState;
118
119	typedef struct PITState
120	{
121	PITChannelState channels[3];
122	/** Speaker data. */
123	int32_t speaker_data_on;
124	#ifdef FAKE_REFRESH_CLOCK
125	/** Speaker dummy. */
126	int32_t dummy_refresh_clock;
127	#else
128	uint32_t Alignment1;
129	#endif
130	/** Pointer to the device instance. */
131	R3PTRTYPE(PPDMDEVINS) pDevIns;
132	#if HC_ARCH_BITS == 32
133	uint32_t Alignment0;
134	#endif
135	/** Number of IRQs that's been raised. */
136	STAMCOUNTER StatPITIrq;
137	/** Profiling the timer callback handler. */
138	STAMPROFILEADV StatPITHandler;
139	} PITState;
140
141
142	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
143	/*******************************************************************************
144	* Internal Functions *
145	*******************************************************************************/
146	__BEGIN_DECLS
147	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
148	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
149	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
150	#ifdef IN_RING3
151	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
152	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time);
153	#endif
154	__END_DECLS
155
156
157
158
159	static int pit_get_count(PITChannelState *s)
160	{
161	uint64_t d;
162	int counter;
163	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
164
165	if (s->mode == 2) /** @todo Implement proper virtual time and get rid of this hack.. */
166	{
167	#if 0
168	d = TMTimerGet(pTimer);
169	d -= s->u64ReloadTS;
170	d = ASMMultU64ByU32DivByU32(d, PIT_FREQ, TMTimerGetFreq(pTimer));
171	#else /* variable time because of catch up */
172	if (s->u64NextTS == UINT64_MAX)
173	return 1; /** @todo check this value. */
174	d = TMTimerGet(pTimer);
175	d = ASMMultU64ByU32DivByU32(d - s->u64ReloadTS, s->count, s->u64NextTS - s->u64ReloadTS);
176	#endif
177	if (d >= s->count)
178	return 1;
179	return s->count - d;
180	}
181	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
182	switch(s->mode) {
183	case 0:
184	case 1:
185	case 4:
186	case 5:
187	counter = (s->count - d) & 0xffff;
188	break;
189	case 3:
190	/* XXX: may be incorrect for odd counts */
191	counter = s->count - ((2 * d) % s->count);
192	break;
193	default:
194	counter = s->count - (d % s->count);
195	break;
196	}
197	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
198	return counter;
199	}
200
201	/* get pit output bit */
202	static int pit_get_out1(PITChannelState *s, int64_t current_time)
203	{
204	uint64_t d;
205	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
206	int out;
207
208	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
209	switch(s->mode) {
210	default:
211	case 0:
212	out = (d >= s->count);
213	break;
214	case 1:
215	out = (d < s->count);
216	break;
217	case 2:
218	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, s->count, (unsigned)(d % s->count)));
219	if ((d % s->count) == 0 && d != 0)
220	out = 1;
221	else
222	out = 0;
223	break;
224	case 3:
225	out = (d % s->count) < ((s->count + 1) >> 1);
226	break;
227	case 4:
228	case 5:
229	out = (d == s->count);
230	break;
231	}
232	return out;
233	}
234
235
236	static int pit_get_out(PITState *pit, int channel, int64_t current_time)
237	{
238	PITChannelState *s = &pit->channels[channel];
239	return pit_get_out1(s, current_time);
240	}
241
242
243	static int pit_get_gate(PITState *pit, int channel)
244	{
245	PITChannelState *s = &pit->channels[channel];
246	return s->gate;
247	}
248
249
250	/* if already latched, do not latch again */
251	static void pit_latch_count(PITChannelState *s)
252	{
253	if (!s->count_latched) {
254	s->latched_count = pit_get_count(s);
255	s->count_latched = s->rw_mode;
256	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
257	s->latched_count, ASMMultU64ByU32DivByU32(s->count - s->latched_count, 1000000000, PIT_FREQ), s->count, s->mode));
258	}
259	}
260
261	#ifdef IN_RING3
262
263	/* val must be 0 or 1 */
264	static void pit_set_gate(PITState *pit, int channel, int val)
265	{
266	PITChannelState *s = &pit->channels[channel];
267	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
268
269	switch(s->mode) {
270	default:
271	case 0:
272	case 4:
273	/* XXX: just disable/enable counting */
274	break;
275	case 1:
276	case 5:
277	if (s->gate < val) {
278	/* restart counting on rising edge */
279	s->count_load_time = TMTimerGet(pTimer);
280	pit_irq_timer_update(s, s->count_load_time);
281	}
282	break;
283	case 2:
284	case 3:
285	if (s->gate < val) {
286	/* restart counting on rising edge */
287	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
288	pit_irq_timer_update(s, s->count_load_time);
289	}
290	/* XXX: disable/enable counting */
291	break;
292	}
293	s->gate = val;
294	}
295
296	static inline void pit_load_count(PITChannelState *s, int val)
297	{
298	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
299	if (val == 0)
300	val = 0x10000;
301	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
302	s->count = val;
303	pit_irq_timer_update(s, s->count_load_time);
304
305	/* log the new rate (ch 0 only). */
306	if ( s->pTimerHC /* ch 0 */
307	&& s->cRelLogEntries++ < 32)
308	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
309	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
310	}
311
312	/* return -1 if no transition will occur. */
313	static int64_t pit_get_next_transition_time(PITChannelState *s,
314	uint64_t current_time)
315	{
316	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
317	uint64_t d, next_time, base;
318	uint32_t period2;
319
320	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
321	switch(s->mode) {
322	default:
323	case 0:
324	case 1:
325	if (d < s->count)
326	next_time = s->count;
327	else
328	return -1;
329	break;
330	/*
331	* Mode 2: The period is count + 1 PIT ticks.
332	* When the counter reaches 1 we sent the output low (for channel 0 that
333	* means raise an irq). On the next tick, where we should be decrementing
334	* from 1 to 0, the count is loaded and the output goes high (channel 0
335	* means clearing the irq).
336	*
337	* In VBox we simplify the tick cycle between 1 and 0 and immediately clears
338	* the irq. We also don't set it until we reach 0, which is a tick late - will
339	* try fix that later some day.
340	*/
341	case 2:
342	base = (d / s->count) * s->count;
343	#ifndef VBOX /* see above */
344	if ((d - base) == 0 && d != 0)
345	next_time = base + s->count;
346	else
347	#endif
348	next_time = base + s->count + 1;
349	break;
350	case 3:
351	base = (d / s->count) * s->count;
352	period2 = ((s->count + 1) >> 1);
353	if ((d - base) < period2)
354	next_time = base + period2;
355	else
356	next_time = base + s->count;
357	break;
358	case 4:
359	case 5:
360	if (d < s->count)
361	next_time = s->count;
362	else if (d == s->count)
363	next_time = s->count + 1;
364	else
365	return -1;
366	break;
367	}
368	/* convert to timer units */
369	LogFlow(("PIT: next_time=%14RI64 %20RI64 mode=%#x count=%#06x\n", next_time,
370	ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), s->mode, s->count));
371	next_time = s->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
372	/* fix potential rounding problems */
373	/* XXX: better solution: use a clock at PIT_FREQ Hz */
374	if (next_time <= current_time)
375	next_time = current_time + 1;
376	return next_time;
377	}
378
379	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time)
380	{
381	uint64_t now;
382	int64_t expire_time;
383	int irq_level;
384	PPDMDEVINS pDevIns;
385	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
386
387	if (!s->CTXSUFF(pTimer))
388	return;
389	expire_time = pit_get_next_transition_time(s, current_time);
390	irq_level = pit_get_out1(s, current_time);
391
392	/* We just flip-flop the irq level to save that extra timer call, which isn't generally required (we haven't served it for months). */
393	pDevIns = s->CTXSUFF(pPit)->pDevIns;
394	PDMDevHlpISASetIrq(pDevIns, s->irq, irq_level);
395	if (irq_level)
396	PDMDevHlpISASetIrq(pDevIns, s->irq, 0);
397	now = TMTimerGet(pTimer);
398	Log3(("pit_irq_timer_update: %lldns late\n", now - s->u64NextTS));
399	if (irq_level)
400	{
401	s->u64ReloadTS = now;
402	STAM_COUNTER_INC(&s->CTXSUFF(pPit)->StatPITIrq);
403	}
404
405	if (expire_time != -1)
406	{
407	s->u64NextTS = expire_time;
408	TMTimerSet(s->CTXSUFF(pTimer), s->u64NextTS);
409	}
410	else
411	{
412	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", s->mode, s->count, irq_level));
413	TMTimerStop(s->CTXSUFF(pTimer));
414	s->u64NextTS = UINT64_MAX;
415	}
416	s->next_transition_time = expire_time;
417	}
418
419	#endif /* IN_RING3 */
420
421
422	/**
423	* Port I/O Handler for IN operations.
424	*
425	* @returns VBox status code.
426	*
427	* @param pDevIns The device instance.
428	* @param pvUser User argument - ignored.
429	* @param Port Port number used for the IN operation.
430	* @param pu32 Where to store the result.
431	* @param cb Number of bytes read.
432	*/
433	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
434	{
435	Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
436	NOREF(pvUser);
437	Port &= 3;
438	if (cb != 1 \|\| Port == 3)
439	{
440	Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
441	return VERR_IOM_IOPORT_UNUSED;
442	}
443
444	PITState pit = PDMINS2DATA(pDevIns, PITState );
445	int ret;
446	PITChannelState *s = &pit->channels[Port];
447	if (s->status_latched)
448	{
449	s->status_latched = 0;
450	ret = s->status;
451	}
452	else if (s->count_latched)
453	{
454	switch (s->count_latched)
455	{
456	default:
457	case RW_STATE_LSB:
458	ret = s->latched_count & 0xff;
459	s->count_latched = 0;
460	break;
461	case RW_STATE_MSB:
462	ret = s->latched_count >> 8;
463	s->count_latched = 0;
464	break;
465	case RW_STATE_WORD0:
466	ret = s->latched_count & 0xff;
467	s->count_latched = RW_STATE_MSB;
468	break;
469	}
470	}
471	else
472	{
473	int count;
474	switch (s->read_state)
475	{
476	default:
477	case RW_STATE_LSB:
478	count = pit_get_count(s);
479	ret = count & 0xff;
480	break;
481	case RW_STATE_MSB:
482	count = pit_get_count(s);
483	ret = (count >> 8) & 0xff;
484	break;
485	case RW_STATE_WORD0:
486	count = pit_get_count(s);
487	ret = count & 0xff;
488	s->read_state = RW_STATE_WORD1;
489	break;
490	case RW_STATE_WORD1:
491	count = pit_get_count(s);
492	ret = (count >> 8) & 0xff;
493	s->read_state = RW_STATE_WORD0;
494	break;
495	}
496	}
497
498	*pu32 = ret;
499	Log2(("pitIOPortRead: Port=%#x cb=%x pu32=%#04x\n", Port, cb, pu32));
500	return VINF_SUCCESS;
501	}
502
503
504	/**
505	* Port I/O Handler for OUT operations.
506	*
507	* @returns VBox status code.
508	*
509	* @param pDevIns The device instance.
510	* @param pvUser User argument - ignored.
511	* @param Port Port number used for the IN operation.
512	* @param u32 The value to output.
513	* @param cb The value size in bytes.
514	*/
515	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
516	{
517	Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
518	NOREF(pvUser);
519	if (cb != 1)
520	return VINF_SUCCESS;
521
522	PITState pit = PDMINS2DATA(pDevIns, PITState );
523	Port &= 3;
524	if (Port == 3)
525	{
526	/*
527	* Port 43h - Mode/Command Register.
528	* 7 6 5 4 3 2 1 0
529	* * * . . . . . . Select channel: 0 0 = Channel 0
530	* 0 1 = Channel 1
531	* 1 0 = Channel 2
532	* 1 1 = Read-back command (8254 only)
533	* (Illegal on 8253)
534	* (Illegal on PS/2 {JAM})
535	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
536	* 0 1 = Access mode: lobyte only
537	* 1 0 = Access mode: hibyte only
538	* 1 1 = Access mode: lobyte/hibyte
539	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
540	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
541	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
542	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
543	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
544	*/
545	unsigned channel = u32 >> 6;
546	if (channel == 3)
547	{
548	/* read-back command */
549	for (channel = 0; channel < ELEMENTS(pit->channels); channel++)
550	{
551	PITChannelState *s = &pit->channels[channel];
552	if (u32 & (2 << channel)) {
553	if (!(u32 & 0x20))
554	pit_latch_count(s);
555	if (!(u32 & 0x10) && !s->status_latched)
556	{
557	/* status latch */
558	/* XXX: add BCD and null count */
559	PTMTIMER pTimer = s->CTXSUFF(pPit)->channels[0].CTXSUFF(pTimer);
560	s->status = (pit_get_out1(s, TMTimerGet(pTimer)) << 7)
561	\| (s->rw_mode << 4)
562	\| (s->mode << 1)
563	\| s->bcd;
564	s->status_latched = 1;
565	}
566	}
567	}
568	}
569	else
570	{
571	PITChannelState *s = &pit->channels[channel];
572	unsigned access = (u32 >> 4) & 3;
573	if (access == 0)
574	pit_latch_count(s);
575	else
576	{
577	s->rw_mode = access;
578	s->read_state = access;
579	s->write_state = access;
580
581	s->mode = (u32 >> 1) & 7;
582	s->bcd = u32 & 1;
583	/* XXX: update irq timer ? */
584	}
585	}
586	}
587	else
588	{
589	#ifndef IN_RING3
590	return VINF_IOM_HC_IOPORT_WRITE;
591	#else /* IN_RING3 */
592	/*
593	* Port 40-42h - Channel Data Ports.
594	*/
595	PITChannelState *s = &pit->channels[Port];
596	switch(s->write_state)
597	{
598	default:
599	case RW_STATE_LSB:
600	pit_load_count(s, u32);
601	break;
602	case RW_STATE_MSB:
603	pit_load_count(s, u32 << 8);
604	break;
605	case RW_STATE_WORD0:
606	s->write_latch = u32;
607	s->write_state = RW_STATE_WORD1;
608	break;
609	case RW_STATE_WORD1:
610	pit_load_count(s, s->write_latch \| (u32 << 8));
611	s->write_state = RW_STATE_WORD0;
612	break;
613	}
614	#endif /* !IN_RING3 */
615	}
616	return VINF_SUCCESS;
617	}
618
619
620	/**
621	* Port I/O Handler for speaker IN operations.
622	*
623	* @returns VBox status code.
624	*
625	* @param pDevIns The device instance.
626	* @param pvUser User argument - ignored.
627	* @param Port Port number used for the IN operation.
628	* @param pu32 Where to store the result.
629	* @param cb Number of bytes read.
630	*/
631	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
632	{
633	NOREF(pvUser);
634	if (cb == 1)
635	{
636	PITState pData = PDMINS2DATA(pDevIns, PITState );
637	const uint64_t u64Now = TMTimerGet(pData->channels[0].CTXSUFF(pTimer));
638	Assert(TMTimerGetFreq(pData->channels[0].CTXSUFF(pTimer)) == 1000000000); /* lazy bird. */
639
640	/* bit 6,7 Parity error stuff. */
641	/* bit 5 - mirrors timer 2 output condition. */
642	const int fOut = pit_get_out(pData, 2, u64Now);
643	/* bit 4 - toggled every with each (DRAM?) refresh request, every 15.085 µs. */
644	#ifdef FAKE_REFRESH_CLOCK
645	pData->dummy_refresh_clock ^= 1;
646	const int fRefresh = pData->dummy_refresh_clock;
647	#else
648	const int fRefresh = (u64Now / 15085) & 1;
649	#endif
650	/* bit 2,3 NMI / parity status stuff. */
651	/* bit 1 - speaker data status */
652	const int fSpeakerStatus = pData->speaker_data_on;
653	/* bit 0 - timer 2 clock gate to speaker status. */
654	const int fTimer2GateStatus = pit_get_gate(pData, 2);
655
656	*pu32 = fTimer2GateStatus
657	\| (fSpeakerStatus << 1)
658	\| (fRefresh << 4)
659	\| (fOut << 5);
660	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x pu32=%#x\n", Port, cb, pu32));
661	return VINF_SUCCESS;
662	}
663	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
664	return VERR_IOM_IOPORT_UNUSED;
665	}
666
667	#ifdef IN_RING3
668
669	/**
670	* Port I/O Handler for speaker OUT operations.
671	*
672	* @returns VBox status code.
673	*
674	* @param pDevIns The device instance.
675	* @param pvUser User argument - ignored.
676	* @param Port Port number used for the IN operation.
677	* @param u32 The value to output.
678	* @param cb The value size in bytes.
679	*/
680	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
681	{
682	NOREF(pvUser);
683	if (cb == 1)
684	{
685	PITState pData = PDMINS2DATA(pDevIns, PITState );
686	pData->speaker_data_on = (u32 >> 1) & 1;
687	pit_set_gate(pData, 2, u32 & 1);
688	}
689	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
690	return VINF_SUCCESS;
691	}
692
693
694	/**
695	* Saves a state of the programmable interval timer device.
696	*
697	* @returns VBox status code.
698	* @param pDevIns The device instance.
699	* @param pSSMHandle The handle to save the state to.
700	*/
701	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
702	{
703	PITState pData = PDMINS2DATA(pDevIns, PITState );
704	unsigned i;
705
706	for (i = 0; i < ELEMENTS(pData->channels); i++)
707	{
708	PITChannelState *s = &pData->channels[i];
709	SSMR3PutU32(pSSMHandle, s->count);
710	SSMR3PutU16(pSSMHandle, s->latched_count);
711	SSMR3PutU8(pSSMHandle, s->count_latched);
712	SSMR3PutU8(pSSMHandle, s->status_latched);
713	SSMR3PutU8(pSSMHandle, s->status);
714	SSMR3PutU8(pSSMHandle, s->read_state);
715	SSMR3PutU8(pSSMHandle, s->write_state);
716	SSMR3PutU8(pSSMHandle, s->write_latch);
717	SSMR3PutU8(pSSMHandle, s->rw_mode);
718	SSMR3PutU8(pSSMHandle, s->mode);
719	SSMR3PutU8(pSSMHandle, s->bcd);
720	SSMR3PutU8(pSSMHandle, s->gate);
721	SSMR3PutU64(pSSMHandle, s->count_load_time);
722	SSMR3PutU64(pSSMHandle, s->u64NextTS);
723	SSMR3PutU64(pSSMHandle, s->u64ReloadTS);
724	SSMR3PutS64(pSSMHandle, s->next_transition_time);
725	if (s->CTXSUFF(pTimer))
726	TMR3TimerSave(s->CTXSUFF(pTimer), pSSMHandle);
727	}
728
729	SSMR3PutS32(pSSMHandle, pData->speaker_data_on);
730	#ifdef FAKE_REFRESH_CLOCK
731	return SSMR3PutS32(pSSMHandle, pData->dummy_refresh_clock);
732	#else
733	return SSMR3PutS32(pSSMHandle, 0);
734	#endif
735	}
736
737
738	/**
739	* Loads a saved programmable interval timer device state.
740	*
741	* @returns VBox status code.
742	* @param pDevIns The device instance.
743	* @param pSSMHandle The handle to the saved state.
744	* @param u32Version The data unit version number.
745	*/
746	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
747	{
748	PITState pData = PDMINS2DATA(pDevIns, PITState );
749	unsigned i;
750
751	if (u32Version != PIT_SAVED_STATE_VERSION)
752	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
753
754	for (i = 0; i < ELEMENTS(pData->channels); i++)
755	{
756	PITChannelState *s = &pData->channels[i];
757	SSMR3GetU32(pSSMHandle, &s->count);
758	SSMR3GetU16(pSSMHandle, &s->latched_count);
759	SSMR3GetU8(pSSMHandle, &s->count_latched);
760	SSMR3GetU8(pSSMHandle, &s->status_latched);
761	SSMR3GetU8(pSSMHandle, &s->status);
762	SSMR3GetU8(pSSMHandle, &s->read_state);
763	SSMR3GetU8(pSSMHandle, &s->write_state);
764	SSMR3GetU8(pSSMHandle, &s->write_latch);
765	SSMR3GetU8(pSSMHandle, &s->rw_mode);
766	SSMR3GetU8(pSSMHandle, &s->mode);
767	SSMR3GetU8(pSSMHandle, &s->bcd);
768	SSMR3GetU8(pSSMHandle, &s->gate);
769	SSMR3GetU64(pSSMHandle, &s->count_load_time);
770	SSMR3GetU64(pSSMHandle, &s->u64NextTS);
771	SSMR3GetU64(pSSMHandle, &s->u64ReloadTS);
772	SSMR3GetS64(pSSMHandle, &s->next_transition_time);
773	if (s->CTXSUFF(pTimer))
774	{
775	TMR3TimerLoad(s->CTXSUFF(pTimer), pSSMHandle);
776	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
777	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100, i));
778	}
779	pData->channels[0].cRelLogEntries = 0;
780	}
781
782	SSMR3GetS32(pSSMHandle, &pData->speaker_data_on);
783	#ifdef FAKE_REFRESH_CLOCK
784	return SSMR3GetS32(pSSMHandle, &pData->dummy_refresh_clock);
785	#else
786	int32_t u32Dummy;
787	return SSMR3GetS32(pSSMHandle, &u32Dummy);
788	#endif
789	}
790
791
792	/**
793	* Device timer callback function.
794	*
795	* @param pDevIns Device instance of the device which registered the timer.
796	* @param pTimer The timer handle.
797	*/
798	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
799	{
800	PITState pData = PDMINS2DATA(pDevIns, PITState );
801	PITChannelState *s = &pData->channels[0];
802	STAM_PROFILE_ADV_START(&s->CTXSUFF(pPit)->StatPITHandler, a);
803	pit_irq_timer_update(s, s->next_transition_time);
804	STAM_PROFILE_ADV_STOP(&s->CTXSUFF(pPit)->StatPITHandler, a);
805	}
806
807
808	/**
809	* Relocation notification.
810	*
811	* @returns VBox status.
812	* @param pDevIns The device instance data.
813	* @param offDelta The delta relative to the old address.
814	*/
815	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
816	{
817	PITState pData = PDMINS2DATA(pDevIns, PITState );
818	unsigned i;
819	LogFlow(("pitRelocate: \n"));
820
821	for (i = 0; i < ELEMENTS(pData->channels); i++)
822	{
823	PITChannelState *pCh = &pData->channels[i];
824	if (pCh->pTimerHC)
825	pCh->pTimerGC = TMTimerGCPtr(pCh->pTimerHC);
826	pData->channels[i].pPitGC = PDMINS2DATA_GCPTR(pDevIns);
827	}
828	}
829
830	/** @todo remove this! */
831	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs);
832
833	/**
834	* Reset notification.
835	*
836	* @returns VBox status.
837	* @param pDevIns The device instance data.
838	*/
839	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
840	{
841	PITState pData = PDMINS2DATA(pDevIns, PITState );
842	unsigned i;
843	LogFlow(("pitReset: \n"));
844
845	for (i = 0; i < ELEMENTS(pData->channels); i++)
846	{
847	PITChannelState *s = &pData->channels[i];
848
849	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
850	s->latched_count = 0;
851	s->count_latched = 0;
852	s->status_latched = 0;
853	s->status = 0;
854	s->read_state = 0;
855	s->write_state = 0;
856	s->write_latch = 0;
857	s->rw_mode = 0;
858	s->bcd = 0;
859	#endif
860	s->cRelLogEntries = 0;
861	s->mode = 3;
862	s->gate = (i != 2);
863	pit_load_count(s, 0);
864	}
865	}
866
867
868	/**
869	* Info handler, device version.
870	*
871	* @param pDevIns Device instance which registered the info.
872	* @param pHlp Callback functions for doing output.
873	* @param pszArgs Argument string. Optional and specific to the handler.
874	*/
875	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
876	{
877	PITState pData = PDMINS2DATA(pDevIns, PITState );
878	unsigned i;
879	for (i = 0; i < ELEMENTS(pData->channels); i++)
880	{
881	const PITChannelState *pCh = &pData->channels[i];
882
883	pHlp->pfnPrintf(pHlp,
884	"PIT (i8254) channel %d status: irq=%#x\n"
885	" count=%08x" " latched_count=%04x count_latched=%02x\n"
886	" status=%02x status_latched=%02x read_state=%02x\n"
887	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
888	" mode=%02x bcd=%02x gate=%02x\n"
889	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
890	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
891	,
892	i, pCh->irq,
893	pCh->count, pCh->latched_count, pCh->count_latched,
894	pCh->status, pCh->status_latched, pCh->read_state,
895	pCh->write_state, pCh->write_latch, pCh->rw_mode,
896	pCh->mode, pCh->bcd, pCh->gate,
897	pCh->count_load_time, pCh->next_transition_time,
898	pCh->u64ReloadTS, pCh->u64NextTS);
899	}
900	#ifdef FAKE_REFRESH_CLOCK
901	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
902	pData->speaker_data_on, pData->dummy_refresh_clock);
903	#else
904	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x\n", pData->speaker_data_on);
905	#endif
906	}
907
908
909	/**
910	* Construct a device instance for a VM.
911	*
912	* @returns VBox status.
913	* @param pDevIns The device instance data.
914	* If the registration structure is needed, pDevIns->pDevReg points to it.
915	* @param iInstance Instance number. Use this to figure out which registers and such to use.
916	* The device number is also found in pDevIns->iInstance, but since it's
917	* likely to be freqently used PDM passes it as parameter.
918	* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
919	* of the device instance. It's also found in pDevIns->pCfgHandle, but like
920	* iInstance it's expected to be used a bit in this function.
921	*/
922	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
923	{
924	PITState pData = PDMINS2DATA(pDevIns, PITState );
925	int rc;
926	uint8_t u8Irq;
927	uint16_t u16Base;
928	bool fSpeaker;
929	bool fGCEnabled;
930	bool fR0Enabled;
931	unsigned i;
932	Assert(iInstance == 0);
933
934	/*
935	* Validate configuration.
936	*/
937	if (!CFGMR3AreValuesValid(pCfgHandle, "Irq\0Base\0Speaker\0GCEnabled\0R0Enabled\0"))
938	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
939
940	/*
941	* Init the data.
942	*/
943	rc = CFGMR3QueryU8(pCfgHandle, "Irq", &u8Irq);
944	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
945	u8Irq = 0;
946	else if (VBOX_FAILURE(rc))
947	return PDMDEV_SET_ERROR(pDevIns, rc,
948	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
949
950	rc = CFGMR3QueryU16(pCfgHandle, "Base", &u16Base);
951	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
952	u16Base = 0x40;
953	else if (VBOX_FAILURE(rc))
954	return PDMDEV_SET_ERROR(pDevIns, rc,
955	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
956
957	rc = CFGMR3QueryBool(pCfgHandle, "SpeakerEnabled", &fSpeaker);
958	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
959	fSpeaker = true;
960	else if (VBOX_FAILURE(rc))
961	return PDMDEV_SET_ERROR(pDevIns, rc,
962	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
963
964	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
965	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
966	fGCEnabled = true;
967	else if (VBOX_FAILURE(rc))
968	return PDMDEV_SET_ERROR(pDevIns, rc,
969	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
970
971	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
972	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
973	fR0Enabled = true;
974	else if (VBOX_FAILURE(rc))
975	return PDMDEV_SET_ERROR(pDevIns, rc,
976	N_("Configuration error: failed to read R0Enabled as boolean"));
977
978	pData->pDevIns = pDevIns;
979	pData->channels[0].irq = u8Irq;
980	for (i = 0; i < ELEMENTS(pData->channels); i++)
981	{
982	pData->channels[i].pPitHC = pData;
983	pData->channels[i].pPitGC = PDMINS2DATA_GCPTR(pDevIns);
984	}
985
986	/*
987	* Create timer, register I/O Ports and save state.
988	*/
989	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, "i8254 Programmable Interval Timer",
990	&pData->channels[0].CTXSUFF(pTimer));
991	if (VBOX_FAILURE(rc))
992	{
993	AssertMsgFailed(("pfnTMTimerCreate -> %Vrc\n", rc));
994	return rc;
995	}
996
997	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
998	if (VBOX_FAILURE(rc))
999	return rc;
1000	if (fGCEnabled)
1001	{
1002	rc = PDMDevHlpIOPortRegisterGC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1003	if (VBOX_FAILURE(rc))
1004	return rc;
1005	}
1006	if (fR0Enabled)
1007	{
1008	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1009	if (VBOX_FAILURE(rc))
1010	return rc;
1011	}
1012
1013	if (fSpeaker)
1014	{
1015	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1016	if (VBOX_FAILURE(rc))
1017	return rc;
1018	if (fGCEnabled)
1019	{
1020	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1021	if (VBOX_FAILURE(rc))
1022	return rc;
1023	}
1024	}
1025
1026	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, PIT_SAVED_STATE_VERSION, sizeof(*pData),
1027	NULL, pitSaveExec, NULL,
1028	NULL, pitLoadExec, NULL);
1029	if (VBOX_FAILURE(rc))
1030	return rc;
1031
1032	/*
1033	* Initialize the device state.
1034	*/
1035	pitReset(pDevIns);
1036
1037	/*
1038	* Register statistics and debug info.
1039	*/
1040	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1041	PDMDevHlpSTAMRegister(pDevIns, &pData->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1042
1043	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1044
1045	return VINF_SUCCESS;
1046	}
1047
1048
1049	/**
1050	* The device registration structure.
1051	*/
1052	const PDMDEVREG g_DeviceI8254 =
1053	{
1054	/* u32Version */
1055	PDM_DEVREG_VERSION,
1056	/* szDeviceName */
1057	"i8254",
1058	/* szGCMod */
1059	"VBoxDDGC.gc",
1060	/* szR0Mod */
1061	"VBoxDDR0.r0",
1062	/* pszDescription */
1063	"Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1064	/* fFlags */
1065	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1066	/* fClass */
1067	PDM_DEVREG_CLASS_PIT,
1068	/* cMaxInstances */
1069	1,
1070	/* cbInstance */
1071	sizeof(PITState),
1072	/* pfnConstruct */
1073	pitConstruct,
1074	/* pfnDestruct */
1075	NULL,
1076	/* pfnRelocate */
1077	pitRelocate,
1078	/* pfnIOCtl */
1079	NULL,
1080	/* pfnPowerOn */
1081	NULL,
1082	/* pfnReset */
1083	pitReset,
1084	/* pfnSuspend */
1085	NULL,
1086	/* pfnResume */
1087	NULL,
1088	/* pfnAttach */
1089	NULL,
1090	/* pfnDetach */
1091	NULL,
1092	/* pfnQueryInterface. */
1093	NULL
1094	};
1095
1096	#endif /* IN_RING3 */
1097	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1098

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 5999

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