DevPit-i8254.cpp@ 59499

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1	/* $Id: DevPit-i8254.cpp 59499 2016-01-27 16:50:04Z vboxsync $ */
2	/** @file
3	* DevPIT-i8254 - Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU 8253/8254 interval timer emulation
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Header Files *
46	*********************************************************************************************************************************/
47	#define LOG_GROUP LOG_GROUP_DEV_PIT
48	#include <VBox/vmm/pdmdev.h>
49	#include <VBox/log.h>
50	#include <VBox/vmm/stam.h>
51	#include <iprt/assert.h>
52	#include <iprt/asm-math.h>
53
54	#ifdef IN_RING3
55	# ifdef RT_OS_LINUX
56	# include <fcntl.h>
57	# include <errno.h>
58	# include <unistd.h>
59	# include <stdio.h>
60	# include <linux/kd.h>
61	# include <linux/input.h>
62	# include <sys/ioctl.h>
63	# endif
64	# include <iprt/alloc.h>
65	# include <iprt/string.h>
66	# include <iprt/uuid.h>
67	#endif /* IN_RING3 */
68
69	#include "VBoxDD.h"
70
71
72	/*********************************************************************************************************************************
73	* Defined Constants And Macros *
74	*********************************************************************************************************************************/
75	/** The PIT frequency. */
76	#define PIT_FREQ 1193182
77
78	#define RW_STATE_LSB 1
79	#define RW_STATE_MSB 2
80	#define RW_STATE_WORD0 3
81	#define RW_STATE_WORD1 4
82
83	/** The current saved state version. */
84	#define PIT_SAVED_STATE_VERSION 4
85	/** The saved state version used by VirtualBox 3.1 and earlier.
86	* This did not include disable by HPET flag. */
87	#define PIT_SAVED_STATE_VERSION_VBOX_31 3
88	/** The saved state version used by VirtualBox 3.0 and earlier.
89	* This did not include the config part. */
90	#define PIT_SAVED_STATE_VERSION_VBOX_30 2
91
92	/** @def FAKE_REFRESH_CLOCK
93	* Define this to flip the 15usec refresh bit on every read.
94	* If not defined, it will be flipped correctly. */
95	/* #define FAKE_REFRESH_CLOCK */
96	#ifdef DOXYGEN_RUNNING
97	# define FAKE_REFRESH_CLOCK
98	#endif
99
100	/** The effective counter mode - if bit 1 is set, bit 2 is ignored. */
101	#define EFFECTIVE_MODE(x) ((x) & ~(((x) & 2) << 1))
102
103
104	/**
105	* Acquires the PIT lock or returns.
106	*/
107	#define DEVPIT_LOCK_RETURN(a_pThis, a_rcBusy) \
108	do { \
109	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
110	if (rcLock != VINF_SUCCESS) \
111	return rcLock; \
112	} while (0)
113
114	/**
115	* Releases the PIT lock.
116	*/
117	#define DEVPIT_UNLOCK(a_pThis) \
118	do { PDMCritSectLeave(&(a_pThis)->CritSect); } while (0)
119
120
121	/**
122	* Acquires the TM lock and PIT lock, returns on failure.
123	*/
124	#define DEVPIT_LOCK_BOTH_RETURN(a_pThis, a_rcBusy) \
125	do { \
126	int rcLock = TMTimerLock((a_pThis)->channels[0].CTX_SUFF(pTimer), (a_rcBusy)); \
127	if (rcLock != VINF_SUCCESS) \
128	return rcLock; \
129	rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
130	if (rcLock != VINF_SUCCESS) \
131	{ \
132	TMTimerUnlock((a_pThis)->channels[0].CTX_SUFF(pTimer)); \
133	return rcLock; \
134	} \
135	} while (0)
136
137	#if IN_RING3
138	/**
139	* Acquires the TM lock and PIT lock, ignores failures.
140	*/
141	# define DEVPIT_R3_LOCK_BOTH(a_pThis) \
142	do { \
143	TMTimerLock((a_pThis)->channels[0].CTX_SUFF(pTimer), VERR_IGNORED); \
144	PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
145	} while (0)
146	#endif /* IN_RING3 */
147
148	/**
149	* Releases the PIT lock and TM lock.
150	*/
151	#define DEVPIT_UNLOCK_BOTH(a_pThis) \
152	do { \
153	PDMCritSectLeave(&(a_pThis)->CritSect); \
154	TMTimerUnlock((a_pThis)->channels[0].CTX_SUFF(pTimer)); \
155	} while (0)
156
157
158
159	/*********************************************************************************************************************************
160	* Structures and Typedefs *
161	*********************************************************************************************************************************/
162	/**
163	* The state of one PIT channel.
164	*/
165	typedef struct PITCHANNEL
166	{
167	/** Pointer to the instance data - R3 Ptr. */
168	R3PTRTYPE(struct PITSTATE *) pPitR3;
169	/** The timer - R3 Ptr.
170	* @note Only channel 0 has a timer. */
171	PTMTIMERR3 pTimerR3;
172	/** Pointer to the instance data - R0 Ptr. */
173	R0PTRTYPE(struct PITSTATE *) pPitR0;
174	/** The timer - R0 Ptr.
175	* @note Only channel 0 has a timer. */
176	PTMTIMERR0 pTimerR0;
177	/** Pointer to the instance data - RC Ptr. */
178	RCPTRTYPE(struct PITSTATE *) pPitRC;
179	/** The timer - RC Ptr.
180	* @note Only channel 0 has a timer. */
181	PTMTIMERRC pTimerRC;
182	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
183	uint64_t u64ReloadTS;
184	/** The actual time of the next tick.
185	* As apposed to the next_transition_time which contains the correct time of the next tick. */
186	uint64_t u64NextTS;
187
188	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
189	uint64_t count_load_time;
190	/* irq handling */
191	int64_t next_transition_time;
192	int32_t irq;
193	/** Number of release log entries. Used to prevent flooding. */
194	uint32_t cRelLogEntries;
195
196	uint32_t count; /* can be 65536 */
197	uint16_t latched_count;
198	uint8_t count_latched;
199	uint8_t status_latched;
200
201	uint8_t status;
202	uint8_t read_state;
203	uint8_t write_state;
204	uint8_t write_latch;
205
206	uint8_t rw_mode;
207	uint8_t mode;
208	uint8_t bcd; /* not supported */
209	uint8_t gate; /* timer start */
210
211	} PITCHANNEL;
212	/** Pointer to the state of one PIT channel. */
213	typedef PITCHANNEL *PPITCHANNEL;
214
215	/** Speaker emulation state. */
216	typedef enum PITSPEAKEREMU
217	{
218	PIT_SPEAKER_EMU_NONE = 0,
219	PIT_SPEAKER_EMU_CONSOLE,
220	PIT_SPEAKER_EMU_EVDEV,
221	PIT_SPEAKER_EMU_TTY
222	} PITSPEAKEREMU;
223
224	/**
225	* The whole PIT state.
226	*/
227	typedef struct PITSTATE
228	{
229	/** Channel state. Must come first? */
230	PITCHANNEL channels[3];
231	/** Speaker data. */
232	int32_t speaker_data_on;
233	#ifdef FAKE_REFRESH_CLOCK
234	/** Refresh dummy. */
235	int32_t dummy_refresh_clock;
236	#else
237	uint32_t Alignment1;
238	#endif
239	/** Config: I/O port base. */
240	RTIOPORT IOPortBaseCfg;
241	/** Config: Speaker enabled. */
242	bool fSpeakerCfg;
243	/** Disconnect PIT from the interrupt controllers if requested by HPET. */
244	bool fDisabledByHpet;
245	/** Config: What to do with speaker activity. */
246	PITSPEAKEREMU enmSpeakerEmu;
247	#ifdef RT_OS_LINUX
248	/** File handle for host speaker functionality. */
249	int hHostSpeaker;
250	int afAlignment2;
251	#endif
252	/** PIT port interface. */
253	PDMIHPETLEGACYNOTIFY IHpetLegacyNotify;
254	/** Pointer to the device instance. */
255	PPDMDEVINSR3 pDevIns;
256	/** Number of IRQs that's been raised. */
257	STAMCOUNTER StatPITIrq;
258	/** Profiling the timer callback handler. */
259	STAMPROFILEADV StatPITHandler;
260	/** Critical section protecting the state. */
261	PDMCRITSECT CritSect;
262	} PITSTATE;
263	/** Pointer to the PIT device state. */
264	typedef PITSTATE *PPITSTATE;
265
266
267	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
268
269
270	/*********************************************************************************************************************************
271	* Internal Functions *
272	*********************************************************************************************************************************/
273	#ifdef IN_RING3
274	static void pit_irq_timer_update(PPITCHANNEL pChan, uint64_t current_time, uint64_t now, bool in_timer);
275	#endif
276
277
278
279	static int pit_get_count(PPITCHANNEL pChan)
280	{
281	uint64_t d;
282	PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
283	Assert(TMTimerIsLockOwner(pTimer));
284
285	if (EFFECTIVE_MODE(pChan->mode) == 2)
286	{
287	if (pChan->u64NextTS == UINT64_MAX)
288	{
289	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - pChan->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
290	return pChan->count - (d % pChan->count); /** @todo check this value. */
291	}
292	uint64_t Interval = pChan->u64NextTS - pChan->u64ReloadTS;
293	if (!Interval)
294	return pChan->count - 1; /** @todo This is WRONG! But I'm too tired to fix it properly and just want to shut up a DIV/0 trap now. */
295	d = TMTimerGet(pTimer);
296	d = ASMMultU64ByU32DivByU32(d - pChan->u64ReloadTS, pChan->count, Interval);
297	if (d >= pChan->count)
298	return 1;
299	return pChan->count - d;
300	}
301
302	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - pChan->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
303	int counter;
304	switch (EFFECTIVE_MODE(pChan->mode))
305	{
306	case 0:
307	case 1:
308	case 4:
309	case 5:
310	counter = (pChan->count - d) & 0xffff;
311	break;
312	case 3:
313	/* XXX: may be incorrect for odd counts */
314	counter = pChan->count - ((2 * d) % pChan->count);
315	break;
316	default:
317	counter = pChan->count - (d % pChan->count);
318	break;
319	}
320	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
321	return counter;
322	}
323
324	/* get pit output bit */
325	static int pit_get_out1(PPITCHANNEL pChan, int64_t current_time)
326	{
327	PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
328	uint64_t d;
329	int out;
330
331	d = ASMMultU64ByU32DivByU32(current_time - pChan->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
332	switch (EFFECTIVE_MODE(pChan->mode))
333	{
334	default:
335	case 0:
336	out = (d >= pChan->count);
337	break;
338	case 1:
339	out = (d < pChan->count);
340	break;
341	case 2:
342	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, pChan->count, (unsigned)(d % pChan->count)));
343	if ((d % pChan->count) == 0 && d != 0)
344	out = 1;
345	else
346	out = 0;
347	break;
348	case 3:
349	out = (d % pChan->count) < ((pChan->count + 1) >> 1);
350	break;
351	case 4:
352	case 5:
353	out = (d != pChan->count);
354	break;
355	}
356	return out;
357	}
358
359
360	static int pit_get_out(PPITSTATE pThis, int channel, int64_t current_time)
361	{
362	PPITCHANNEL pChan = &pThis->channels[channel];
363	return pit_get_out1(pChan, current_time);
364	}
365
366
367	static int pit_get_gate(PPITSTATE pThis, int channel)
368	{
369	PPITCHANNEL pChan = &pThis->channels[channel];
370	return pChan->gate;
371	}
372
373
374	/* if already latched, do not latch again */
375	static void pit_latch_count(PPITCHANNEL pChan)
376	{
377	if (!pChan->count_latched)
378	{
379	pChan->latched_count = pit_get_count(pChan);
380	pChan->count_latched = pChan->rw_mode;
381	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
382	pChan->latched_count, ASMMultU64ByU32DivByU32(pChan->count - pChan->latched_count, 1000000000, PIT_FREQ),
383	pChan->count, pChan->mode));
384	}
385	}
386
387	#ifdef IN_RING3
388
389	/* val must be 0 or 1 */
390	static void pit_set_gate(PPITSTATE pThis, int channel, int val)
391	{
392	PPITCHANNEL pChan = &pThis->channels[channel];
393	PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
394
395	Assert((val & 1) == val);
396	Assert(TMTimerIsLockOwner(pTimer));
397
398	switch (EFFECTIVE_MODE(pChan->mode))
399	{
400	default:
401	case 0:
402	case 4:
403	/* XXX: just disable/enable counting */
404	break;
405	case 1:
406	case 5:
407	if (pChan->gate < val)
408	{
409	/* restart counting on rising edge */
410	Log(("pit_set_gate: restarting mode %d\n", pChan->mode));
411	pChan->count_load_time = TMTimerGet(pTimer);
412	pit_irq_timer_update(pChan, pChan->count_load_time, pChan->count_load_time, false);
413	}
414	break;
415	case 2:
416	case 3:
417	if (pChan->gate < val)
418	{
419	/* restart counting on rising edge */
420	Log(("pit_set_gate: restarting mode %d\n", pChan->mode));
421	pChan->count_load_time = pChan->u64ReloadTS = TMTimerGet(pTimer);
422	pit_irq_timer_update(pChan, pChan->count_load_time, pChan->count_load_time, false);
423	}
424	/* XXX: disable/enable counting */
425	break;
426	}
427	pChan->gate = val;
428	}
429
430	static void pit_load_count(PPITCHANNEL pChan, int val)
431	{
432	PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
433	Assert(TMTimerIsLockOwner(pTimer));
434
435	if (val == 0)
436	val = 0x10000;
437	pChan->count_load_time = pChan->u64ReloadTS = TMTimerGet(pTimer);
438	pChan->count = val;
439	pit_irq_timer_update(pChan, pChan->count_load_time, pChan->count_load_time, false);
440
441	/* log the new rate (ch 0 only). */
442	if (pChan->pTimerR3 /* ch 0 */)
443	{
444	if (pChan->cRelLogEntries++ < 32)
445	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
446	pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100));
447	else
448	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
449	pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100));
450	TMTimerSetFrequencyHint(pChan->CTX_SUFF(pTimer), PIT_FREQ / pChan->count);
451	}
452	else
453	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d)\n",
454	pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100,
455	pChan - &pChan->CTX_SUFF(pPit)->channels[0]));
456	}
457
458	/* return -1 if no transition will occur. */
459	static int64_t pit_get_next_transition_time(PPITCHANNEL pChan, uint64_t current_time)
460	{
461	PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
462	uint64_t d, next_time, base;
463	uint32_t period2;
464
465	d = ASMMultU64ByU32DivByU32(current_time - pChan->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
466	switch(EFFECTIVE_MODE(pChan->mode))
467	{
468	default:
469	case 0:
470	case 1:
471	if (d < pChan->count)
472	next_time = pChan->count;
473	else
474	return -1;
475	break;
476
477	/*
478	* Mode 2: The period is 'count' PIT ticks.
479	* When the counter reaches 1 we set the output low (for channel 0 that
480	* means lowering IRQ0). On the next tick, where we should be decrementing
481	* from 1 to 0, the count is loaded and the output goes high (channel 0
482	* means raising IRQ0 again and triggering timer interrupt).
483	*
484	* In VirtualBox we compress the pulse and flip-flop the IRQ line at the
485	* end of the period, which signals an interrupt at the exact same time.
486	*/
487	case 2:
488	base = (d / pChan->count) * pChan->count;
489	#ifndef VBOX /* see above */
490	if ((d - base) == 0 && d != 0)
491	next_time = base + pChan->count - 1;
492	else
493	#endif
494	next_time = base + pChan->count;
495	break;
496	case 3:
497	base = (d / pChan->count) * pChan->count;
498	period2 = ((pChan->count + 1) >> 1);
499	if ((d - base) < period2)
500	next_time = base + period2;
501	else
502	next_time = base + pChan->count;
503	break;
504
505	/* Modes 4 and 5 generate a short pulse at the end of the time delay. This
506	* is similar to mode 2, except modes 4/5 aren't periodic. We use the same
507	* optimization - only use one timer callback and pulse the IRQ.
508	* Note: Tickless Linux kernels use PIT mode 4 with 'nolapic'.
509	*/
510	case 4:
511	case 5:
512	#ifdef VBOX
513	if (d <= pChan->count)
514	next_time = pChan->count;
515	#else
516	if (d < pChan->count)
517	next_time = pChan->count;
518	else if (d == pChan->count)
519	next_time = pChan->count + 1;
520	#endif
521	else
522	return -1;
523	break;
524	}
525
526	/* convert to timer units */
527	LogFlow(("PIT: next_time=%'14RU64 %'20RU64 mode=%#x count=%#06x\n", next_time,
528	ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), pChan->mode, pChan->count));
529	next_time = pChan->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
530
531	/* fix potential rounding problems */
532	if (next_time <= current_time)
533	next_time = current_time;
534
535	/* Add one to next_time; if we don't, integer truncation will cause
536	* the algorithm to think that at the end of each period, it'pChan still
537	* within the first one instead of at the beginning of the next one.
538	*/
539	return next_time + 1;
540	}
541
542	static void pit_irq_timer_update(PPITCHANNEL pChan, uint64_t current_time, uint64_t now, bool in_timer)
543	{
544	int64_t expire_time;
545	int irq_level;
546	PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
547	Assert(TMTimerIsLockOwner(pTimer));
548
549	if (!pChan->CTX_SUFF(pTimer))
550	return;
551	expire_time = pit_get_next_transition_time(pChan, current_time);
552	irq_level = pit_get_out1(pChan, current_time) ? PDM_IRQ_LEVEL_HIGH : PDM_IRQ_LEVEL_LOW;
553
554	/* If PIT is disabled by HPET - simply disconnect ticks from interrupt controllers,
555	* but do not modify other aspects of device operation.
556	*/
557	if (!pChan->pPitR3->fDisabledByHpet)
558	{
559	PPDMDEVINS pDevIns = pChan->CTX_SUFF(pPit)->pDevIns;
560
561	switch (EFFECTIVE_MODE(pChan->mode))
562	{
563	case 2:
564	case 4:
565	case 5:
566	/* We just flip-flop the IRQ line to save an extra timer call,
567	* which isn't generally required. However, the pulse is only
568	* generated when running on the timer callback (and thus on
569	* the trailing edge of the output signal pulse).
570	*/
571	if (in_timer)
572	{
573	PDMDevHlpISASetIrq(pDevIns, pChan->irq, PDM_IRQ_LEVEL_FLIP_FLOP);
574	break;
575	}
576	/* Else fall through! */
577	default:
578	PDMDevHlpISASetIrq(pDevIns, pChan->irq, irq_level);
579	break;
580	}
581	}
582
583	if (irq_level)
584	{
585	pChan->u64ReloadTS = now;
586	STAM_COUNTER_INC(&pChan->CTX_SUFF(pPit)->StatPITIrq);
587	}
588
589	if (expire_time != -1)
590	{
591	Log3(("pit_irq_timer_update: next=%'RU64 now=%'RU64\n", expire_time, now));
592	pChan->u64NextTS = expire_time;
593	TMTimerSet(pChan->CTX_SUFF(pTimer), pChan->u64NextTS);
594	}
595	else
596	{
597	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", pChan->mode, pChan->count, irq_level));
598	TMTimerStop(pChan->CTX_SUFF(pTimer));
599	pChan->u64NextTS = UINT64_MAX;
600	}
601	pChan->next_transition_time = expire_time;
602	}
603
604	#endif /* IN_RING3 */
605
606
607	/**
608	* @callback_method_impl{FNIOMIOPORTIN}
609	*/
610	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
611	{
612	Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
613	NOREF(pvUser);
614	Port &= 3;
615	if (cb != 1 \|\| Port == 3)
616	{
617	Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
618	return VERR_IOM_IOPORT_UNUSED;
619	}
620
621	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
622	PPITCHANNEL pChan = &pThis->channels[Port];
623	int ret;
624
625	DEVPIT_LOCK_RETURN(pThis, VINF_IOM_R3_IOPORT_READ);
626	if (pChan->status_latched)
627	{
628	pChan->status_latched = 0;
629	ret = pChan->status;
630	DEVPIT_UNLOCK(pThis);
631	}
632	else if (pChan->count_latched)
633	{
634	switch (pChan->count_latched)
635	{
636	default:
637	case RW_STATE_LSB:
638	ret = pChan->latched_count & 0xff;
639	pChan->count_latched = 0;
640	break;
641	case RW_STATE_MSB:
642	ret = pChan->latched_count >> 8;
643	pChan->count_latched = 0;
644	break;
645	case RW_STATE_WORD0:
646	ret = pChan->latched_count & 0xff;
647	pChan->count_latched = RW_STATE_MSB;
648	break;
649	}
650	DEVPIT_UNLOCK(pThis);
651	}
652	else
653	{
654	DEVPIT_UNLOCK(pThis);
655	DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_READ);
656	int count;
657	switch (pChan->read_state)
658	{
659	default:
660	case RW_STATE_LSB:
661	count = pit_get_count(pChan);
662	ret = count & 0xff;
663	break;
664	case RW_STATE_MSB:
665	count = pit_get_count(pChan);
666	ret = (count >> 8) & 0xff;
667	break;
668	case RW_STATE_WORD0:
669	count = pit_get_count(pChan);
670	ret = count & 0xff;
671	pChan->read_state = RW_STATE_WORD1;
672	break;
673	case RW_STATE_WORD1:
674	count = pit_get_count(pChan);
675	ret = (count >> 8) & 0xff;
676	pChan->read_state = RW_STATE_WORD0;
677	break;
678	}
679	DEVPIT_UNLOCK_BOTH(pThis);
680	}
681
682	*pu32 = ret;
683	Log2(("pitIOPortRead: Port=%#x cb=%x pu32=%#04x\n", Port, cb, pu32));
684	return VINF_SUCCESS;
685	}
686
687
688	/**
689	* @callback_method_impl{FNIOMIOPORTOUT}
690	*/
691	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
692	{
693	Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
694	NOREF(pvUser);
695	if (cb != 1)
696	return VINF_SUCCESS;
697
698	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
699	Port &= 3;
700	if (Port == 3)
701	{
702	/*
703	* Port 43h - Mode/Command Register.
704	* 7 6 5 4 3 2 1 0
705	* * * . . . . . . Select channel: 0 0 = Channel 0
706	* 0 1 = Channel 1
707	* 1 0 = Channel 2
708	* 1 1 = Read-back command (8254 only)
709	* (Illegal on 8253)
710	* (Illegal on PS/2 {JAM})
711	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
712	* 0 1 = Access mode: lobyte only
713	* 1 0 = Access mode: hibyte only
714	* 1 1 = Access mode: lobyte/hibyte
715	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
716	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
717	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
718	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
719	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
720	*/
721	unsigned channel = u32 >> 6;
722	if (channel == 3)
723	{
724	/* read-back command */
725	DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_WRITE);
726	for (channel = 0; channel < RT_ELEMENTS(pThis->channels); channel++)
727	{
728	PPITCHANNEL pChan = &pThis->channels[channel];
729	if (u32 & (2 << channel)) {
730	if (!(u32 & 0x20))
731	pit_latch_count(pChan);
732	if (!(u32 & 0x10) && !pChan->status_latched)
733	{
734	/* status latch */
735	/* XXX: add BCD and null count */
736	PTMTIMER pTimer = pChan->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
737	pChan->status = (pit_get_out1(pChan, TMTimerGet(pTimer)) << 7)
738	\| (pChan->rw_mode << 4)
739	\| (pChan->mode << 1)
740	\| pChan->bcd;
741	pChan->status_latched = 1;
742	}
743	}
744	}
745	DEVPIT_UNLOCK_BOTH(pThis);
746	}
747	else
748	{
749	PPITCHANNEL pChan = &pThis->channels[channel];
750	unsigned access = (u32 >> 4) & 3;
751	if (access == 0)
752	{
753	DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_WRITE);
754	pit_latch_count(pChan);
755	DEVPIT_UNLOCK_BOTH(pThis);
756	}
757	else
758	{
759	DEVPIT_LOCK_RETURN(pThis, VINF_IOM_R3_IOPORT_WRITE);
760	pChan->rw_mode = access;
761	pChan->read_state = access;
762	pChan->write_state = access;
763
764	pChan->mode = (u32 >> 1) & 7;
765	pChan->bcd = u32 & 1;
766	/* XXX: update irq timer ? */
767	DEVPIT_UNLOCK(pThis);
768	}
769	}
770	}
771	else
772	{
773	#ifndef IN_RING3
774	/** @todo There is no reason not to do this in all contexts these
775	* days... */
776	return VINF_IOM_R3_IOPORT_WRITE;
777	#else /* IN_RING3 */
778	/*
779	* Port 40-42h - Channel Data Ports.
780	*/
781	PPITCHANNEL pChan = &pThis->channels[Port];
782	uint8_t const write_state = pChan->write_state;
783	DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_WRITE);
784	switch (pChan->write_state)
785	{
786	default:
787	case RW_STATE_LSB:
788	pit_load_count(pChan, u32);
789	break;
790	case RW_STATE_MSB:
791	pit_load_count(pChan, u32 << 8);
792	break;
793	case RW_STATE_WORD0:
794	pChan->write_latch = u32;
795	pChan->write_state = RW_STATE_WORD1;
796	break;
797	case RW_STATE_WORD1:
798	pit_load_count(pChan, pChan->write_latch \| (u32 << 8));
799	pChan->write_state = RW_STATE_WORD0;
800	break;
801	}
802	DEVPIT_UNLOCK_BOTH(pThis);
803	#endif /* !IN_RING3 */
804	}
805	return VINF_SUCCESS;
806	}
807
808
809	/**
810	* @callback_method_impl{FNIOMIOPORTIN, Speaker}
811	*/
812	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
813	{
814	NOREF(pvUser);
815	if (cb == 1)
816	{
817	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
818	DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_READ);
819
820	const uint64_t u64Now = TMTimerGet(pThis->channels[0].CTX_SUFF(pTimer));
821	Assert(TMTimerGetFreq(pThis->channels[0].CTX_SUFF(pTimer)) == 1000000000); /* lazy bird. */
822
823	/* bit 6,7 Parity error stuff. */
824	/* bit 5 - mirrors timer 2 output condition. */
825	const int fOut = pit_get_out(pThis, 2, u64Now);
826	/* bit 4 - toggled with each (DRAM?) refresh request, every 15.085 µpChan.
827	ASSUMES ns timer freq, see assertion above. */
828	#ifndef FAKE_REFRESH_CLOCK
829	const int fRefresh = (u64Now / 15085) & 1;
830	#else
831	pThis->dummy_refresh_clock ^= 1;
832	const int fRefresh = pThis->dummy_refresh_clock;
833	#endif
834	/* bit 2,3 NMI / parity status stuff. */
835	/* bit 1 - speaker data status */
836	const int fSpeakerStatus = pThis->speaker_data_on;
837	/* bit 0 - timer 2 clock gate to speaker status. */
838	const int fTimer2GateStatus = pit_get_gate(pThis, 2);
839
840	DEVPIT_UNLOCK_BOTH(pThis);
841
842	*pu32 = fTimer2GateStatus
843	\| (fSpeakerStatus << 1)
844	\| (fRefresh << 4)
845	\| (fOut << 5);
846	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x pu32=%#x\n", Port, cb, pu32));
847	return VINF_SUCCESS;
848	}
849	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
850	return VERR_IOM_IOPORT_UNUSED;
851	}
852
853	#ifdef IN_RING3
854
855	/**
856	* @callback_method_impl{FNIOMIOPORTOUT, Speaker}
857	*/
858	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
859	{
860	NOREF(pvUser);
861	if (cb == 1)
862	{
863	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
864	DEVPIT_LOCK_BOTH_RETURN(pThis, VERR_IGNORED);
865
866	pThis->speaker_data_on = (u32 >> 1) & 1;
867	pit_set_gate(pThis, 2, u32 & 1);
868
869	/** @todo r=klaus move this to a (system-specific) driver, which can
870	* abstract the details, and if necessary create a thread to minimize
871	* impact on VM execution. */
872	#ifdef RT_OS_LINUX
873	if (pThis->enmSpeakerEmu != PIT_SPEAKER_EMU_NONE)
874	{
875	PPITCHANNEL pChan = &pThis->channels[2];
876	if (pThis->speaker_data_on)
877	{
878	Log2Func(("starting beep freq=%d\n", PIT_FREQ / pChan->count));
879	switch (pThis->enmSpeakerEmu)
880	{
881	case PIT_SPEAKER_EMU_CONSOLE:
882	int res;
883	res = ioctl(pThis->hHostSpeaker, KIOCSOUND, pChan->count);
884	if (res == -1)
885	{
886	LogRel(("PIT: speaker: ioctl failed errno=%d\n", errno));
887	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
888	}
889	break;
890	case PIT_SPEAKER_EMU_EVDEV:
891	struct input_event e;
892	e.type = EV_SND;
893	e.code = SND_TONE;
894	e.value = PIT_FREQ / pChan->count;
895	write(pThis->hHostSpeaker, &e, sizeof(struct input_event));
896	break;
897	case PIT_SPEAKER_EMU_TTY:
898	write(pThis->hHostSpeaker, "\a", 1);
899	break;
900	case PIT_SPEAKER_EMU_NONE:
901	break;
902	default:
903	Log2Func(("unknown speaker emulation %d\n", pThis->enmSpeakerEmu));
904	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
905	}
906	}
907	else
908	{
909	Log2Func(("stopping beep\n"));
910	switch (pThis->enmSpeakerEmu)
911	{
912	case PIT_SPEAKER_EMU_CONSOLE:
913	ioctl(pThis->hHostSpeaker, KIOCSOUND, 0);
914	break;
915	case PIT_SPEAKER_EMU_EVDEV:
916	struct input_event e;
917	e.type = EV_SND;
918	e.code = SND_TONE;
919	e.value = 0;
920	write(pThis->hHostSpeaker, &e, sizeof(struct input_event));
921	break;
922	case PIT_SPEAKER_EMU_TTY:
923	break;
924	case PIT_SPEAKER_EMU_NONE:
925	break;
926	default:
927	Log2Func(("unknown speaker emulation %d\n", pThis->enmSpeakerEmu));
928	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
929	}
930	}
931	}
932	#endif
933
934	DEVPIT_UNLOCK_BOTH(pThis);
935	}
936	Log(("pitIOPortSpeakerWrite: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
937	return VINF_SUCCESS;
938	}
939
940
941	/* -=-=-=-=-=- Saved state -=-=-=-=-=- */
942
943	/**
944	* @callback_method_impl{FNSSMDEVLIVEEXEC}
945	*/
946	static DECLCALLBACK(int) pitLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
947	{
948	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
949	SSMR3PutIOPort(pSSM, pThis->IOPortBaseCfg);
950	SSMR3PutU8( pSSM, pThis->channels[0].irq);
951	SSMR3PutBool( pSSM, pThis->fSpeakerCfg);
952	return VINF_SSM_DONT_CALL_AGAIN;
953	}
954
955
956	/**
957	* @callback_method_impl{FNSSMDEVSAVEEXEC}
958	*/
959	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
960	{
961	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
962	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
963
964	/* The config. */
965	pitLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
966
967	/* The state. */
968	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
969	{
970	PPITCHANNEL pChan = &pThis->channels[i];
971	SSMR3PutU32(pSSM, pChan->count);
972	SSMR3PutU16(pSSM, pChan->latched_count);
973	SSMR3PutU8(pSSM, pChan->count_latched);
974	SSMR3PutU8(pSSM, pChan->status_latched);
975	SSMR3PutU8(pSSM, pChan->status);
976	SSMR3PutU8(pSSM, pChan->read_state);
977	SSMR3PutU8(pSSM, pChan->write_state);
978	SSMR3PutU8(pSSM, pChan->write_latch);
979	SSMR3PutU8(pSSM, pChan->rw_mode);
980	SSMR3PutU8(pSSM, pChan->mode);
981	SSMR3PutU8(pSSM, pChan->bcd);
982	SSMR3PutU8(pSSM, pChan->gate);
983	SSMR3PutU64(pSSM, pChan->count_load_time);
984	SSMR3PutU64(pSSM, pChan->u64NextTS);
985	SSMR3PutU64(pSSM, pChan->u64ReloadTS);
986	SSMR3PutS64(pSSM, pChan->next_transition_time);
987	if (pChan->CTX_SUFF(pTimer))
988	TMR3TimerSave(pChan->CTX_SUFF(pTimer), pSSM);
989	}
990
991	SSMR3PutS32(pSSM, pThis->speaker_data_on);
992	#ifdef FAKE_REFRESH_CLOCK
993	SSMR3PutS32(pSSM, pThis->dummy_refresh_clock);
994	#else
995	SSMR3PutS32(pSSM, 0);
996	#endif
997
998	SSMR3PutBool(pSSM, pThis->fDisabledByHpet);
999
1000	PDMCritSectLeave(&pThis->CritSect);
1001	return VINF_SUCCESS;
1002	}
1003
1004
1005	/**
1006	* @callback_method_impl{FNSSMDEVLOADEXEC}
1007	*/
1008	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1009	{
1010	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1011	int rc;
1012
1013	if ( uVersion != PIT_SAVED_STATE_VERSION
1014	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_30
1015	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_31)
1016	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1017
1018	/* The config. */
1019	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_30)
1020	{
1021	RTIOPORT IOPortBaseCfg;
1022	rc = SSMR3GetIOPort(pSSM, &IOPortBaseCfg); AssertRCReturn(rc, rc);
1023	if (IOPortBaseCfg != pThis->IOPortBaseCfg)
1024	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - IOPortBaseCfg: saved=%RTiop config=%RTiop"),
1025	IOPortBaseCfg, pThis->IOPortBaseCfg);
1026
1027	uint8_t u8Irq;
1028	rc = SSMR3GetU8(pSSM, &u8Irq); AssertRCReturn(rc, rc);
1029	if (u8Irq != pThis->channels[0].irq)
1030	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - u8Irq: saved=%#x config=%#x"),
1031	u8Irq, pThis->channels[0].irq);
1032
1033	bool fSpeakerCfg;
1034	rc = SSMR3GetBool(pSSM, &fSpeakerCfg); AssertRCReturn(rc, rc);
1035	if (fSpeakerCfg != pThis->fSpeakerCfg)
1036	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fSpeakerCfg: saved=%RTbool config=%RTbool"),
1037	fSpeakerCfg, pThis->fSpeakerCfg);
1038	}
1039
1040	if (uPass != SSM_PASS_FINAL)
1041	return VINF_SUCCESS;
1042
1043	/* The state. */
1044	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1045	{
1046	PPITCHANNEL pChan = &pThis->channels[i];
1047	SSMR3GetU32(pSSM, &pChan->count);
1048	SSMR3GetU16(pSSM, &pChan->latched_count);
1049	SSMR3GetU8(pSSM, &pChan->count_latched);
1050	SSMR3GetU8(pSSM, &pChan->status_latched);
1051	SSMR3GetU8(pSSM, &pChan->status);
1052	SSMR3GetU8(pSSM, &pChan->read_state);
1053	SSMR3GetU8(pSSM, &pChan->write_state);
1054	SSMR3GetU8(pSSM, &pChan->write_latch);
1055	SSMR3GetU8(pSSM, &pChan->rw_mode);
1056	SSMR3GetU8(pSSM, &pChan->mode);
1057	SSMR3GetU8(pSSM, &pChan->bcd);
1058	SSMR3GetU8(pSSM, &pChan->gate);
1059	SSMR3GetU64(pSSM, &pChan->count_load_time);
1060	SSMR3GetU64(pSSM, &pChan->u64NextTS);
1061	SSMR3GetU64(pSSM, &pChan->u64ReloadTS);
1062	SSMR3GetS64(pSSM, &pChan->next_transition_time);
1063	if (pChan->CTX_SUFF(pTimer))
1064	{
1065	TMR3TimerLoad(pChan->CTX_SUFF(pTimer), pSSM);
1066	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
1067	pChan->mode, pChan->count, pChan->count, PIT_FREQ / pChan->count, (PIT_FREQ * 100 / pChan->count) % 100, i));
1068	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1069	TMTimerSetFrequencyHint(pChan->CTX_SUFF(pTimer), PIT_FREQ / pChan->count);
1070	PDMCritSectLeave(&pThis->CritSect);
1071	}
1072	pThis->channels[i].cRelLogEntries = 0;
1073	}
1074
1075	SSMR3GetS32(pSSM, &pThis->speaker_data_on);
1076	#ifdef FAKE_REFRESH_CLOCK
1077	SSMR3GetS32(pSSM, &pThis->dummy_refresh_clock);
1078	#else
1079	int32_t u32Dummy;
1080	SSMR3GetS32(pSSM, &u32Dummy);
1081	#endif
1082	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_31)
1083	SSMR3GetBool(pSSM, &pThis->fDisabledByHpet);
1084
1085	return VINF_SUCCESS;
1086	}
1087
1088
1089	/* -=-=-=-=-=- Timer -=-=-=-=-=- */
1090
1091	/**
1092	* @callback_method_impl{FNTMTIMERDEV}
1093	* @param pvUser Pointer to the PIT channel state.
1094	*/
1095	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1096	{
1097	PPITCHANNEL pChan = (PPITCHANNEL)pvUser;
1098	STAM_PROFILE_ADV_START(&pChan->CTX_SUFF(pPit)->StatPITHandler, a);
1099
1100	Log(("pitTimer\n"));
1101	Assert(PDMCritSectIsOwner(&PDMINS_2_DATA(pDevIns, PPITSTATE)->CritSect));
1102	Assert(TMTimerIsLockOwner(pTimer));
1103
1104	pit_irq_timer_update(pChan, pChan->next_transition_time, TMTimerGet(pTimer), true);
1105
1106	STAM_PROFILE_ADV_STOP(&pChan->CTX_SUFF(pPit)->StatPITHandler, a);
1107	}
1108
1109
1110	/* -=-=-=-=-=- Debug Info -=-=-=-=-=- */
1111
1112	/**
1113	* @callback_method_impl{FNDBGFHANDLERDEV}
1114	*/
1115	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1116	{
1117	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1118	unsigned i;
1119	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1120	{
1121	const PITCHANNEL *pChan = &pThis->channels[i];
1122
1123	pHlp->pfnPrintf(pHlp,
1124	"PIT (i8254) channel %d status: irq=%#x\n"
1125	" count=%08x" " latched_count=%04x count_latched=%02x\n"
1126	" status=%02x status_latched=%02x read_state=%02x\n"
1127	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
1128	" mode=%02x bcd=%02x gate=%02x\n"
1129	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
1130	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
1131	,
1132	i, pChan->irq,
1133	pChan->count, pChan->latched_count, pChan->count_latched,
1134	pChan->status, pChan->status_latched, pChan->read_state,
1135	pChan->write_state, pChan->write_latch, pChan->rw_mode,
1136	pChan->mode, pChan->bcd, pChan->gate,
1137	pChan->count_load_time, pChan->next_transition_time,
1138	pChan->u64ReloadTS, pChan->u64NextTS);
1139	}
1140	#ifdef FAKE_REFRESH_CLOCK
1141	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
1142	pThis->speaker_data_on, pThis->dummy_refresh_clock);
1143	#else
1144	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x\n", pThis->speaker_data_on);
1145	#endif
1146	if (pThis->fDisabledByHpet)
1147	pHlp->pfnPrintf(pHlp, "Disabled by HPET\n");
1148	}
1149
1150
1151	/* -=-=-=-=-=- IHpetLegacyNotify -=-=-=-=-=- */
1152
1153	/**
1154	* @interface_method_impl{PDMIHPETLEGACYNOTIFY,pfnModeChanged}
1155	*/
1156	static DECLCALLBACK(void) pitNotifyHpetLegacyNotify_ModeChanged(PPDMIHPETLEGACYNOTIFY pInterface, bool fActivated)
1157	{
1158	PPITSTATE pThis = RT_FROM_MEMBER(pInterface, PITSTATE, IHpetLegacyNotify);
1159	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1160
1161	pThis->fDisabledByHpet = fActivated;
1162
1163	PDMCritSectLeave(&pThis->CritSect);
1164	}
1165
1166
1167	/* -=-=-=-=-=- PDMDEVINS::IBase -=-=-=-=-=- */
1168
1169	/**
1170	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
1171	*/
1172	static DECLCALLBACK(void ) pitQueryInterface(PPDMIBASE pInterface, const char pszIID)
1173	{
1174	PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase);
1175	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1176	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase);
1177	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIHPETLEGACYNOTIFY, &pThis->IHpetLegacyNotify);
1178	return NULL;
1179	}
1180
1181
1182	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
1183
1184	/**
1185	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1186	*/
1187	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1188	{
1189	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1190	LogFlow(("pitRelocate: \n"));
1191
1192	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1193	{
1194	PPITCHANNEL pChan = &pThis->channels[i];
1195	if (pChan->pTimerR3)
1196	pChan->pTimerRC = TMTimerRCPtr(pChan->pTimerR3);
1197	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
1198	}
1199	}
1200
1201
1202	/**
1203	* @interface_method_impl{PDMDEVREG,pfnReset}
1204	*/
1205	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
1206	{
1207	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1208	LogFlow(("pitReset: \n"));
1209
1210	DEVPIT_R3_LOCK_BOTH(pThis);
1211
1212	pThis->fDisabledByHpet = false;
1213
1214	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1215	{
1216	PPITCHANNEL pChan = &pThis->channels[i];
1217
1218	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
1219	pChan->latched_count = 0;
1220	pChan->count_latched = 0;
1221	pChan->status_latched = 0;
1222	pChan->status = 0;
1223	pChan->read_state = 0;
1224	pChan->write_state = 0;
1225	pChan->write_latch = 0;
1226	pChan->rw_mode = 0;
1227	pChan->bcd = 0;
1228	#endif
1229	pChan->u64NextTS = UINT64_MAX;
1230	pChan->cRelLogEntries = 0;
1231	pChan->mode = 3;
1232	pChan->gate = (i != 2);
1233	pit_load_count(pChan, 0);
1234	}
1235
1236	DEVPIT_UNLOCK_BOTH(pThis);
1237	}
1238
1239
1240	/**
1241	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1242	*/
1243	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1244	{
1245	PPITSTATE pThis = PDMINS_2_DATA(pDevIns, PPITSTATE);
1246	int rc;
1247	uint8_t u8Irq;
1248	uint16_t u16Base;
1249	bool fSpeaker;
1250	bool fGCEnabled;
1251	bool fR0Enabled;
1252	unsigned i;
1253	Assert(iInstance == 0);
1254
1255	/*
1256	* Validate configuration.
1257	*/
1258	if (!CFGMR3AreValuesValid(pCfg, "Irq\0" "Base\0" "SpeakerEnabled\0" "PassthroughSpeaker\0" "R0Enabled\0"))
1259	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1260
1261	/*
1262	* Init the data.
1263	*/
1264	rc = CFGMR3QueryU8Def(pCfg, "Irq", &u8Irq, 0);
1265	if (RT_FAILURE(rc))
1266	return PDMDEV_SET_ERROR(pDevIns, rc,
1267	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
1268
1269	rc = CFGMR3QueryU16Def(pCfg, "Base", &u16Base, 0x40);
1270	if (RT_FAILURE(rc))
1271	return PDMDEV_SET_ERROR(pDevIns, rc,
1272	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
1273
1274	rc = CFGMR3QueryBoolDef(pCfg, "SpeakerEnabled", &fSpeaker, true);
1275	if (RT_FAILURE(rc))
1276	return PDMDEV_SET_ERROR(pDevIns, rc,
1277	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
1278
1279	bool fPassthroughSpeaker;
1280	rc = CFGMR3QueryBoolDef(pCfg, "PassthroughSpeaker", &fPassthroughSpeaker, false);
1281	if (RT_FAILURE(rc))
1282	return PDMDEV_SET_ERROR(pDevIns, rc,
1283	N_("Configuration error: failed to read PassthroughSpeaker as boolean"));
1284
1285	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1286	if (RT_FAILURE(rc))
1287	return PDMDEV_SET_ERROR(pDevIns, rc,
1288	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
1289
1290	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1291	if (RT_FAILURE(rc))
1292	return PDMDEV_SET_ERROR(pDevIns, rc,
1293	N_("Configuration error: failed to read R0Enabled as boolean"));
1294
1295	pThis->pDevIns = pDevIns;
1296	pThis->IOPortBaseCfg = u16Base;
1297	pThis->fSpeakerCfg = fSpeaker;
1298	if (fPassthroughSpeaker)
1299	{
1300	/** @todo r=klaus move this to a (system-specific) driver */
1301	#ifdef RT_OS_LINUX
1302	int fd;
1303	fd = open("/dev/input/by-path/platform-pcspkr-event-spkr", O_WRONLY);
1304	if (fd == -1)
1305	fd = open("/dev/tty0", O_WRONLY);
1306	if (fd == -1)
1307	fd = open("/dev/vc/0", O_WRONLY);
1308	if (fd == -1)
1309	{
1310	LogRel(("PIT: speaker: could not open console/speaker device\n"));
1311	fd = open("/dev/tty", O_WRONLY);
1312	if (fd == -1)
1313	{
1314	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
1315	LogRel(("PIT: speaker: no emulation possible\n"));
1316	}
1317	else
1318	{
1319	pThis->hHostSpeaker = fd;
1320	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_TTY;
1321	LogRel(("PIT: speaker: emulation mode tty\n"));
1322	}
1323	}
1324	else
1325	{
1326	pThis->hHostSpeaker = fd;
1327	if (ioctl(fd, EVIOCGSND(0)) != -1)
1328	{
1329	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_EVDEV;
1330	LogRel(("PIT: speaker: emulation mode evdev\n"));
1331	}
1332	else
1333	{
1334	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_CONSOLE;
1335	LogRel(("PIT: speaker: emulation mode console\n"));
1336	}
1337	}
1338	#else
1339	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
1340	#endif
1341	}
1342	else
1343	pThis->enmSpeakerEmu = PIT_SPEAKER_EMU_NONE;
1344	pThis->channels[0].irq = u8Irq;
1345	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1346	{
1347	pThis->channels[i].pPitR3 = pThis;
1348	pThis->channels[i].pPitR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1349	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
1350	}
1351
1352	/*
1353	* Interfaces
1354	*/
1355	/* IBase */
1356	pDevIns->IBase.pfnQueryInterface = pitQueryInterface;
1357	/* IHpetLegacyNotify */
1358	pThis->IHpetLegacyNotify.pfnModeChanged = pitNotifyHpetLegacyNotify_ModeChanged;
1359
1360	/*
1361	* We do our own locking. This must be done before creating timers.
1362	*/
1363	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "pit#%u", iInstance);
1364	AssertRCReturn(rc, rc);
1365
1366	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1367	AssertRCReturn(rc, rc);
1368
1369	/*
1370	* Create the timer, make it take our critsect.
1371	*/
1372	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, &pThis->channels[0],
1373	TMTIMER_FLAGS_NO_CRIT_SECT, "i8254 Programmable Interval Timer",
1374	&pThis->channels[0].pTimerR3);
1375	if (RT_FAILURE(rc))
1376	return rc;
1377	pThis->channels[0].pTimerRC = TMTimerRCPtr(pThis->channels[0].pTimerR3);
1378	pThis->channels[0].pTimerR0 = TMTimerR0Ptr(pThis->channels[0].pTimerR3);
1379	rc = TMR3TimerSetCritSect(pThis->channels[0].pTimerR3, &pThis->CritSect);
1380	AssertRCReturn(rc, rc);
1381
1382	/*
1383	* Register I/O ports.
1384	*/
1385	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
1386	if (RT_FAILURE(rc))
1387	return rc;
1388	if (fGCEnabled)
1389	{
1390	rc = PDMDevHlpIOPortRegisterRC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1391	if (RT_FAILURE(rc))
1392	return rc;
1393	}
1394	if (fR0Enabled)
1395	{
1396	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1397	if (RT_FAILURE(rc))
1398	return rc;
1399	}
1400
1401	if (fSpeaker)
1402	{
1403	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1404	if (RT_FAILURE(rc))
1405	return rc;
1406	if (fGCEnabled)
1407	{
1408	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1409	if (RT_FAILURE(rc))
1410	return rc;
1411	}
1412	}
1413
1414	/*
1415	* Saved state.
1416	*/
1417	rc = PDMDevHlpSSMRegister3(pDevIns, PIT_SAVED_STATE_VERSION, sizeof(*pThis), pitLiveExec, pitSaveExec, pitLoadExec);
1418	if (RT_FAILURE(rc))
1419	return rc;
1420
1421	/*
1422	* Initialize the device state.
1423	*/
1424	pitReset(pDevIns);
1425
1426	/*
1427	* Register statistics and debug info.
1428	*/
1429	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1430	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1431
1432	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1433
1434	return VINF_SUCCESS;
1435	}
1436
1437
1438	/**
1439	* The device registration structure.
1440	*/
1441	const PDMDEVREG g_DeviceI8254 =
1442	{
1443	/* u32Version */
1444	PDM_DEVREG_VERSION,
1445	/* szName */
1446	"i8254",
1447	/* szRCMod */
1448	"VBoxDDRC.rc",
1449	/* szR0Mod */
1450	"VBoxDDR0.r0",
1451	/* pszDescription */
1452	"Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1453	/* fFlags */
1454	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1455	/* fClass */
1456	PDM_DEVREG_CLASS_PIT,
1457	/* cMaxInstances */
1458	1,
1459	/* cbInstance */
1460	sizeof(PITSTATE),
1461	/* pfnConstruct */
1462	pitConstruct,
1463	/* pfnDestruct */
1464	NULL,
1465	/* pfnRelocate */
1466	pitRelocate,
1467	/* pfnMemSetup */
1468	NULL,
1469	/* pfnPowerOn */
1470	NULL,
1471	/* pfnReset */
1472	pitReset,
1473	/* pfnSuspend */
1474	NULL,
1475	/* pfnResume */
1476	NULL,
1477	/* pfnAttach */
1478	NULL,
1479	/* pfnDetach */
1480	NULL,
1481	/* pfnQueryInterface */
1482	NULL,
1483	/* pfnInitComplete */
1484	NULL,
1485	/* pfnPowerOff */
1486	NULL,
1487	/* pfnSoftReset */
1488	NULL,
1489	/* u32VersionEnd */
1490	PDM_DEVREG_VERSION
1491	};
1492
1493	#endif /* IN_RING3 */
1494	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 59499

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