DevPit-i8254.cpp@ 32484

Last change on this file since 32484 was 32484, checked in by vboxsync, 14 years ago
TM,DevPit,DevApic,DevRtc: Timer frequency hints for calculating the max timer frequency.
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1	/* $Id: DevPit-i8254.cpp 32484 2010-09-14 14:01:48Z vboxsync $ */
2	/** @file
3	* DevPIT-i8254 - Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU 8253/8254 interval timer emulation
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43	/*******************************************************************************
44	* Header Files *
45	*******************************************************************************/
46	#define LOG_GROUP LOG_GROUP_DEV_PIT
47	#include <VBox/pdmdev.h>
48	#include <VBox/log.h>
49	#include <VBox/stam.h>
50	#include <iprt/assert.h>
51	#include <iprt/asm-math.h>
52
53	#ifdef IN_RING3
54	# include <iprt/alloc.h>
55	# include <iprt/string.h>
56	# include <iprt/uuid.h>
57	#endif /* IN_RING3 */
58
59	#include "../Builtins.h"
60
61
62	/*******************************************************************************
63	* Defined Constants And Macros *
64	*******************************************************************************/
65	/** The PIT frequency. */
66	#define PIT_FREQ 1193182
67
68	#define RW_STATE_LSB 1
69	#define RW_STATE_MSB 2
70	#define RW_STATE_WORD0 3
71	#define RW_STATE_WORD1 4
72
73	/** The current saved state version. */
74	#define PIT_SAVED_STATE_VERSION 4
75	/** The saved state version used by VirtualBox 3.1 and earlier.
76	* This did not include disable by HPET flag. */
77	#define PIT_SAVED_STATE_VERSION_VBOX_31 3
78	/** The saved state version used by VirtualBox 3.0 and earlier.
79	* This did not include the config part. */
80	#define PIT_SAVED_STATE_VERSION_VBOX_30 2
81
82	/** @def FAKE_REFRESH_CLOCK
83	* Define this to flip the 15usec refresh bit on every read.
84	* If not defined, it will be flipped correctly. */
85	/* #define FAKE_REFRESH_CLOCK */
86	#ifdef DOXYGEN_RUNNING
87	# define FAKE_REFRESH_CLOCK
88	#endif
89
90
91	/*******************************************************************************
92	* Structures and Typedefs *
93	*******************************************************************************/
94	typedef struct PITChannelState
95	{
96	/** Pointer to the instance data - R3 Ptr. */
97	R3PTRTYPE(struct PITState *) pPitR3;
98	/** The timer - R3 Ptr. */
99	PTMTIMERR3 pTimerR3;
100	/** Pointer to the instance data - R0 Ptr. */
101	R0PTRTYPE(struct PITState *) pPitR0;
102	/** The timer - R0 Ptr. */
103	PTMTIMERR0 pTimerR0;
104	/** Pointer to the instance data - RC Ptr. */
105	RCPTRTYPE(struct PITState *) pPitRC;
106	/** The timer - RC Ptr. */
107	PTMTIMERRC pTimerRC;
108	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
109	uint64_t u64ReloadTS;
110	/** The actual time of the next tick.
111	* As apposed to the next_transition_time which contains the correct time of the next tick. */
112	uint64_t u64NextTS;
113
114	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
115	uint64_t count_load_time;
116	/* irq handling */
117	int64_t next_transition_time;
118	int32_t irq;
119	/** Number of release log entries. Used to prevent floading. */
120	uint32_t cRelLogEntries;
121
122	uint32_t count; /* can be 65536 */
123	uint16_t latched_count;
124	uint8_t count_latched;
125	uint8_t status_latched;
126
127	uint8_t status;
128	uint8_t read_state;
129	uint8_t write_state;
130	uint8_t write_latch;
131
132	uint8_t rw_mode;
133	uint8_t mode;
134	uint8_t bcd; /* not supported */
135	uint8_t gate; /* timer start */
136
137	} PITChannelState;
138
139	typedef struct PITState
140	{
141	PITChannelState channels[3];
142	/** Speaker data. */
143	int32_t speaker_data_on;
144	#ifdef FAKE_REFRESH_CLOCK
145	/** Speaker dummy. */
146	int32_t dummy_refresh_clock;
147	#else
148	uint32_t Alignment1;
149	#endif
150	/** Config: I/O port base. */
151	RTIOPORT IOPortBaseCfg;
152	/** Config: Speaker enabled. */
153	bool fSpeakerCfg;
154	bool fDisabledByHpet;
155	bool afAlignment0[HC_ARCH_BITS == 32 ? 4 : 4];
156	/** PIT port interface. */
157	PDMIHPETLEGACYNOTIFY IHpetLegacyNotify;
158	/** Pointer to the device instance. */
159	PPDMDEVINSR3 pDevIns;
160	/** Number of IRQs that's been raised. */
161	STAMCOUNTER StatPITIrq;
162	/** Profiling the timer callback handler. */
163	STAMPROFILEADV StatPITHandler;
164	} PITState;
165
166
167	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
168	/*******************************************************************************
169	* Internal Functions *
170	*******************************************************************************/
171	RT_C_DECLS_BEGIN
172	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
173	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
174	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
175	#ifdef IN_RING3
176	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
177	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time, uint64_t now);
178	#endif
179	RT_C_DECLS_END
180
181
182
183
184	static int pit_get_count(PITChannelState *s)
185	{
186	uint64_t d;
187	int counter;
188	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
189
190	if (s->mode == 2)
191	{
192	if (s->u64NextTS == UINT64_MAX)
193	{
194	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
195	return s->count - (d % s->count); /** @todo check this value. */
196	}
197	uint64_t Interval = s->u64NextTS - s->u64ReloadTS;
198	if (!Interval)
199	return s->count - 1; /** @todo This is WRONG! But I'm too tired to fix it properly and just want to shut up a DIV/0 trap now. */
200	d = TMTimerGet(pTimer);
201	d = ASMMultU64ByU32DivByU32(d - s->u64ReloadTS, s->count, Interval);
202	if (d >= s->count)
203	return 1;
204	return s->count - d;
205	}
206	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
207	switch(s->mode) {
208	case 0:
209	case 1:
210	case 4:
211	case 5:
212	counter = (s->count - d) & 0xffff;
213	break;
214	case 3:
215	/* XXX: may be incorrect for odd counts */
216	counter = s->count - ((2 * d) % s->count);
217	break;
218	default:
219	counter = s->count - (d % s->count);
220	break;
221	}
222	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
223	return counter;
224	}
225
226	/* get pit output bit */
227	static int pit_get_out1(PITChannelState *s, int64_t current_time)
228	{
229	uint64_t d;
230	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
231	int out;
232
233	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
234	switch(s->mode) {
235	default:
236	case 0:
237	out = (d >= s->count);
238	break;
239	case 1:
240	out = (d < s->count);
241	break;
242	case 2:
243	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, s->count, (unsigned)(d % s->count)));
244	if ((d % s->count) == 0 && d != 0)
245	out = 1;
246	else
247	out = 0;
248	break;
249	case 3:
250	out = (d % s->count) < ((s->count + 1) >> 1);
251	break;
252	case 4:
253	case 5:
254	out = (d == s->count);
255	break;
256	}
257	return out;
258	}
259
260
261	static int pit_get_out(PITState *pit, int channel, int64_t current_time)
262	{
263	PITChannelState *s = &pit->channels[channel];
264	return pit_get_out1(s, current_time);
265	}
266
267
268	static int pit_get_gate(PITState *pit, int channel)
269	{
270	PITChannelState *s = &pit->channels[channel];
271	return s->gate;
272	}
273
274
275	/* if already latched, do not latch again */
276	static void pit_latch_count(PITChannelState *s)
277	{
278	if (!s->count_latched) {
279	s->latched_count = pit_get_count(s);
280	s->count_latched = s->rw_mode;
281	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
282	s->latched_count, ASMMultU64ByU32DivByU32(s->count - s->latched_count, 1000000000, PIT_FREQ), s->count, s->mode));
283	}
284	}
285
286	#ifdef IN_RING3
287
288	/* val must be 0 or 1 */
289	static void pit_set_gate(PITState *pit, int channel, int val)
290	{
291	PITChannelState *s = &pit->channels[channel];
292	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
293	Assert((val & 1) == val);
294
295	switch(s->mode) {
296	default:
297	case 0:
298	case 4:
299	/* XXX: just disable/enable counting */
300	break;
301	case 1:
302	case 5:
303	if (s->gate < val) {
304	/* restart counting on rising edge */
305	Log(("pit_set_gate: restarting mode %d\n", s->mode));
306	s->count_load_time = TMTimerGet(pTimer);
307	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
308	}
309	break;
310	case 2:
311	case 3:
312	if (s->gate < val) {
313	/* restart counting on rising edge */
314	Log(("pit_set_gate: restarting mode %d\n", s->mode));
315	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
316	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
317	}
318	/* XXX: disable/enable counting */
319	break;
320	}
321	s->gate = val;
322	}
323
324	DECLINLINE(void) pit_load_count(PITChannelState *s, int val)
325	{
326	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
327	if (val == 0)
328	val = 0x10000;
329	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
330	s->count = val;
331	pit_irq_timer_update(s, s->count_load_time, s->count_load_time);
332
333	/* log the new rate (ch 0 only). */
334	if (s->pTimerR3 /* ch 0 */)
335	{
336	if (s->cRelLogEntries++ < 32)
337	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
338	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
339	else
340	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
341	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
342	TMTimerSetFrequencyHint(s->CTX_SUFF(pTimer), PIT_FREQ / s->count);
343	}
344	else
345	Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d)\n",
346	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100,
347	s - &s->CTX_SUFF(pPit)->channels[0]));
348	}
349
350	/* return -1 if no transition will occur. */
351	static int64_t pit_get_next_transition_time(PITChannelState *s,
352	uint64_t current_time)
353	{
354	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
355	uint64_t d, next_time, base;
356	uint32_t period2;
357
358	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
359	switch(s->mode) {
360	default:
361	case 0:
362	case 1:
363	if (d < s->count)
364	next_time = s->count;
365	else
366	return -1;
367	break;
368	/*
369	* Mode 2: The period is count + 1 PIT ticks.
370	* When the counter reaches 1 we sent the output low (for channel 0 that
371	* means raise an irq). On the next tick, where we should be decrementing
372	* from 1 to 0, the count is loaded and the output goes high (channel 0
373	* means clearing the irq).
374	*
375	* In VBox we simplify the tick cycle between 1 and 0 and immediately clears
376	* the irq. We also don't set it until we reach 0, which is a tick late - will
377	* try fix that later some day.
378	*/
379	case 2:
380	base = (d / s->count) * s->count;
381	#ifndef VBOX /* see above */
382	if ((d - base) == 0 && d != 0)
383	next_time = base + s->count;
384	else
385	#endif
386	next_time = base + s->count + 1;
387	break;
388	case 3:
389	base = (d / s->count) * s->count;
390	period2 = ((s->count + 1) >> 1);
391	if ((d - base) < period2)
392	next_time = base + period2;
393	else
394	next_time = base + s->count;
395	break;
396	case 4:
397	case 5:
398	if (d < s->count)
399	next_time = s->count;
400	else if (d == s->count)
401	next_time = s->count + 1;
402	else
403	return -1;
404	break;
405	}
406	/* convert to timer units */
407	LogFlow(("PIT: next_time=%'14RU64 %'20RU64 mode=%#x count=%#06x\n", next_time,
408	ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), s->mode, s->count));
409	next_time = s->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
410	/* fix potential rounding problems */
411	/* XXX: better solution: use a clock at PIT_FREQ Hz */
412	if (next_time <= current_time)
413	next_time = current_time + 1;
414	return next_time;
415	}
416
417	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time, uint64_t now)
418	{
419	int64_t expire_time;
420	int irq_level;
421	PPDMDEVINS pDevIns;
422	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
423
424	if (!s->CTX_SUFF(pTimer))
425	return;
426	expire_time = pit_get_next_transition_time(s, current_time);
427	irq_level = pit_get_out1(s, current_time);
428
429	/* We just flip-flop the irq level to save that extra timer call, which isn't generally required (we haven't served it for months). */
430	pDevIns = s->CTX_SUFF(pPit)->pDevIns;
431
432	/* If PIT disabled by HPET - just disconnect ticks from interrupt controllers, and not modify
433	* other moments of device functioning.
434	* @todo: is it correct?
435	*/
436	if (!s->pPitR3->fDisabledByHpet)
437	{
438	PDMDevHlpISASetIrq(pDevIns, s->irq, irq_level);
439	if (irq_level)
440	PDMDevHlpISASetIrq(pDevIns, s->irq, 0);
441	}
442
443	if (irq_level)
444	{
445	s->u64ReloadTS = now;
446	STAM_COUNTER_INC(&s->CTX_SUFF(pPit)->StatPITIrq);
447	}
448
449	if (expire_time != -1)
450	{
451	Log3(("pit_irq_timer_update: next=%'RU64 now=%'RU64\n", expire_time, now));
452	s->u64NextTS = expire_time;
453	TMTimerSet(s->CTX_SUFF(pTimer), s->u64NextTS);
454	}
455	else
456	{
457	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", s->mode, s->count, irq_level));
458	TMTimerStop(s->CTX_SUFF(pTimer));
459	s->u64NextTS = UINT64_MAX;
460	}
461	s->next_transition_time = expire_time;
462	}
463
464	#endif /* IN_RING3 */
465
466
467	/**
468	* Port I/O Handler for IN operations.
469	*
470	* @returns VBox status code.
471	*
472	* @param pDevIns The device instance.
473	* @param pvUser User argument - ignored.
474	* @param Port Port number used for the IN operation.
475	* @param pu32 Where to store the result.
476	* @param cb Number of bytes read.
477	*/
478	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
479	{
480	Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
481	NOREF(pvUser);
482	Port &= 3;
483	if (cb != 1 \|\| Port == 3)
484	{
485	Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
486	return VERR_IOM_IOPORT_UNUSED;
487	}
488
489	PITState pit = PDMINS_2_DATA(pDevIns, PITState );
490	int ret;
491	PITChannelState *s = &pit->channels[Port];
492	if (s->status_latched)
493	{
494	s->status_latched = 0;
495	ret = s->status;
496	}
497	else if (s->count_latched)
498	{
499	switch (s->count_latched)
500	{
501	default:
502	case RW_STATE_LSB:
503	ret = s->latched_count & 0xff;
504	s->count_latched = 0;
505	break;
506	case RW_STATE_MSB:
507	ret = s->latched_count >> 8;
508	s->count_latched = 0;
509	break;
510	case RW_STATE_WORD0:
511	ret = s->latched_count & 0xff;
512	s->count_latched = RW_STATE_MSB;
513	break;
514	}
515	}
516	else
517	{
518	int count;
519	switch (s->read_state)
520	{
521	default:
522	case RW_STATE_LSB:
523	count = pit_get_count(s);
524	ret = count & 0xff;
525	break;
526	case RW_STATE_MSB:
527	count = pit_get_count(s);
528	ret = (count >> 8) & 0xff;
529	break;
530	case RW_STATE_WORD0:
531	count = pit_get_count(s);
532	ret = count & 0xff;
533	s->read_state = RW_STATE_WORD1;
534	break;
535	case RW_STATE_WORD1:
536	count = pit_get_count(s);
537	ret = (count >> 8) & 0xff;
538	s->read_state = RW_STATE_WORD0;
539	break;
540	}
541	}
542
543	*pu32 = ret;
544	Log2(("pitIOPortRead: Port=%#x cb=%x pu32=%#04x\n", Port, cb, pu32));
545	return VINF_SUCCESS;
546	}
547
548
549	/**
550	* Port I/O Handler for OUT operations.
551	*
552	* @returns VBox status code.
553	*
554	* @param pDevIns The device instance.
555	* @param pvUser User argument - ignored.
556	* @param Port Port number used for the IN operation.
557	* @param u32 The value to output.
558	* @param cb The value size in bytes.
559	*/
560	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
561	{
562	Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
563	NOREF(pvUser);
564	if (cb != 1)
565	return VINF_SUCCESS;
566
567	PITState pit = PDMINS_2_DATA(pDevIns, PITState );
568	Port &= 3;
569	if (Port == 3)
570	{
571	/*
572	* Port 43h - Mode/Command Register.
573	* 7 6 5 4 3 2 1 0
574	* * * . . . . . . Select channel: 0 0 = Channel 0
575	* 0 1 = Channel 1
576	* 1 0 = Channel 2
577	* 1 1 = Read-back command (8254 only)
578	* (Illegal on 8253)
579	* (Illegal on PS/2 {JAM})
580	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
581	* 0 1 = Access mode: lobyte only
582	* 1 0 = Access mode: hibyte only
583	* 1 1 = Access mode: lobyte/hibyte
584	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
585	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
586	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
587	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
588	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
589	*/
590	unsigned channel = u32 >> 6;
591	if (channel == 3)
592	{
593	/* read-back command */
594	for (channel = 0; channel < RT_ELEMENTS(pit->channels); channel++)
595	{
596	PITChannelState *s = &pit->channels[channel];
597	if (u32 & (2 << channel)) {
598	if (!(u32 & 0x20))
599	pit_latch_count(s);
600	if (!(u32 & 0x10) && !s->status_latched)
601	{
602	/* status latch */
603	/* XXX: add BCD and null count */
604	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
605	s->status = (pit_get_out1(s, TMTimerGet(pTimer)) << 7)
606	\| (s->rw_mode << 4)
607	\| (s->mode << 1)
608	\| s->bcd;
609	s->status_latched = 1;
610	}
611	}
612	}
613	}
614	else
615	{
616	PITChannelState *s = &pit->channels[channel];
617	unsigned access = (u32 >> 4) & 3;
618	if (access == 0)
619	pit_latch_count(s);
620	else
621	{
622	s->rw_mode = access;
623	s->read_state = access;
624	s->write_state = access;
625
626	s->mode = (u32 >> 1) & 7;
627	s->bcd = u32 & 1;
628	/* XXX: update irq timer ? */
629	}
630	}
631	}
632	else
633	{
634	#ifndef IN_RING3
635	return VINF_IOM_HC_IOPORT_WRITE;
636	#else /* IN_RING3 */
637	/*
638	* Port 40-42h - Channel Data Ports.
639	*/
640	PITChannelState *s = &pit->channels[Port];
641	switch(s->write_state)
642	{
643	default:
644	case RW_STATE_LSB:
645	pit_load_count(s, u32);
646	break;
647	case RW_STATE_MSB:
648	pit_load_count(s, u32 << 8);
649	break;
650	case RW_STATE_WORD0:
651	s->write_latch = u32;
652	s->write_state = RW_STATE_WORD1;
653	break;
654	case RW_STATE_WORD1:
655	pit_load_count(s, s->write_latch \| (u32 << 8));
656	s->write_state = RW_STATE_WORD0;
657	break;
658	}
659	#endif /* !IN_RING3 */
660	}
661	return VINF_SUCCESS;
662	}
663
664
665	/**
666	* Port I/O Handler for speaker IN operations.
667	*
668	* @returns VBox status code.
669	*
670	* @param pDevIns The device instance.
671	* @param pvUser User argument - ignored.
672	* @param Port Port number used for the IN operation.
673	* @param pu32 Where to store the result.
674	* @param cb Number of bytes read.
675	*/
676	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
677	{
678	NOREF(pvUser);
679	if (cb == 1)
680	{
681	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
682	const uint64_t u64Now = TMTimerGet(pThis->channels[0].CTX_SUFF(pTimer));
683	Assert(TMTimerGetFreq(pThis->channels[0].CTX_SUFF(pTimer)) == 1000000000); /* lazy bird. */
684
685	/* bit 6,7 Parity error stuff. */
686	/* bit 5 - mirrors timer 2 output condition. */
687	const int fOut = pit_get_out(pThis, 2, u64Now);
688	/* bit 4 - toggled with each (DRAM?) refresh request, every 15.085 µs.
689	ASSUMES ns timer freq, see assertion above. */
690	#ifndef FAKE_REFRESH_CLOCK
691	const int fRefresh = (u64Now / 15085) & 1;
692	#else
693	pThis->dummy_refresh_clock ^= 1;
694	const int fRefresh = pThis->dummy_refresh_clock;
695	#endif
696	/* bit 2,3 NMI / parity status stuff. */
697	/* bit 1 - speaker data status */
698	const int fSpeakerStatus = pThis->speaker_data_on;
699	/* bit 0 - timer 2 clock gate to speaker status. */
700	const int fTimer2GateStatus = pit_get_gate(pThis, 2);
701
702	*pu32 = fTimer2GateStatus
703	\| (fSpeakerStatus << 1)
704	\| (fRefresh << 4)
705	\| (fOut << 5);
706	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x pu32=%#x\n", Port, cb, pu32));
707	return VINF_SUCCESS;
708	}
709	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
710	return VERR_IOM_IOPORT_UNUSED;
711	}
712
713	#ifdef IN_RING3
714
715	/**
716	* Port I/O Handler for speaker OUT operations.
717	*
718	* @returns VBox status code.
719	*
720	* @param pDevIns The device instance.
721	* @param pvUser User argument - ignored.
722	* @param Port Port number used for the IN operation.
723	* @param u32 The value to output.
724	* @param cb The value size in bytes.
725	*/
726	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
727	{
728	NOREF(pvUser);
729	if (cb == 1)
730	{
731	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
732	pThis->speaker_data_on = (u32 >> 1) & 1;
733	pit_set_gate(pThis, 2, u32 & 1);
734	}
735	Log(("pitIOPortSpeakerWrite: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
736	return VINF_SUCCESS;
737	}
738
739
740	/**
741	* @copydoc FNSSMDEVLIVEEXEC
742	*/
743	static DECLCALLBACK(int) pitLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
744	{
745	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
746	SSMR3PutIOPort(pSSM, pThis->IOPortBaseCfg);
747	SSMR3PutU8( pSSM, pThis->channels[0].irq);
748	SSMR3PutBool( pSSM, pThis->fSpeakerCfg);
749	return VINF_SSM_DONT_CALL_AGAIN;
750	}
751
752
753	/**
754	* @copydoc FNSSMDEVSAVEEXEC
755	*/
756	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
757	{
758	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
759	unsigned i;
760
761	/* The config. */
762	pitLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
763
764	/* The state. */
765	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
766	{
767	PITChannelState *s = &pThis->channels[i];
768	SSMR3PutU32(pSSM, s->count);
769	SSMR3PutU16(pSSM, s->latched_count);
770	SSMR3PutU8(pSSM, s->count_latched);
771	SSMR3PutU8(pSSM, s->status_latched);
772	SSMR3PutU8(pSSM, s->status);
773	SSMR3PutU8(pSSM, s->read_state);
774	SSMR3PutU8(pSSM, s->write_state);
775	SSMR3PutU8(pSSM, s->write_latch);
776	SSMR3PutU8(pSSM, s->rw_mode);
777	SSMR3PutU8(pSSM, s->mode);
778	SSMR3PutU8(pSSM, s->bcd);
779	SSMR3PutU8(pSSM, s->gate);
780	SSMR3PutU64(pSSM, s->count_load_time);
781	SSMR3PutU64(pSSM, s->u64NextTS);
782	SSMR3PutU64(pSSM, s->u64ReloadTS);
783	SSMR3PutS64(pSSM, s->next_transition_time);
784	if (s->CTX_SUFF(pTimer))
785	TMR3TimerSave(s->CTX_SUFF(pTimer), pSSM);
786	}
787
788	SSMR3PutS32(pSSM, pThis->speaker_data_on);
789	#ifdef FAKE_REFRESH_CLOCK
790	SSMR3PutS32(pSSM, pThis->dummy_refresh_clock);
791	#else
792	SSMR3PutS32(pSSM, 0);
793	#endif
794
795	return SSMR3PutBool(pSSM, pThis->fDisabledByHpet);
796	}
797
798
799	/**
800	* @copydoc FNSSMDEVLOADEXEC
801	*/
802	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
803	{
804	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
805	int rc;
806
807	if ( uVersion != PIT_SAVED_STATE_VERSION
808	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_30
809	&& uVersion != PIT_SAVED_STATE_VERSION_VBOX_31)
810	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
811
812	/* The config. */
813	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_30)
814	{
815	RTIOPORT IOPortBaseCfg;
816	rc = SSMR3GetIOPort(pSSM, &IOPortBaseCfg); AssertRCReturn(rc, rc);
817	if (IOPortBaseCfg != pThis->IOPortBaseCfg)
818	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - IOPortBaseCfg: saved=%RTiop config=%RTiop"),
819	IOPortBaseCfg, pThis->IOPortBaseCfg);
820
821	uint8_t u8Irq;
822	rc = SSMR3GetU8(pSSM, &u8Irq); AssertRCReturn(rc, rc);
823	if (u8Irq != pThis->channels[0].irq)
824	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - u8Irq: saved=%#x config=%#x"),
825	u8Irq, pThis->channels[0].irq);
826
827	bool fSpeakerCfg;
828	rc = SSMR3GetBool(pSSM, &fSpeakerCfg); AssertRCReturn(rc, rc);
829	if (fSpeakerCfg != pThis->fSpeakerCfg)
830	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fSpeakerCfg: saved=%RTbool config=%RTbool"),
831	fSpeakerCfg, pThis->fSpeakerCfg);
832	}
833
834	if (uPass != SSM_PASS_FINAL)
835	return VINF_SUCCESS;
836
837	/* The state. */
838	for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
839	{
840	PITChannelState *s = &pThis->channels[i];
841	SSMR3GetU32(pSSM, &s->count);
842	SSMR3GetU16(pSSM, &s->latched_count);
843	SSMR3GetU8(pSSM, &s->count_latched);
844	SSMR3GetU8(pSSM, &s->status_latched);
845	SSMR3GetU8(pSSM, &s->status);
846	SSMR3GetU8(pSSM, &s->read_state);
847	SSMR3GetU8(pSSM, &s->write_state);
848	SSMR3GetU8(pSSM, &s->write_latch);
849	SSMR3GetU8(pSSM, &s->rw_mode);
850	SSMR3GetU8(pSSM, &s->mode);
851	SSMR3GetU8(pSSM, &s->bcd);
852	SSMR3GetU8(pSSM, &s->gate);
853	SSMR3GetU64(pSSM, &s->count_load_time);
854	SSMR3GetU64(pSSM, &s->u64NextTS);
855	SSMR3GetU64(pSSM, &s->u64ReloadTS);
856	SSMR3GetS64(pSSM, &s->next_transition_time);
857	if (s->CTX_SUFF(pTimer))
858	{
859	TMR3TimerLoad(s->CTX_SUFF(pTimer), pSSM);
860	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
861	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100, i));
862	TMTimerSetFrequencyHint(s->CTX_SUFF(pTimer), PIT_FREQ / s->count);
863	}
864	pThis->channels[i].cRelLogEntries = 0;
865	}
866
867	SSMR3GetS32(pSSM, &pThis->speaker_data_on);
868	#ifdef FAKE_REFRESH_CLOCK
869	SSMR3GetS32(pSSM, &pThis->dummy_refresh_clock);
870	#else
871	int32_t u32Dummy;
872	SSMR3GetS32(pSSM, &u32Dummy);
873	#endif
874	if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_31)
875	SSMR3GetBool(pSSM, &pThis->fDisabledByHpet);
876
877	return VINF_SUCCESS;
878	}
879
880
881	/**
882	* Device timer callback function.
883	*
884	* @param pDevIns Device instance of the device which registered the timer.
885	* @param pTimer The timer handle.
886	* @param pvUser Pointer to the PIT channel state.
887	*/
888	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
889	{
890	PITChannelState s = (PITChannelState )pvUser;
891	STAM_PROFILE_ADV_START(&s->CTX_SUFF(pPit)->StatPITHandler, a);
892	Log(("pitTimer\n"));
893	pit_irq_timer_update(s, s->next_transition_time, TMTimerGet(pTimer));
894	STAM_PROFILE_ADV_STOP(&s->CTX_SUFF(pPit)->StatPITHandler, a);
895	}
896
897
898	/**
899	* Info handler, device version.
900	*
901	* @param pDevIns Device instance which registered the info.
902	* @param pHlp Callback functions for doing output.
903	* @param pszArgs Argument string. Optional and specific to the handler.
904	*/
905	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
906	{
907	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
908	unsigned i;
909	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
910	{
911	const PITChannelState *pCh = &pThis->channels[i];
912
913	pHlp->pfnPrintf(pHlp,
914	"PIT (i8254) channel %d status: irq=%#x\n"
915	" count=%08x" " latched_count=%04x count_latched=%02x\n"
916	" status=%02x status_latched=%02x read_state=%02x\n"
917	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
918	" mode=%02x bcd=%02x gate=%02x\n"
919	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
920	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
921	,
922	i, pCh->irq,
923	pCh->count, pCh->latched_count, pCh->count_latched,
924	pCh->status, pCh->status_latched, pCh->read_state,
925	pCh->write_state, pCh->write_latch, pCh->rw_mode,
926	pCh->mode, pCh->bcd, pCh->gate,
927	pCh->count_load_time, pCh->next_transition_time,
928	pCh->u64ReloadTS, pCh->u64NextTS);
929	}
930	#ifdef FAKE_REFRESH_CLOCK
931	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
932	pThis->speaker_data_on, pThis->dummy_refresh_clock);
933	#else
934	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x\n", pThis->speaker_data_on);
935	#endif
936	if (pThis->fDisabledByHpet)
937	pHlp->pfnPrintf(pHlp, "Disabled by HPET\n");
938	}
939
940
941	/**
942	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
943	*/
944	static DECLCALLBACK(void ) pitQueryInterface(PPDMIBASE pInterface, const char pszIID)
945	{
946	PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase);
947	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
948	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase);
949	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIHPETLEGACYNOTIFY, &pThis->IHpetLegacyNotify);
950	return NULL;
951	}
952
953
954	/**
955	* @interface_method_impl{PDMIHPETLEGACYNOTIFY,pfnModeChanged}
956	*/
957	static DECLCALLBACK(void) pitNotifyHpetLegacyNotify_ModeChanged(PPDMIHPETLEGACYNOTIFY pInterface, bool fActivated)
958	{
959	PITState *pThis = RT_FROM_MEMBER(pInterface, PITState, IHpetLegacyNotify);
960	pThis->fDisabledByHpet = fActivated;
961	}
962
963
964	/**
965	* Relocation notification.
966	*
967	* @returns VBox status.
968	* @param pDevIns The device instance data.
969	* @param offDelta The delta relative to the old address.
970	*/
971	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
972	{
973	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
974	unsigned i;
975	LogFlow(("pitRelocate: \n"));
976
977	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
978	{
979	PITChannelState *pCh = &pThis->channels[i];
980	if (pCh->pTimerR3)
981	pCh->pTimerRC = TMTimerRCPtr(pCh->pTimerR3);
982	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
983	}
984	}
985
986
987	/**
988	* Reset notification.
989	*
990	* @returns VBox status.
991	* @param pDevIns The device instance data.
992	*/
993	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
994	{
995	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
996	unsigned i;
997	LogFlow(("pitReset: \n"));
998
999	pThis->fDisabledByHpet = false;
1000
1001	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1002	{
1003	PITChannelState *s = &pThis->channels[i];
1004
1005	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
1006	s->latched_count = 0;
1007	s->count_latched = 0;
1008	s->status_latched = 0;
1009	s->status = 0;
1010	s->read_state = 0;
1011	s->write_state = 0;
1012	s->write_latch = 0;
1013	s->rw_mode = 0;
1014	s->bcd = 0;
1015	#endif
1016	s->u64NextTS = UINT64_MAX;
1017	s->cRelLogEntries = 0;
1018	s->mode = 3;
1019	s->gate = (i != 2);
1020	pit_load_count(s, 0);
1021	}
1022	}
1023
1024
1025	/**
1026	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1027	*/
1028	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1029	{
1030	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
1031	int rc;
1032	uint8_t u8Irq;
1033	uint16_t u16Base;
1034	bool fSpeaker;
1035	bool fGCEnabled;
1036	bool fR0Enabled;
1037	unsigned i;
1038	Assert(iInstance == 0);
1039
1040	/*
1041	* Validate configuration.
1042	*/
1043	if (!CFGMR3AreValuesValid(pCfg, "Irq\0" "Base\0" "SpeakerEnabled\0" "GCEnabled\0" "R0Enabled\0"))
1044	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1045
1046	/*
1047	* Init the data.
1048	*/
1049	rc = CFGMR3QueryU8Def(pCfg, "Irq", &u8Irq, 0);
1050	if (RT_FAILURE(rc))
1051	return PDMDEV_SET_ERROR(pDevIns, rc,
1052	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
1053
1054	rc = CFGMR3QueryU16Def(pCfg, "Base", &u16Base, 0x40);
1055	if (RT_FAILURE(rc))
1056	return PDMDEV_SET_ERROR(pDevIns, rc,
1057	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
1058
1059	rc = CFGMR3QueryBoolDef(pCfg, "SpeakerEnabled", &fSpeaker, true);
1060	if (RT_FAILURE(rc))
1061	return PDMDEV_SET_ERROR(pDevIns, rc,
1062	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
1063
1064	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1065	if (RT_FAILURE(rc))
1066	return PDMDEV_SET_ERROR(pDevIns, rc,
1067	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
1068
1069	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1070	if (RT_FAILURE(rc))
1071	return PDMDEV_SET_ERROR(pDevIns, rc,
1072	N_("Configuration error: failed to read R0Enabled as boolean"));
1073
1074	pThis->pDevIns = pDevIns;
1075	pThis->IOPortBaseCfg = u16Base;
1076	pThis->fSpeakerCfg = fSpeaker;
1077	pThis->channels[0].irq = u8Irq;
1078	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1079	{
1080	pThis->channels[i].pPitR3 = pThis;
1081	pThis->channels[i].pPitR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1082	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
1083	}
1084
1085	/*
1086	* Interfaces
1087	*/
1088	/* IBase */
1089	pDevIns->IBase.pfnQueryInterface = pitQueryInterface;
1090	/* IHpetLegacyNotify */
1091	pThis->IHpetLegacyNotify.pfnModeChanged = pitNotifyHpetLegacyNotify_ModeChanged;
1092
1093	/*
1094	* Create timer, register I/O Ports and save state.
1095	*/
1096	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, &pThis->channels[0],
1097	TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "i8254 Programmable Interval Timer",
1098	&pThis->channels[0].pTimerR3);
1099	if (RT_FAILURE(rc))
1100	return rc;
1101	pThis->channels[0].pTimerRC = TMTimerRCPtr(pThis->channels[0].pTimerR3);
1102	pThis->channels[0].pTimerR0 = TMTimerR0Ptr(pThis->channels[0].pTimerR3);
1103
1104	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
1105	if (RT_FAILURE(rc))
1106	return rc;
1107	if (fGCEnabled)
1108	{
1109	rc = PDMDevHlpIOPortRegisterRC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1110	if (RT_FAILURE(rc))
1111	return rc;
1112	}
1113	if (fR0Enabled)
1114	{
1115	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1116	if (RT_FAILURE(rc))
1117	return rc;
1118	}
1119
1120	if (fSpeaker)
1121	{
1122	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1123	if (RT_FAILURE(rc))
1124	return rc;
1125	if (fGCEnabled)
1126	{
1127	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1128	if (RT_FAILURE(rc))
1129	return rc;
1130	}
1131	}
1132
1133	rc = PDMDevHlpSSMRegister3(pDevIns, PIT_SAVED_STATE_VERSION, sizeof(*pThis), pitLiveExec, pitSaveExec, pitLoadExec);
1134	if (RT_FAILURE(rc))
1135	return rc;
1136
1137	/*
1138	* Initialize the device state.
1139	*/
1140	pitReset(pDevIns);
1141
1142	/*
1143	* Register statistics and debug info.
1144	*/
1145	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1146	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1147
1148	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1149
1150	return VINF_SUCCESS;
1151	}
1152
1153
1154	/**
1155	* The device registration structure.
1156	*/
1157	const PDMDEVREG g_DeviceI8254 =
1158	{
1159	/* u32Version */
1160	PDM_DEVREG_VERSION,
1161	/* szName */
1162	"i8254",
1163	/* szRCMod */
1164	"VBoxDDGC.gc",
1165	/* szR0Mod */
1166	"VBoxDDR0.r0",
1167	/* pszDescription */
1168	"Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1169	/* fFlags */
1170	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1171	/* fClass */
1172	PDM_DEVREG_CLASS_PIT,
1173	/* cMaxInstances */
1174	1,
1175	/* cbInstance */
1176	sizeof(PITState),
1177	/* pfnConstruct */
1178	pitConstruct,
1179	/* pfnDestruct */
1180	NULL,
1181	/* pfnRelocate */
1182	pitRelocate,
1183	/* pfnIOCtl */
1184	NULL,
1185	/* pfnPowerOn */
1186	NULL,
1187	/* pfnReset */
1188	pitReset,
1189	/* pfnSuspend */
1190	NULL,
1191	/* pfnResume */
1192	NULL,
1193	/* pfnAttach */
1194	NULL,
1195	/* pfnDetach */
1196	NULL,
1197	/* pfnQueryInterface */
1198	NULL,
1199	/* pfnInitComplete */
1200	NULL,
1201	/* pfnPowerOff */
1202	NULL,
1203	/* pfnSoftReset */
1204	NULL,
1205	/* u32VersionEnd */
1206	PDM_DEVREG_VERSION
1207	};
1208
1209	#endif /* IN_RING3 */
1210	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 32484

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